TB62709N/F TOSHIBA Bi−CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC TB62709N,TB62709F 7−SEGMENT DRIVERS WITH BUILT−IN DECODERS (COMMON ANODE CAPABILITY, MAXIMUM 4−DIGIT CONTROL) The TB62709N and TB62709F are multifunctional, compact, 7−segment LED display drivers. These ICs can directly drive 7−segment displays and individual LEDs, and can control either a 4−digit display with decimal points, or 32 individual LEDs. These ICs can also be used with common−anode displays. Their outputs are constant current, the ampere levels at which are set using an external resistor. A synchronous serial port connects the IC to the CPU. The different modes of control provided by this device including Duty Control Register Set, Digit Set, Decode Set and Standby Set, are all based on every 16−bit of serial data. TB62709N TB62709F FEATURES Control circuit power supply voltage : VDD = 4.5 to 5.5 V Digit output rating : 17 V / −400 mA Weight SDIP24-P-300-1.78: 1.62 g (typ.) SSOP24-P-300-1.00: 0.32 g (typ.) Decoder output rating : 17 V / 50 mA Built−in decoder : Decodes the numerals 0 to 9, certain alphabetic characters, and of course blanks code. Digit control function : Can scan digit outputs DIG−0 to DIG−3 when connected to the common anode pins of a 7−segment display. Maximum transmission frequency : fCLK = 15 MHz Decoder outputs (OUT−A to OUT−Dp) Output current can be set up to a 40mA maximum using an external resistor. Constant current tolerance (Ta = 25°C, VDD = 5.0 V) : Variation between bits = ±7%, variation between devices (including variation between bits) = ±15% at VCE ≥ 0.7 V Package : 24−pin SDIP (SDIP24−P−300−1.78) 24−pin SSOP (SSOP24−P−300−1.00) 1 2006-06-14 TB62709N/F PIN ASSIGNMENT (Top view) BLOCK DIAGRAM 2 2006-06-14 TB62709N/F PIN FUNCTIONS PIN NUMBER PIN NAME 1 VDD 2 DATA−IN (DI) Serial data input pin. 3 CLOCK (CK) Clock input pin. The shift register shifts data on the clock's rising edge. 4 LOAD (LD) Load signal input pin. The data in the D8 to D15 are read on the rising edge and the current load register the is selected from among the Duty Register, the Decode & Digit Register, or Data Registers 0 to 3. The D0 to D7 bits of the 16−bit shift register contain data corresponding to the same registers just described, which are read on the load signal's falling edge. 5~12 OUT−A to OUT−Dp Segment drive output pins. The A to Dp outputs correspond to the seven segments. These pins output constant sink current. Connect each of these pins to the corresponding LED's cathode. 13, 21 P−GND 14 TEST−IN2 15 TEST−IN1 16, 17, 19, 20 DIG−0 to DIG−3 18 VCC 22 R−EXT 23 DATA−OUT (DO) 24 L−GND FUNCTION 5 V power pin. Ground pins, There are two which can be used to ground the output OUT−A to OUT−Dp pins. Product test pin. In normal use, be sure to connect to ground. Product test pin. In normal use, be sure to connect to ground. Digit output pins. Each of these pins can control one of the four seven−segment digits in a display. These pins output the VCC pin voltage as a source current output. Connect these pins to the LED anodes. Power pin for digit output. Current setting pin for the OUT−A to OUT−Dp pins. Connect a resistor between this pin and ground when setting the current. Serial data output pin. Use when TB62709N or TB62709F devices are used in cascade connections. Ground pin for logic and analog circuits. 3 2006-06-14 TB62709N/F TIMING DIAGRAM DATA INPUT Transfer data to the DATA−IN pin on every 16−bit combining address (8bits) and data (8bits). After the 16th clock signal input following this data transfer input a load signal from the LD pin. Input the load signal using an Active High pulse. The register address is set on the rising edge of the load pulse. On the subsequent falling edge, the data are read as data of the mode of the register. 4 2006-06-14 TB62709N/F DESCRIPTION OF OPERATION Data input (SERIAL−IN, CLOCK, LOAD) The data are input serially using the SERIAL−IN pin. The data input interface consists of a total of three inputs : SERIAL−IN, LOAD, and CLOCK. Binary code stored in the 16−bit shift register offers control modes including duty Control Register Set, Digitset, Decode Set, and Standby Set, The data are shifted on the rising edge of the clock, starting from the MSB. Cascade−connecting TB62709N or TB62709F devices provides capability for controlling a larger number of digits. The serial data in the 16−bit shift register are used as follows : the four bits D15 (MSB) to D12 select the IC operating mode (Table 1), while D11 to D8 select the register corresponding to the operating mode (Table 2). Bits D7 to D0 (LSB) of the 16−bit shift register are used for detail settings, such as number of digits in use, character settings in each digit, and light intensity. The internal registers are loaded on the rising edge of the LOAD signal, which causes loading of data from an external source into the D15 (MSB) to D8 bits of the shift register, operating mode and the corresponding register selection data. On the subsequent falling edge, the detail setting data of D7 to D0 (LSB) are loaded. Normally LOAD is Low. After a serial transfer of 16bits, the input of a High−level pulse loads the data. Note the following caution : Use the D15 to D8 setting and the D7 to D0 detail data setting as a pair. If only the D7 to D0 data are input without setting D15 to D8 an error condition may result, in which the device will not operate normally. If the current mode is set again by a new signal, the data for D15 to D8 must also be re−input. Operating precautions At power−on or after operation in Clear mode (in initial state), set the IC to Normal mode again. Otherwise, the IC will not drive the LED. Operating the IC in Blank mode (all lights off) or in All On mode (all lights lit) does not affect the internal data. Setting the IC to Normal mode again continues the LED lighting in the state governed by the settings made immediately before mode change. Normal mode (not Shut Down, Clear, Blank, or All On mode) continues the operations set in Load Register mode. In Normal mode, operations are governed by any new settings made in the Load Register, as soon as the changed setting values are loaded. 5 2006-06-14 TB62709N/F Operating modes (Table 1.) These ICs support the following five operating modes : 1. Blank : Forcibly turns OFF the constant−current output both for data and for digit setting. This mode is not affected by the values in bits D11 to D0. 2. Normal Operate : Used for display operations after the settings of the digits are complete. Note that setting this mode without making any other settings will cause display of the numeral 0. 3. Load Register : Used for the detail settings of the Duty Control Register, for setting Decode / No Decode, for inputting display data, and for setting the number of digits to drive. D11 to D0 of the shift register are used for the detail settings of the digits currently being driven (Table 2). 4. All On : Forcibly turns ON the data−side constant−current output. This mode is not affected by D11 to D0. The initial setting is four digits. When the digits must be changed, use Load Register mode to set the number of digits to drive. 5. Standby : Used to set Standby state (in which internal data are not cleared) and to clear data (initialization). The settings in D3 to D0 of the shift register determine the choice between standby state or initialization. Table 1 Operating mode settings REGISTER DATA D12 D11~D8 D7~D4 D3~D0 HEX CODE INITIAL SETTING ― ― 0−−−H ■ ― ― ― 1−−−H 0 X X X 2XXXH 1 1 ― ― ― 3−−−H 0 0 ― ― X 4−−XH D15 D14 D13 BLANK (OUT−n & DIG−0~3 ALL−OFF) 0 0 0 0 ― NORMAL (OPERATION) 0 0 0 1 LOAD REGISTER (DUTY, DECODE, DIGIT & DATA) 0 0 1 ALL ON (OUTn ALL−ON) 0 0 STAND−BY 0 1 X = Input H or L. "−" = Are not affected by the truth table. 6 2006-06-14 TB62709N/F Load Register Selection modes (Table 2) These modes select the register to provide the data to control the IC operation. The Load Register selection mode is determined by the settings of D15 to D12 and D11 to D8 of the shift register. 1. Duty Register : The data in D7 to D0 of this register set the digit output duty cycle. Duty settings can be made in 16 steps from 0 / 16 to 15 / 16. (See Table 3) 2. Decode & Digit Register : Sets Decode / No Decode and the number of digits to drive. Decode can be set using D7 to D4. The number of digits driven can be set using D3 to D0. Decode / No Decode and the number of digits driven are set simultaneously. 3. Data registers 0 to 3 : Set the display data corresponding to DIG0 to DIG3 respectively. D7 to D0 of the shift register are used to set the display data. Table 2 Load register selection REGISTER DATA D15~D12 D11 D10 D9 D8 D7~D4 D3~D0 HEX CODE LOAD DUTY REGISTER 2H 0 0 0 0 X X 20XXH LOAD DECODE & DIGIT REGISTER 2H 0 0 0 1 X X 21XXH LOAD DATA REGISTER 0 2H 0 0 1 0 X X 22XXH LOAD DATA REGISTER 1 2H 0 0 1 1 X X 23XXH LOAD DATA REGISTER 2 2H 0 1 0 0 X X 24XXH LOAD DATA REGISTER 3 2H 0 1 0 1 X X 25XXH X = Input H or L. 7 2006-06-14 TB62709N/F DUTY CONTROL REGISTER SETTINGS Duty Control Register detail settings and operation (Table 3) Writing 20H to D15~D8 and writing 0~FH to D3~D0 sets the duty cycle shown in the following table for the digit−side source driver output. The duty cycle can be set in 16 steps. The initial setting is 15 / 16. After Data Clear, the setting is also 15 / 16. The current settings continue until changed (by reset execution, or to the initial state, Data Clear state, or standby state). Table 3 Duty control register settings DUTY CYCLE REGISTER DATA D15~D8 D7~D4 D3 D2 D1 D0 HEX CODE 0 / 16 20H ― 0 0 0 0 20X0H 1 / 16 20H ― 0 0 0 1 20X1H 2 / 16 20H ― 0 0 1 0 20X2H 3 / 16 20H ― 0 0 1 1 20X3H 4 / 16 20H ― 0 1 0 0 20X4H 5 / 16 20H ― 0 1 0 1 20X5H 6 / 16 20H ― 0 1 1 0 20X6H 7 / 16 20H ― 0 1 1 1 20X7H 8 / 16 20H ― 1 0 0 0 20X8H 9 / 16 20H ― 1 0 0 1 20X9H 10 / 16 20H ― 1 0 1 0 20XAH 11 / 16 20H ― 1 0 1 1 20XBH 12 / 16 20H ― 1 1 0 0 20XCH 13 / 16 20H ― 1 1 0 1 20XDH 14 / 16 20H ― 1 1 1 0 20XEH 15 / 16 20H ― 1 1 1 1 20XFH INITIAL SETTING ■ X = Input H or L. "−" = Are not affected by the truth table. 8 2006-06-14 TB62709N/F DIGIT SETTINGS Setting the number of digits (Table 4) Writing 21H to D15~D8 and at the same step writing 0H~3H to D3~D0 sets the number of digits to a maximum of four the display. The initial setting is four digits, and four will also be set by a Data Clear. The current settings continue until changed (by reset execution, or to the initial state, Data Clear state, or standby state). When changing the number of digits, also set D7 to D4. Table 4 Digit settings REGISTER DATA D2 D1 D15~D8 D7~D4 D3 D0 HEX CODE ACTIVATED DIG−−0 ONLY 21H X 0 0 0 0 21X0H ACTIVATED DIG−−0~1 21H X 0 ACTIVATED DIG−−0~2 21H X 0 0 0 1 21X1H 0 1 0 21X2H ACTIVATED DIG−−0~3 21H X 0 0 1 1 21X3H INITIAL SETTING ■ X = Input H or L. DECODE SETTINGS Decode settings (Table 5) The settings for Decode are the same as the settings for the number of digits, described under setting, above. Writing 21H to D15~D8 and writing 0~1H to D7~D4 set Decode mode. When using this IC for controlling the lighting on individual LEDs used for a dot matrix rather than a 7−segment display, set to No Decode. As Table 6 shows, D0 in the data register is used to turn OUT−a ON and OFF ; D1 turns OUT−b ON and OFF. The initial setting is Decode mode, and Decode mode will also be set by a Data Clear. The current settings continue until changed (by reset execution, or to the initial state, Data Clear state, or standby state). Since D3 to D0 are also used for setting the number of digits, when changing the Decode setting, also set D3 to D0. Table 5 Decode settings REGISTER DATA D5 D4 D15~D8 D7 D6 PASS DECODER (NO DECODE) 21H 0 0 0 DECODE 21H 0 0 0 D3~D0 HEX CODE 0 X 210XH 1 X 211XH INITIAL SETTING ■ X = Input H or L. 9 2006-06-14 TB62709N/F THE FOLLOWING TABLE SHOWS THE CORRESPONDENCE BETWEEN THE SERIAL DATA AND THE OUTPUT PINS WHEN NO DECODE IS SET Table 6 Correspondence between serial data and output pins in no decode mode REGISTER DATA OUTPUT INITIAL STATE D0 OUT−a L D1 OUT−b L D2 OUT−c L D3 OUT−d L D4 OUT−e L D5 OUT−f L D6 OUT−g L D7 OUT−Dp L NOTE Output is ON when data = H and OFF when data = L. STANDBY SETTINGS Standby mode settings and operation (Table 7) Writing 4H to D15~D12 and writing 0H to D3~D0 sets Standby mode. Writing 4H to D15~D12 and writing 1H to D3~D0 sets All Data Clear mode. Standby mode maintains the settings made immediately before this mode came in force, turns the output current OFF, and controls the bias current flowing in the internal circuits. All Data Clear resets all settings to their initial states. Table 7 Standby settings REGISTER DATA D2 D1 D15~D8 D7~D4 D3 D0 HEX CODE STANDBY (NO DATA CLEAR) 4−H ― 0 0 0 0 4XX0H ALL DATA CLEAR 4−H ― 0 0 0 1 4XX1H X = Input H or L. "−" Are not affected by the truth table. 10 2006-06-14 TB62709N/F LIST OF CHARACTER GENERATOR DECODING DATA Character generator decoding (Table 8) As the following table shows, the characters are decoded using combinations of the data in D0 to D3 and D5 to D4. In decoding, D6 is used exclusively for setting decimal points. Spaces where (D0, D1, D2, D3) = (0000) and (D5, D4) = (01) are regarded as blank. Table 8 List of character generator decoding data D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D5 D4 HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 1 1 D7 D6 X 0 Dp OFF X 1 Dp ON 11 2006-06-14 TB62709N/F DATA INPUT (Example 1: Displays and blinks characters a, b, c and d in digits 0, 1, 2 and 3 respectively. Period after "d" part of it, or a sentence−end marker?) STEP D15~ D12 D11~ D8 D7~ D4 D3~ D0 DIG −0~3 SEG −a, b, c, d, e, f, g SEG −Dp MODE DISPLAY INDICATE 0 ― ― ― ― OFF OFF OFF At power−on ( = CLEAR MODE) ALL BLANK 1 0010 0000 XXXX 1111 OFF OFF OFF DUTY = 15 / 16 ALL BLANK 2 0010 0001 0001 0011 OFF OFF OFF DECODE, 4DIG ALL BLANK 3 0010 0010 X000 1010 OFF OFF OFF DIG−0 = a ALL BLANK 4 0010 0011 X000 1011 OFF OFF OFF DIG−1 = b ALL BLANK 5 0010 0100 X000 1100 OFF OFF OFF DIG−2 = c ALL BLANK 6 0010 0101 X000 1101 OFF OFF OFF DIG−3 = d ALL BLANK 7 0001 XXXX XXXX XXXX ON ON OFF NORMAL a−b−c−d 8 0010 0000 XXXX 1000 ON ON OFF DUTY = 8 / 16 a−b−c−d 9 0000 XXXX XXXX XXXX OFF OFF OFF BLANK ALL BLANK 10 0001 XXXX XXXX XXXX ON ON OFF NORMAL a−b−c−d 11 0000 XXXX XXXX XXXX OFF OFF OFF BLANK ALL BLANK 12 0001 XXXX XXXX XXXX ON ON OFF NORMAL a−b−c−d 13 0000 XXXX XXXX XXXX OFF OFF OFF BLANK ALL BLANK 14 0001 XXXX XXXX XXXX ON ON OFF NORMAL a−b−c−d OFF STAND−BY (SHUT DOWN) ALL BLANK 15 0100 XXXX XXXX 0000 OFF OFF DATA INPUT (Example 2: Scroll−lights digits 0, 1, 2, 3 = a., −b., −c., −d. ?SEQ; and please explain the data on rhs? digit by digit (with decimal points)) STEP D15~ D12 D11~D 8 D7~ D4 D3~ D0 DIG −0~3 SEG −a, b, c, d, e, f, g SEG −Dp MODE DISPLAY INDICATE 0 ― ― ― ― OFF OFF OFF At power−on ( = CLEAR MODE) ALL BLANK 1 0010 0000 XXXX 1111 OFF OFF OFF DUTY = 15 / 16 ALL BLANK 2 0010 0001 0001 0011 OFF OFF OFF DECODE, 4DIG ALL BLANK 3 0010 0010 X100 1010 OFF OFF OFF DIG−0 = a. ALL BLANK 4 0010 0011 X001 0000 OFF OFF OFF DIG−1 = blank ALL BLANK 5 0010 0100 X001 0000 OFF OFF OFF DIG−2 = blank ALL BLANK 6 0010 0101 X001 0000 OFF OFF OFF DIG−3 = blank ALL BLANK 7 0001 XXXX XXXX XXXX ON ON ON NORMAL a.−−− 8 0010 0010 X001 0000 OFF ON OFF DIG−0 = blank ALL BLANK 9 0010 0011 X100 1011 ON ON ON DIG−1 = b. −b.−− 10 0010 0011 X001 0000 OFF ON OFF DIG−1 = blank ALL BLANK 11 0010 0100 X100 1100 ON ON ON DIG−2 = c. −−c.− 12 0010 0100 X001 0000 OFF ON OFF DIG−2 = blank ALL BLANK 13 0010 0101 X100 1101 ON ON ON DIG−3 = d. −−−d. 14 0100 XXXX XXXX 0000 OFF OFF OFF STAND−BY (SHUT DOWN) ALL BLANK 12 2006-06-14 TB62709N/F STATE TRANSITION DIAGRAM 13 2006-06-14 TB62709N/F ABSOLUTE MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING UNIT Supply Voltage for Logic Circuits VDD 7.0 V Supply Voltage VCC 17 V DIG−0 to DIG−3 Output Current IDIG −400 mA OUT−a to Dp Output Current IOUT 50 mA IOH / IOL ±5 mA VIN −0.3~VDD + 0.3 V Operating Frequency fCK 15.0 MHz Total Supply Current IVDD 400 mA Output Current for Logic Block Input Voltage Power Dissipation TB62709N TB62709F 1.78 PD W 0.62 Operating Temperature Topr −40~85 °C Storage Temperature Tstg −55~150 °C ELECTRICAL CHARACTERISTICS (Unless otherwise stated, VDD = 5.0 V, VCC = 5.0 V, REXT = 760 Ω, Ta = −40~85°C) SYMBOL TEST CIR− CUIT TEST CONDITION MIN TYP. MAX ICC1 1 SET NORMAL OPE. MODE, REXT = 760 Ω @OUT−a~Dp ALL ON, Ta = 25°C ― 300 ― ICC2 1 SET NORMAL OPE. MODE, REXT = 760 Ω @OUT−a~Dp ALL ON VCC = 12 V, Ta = 25°C ― 320 ― DIG−0 to DIG−3 Scan Frequency fOSC 2 NORMAL OPE. MODE, VDD = 4.5~5.5 V 240 480 960 Hz OUT−a to Dp Output Sink Current ISEG 3 NORMAL OPE. MODE, VCE = 0.7 V, REXT = 760 Ω 29 34 40 mA DIG−0 to 3 Output Leakage Current Ileak1 4 ALL OFF MODE, VCC = 17 V ― ― −20 µA OUT−a to Dp Output Leakage Current Ileak2 4 ALL OFF MODE, VCC = 17 V ― ― 20 µA DIG−0 to 3 Output Voltage VOUT 5 NORMAL OPE. MODE, IDIG = −320 mA 3.0 ― ― V CHARACTERISTIC Operating Power Supply Current for Output Block 14 UNIT mA 2006-06-14 TB62709N/F Logic block CHARACTERISTIC SYMBOL TEST CIR− CUIT TEST CONDITION MIN TYP. MAX UNIT IDD1 6 STANDBY MODE, Ta = 25°C ― ― 200 µA IDD2 6 BLANK MODE, Ta = 25°C ― ― 12.5 mA IDD3 6 NORMAL OPE. MODE, fCLK = 10MHz, DATA−IN : OUT−a~Dp = ON, Ta = 25°C ― ― 20.5 mA High Input Current for Logic Circuits IIH ― DATA−IN, LOAD & CLOCK : VIN = 5 V ― ― 1 µA Low Input Current for Logic Circuits IIL ― DATA−IN, LOAD & CLOCK : VIN = 0 V ― ― −1 µA Static Power Supply Current for Logic Circuits Operating Power Supply Current for Logic Circuits High Output Voltage for Logic Circuits Low Output Voltage for Logic Circuits Clock Frequency VOH1 6 DATA−OUT, IOH = −1.0 mA 4.6 ― ― VOH2 6 DATA−OUT, IOH = −1.0 µA ― VDD ― VOL1 6 DATA−OUT, IOL = 1.0 mA ― ― 0.4 VOL2 6 DATA−OUT, IOH = 1.0 µA ― 0.1 ― fCLK 6 CASCADE CONNECTED, Ta = −40~85°C 10 ― ― 15 V V MHz 2006-06-14 TB62709N/F SWITCHING CHARACTERISTICS (Unless otherwise stated, VDD = 5.0 V, VCC = 5.0 V, Ta = 25°C) SYMBOL TEST CIR− CUIT TEST CONDITION MIN TYP. MAX UNIT Data Hold Time (D−IN−CLOCK) tDHO ― ― ― 10 ― ns Data Setup Time (D−IN−CLOCK) tDST ― ― ― 20 ― ns CL = 10 pF ― 25 ― CL = 10 pF ― 25 ― 30 ― ns CHARACTERISTIC Serial Output Delay Time (CLOCK−D−OUT) High Clock Pulse Width tpHL−SO tpLH−SO ― ns tCKH ― ― ― Low Clock Pulse Width tCKL ― ― ― 30 ― ns Load Pulse Width twLD ― ― ― 100 ― ns Load Clock Time (CLOCK−LOAD) tCLK−LD ― ― ― 50 ― ns Clock Load Time (LOAD−CLOCK) tLD−CLK ― ― ― 50 ― ns OUT−a to Dp Output Delay Time (LOAD−OUTn) tpHL−SEG tpLH−SEG ― CL = 10 pF ― ― 5.0 CL = 10 pF ― ― 5.0 µs OUT−a to Dp Output Rise Time (OUTn) tr SEG ― CL = 10 pF 0.2 1.0 ― µs OUT−a to Dp Output Fall Time (OUTn) tf SEG ― CL = 10 pF 0.2 1.0 ― µs DIG−0~DIG−3 Output Delay Time (LOAD−DIGn) tpHL−DIG tpLH−DIG DIG−0~DIG−3 Output Rise Time (DIGn) tr DIG DIG−0~DIG−3 Output Fall Time (DIGn) tf DIG ― ― CL = 10 pF ― ― 10.0 CL = 10 pF ― ― 10.0 CL = 10 pF 0.4 2.0 ― µs CL = 10 pF 0.4 2.0 ― µs 16 µs 2006-06-14 TB62709N/F RECOMMENDED OPERATING CONDITIONS (Unless otherwise stated, VDD = 5.0 V, VCC = 5.0 V, Ta = −40~85°C) CHARACTERISTIC SYMBOL TEST CIR− CUIT TEST CONDITION MIN TYP. MAX UNIT Supply Voltage for Output Block VCC ― ― 4.0 ― 6.0 V DIG−0 to DIG−3 Output Source Current IDIG ― VOUT = 3.0 V ― ― −320 mA OUT−a to OUT−Dp Output Sink Current ISEG ― VCE = 0.7 V ― ― 40 mA SYMBOL TEST CIR− CUIT TEST CONDITION MIN TYP. MAX UNIT VDD ― ― Logic block CHARACTERISTIC Supply Voltage for Logic Block 4.5 ― 5.5 V ― DATA−IN, LOAD & CLOCK, VIN = VDD ― ― 1 µA IIL ― DATA−IN, LOAD & CLOCK, VIN = 0V ― ― −1 µA High Input Voltage for Logic Circuits VIH ― ― 0.7 VDD ― ― V Low Input Voltage for Logic Circuits VIL ― ― ― ― 0.3 VDD V SYMBOL TEST CIR− CUIT TEST CONDITION MIN TYP. MAX UNIT Data Hold Time (D−IN−CLOCK) tDHO ― ― 30 ― ― ns Data Setup Time (D−IN−CLOCK) tDST ― ― 50 ― ― ns tPDSO ― 50 ― ― ns High Clock Pulse Width tCKH ― ― 30 ― ― ns Low Clock Pulse Width tCKL ― ― 30 ― ― ns Load Pulse Width twLD ― ― 150 ― ― ns Load Clock Time (CLOCK−LOAD) tCLKLD ― ― 100 ― ― ns Clock Load Time (LOAD−CLOCK) tLDCLK ― ― 100 ― ― ns High Input Current for Logic Circuits IIH Low Input Current for Logic Circuits SWITCHING CONDITIONS CHARACTERISTIC Serial Output Delay Time (CLOCK−D−OUT) CL = 10 pF 17 2006-06-14 TB62709N/F TEST CIRCUITS (1) ICC1, ICC2 (2) fOSC 18 2006-06-14 TB62709N/F (3) ISEG (4) Ileak1, Ileak2 19 2006-06-14 TB62709N/F (5) VOUT (6) IDD1, IDD2, IDD3, VOH1, VOH2, VOL1, VOL2, fCLK 20 2006-06-14 TB62709N/F DUTY CYCLE SETTINGS AND OUTPUT CURRENT VALUES 21 2006-06-14 TB62709N/F EXTERNAL RESISTANCE AND OUTPUT CURRENT VALUES The following diagram shows application circuits. Because operation may be unstable due to influences such as the electromagnetic induction of the wiring, the IC should be located as close as possible to the LED. The L−GND and P−GND of the IC are connected to the substrate in the IC. Take care to avoid a potential difference exceeding 0.4V at two pins. When executing the pattern layout, Toshiba recommends not including inductance components in the GND or output pin lines, and not inserting capacitance components exceeding 50pF between the REXT and GND. 22 2006-06-14 TB62709N/F APPLICATION CIRCUIT EXAMPLE (Connection example) PRECAUTIONS for USING Utmost care is necessary in the design of the output line, VCC (VDD) and (L−GND, P−GND) line since IC may be destroyed due to short−circuit between outputs, air contamination fault, or fault by improper grounding. 23 2006-06-14 TB62709N/F Package Dimensions Weight: 1.62 g (typ.) 24 2006-06-14 TB62709N/F Package Dimensions Weight: 0.32 g (typ.) 25 2006-06-14 TB62709N/F Notes on Contents 1. Block Diagrams Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. Timing Charts Timing charts may be simplified for explanatory purposes. 4. Application Circuits The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. Test Circuits Components in the test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. 26 2006-06-14 TB62709N/F IC Usage Considerations Notes on Handling of ICs (1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. (2) Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. (3) If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition. (4) Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. (5) Carefully select external components (such as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. If there is a large amount of leakage current such as input or negative feedback condenser, the IC output DC voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC that inputs output DC voltage to a speaker directly. Points to Remember on Handling of ICs (1) Heat Radiation Design In using an IC with large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (Tj) at any time and condition. These ICs generate heat even during normal use. An inadequate IC heat radiation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In addition, please design the device taking into considerate the effect of IC heat radiation with peripheral components. (2) Back-EMF When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor’s power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the device’s motor power supply and output pins might be exposed to conditions beyond maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in system design. 27 2006-06-14 TB62709N/F RESTRICTIONS ON PRODUCT USE 060116EBA • The information contained herein is subject to change without notice. 021023_D • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E 28 2006-06-14