TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L Series TMP93PW20A Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0 to INT4, INTKEY and INTRTC), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (RUN and IDLE2 are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP93PW20A Low Voltage/Low Power CMOS 16-Bit Microcontroller TMP93PW20AF 1. Outline and Device Characteristics The TMP93PW20A is OTP type MCU which includes 128 Kbytes one-time PROM. Using the adapter-socket, you can write and verify the data for the TMP93CS20 by general EPROM programmer. The TMP93PW20A has the same pin-assignment as the TMP93CS20 (Mask ROM type). Writing the program to built-in PROM, the TMP93PW20A operates as the same way as the TMP93CS20. There are differences in the memory mapping area and the memory capacity of the internal PROM and RAM between the TMP93PW20A and the TMP93CS20. The internal PROM of the TMP93PW20A is 128 Kbytes, and the internal RAM is 4 Kbytes. The internal ROM of the TMP93CS20 is 64 Kbytes, and the internal RAM is 2 Kbytes. Memory maps are described as follows. 030619EBP1 • The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 93PW20A-1 2004-02-10 TMP93PW20A 000000H 000000H Internal I/O (128 bytes) 0000A0H Internal I/O (128 bytes) 0000A0H Internal RAM (2 Kbytes) Internal RAM (4 Kbytes) 0008A0H 0010A0H FE0000H FF0000H Internal PROM (128 Kbytes) Internal ROM (64 Kbytes) FFFF00H FFFF00H Interrupt vector table area (256 bytes) Interrupt vector table area (256 bytes) FFFFFFH FFFFFFH Memory map of TMP93PW20A Memory map of TMP93CS20 Product No. ROM RAM Package Adapter Socket TMP93PW20A OTP 128 Kbytes 4 Kbytes P-LQFP144-1616-0.40 BM11141 93PW20A-2 2004-02-10 TMP93PW20A ADTRG (P37) AN0 to AN7 (P50 to P57) AVCC AVSS VREFH VREFL VCC [3] VSS [8] CPU (900/L) 10-bit 8 channel AD converter SCK (P60) SO/SDA (P61) SI/SCL (P62) Serial bus interface TXD0 (P63) RXD0 (P64) SCLK0/ CTS0 (P65) Serial I/O (Cannel 0) TXD1 (P80) RXD1 (P81) Serial I/O (Channel 1) W A B C D E H L IX IY IZ SP XWA XBC XDE XHL XIX XIY XIZ XSP OSC1 Clock Gear 32 bits P OSC2 F SR X1 X2 C XT1 (P86) XT2 (P87) CLK ALE SCOUT (P73) EA RESET RD (P30) WR (P31) HWR (P32) WAIT (P84) 4 Kbytes RAM TI0 (P66) 8-bit timer (Timer 0) TO1 (P67) 8-bit timer (Timer 1) Port 0 P00 to P07 (AD0 to AD7) TI2 (P82) 8-bit timer (Timer 2) Port 1 P10 to P17 (AD8/A8 to AD15/A15) TO3 (P83) 8-bit timer (Timer 3) Port 2 P20 to P27 (A0/A16 to A7/A23) 128 Kbytes ROM TI4 (P40) TO4 (P41) TI6 (P42) TO6 (P43) 16-bit timer (Timer 4) 16-bit timer (Timer 8) TI8/INT8 (P70) TI9/INT9 (P71) TO8 (P72) 16-bit timer (Timer A) TIA/INTA (P74) TIB/INTB (P75) TOA (P76) 16-bit timer (Timer 6) Interrupt controller KEY0 to KEY7 (P40 to P47) Key wakeup (KEY0 to KEY7) NMI (P77) INT0 to INT4 (P33 to P37) INT7 (P66) Watchdog timer LCD driver Real time counter V1 to V3 C0 to C1 SEG0 to SEG23 SEG24 to SEG39 (P90 to PA7) COM0 to COM3 Note: The item in parentheses ( ) are the initial setting after reset. Figure 1.1 TMP93PW20A Block Diagram 93PW20A-3 2004-02-10 TMP93PW20A 2. Pin Assignment and Functions The assignment of input/output pins for the TMP93PW20A their names and outline functions are described below. 2.1 Pin Assignment PA1 (SEG33) PA0 (SEG32) P97 (SEG31) P96 (SEG30) P95 (SEG29) P94 (SEG28) P93 (SEG27) P92 (SEG26) VSS P91 (SEG25) P90 (SEG24) SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 VSS SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 Figure 2.1.1 shows pin assignment of the TMP93PW20AF. 108 109 72 110 105 100 95 90 85 80 75 70 115 65 120 60 TMP93PW20AF LQFP144 125 55 Top view 130 50 135 45 140 40 5 15 20 25 30 1 35 36 Figure 2.1.1 37 COM3 COM2 COM1 COM0 C1 C0 V3 VCC VSS V2 V1 P47 (KEY7) P46 (KEY6) P45 (KEY5) P44 (KEY4) P43 (TO6/KEY3) P42 (TI6/KEY2) P41 (TO4/KEY1) P40 (TI4/KEY0) P85 P84 ( WAIT ) P83 (TO3) P82 (TI2) P81 (RXD1) P80 (TXD1) P77 ( NMI ) P76 (TOA) P75 (TIB/INTB) VSS P74 (TIA/INTA) P73 (SCOUT) P72 (TO8) P71 (TI9/INT9) P70 (TI8/INT8) P67 (TO1) P66 (TI0/INT7) RESET (SCK) P60 (SO/SDA) P61 (SI/SCL) P62 (TXD0) P63 (RXD0) P64 (SCLK0/CTS0) P65 144 10 (AD7) P07 (AD8/A8) P10 (AD9/A9) P11 (AD10/A10) P12 (AD11/A11) P13 (AD12/A12) P14 (AD13/A13) P15 VSS (AD14/A14) P16 (AD15/A15) P17 (A0/A16) P20 (A1/A17) P21 (A2/A18) P22 (A3/A19) P23 (A4/A20) P24 (A5/A21) P25 (A6/A22) P26 (A7/A23) P27 CLK ALE EA X1 X2 TEST1 TEST2 (XT1) P86 (XT2) P87 VSS VCC (SEG34) PA2 (SEG35) PA3 (SEG36) PA4 (SEG37) PA5 (SEG38) PA6 (SEG39) PA7 ( RD ) P30 VSS ( WR ) P31 ( HWR ) P32 (INT0) P33 (INT1) P34 (INT2) P35 (INT3) P36 (INT4/ ADTRG ) P37 VREFH VREFL (AN7) P57 (AN6) P56 (AN5) P55 (AN4) P54 (AN3) P53 (AN2) P52 (AN1) P51 (AN0) P50 AVCC AVSS VSS VCC (AD0) P00 (AD1) P01 (AD2) P02 (AD3) P03 (AD4) P04 (AD5) P05 (AD6) P06 73 Pin Assignment (144-pin LQFP) 93PW20A-4 2004-02-10 TMP93PW20A 2.2 Pin Names and Functions The TMP93PW20A has MCU mode and PROM mode. (1) Pin functions of TMP93PW20A in MCU mode. Table 2.2.1 Pin Names Number of Pins Name and Function in MCU Mode (1/3) I/O Functions Port 0: I/O port that allows I/O to be selected at the bit level. Address and data (lower): Bits 0 to 7 for address and data bus. P00 to P07 AD0 to AD7 8 I/O I/O P10 to P17 AD8 to AD15 A8 to A15 8 I/O I/O Output Port 1: I/O port that allows I/O to be selected at the bit level. Address and data (Upper): Bits 8 to 15 for address and data bus. Address: Bits 8 to 15 for address bus. P20 to P27 A0 to A7 A16 to A23 8 I/O Output Output Port 2: I/O port that allows I/O to be selected at the bit level (with pull-up resistor). Address: Bits 0 to 7 for address bus. Address: Bits 16 to 23 for address bus. P30 1 Output Output Port 30: Output port. Read: Strobe signal for reading external memory. (Read when reading internal memory at P3<P30> = 0, P3FC<P30F> = 1.) 1 Output Output Port 31: Output port. Write: Strobe signal for writing data on pins AD0 to AD7. 1 I/O Output Port 32: I/O port (with pull-up resistor). High write: Strobe signal for writing data on pins AD8 to AD15. P33 INT0 1 I/O Input Port 33: I/O port (with pull-up resistor). Interrupt request pin 0: Interrupt request pin with programmable level/rising/falling edge. P34 INT1 1 I/O Input Port 34: I/O port (with pull-up resistor). Interrupt request pin 1: Interrupt request pin with programmable rising/falling edge. P35 INT2 1 I/O Input Port 35: I/O port (with pull-up resistor). Interrupt request pin 2: Interrupt request pin with programmable rising/falling edge. P36 INT3 1 I/O Input Port 36: I/O port (with pull-up resistor). Interrupt request pin 3: Interrupt request pin with programmable rising/falling edge. P37 INT4 1 I/O Input Input Port 37: I/O port (with pull-up resistor). Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge. ADTRG Input AD external trigger pin: External trigger pin to start AD conversion. RD P31 WR P32 HWR ADTRG P40 TI4 KEY0 1 I/O Input Input Port 40: I/O port (with pull-up resistor). Timer input 4: 16-bit timer 4 input. Key input 0: Key-on wakeup pin 0. P41 TO4 KEY1 1 I/O Output Input Port 41: I/O port (with pull-up resistor). Timer output 4: 16-bit timer 4 output. Key input 1: Key-on wakeup pin 1. P42 TI6 KEY2 1 I/O Input Input Port 42: I/O port (with pull-up resistor). Timer input 6: 16-bit timer 6 input. Key input 2: Key-on wakeup pin 2. P43 TO6 KEY3 1 I/O Output Input Port 43: I/O port (with pull-up resistor). Timer output 6: 16-bit timer 6 output. Key input 3: Key-on wakeup pin 3. P44 to P47 KEY4 to KEY7 4 I/O Input Port 44 to 47: I/O port (with pull-up resistor). Key input 4 to 7: Key-on wakeup pin 4 to 7. P50 to P57 AN0 to AN7 8 Input Input Port 50 to 57: Pin used to input port. Analog input 0 to 7. 93PW20A-5 2004-02-10 TMP93PW20A Table 2.2.1 Pin Names Number of Pins Name and Function in MCU Mode (2/3) I/O Functions P60 SCK 1 I/O I/O P61 SO SDA 1 I/O Output I/O P62 SI SCL 1 I/O Input I/O P63 TXD0 1 I/O Output P64 RXD0 1 I/O Input Port 64: I/O port. Serial receive data 0. P65 SCLK0 1 I/O I/O Input Port 65: I/O port. Serial clock I/O 0. Serial data send enable 0 (Clear to send). P66 TI0 INT7 1 I/O Input Input Port 66: I/O port. Timer input 0: 8-bit timer 0 input. Interrupt request pin 7: Interrupt request pin with programmable rising/falling edge. P67 TO1 1 I/O Output P70 TI8 INT8 1 I/O Input Input Port 70: I/O port (with pull-up resistor). Timer input 8: 16-bit timer 8 input. Interrupt request pin 8: Interrupt request pin with programmable rising/falling edge. P71 TI9 INT9 1 I/O Input Input Port 71: I/O port (with pull-up resistor). Timer input 9: 16-bit timer 8 input. Interrupt request pin 9: Interrupt request pin with rising edge. P72 TO8 1 I/O Output Port 72: I/O port (with pull-up resistor). Timer output 8: 16-bit timer 8 output. P73 SCOUT 1 I/O Output Port 73: I/O port (with pull-up resistor). System clock output: System clock or double system clock output to be synchronized with the external circuit. P74 TIA INTA 1 I/O Input Input Port 74: I/O port (with pull-up resistor). Timer input A: 16-bit timer A input. Interrupt request pin A: Interrupt request pin with programmable rising/falling edge. P75 TIB INTB 1 I/O Input Input Port 75: I/O port (with pull-up resistor). Timer input B: 16-bit timer B input. Interrupt request pin B: Interrupt request pin with rising edge. P76 TOA 1 I/O Output P77 1 I/O Input P80 TXD1 1 I/O Output Port 80: I/O port (with programmable open drain). Serial send data 1. P81 RXD1 1 I/O Input Port 81: I/O port (with programmable open drain). Serial receive data 1. P82 TI2 1 I/O Input Port 82: I/O port (with programmable open drain). Timer input 2: 8-bit timer 2 input pin. P83 TO3 1 I/O Output Port 83: I/O port (with programmable open drain). Timer output 3: 8-bit timer 2, 3 output pin. P84 1 I/O Input Port 84: I/O port (with programmable open drain). Wait: Pin used to request CPU bus wait. CTS0 NMI WAIT Port 60: I/O port. Clock I/O pin in SIO mode of the serial bus interface. Port 61: I/O port (with programmable open drain). Data send channel in SIO mode of the serial bus interface. Data I/O pin in I2C bus mode of the serial bus interface. Port 62: I/O port (with programmable open drain). Data receive channel in SIO mode of the serial bus interface. Clock I/O pin in I2C bus mode of the serial bus interface. Port 63: I/O port (with programmable open drain). Serial send data 0. Port 67: I/O port. Timer output1: 8-bit timer 0 or timer 1 output. Port 76: I/O port (with pull-up resistor). Timer output A: 16-bit timer A output. Port 77: I/O port (with pull-up resistor). Non-maskable interrupt request pin: Interrupt request pin with programmable falling edge or both edges. 93PW20A-6 2004-02-10 TMP93PW20A Table 2.2.1 Name and Function in MCU Mode (3/3) Number of Pins I/O P85 1 I/O P86 XT1 1 I/O Input Port 86: I/O port (Open drain). Low-frequency oscillator connecting pin. P87 XT2 1 I/O Output Port 87: I/O port (Open drain). Low-frequency oscillator connecting pin. P90 to P97 SEG24 to SEG31 8 Output Output Port 90 to port 97: Output port (Open drain). Segment data output pin. PA0 to PA7 SEG32 to SEG39 8 Output Output Port A0 to A7: Output port, large current port (Open drain). LCD segment output pin. SEG0 to SEG23 24 Output LCD segment output. COM0 to COM3 4 Output LCD common output. AVCC 1 Power supply Power supply pin for AD converter. AVSS 1 Power supply GND pin for AD converter (0 V). VREFH 1 Input VREFL 1 Input Pin for reference voltage input to AD converter (L). X1 1 Input Oscillator connecting pin. X2 1 Output RESET 1 Input ALE 1 Output Address latch enable. Can be disabled for reducing noise. CLK 1 Output Clock output: Outputs “external input clock × 1 ÷ 4” clock. Pulled-up during reset. Can be disabled for reducing noise. Pin Names Input Functions Port 85: I/O port (with programmable open drain). Pin for reference voltage input to AD converter (H). Oscillator connecting pin. Reset: Initializes LSI. EA 1 VCC 3 Power supply Power supply pin (All Vcc pins should be connected with the power supply pin). The VCC pin should be connected. VSS 8 Power supply GND pin (0 V) (All Vss pins should be connected with GND (0 V)). TEST1 TEST2 2 Output Input C0, C1, V1 to V3 5 LCD pin TEST1 should be connected with TEST2 pin. Do not connect to any other pins. LCD drive boosting pin. A condenser should be connected between C0 and C1, V1, V2, V3 and GND. Note: All pins that have built-in pull-up resistors can be disconnected from the built-in pull-up resistor by software. 93PW20A-7 2004-02-10 TMP93PW20A (2) Pin function of the TMP93PW20A in PROM mode Pin names and functions are shown in Table 2.2.2. Table 2.2.2 Pin Names Pin Names and Function in PROM Mode Number of Input/Output Pins A7 to A0 8 Input A15 to A8 8 Input A16 1 Input D7 to D0 8 I/O CE 1 OE PGM Functions Pin Names (in MCU mode) P27 to P20 Memory address of program P17 to P10 P67 Memory data of program P07 to P00 Input Chip enable P32 1 Input Output control P30 1 Input Program control P31 VPP 1 Power supply 12.75 V/5 V (Power supply of program) EA VCC 4 Power supply 6.25 V/5 V VCC, AVCC VSS 9 Power supply 0V VSS, AVSS Pin Names Number of Input/Output Pins P60 1 Input RESET 1 Input CLK 1 Input ALE 1 Output X1 1 Input X2 1 Output P66 to P61 6 Input TEST1 TEST2 2 Output Input 88 I/O P37 to P33 P47 to P40 P57 to P50 P77 to P70 P87 to P80 P97 to P90 PA7 to PA0 SEG23 to SEG0 VREFH VREFL C0, C1 COM3 to COM0 V3 to V1 Pin State Fix to low level (Security pin) Fix to low level (PROM mode) Open Self oscillation with resonator Fix to high level TEST1 should be connected with TEST2 pin Do not connect to any other pins Open 93PW20A-8 2004-02-10 TMP93PW20A 3. Operation This section describes the functions and basic operational blocks of the TMP93PW20A. The TMP93PW20A has PROM in place of the mask ROM which is included in the TMP93CS20. The other configuration and functions are the same as the TMP93CS20. Regarding the function of the TMP93PW20A, which is not described herein, see the TMP93CS20. The TMP93PW20A has two operational modes: MCU mode and PROM mode. 3.1 MCU mode (1) Mode setting and function The MCU mode is set by releasing the CLK pin (Pin open). In the MCU mode, the operation is the same as TMP93CS20. (2) Memory map The memory map of TMP93PW20A differs from that of TMP93CS20. The memory map in MCU mode is show in Figure 3.1.1, and the memory map in PROM mode is shown in Figure 3.1.2. 00000H 000000H Internal I/O (160 bytes) 0000A0H Internal RAM (4 Kbytes) 0010A0H Internal PROM (128 Kbytes) FE0000H Internal PROM (128 Kbytes) 1FFFFH FFFF00H FFFFFFH ( Interrupt vector table area (256 bytes) Figure 3.1.1 Memory Map in MCU Mode Figure 3.1.2 93PW20A-9 =Internal area) Memory Map in PROM Mode 2004-02-10 TMP93PW20A (3) Note on setting of the wait controller The TMP93PW20A has a wide memory area compared as the TMP93CS20. For the addressing area of WAITC1, there is a difference between the TMP93PW20A and the TMP93CS20. When bits 1 and 0 < B1C1:0> in the chip select and wait control register 1 (WAITC1) is set to 00, the address area is specified as follows. 3.2 TMP93PW20A TMP93CS20 10A0H to 7FFFH 8A0H to 7FFFH PROM Mode (1) Mode setting and programming PROM mode is set by setting the RESET and CLK pins to the “Low” level. The programming and verification for the internal PROM is achieved by using a general PROM programmer with the adaptor socket. 1. OTP adaptor BM11141: TMP93PW20AF adaptor 2. Setting OTP adaptor Set the switch (SW1) to N side. 3. Setting PROM programmer i) Set PROM type to TC571000D. Size: 1 Mbits (128 K × 8 bits) VPP: 12.75 V tPW: 100 µs Electric signature function: None ii) Transferring the data (Copy) In TMP93PW20AF, PROM is placed on addresses 00000H to 1FFFFH in PROM mode, and addresses FE0000H to FFFFFFH in MCU mode. Therefore data should be transferred to addresses 00000H to 1FFFFH in PROM mode using the object converter (tuconv) or the block transfer mode. (See instruction manual of PROM programmer.) iii) Setting program address Start address: 00000H End address: 4. 1FFFFH Programming Program/verify according to the procedures of PROM programmer. 93PW20A-10 2004-02-10 TMP93PW20A VPP (12.75 V/5 V) VCC AVCC, VCC EA TEST1 TEST2 A16 to A0 P30 P32 P31 P67 P17 to P10 P27 to P20 OE CE PGM P07 to P00 D7 to D0 RESET CLK VCC X1 See “Pin Names and Function in PROM Mode” in Table 2.2.2 for other pin’s states. Use the 10 MHz resonator in case of programming and verification by a general EPROM programmer. P65 to P61 X2 VSS AVSS Figure 3.2.1 * P60 Security Pin Setting in PROM Mode (2) Note on electric signature The electric signature mode (Hereinafter referred to as “signature”) is not supported in the TMP93PW20A. Therefore using signature with PROM programmer applies voltage of 12 ± 0.5 V to pin 9 (A9) of the address, and the device is damaged. Do not use signature. (3) Program mode The TMP93PW20A is provided with all bits set to 1 (OFF). When programming it, write data 0 to necessary bit locations. Applying VPP = 12.5 V, OE = VIH CE = VIL enables writing data. The one-time PROM which is included in the TMP93PW20A can write data in any order. It is possible to write a special address. (4) Adapter socket (BM11141) The BM11141 is an adapter socket to write data to the one-time PROM in the TMP93PW20A using a general PROM programmer. (5) Program storage area in PROM mode The TMP93PW20A has a program area (FE0000H to FFFFFFH) of 128 Kbytes. In PROM mode, addresses 00000H to 1FFFFH correspond to addresses FE0000H to FFFFFFH in MCU mode. 93PW20A-11 2004-02-10 TMP93PW20A (6) How to program with a general PROM programmer The PROM programmer should be equivalent to TC571000D. 1. Set a switch (SW1) of BM11141 to a program side (NOR). (BM11141 is hereinafter referred as an adapter.) (Note 1) 2. Set a MCU to the adapter. (Note 2) 3. Set the adapter to the PROM programmer. (Note 2) 4. Specify TC571000D as a type of the PROM. 5. Set a start address to 00000H and an end address to 1FFFFH to write the PROM. (Note 3) 6. Write the one-time PROM and verify according to operational procedures of the PROM programmer. Note 1: If you write a data to the one-time PROM without setting the switch (SW1) to the program side, a device should be damaged. Note 2: 1 pin marked on the socket of the PROM programmer must be matched to the 1 pin of the adapter. If you set them in reverse, the MCU or the PROM programmer should be damaged. Note 3: When data 0 is written to an address over 1FFFFH, there is a possibility that the data is written to addresses 00000H to 1FFFFH and an original program is corrupted. (7) Programming flow chart The programming mode is set by applying 12.75 V (programming voltage) to the VPP pin when the following pins are set as follows, (VCC: 6.25 V, RESET : “Low” level, CLK: “Low” level). While address and data are fixed and CE pin is set to “L” level, 0.1 ms of “Low” level pulse is applied to PGM pin to program the data. Then the data in the address is verified. If the programmed data is incorrect, another 0.1 ms pulse is applied to PGM pin. This programming procedure is repeated until correct data is read from the address (25 times maximum). Subsequently, all data are programmed in all addresses. The verification for all data is done under the condition of VPP = VCC = 5 V after all data were written. Figure 3.2.2 shows the programming flowchart. 93PW20A-12 2004-02-10 TMP93PW20A High Speed Program Writing. Flowchart Start VCC = 6.25 V ± 0.25 V VPP = 12.75 V ± 0.25 V Address = Start address X=0 Program 0.1 ms pulse X=X+1 X > 25? Yes No Error Verify Address = Address + 1 OK No Last address? Yes VCC = 5 V VPP = 5 V Read all data Error OK Pass Figure 3.2.2 Failure Flowchart 93PW20A-13 2004-02-10 TMP93PW20A (8) Security bit The TMP93PW20A has a security bit. If the security bit is programmed to 0, the content of the PROM can not be read in PROM mode. (Outputs data FFH) (How to program the security bit) The difference from the programming procedures described in section 3.2 (1) are follows. 1. Setting OTP adapter Set the switch (SW1) to S side. 2. Setting PROM programmer i) Transferring the data ii) Setting programming address The security bit is in bit 0 of address 00000H. Set the start address 00000H and the end address 00000H. Set the data FEH at the address 00000H. 93PW20A-14 2004-02-10 TMP93PW20A 4. Electrical Characteristics 4.1 “X” used in an expression shows a frequency for the clock fFPH selected by SYSCR1<SYSCK>. The value of X changes according to whether a clock gear or a low speed oscillator is selected. An example value is calculated for fc, with gear = fc/1 (SYSCR1<SYSCK, GEAR2:0> = 0000). Maximum Rating (TMP93PW20A) Symbol Rating Power supply voltage Parameter VCC −0.5 to 6.5 Input voltage VIN Output current (Per one pin), large current port IOL1 20 Output current (Per one pin) IOL2 2 Output current (Total of large current port) ΣIOL1 80 Output current (Total) ΣIOL 120 Output current (Total) ΣIOH −80 Power dissipation (Ta = 85°C) PD 600 Soldering temperature (10 s) TSOLDER 260 Storage temperature TSTG −65 to150 Operating temperature TOPR −40 to 85 Unit Except EA pin −0.5 to VCC + 0.5 EA pin −0.5 to 14.0 V mA mW °C Note: The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. 4.2 DC Characteristics (1/2) Ta = −40 to 85°C Parameter Power supply voltage AVCC = VCC AVSS = VSS = 0 V AD0 to AD15 Input low voltage Symbol fc = 4 to 20 MHz VCC fs = 30 to fc = 4 to 12.5 MHz 34 kHz VIL VCC ≥ 4.5 V VIL1 VCC < 4.5 V Port VIL1 KEY0 to KEY7, NMI, INT0 to INT4 VIL2 EA VIL3 X1 VIL4 RESET VIL5 AD0 to AD15 Port Input high KEY0 to KEY7, voltage NMI , INT0 to INT4 Condition Min Typ. (Note) Max Unit 5.5 V 4.5 2.7 0.8 0.6 0.3 VCC −0.3 VCC = 2.7 to 5.5 V 0.25 VCC 0.3 0.2 VCC 0.1 VCC VIH VCC ≥ 4.5 V VIH VCC ≥ 4.5 V VIH1 2.2 V 2.0 0.7 VCC VIH2 0.75 VCC VCC = 2.7 to 5.5 V VCC + 0.3 Vcc − 0.3 EA VIH3 X1 VIH4 0.8 VCC RESET VIH5 0.6 VCC Note: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. 93PW20A-15 2004-02-10 TMP93PW20A 4.2 DC Characteristics (2/2) Parameter Symbol Condition Min Typ. (Note 1) Max Unit 0.45 V Output low voltage VOL IOL = 1.6 mA (VCC = 2.7 to 5.5 V) Output low current (PA0 to PA7) IOLA VOL = 1.0 V VOH1 IOH = −400 µA (VCC = 3 V ± 10%) 2.4 VOH2 IOH = −400 µA (VCC = 5 V ± 10%) 4.2 IDAR (Note 2) VEXT = 1.5 V REXT = 1.1 kΩ (VCC = 5 V ± 10% only) −1.0 Input leakage current ILI 0.0 ≤ VIN ≤ VCC 0.02 ±5 Output leakage current ILO 0.2 ≤ VIN ≤ VCC − 0.2 0.05 ±10 Power down voltage (at stop, RAM backup) VSTOP VIL2 = 0.2 VCC, VIH2 = 0.8 VCC Pin capacitance CIO fc = 1 MHz Shumitt width KEYx, NMI , INT0 to INT4, RESET VTH Programmable pull-up resistance RKH Output high voltage Darlington drive current (8 output pins max) (VCC = 5 V ± 10%) 16 (VCC = 3 V ± 10%) 7 V 0.4 10 pF 1.0 V 50 150 VCC = 3 V ± 10% 100 300 32 40 24 30 17 21 4.5 7 NORMAL 14 20 10 14 7 10 VCC = 3 V ± 10% fc = 12.5 MHz (Typ. VCC = 3.0 V) IDLE2 IDLE1 ICC Vcc = 3 V ± 10% fs = 32.768 kHz (Typ. VCC = 3.0 V) at boosting frequency = 1 kHz SLOW RUN IDLE2 IDLE1 2 3 40 55 30 42 20 33 10 24 Ta ≤ 50°C STOP Ta ≤ 70°C Ta ≤ 85°C Note 1: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. Note 2: IDAR is guaranteed for up to eight ports. µA V IDLE1 RUN mA 6.0 VCC = 5 V ± 10% VCC = 5 V ± 10% fc = 20 MHz IDLE2 −3.5 2.0 NORMAL RUN mA kΩ mA mA µA 10 0.2 20 µA 50 Note 3: Segment or common output is not loaded. Note 4: ICC measurement conditions (NORMAL, SLOW): Only CPU is operational; output pins are open and input pins are fixed. (e.g.) Diagram of IDAR REXT IDAR VEXT 93PW20A-16 2004-02-10 TMP93PW20A 4.3 AC Electrical Characteristics (1) VCC = 5 V ± 10% No. Parameter Symbol Variable Min 16 MHz Max 31250 Min 20 MHz Max Min Max Unit 1 Osc. period (= x) tOSC 50 62.5 50 ns 2 CLK width tCLK 2x − 40 85 60 ns 3 A0 to A23 valid → CLK hold tAK 0.5x − 20 11 5 ns 4 CLK valid → A0 to A23 hold tKA 1.5x − 70 24 5 ns 5 A0 to A15 valid → ALE fall tAL 0.5x − 15 16 10 ns 6 ALE fall → A0 to A15 hold tLA 0.5x − 20 11 5 ns 7 ALE high width tLL x − 40 23 10 ns 8 ALE fall → RD / WR fall tLC 0.5x − 25 6 0 ns 9 RD / WR rise → ALE rise tCL ns 0.5x − 20 11 5 10 A0 to A15 valid → RD / WR fall tACL x − 25 38 25 ns 11 A0 to A23 valid → RD / WR fall tACH 1.5x − 50 44 25 ns tCA 0.5x − 25 12 RD / WR rise → A0 to A23 hold 13 A0 to A15 valid → D0 to D15 input 14 A0 to A23 valid → D0 to D15 input 6 0 ns tADL 3.0x − 55 133 95 ns tADH 3.5x − 65 154 110 ns 15 RD fall → D0 to D15 input tRD 2.0x − 60 65 40 ns 16 RD low pulse width tRR 2.0x − 40 85 60 17 RD rise → D0 to D15 hold tHR 0 0 0 ns 18 RD rise → A0 to A15 output tRAE x − 15 48 35 ns 19 WR low pulse width tWW 2.0x − 40 85 60 ns tDW 2.0x − 55 70 45 ns tWD 0.5x − 15 16 10 20 D0 to D15 valid → WR rise 21 WR rise → D0 to D15 hold 22 A0 to A23 valid → WAIT input 23 A0 to A15 valid → WAIT input 24 RD / WR fall → WAIT hold (1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode tAPH 26 A0 to A23 valid → Port hold tAPH2 WR rise → Port valid 129 3.0x − 80 tAWL tCW 25 A0 to A23 valid → Port input 27 3.5x − 90 tAWH 2.0x + 0 108 125 2.5x − 120 2.5x + 50 tCP ns 85 ns 70 ns 5 ns 200 ns 100 36 206 200 ns ns 175 200 ns AC measuring conditions • Output level: High 2.2 V/Low 0.8 V, CL = 50 pF (However, CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , CLK) • Input level: High 2.4 V/Low 0.45 V (AD0 to AD15) High 0.8 × VCC/Low 0.2 × VCC (except AD0 to AD15) 93PW20A-17 2004-02-10 TMP93PW20A (2) VCC = 3 V ± 10% No. Parameter Variable Symbol Min 12.5 MHz Max Max Unit 1 Osc. period (= x) tOSC 80 80 ns 2 CLK width tCLK 2x − 40 120 ns 3 A0 to A23 valid → CLK hold tAK 0.5x − 30 10 ns 4 CLK valid → A0 to A23 hold tKA 1.5x − 80 40 ns 5 A0 to A15 valid → ALE fall tAL 0.5x − 35 5 ns 6 ALE fall → A0 to A15 hold tLA 0.5x − 35 5 ns 7 ALE high width tLL x − 60 20 ns 8 ALE fall → RD / WR fall tLC 0.5x − 35 5 ns 9 RD / WR rise → ALE rise tCL 0.5x − 40 0 ns tACL x − 50 30 ns tACH 1.5x − 50 70 ns tCA 0.5x − 40 0 10 A0 to A15 valid → RD / WR fall 11 A0 to A23 valid → RD / WR fall 12 RD / WR rise → A0 to A23 hold 13 A0 to A15 valid → D0 to D15 input 14 A0 to A23 valid → D0 to D15 input 31250 Min ns tADL 3.0x − 110 130 ns tADH 3.5x − 125 155 ns 15 RD fall → D0 to D15 input tRD 2.0x − 115 45 ns 16 RD low pulse width tRR 2.0x − 40 120 17 RD rise → D0 to D15 hold tHR 0 0 ns 18 RD rise → A0 to A15 output tRAE x − 25 55 ns 19 WR low pulse width tWW 2.0x − 40 120 ns tDW 2.0x − 120 40 ns tWD 0.5x − 40 0 20 D0 to D15 valid → WR rise 21 WR rise → D0 to D15 hold (1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode 22 A0 to A23 valid → WAIT input 23 A0 to A15 valid → WAIT input 24 RD / WR fall → WAIT hold tCW tAPH 26 A0 to A23 valid → Port hold tAPH2 WR rise → Port valid 3.0x − 100 tAWL 25 A0 to A23 valid → Port input 27 3.5x − 130 tAWH 2.0x + 0 ns 150 ns 140 ns 160 2.5x − 120 2.5x + 50 tCP ns ns 80 ns 200 ns 250 200 ns AC measuring conditions • Output level: High 0.7 × VCC/Low 0.3 × VCC, CL = 50 pF • Input level: High 0.9 × VCC/Low 0.1 × VCC 93PW20A-18 2004-02-10 TMP93PW20A (1) Read cycle tOSC X1/XT1 tCLK CLK tAK tKA A0 to A23 tAWH tCW tAWL WAIT tAPH tAPH2 Port input (Note) tADH RD tRR tCA tACH tACL AD0 to AD15 tLC tRD tADL A0 to A15 tAL tRAE tHR D0 to D15 tLA tCL ALE tLL Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93PW20A-19 2004-02-10 TMP93PW20A (2) Write cycle X1/XT1 CLK A0 to A23 WAIT Port output (Note) tWW tCP WR , HWR tDW AD0 to AD15 A0 to A15 tWD D0 to D15 ALE Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93PW20A-20 2004-02-10 TMP93PW20A 4.4 Serial Channel Timing (1) I/O interface mode 1. SCLK input mode Parameter Variable Symbol 32.768 MHz (Note) 12.5 MHz Min Max Min Max Min Max 20 MHz Min Unit Max SCLK cycle tSCY 16x 488 µs 1.28 0.8 µs Output data → SCLK rising edge or falling edge* tOSS tSCY/2 − 5x − 50 91.5 µs 190 100 ns SCLK rising edge or falling edge* → Output data hold tOHS 5x − 100 152 µs 300 150 ns SCLK rising edge or falling edge* → Input data hold tHSR 0 0 0 0 ns SCLK rising edge or falling edge* → Effective data input tSRD tSCY − 5x − 100 336 µs 780 450 ns Note: System clock is fs, or input clock to prescaler is divisor clock of fs. *) The rising edge is used in SCLK Rising mode. The falling edge is used in SCLK Falling mode. 2. SCLK output mode Parameter 32.768 kHz (Note) Variable Symbol Min Max 8192x Min 12.5 MHz Max Min Max 20 MHz Min Unit Max SCLK cycle (Programmable) tSCY 16x 488 µs 250 ms 1.28 655.36 0.8 409.6 µs Output data → SCLK rising edge tOSS tSCY − 2x − 150 427 µs 970 550 ns SCLK rising edge → Output data hold tOHS 2x − 80 60 µs 80 20 ns SCLK rising edge → Input data hold tHSR 0 0 0 0 ns SCLK rising edge t → Effective data hold SRD tSCY − 2x − 150 428 µs 970 550 ns Note: System clock is fs, or input clock to prescaler is divisor clock of fs. SCLK tSCY SCLK output mode (Only rising edge is used) or SCLK input mode (SCLK rising edge mode) SCLK SCLK input mode (SCLK falling edge mode) tOSS Output data TXD tOHS 0 1 2 tSRD Input data RXD 3 tHSR 0 Valid 1 Valid 2 Valid 3 Valid (2) UART mode (SCLK0 and SCLK1 external input) Parameter Variable Symbol Min 32.768 kHz (Note) Max Min Max 12.5 MHz Min Max 20 MHz Min Unit Max SCLK cycle tSCY 4x + 20 122 µs 340 220 ns SCLK low level pulse width tSCYL 2x + 5 6 µs 165 105 ns SCLK high level pulse width tSCYH 2x + 5 6 µs 165 105 ns Note: System clock is fs, or input clock to prescaler is divisor clock of fs. 93PW20A-21 2004-02-10 TMP93PW20A 4.5 AD Converter Characteristics (VSS = 0 V, AVCC = VCC, AVSS = VSS, Ta = −40 to 85°C) AVCC = VCC, AVSS = VSS Parameter Analog reference voltage (+) Symbol VREFH Analog reference voltage (−) VREFL Analog input voltage range VAIN Analog current for analog reference voltage <VREFON> = 1 <VREFON> = 0 Condition Min Typ. Max VCC = 5 V ± 10% VCC − 1.5 V VCC VCC VCC = 3 V ± 10% VCC − 0.2 V VCC VCC VCC = 5 V ± 10% VSS VCC = 3 V ± 10% VSS IREF = 3 V ± 10% V (VREFL = 0 V) CC VCC = 2.7~5.5 V Error (Not including quantizing errors) V VREFL VCC = 5 V ± 10% − Unit VREFH 1.6 2.0 1.0 1.5 0.02 5.0 VCC = 5 V ± 10% ±1.0 ±3.0 VCC = 3 V ± 10% ±1.0 ±5.0 mA µA LSB Note 1: 1LSB = (VREFH − VREFL)/210 [V] Note 2: Minimum operation frequency. The operation of the AD converter is guaranteed only when fc (High-frequency oscillator) is used. (It is not guaranteed when fs is used.) Additionally, it is guaranteed when the clock frequency which is selected by the clock gear is 4 MHz or more. Note 3: The value ICC includes the current which flows through the AVCC pin. 4.6 LCD Driver Characteristics Charge and Pump Characteristics Symbol Min Typ. Reference input voltage VL1 0.9 Output voltage V2 pin VL2 2 × VL1 V3 pin VL3 3 × VL1 Max Unit 1.83 V External capacity C0, C1 CPMP 0.1 1.0 V1 pin CVL1 0.1 1.0 V2 pin CVL2 0.1 1.0 V3 pin CVL3 0.1 1.0 µF Note: Output voltage and External capacity are not loaded. 93PW20A-22 2004-02-10 TMP93PW20A 4.7 Event Counter (TI0, TI2, TI4, TI6, TI8 to TIB) Parameter 4.8 Symbol Variable Min Max 12.5 MHz Min Max 20 MHz Min Max Unit Clock cycle tVCK 8X + 100 740 500 ns Low level clock pulse width tVCKL 4X + 40 360 240 ns High level clock pulse width tVCKH 4X + 40 360 240 ns Interrupt and Capture (1) NMI , INT0 to INT4 interrupts and INTKEY interrupt Parameter Symbol Variable Min Max 12.5 MHz Min Max 20 MHz Min Max Unit Low level pulse width tINTAL 4X 320 200 ns High level pulse width tINTAH 4X 320 200 ns (2) INT7 to INTB interrupts and capture Parameter 4.9 Symbol Variable Min Max 12.5 MHz Min Max 20 MHz Min Max Unit Low level pulse width tINTBL 4X + 100 420 300 ns High level pulse width tINTBH 4X + 100 420 300 ns SCOUT Pin AC Characteristics Parameter Symbol High level pulse width VCC = 5 V ± 10% High level pulse width VCC = 3 V ± 10% Low level pulse width Min Max 12.5 MHz Min Max 20 MHz Min 0.5X − 10 30 15 0.5X − 20 20 − 0.5X − 10 30 15 0.5X − 20 20 − Max − tSCL VCC = 3 V ± 10% Unit ns tSCH Low level pulse width VCC = 5 V ± 10% Variable ns − Measurement condition • Output level: High 2.2 V/Low 0.8 V, CL = 10 pF tSCH tSCL SCOUT 93PW20A-23 2004-02-10 TMP93PW20A 4.10 Timing Chart for Serial Bus Interface (1) I2C bus mode Parameter Variable Symbol START instruction → SDA falling edge Min Typ. Unit Max tGSTA 3X s Start condition hold time tHD:STA 2nX s SCL low level pulse width tLOW 2nX s SCL high level pulse width tHIGH 2nX + 12X s Data hold time (Input) tHD:IDAT 0 ns Data setup time (Input) tSU:IDAT 250 ns Data hold time (Output) tHD:ODAT 7X 11X s 2nX − tHD:ODAT Data valid → SCL rising edge tODAT STOP instruction → SDA falling edge tFSDA 3X SDA falling edge → SCL rising edge tFDRC 2nX s tSU:STO 2nX + 16X s Stop condition hold time s s Note: SBICR1<SCK2:0> sets n. Start instruction Stop instruction SDA tGSTA tLOW tODAT tHD:ODAT SCL tHD:STA tHD:IDAT tHIGH tSU:IDAT 93PW20A-24 tFSDA tFDRC tSU:STO 2004-02-10 TMP93PW20A (2) Clock-synchronous 8-bit SIO mode (Serial bus interface) clock 1. SCK input mode Parameter Variable Symbol Min Unit Max SCK cycle tSCY2 25X s SCK falling edge → Output data hold tOHS2 6X s Output data → SCK rising edge tOSS2 tSCY2 − 6X s SCK rising edge → Input data hold tHSR2 6X ns Input data → SCK rising edge tISS2 0 ns 2. SCK output mode Parameter Variable Symbol Min Max 211X Unit SCK cycle tSCY2 25X SCK falling edge → Output data hold tOHS2 2X Output data → SCK rising edge tOSS2 tSCY2 − 2X s SCK rising edge → Input data hold tHSR2 2X s Input data → SCK rising edge tISS2 0 ns tSCY2 s s tOSS2 SCK (Input/output mode) SO (Output mode) SI (Input mode) tOHS2 tISS2 tHSR2 93PW20A-25 2004-02-10 TMP93PW20A 4.11 Operation in PROM Mode (1) DC and AC characteristics in read operation Ta = 25 ± 5°C VCC = 5 V ± 10% Symbol Condition Min Max VPP read voltage Parameter VPP − 4.5 5.5 Unit Input high voltage (A0 to A16, CE , OE , PGM ) VIH1 − 2.2 VCC + 0.3 Input low voltage (A0 to A16, CE , OE , PGM ) VIL1 − −0.3 0.8 Address to output delay tACC CL = 50 PF − 2.25 TCYC + α V ns TCYC = 400 ns (10 MHz clock) α = 200 ns A0 to A16 CE OE PGM D0 to D7 tACC Data output 93PW20A-26 2004-02-10 TMP93PW20A (2) DC and AC characteristics in programming Ta = 25 ± 5°C VCC = 6.25 V ± 0.25 V Symbol Condition Min Typ. Max Programming supply voltage Parameter VPP − 12.50 12.75 13.00 Input high voltage (D0 to D7, A0 to A16, CE , OE , PGM ) VIH − 2.6 VCC + 0.3 Input low voltage (D0 to D7, A0 to A16, CE , OE , PGM ) VIL − −0.3 0.8 VCC supply current ICC fc = 10 MHz − 50 VPP supply current IPP VPP = 13.00 V − 50 PGM program pulse width tPW CL = 50 PF 0.095 0.1 0.105 Unit V mA ms A0 to A16 CE OE D0 to D7 Unknown Data in stable Data out valid tPW PGM VPP Note 1: The power supply of VPP (12.75 V) must be turned on at the same time or the later time for a power supply of VCC and must be turned off at the same time or early time for a power supply of VCC. Note 2: The device suffers a damage taking out and putting in on the condition of VPP = 12.75 V. Note 3: The maximum spec of VPP pin is 14.0 V. Be carefull a overshoot at the programming. 93PW20A-27 2004-02-10 TMP93PW20A 5. Port Section Equivalent Circuit Diagram • Reading the circuit diagram Basically, the gate symbols written are the same as those used for the standard CMOS logic IC [74HCXX] series. The dedicated signal is described below. Stop: This signal becomes active 1 when the HALT mode setting register is set to the Stop mode and the CPU executes the HALT instruction. When the drive enable bit [DRVE] is set to 1, however, Stop remains at 0. • The input protection resistance ranges from several tens of ohms to several hundreds of ohms. ■ P0 (AD0 to AD7), P1 (AD8 to AD15, A8 to A15), and P67 (TO1) VCC Output data P-ch Output enable STOP N-ch I/O Input data Input enable ■ P30 ( RD ) and P31 ( WR ) VCC Output data Output STOP 93PW20A-28 2004-02-10 TMP93PW20A ■ P2 (A16 to A23, A0 to A7), P32 (HWR), P72 (TO8), P73 (SCOUT), and P76 (TOA) VCC Output data VCC Output enable STOP Programmable pull-up resistance I/O Input data Input enable ■ P70 (TI8/INT8), P71 (TI9/INT9), P74 (TIA/INTA), and P75 (TIB/INTB) VCC Output data VCC Output enable STOP I/O Input data INT8 to INTB TI8 to TIB ■ Programmable pull-up resistance Input enable P33 to P36 (INT0 to INT3) VCC Output data VCC Output enable STOP I/O Input data INT0 to INT3 Programmable pull-up resistance Input enable 93PW20A-29 2004-02-10 TMP93PW20A ■ P4 (TIx, TOx, KEYx) and P77 ( NMI ) VCC Output data VCC Output enable STOP Programmable pull-up resistance I/O Input data Input enable TI4, TI6 NMI , KEY0 to KEY7 ■ P37 (INT4/ ADTRG ) VCC Output data VCC Output enable STOP Programmable pull-up resistance I/O Input data Input enable AD trigger STOP ■ INT4 P5 (AN0 to AN7) Analog input channel select Input Analog data Input data Input enable 93PW20A-30 2004-02-10 TMP93PW20A ■ P63 (TXD0), P80 (TXD1), P83 (TO3), and P85 VCC Output data Open-drain output enable Output enable STOP I/O Input data Input enable ■ P60 (SCK), P64 (RXD0), P65 (SCLK0), and P66 (TI0/INT7) VCC Output P-ch Output enable STOP N-ch I/O Input data SCK RXD0 SCLK0 TI0 INT7 Input enable 93PW20A-31 2004-02-10 TMP93PW20A ■ P61 (SO/SDA), P62 (SI/SCL), P81 (RXD1), P82 (TI2), and P84 ( WAIT ) VCC Output data Open-drain output enable Output enable STOP I/O Input data SDA SI SCL RXD1 TI2 Input enable WAIT ■ P86 (XT1) and P87 (XT2) Input enable Clock Input data Output data Output enable Oscillator P87 (XT2) Input enable Input data P86 (XT1) Output data Output enable STOP Low-frequency oscillation enable 93PW20A-32 2004-02-10 TMP93PW20A ■ P90 to P97 (SEG24 to SEG31), PA0 to PA7 (SEG32 to SEG39) Segment output Output data Output Output enable STOP ■ CLK VCC Output enable VCC Internal CLK P-ch Output STOP N-ch Internal reset Test circuit ■ VREFH and VREFL VREFON P-ch VREFH String resistance VREFL 93PW20A-33 2004-02-10 TMP93PW20A ■ EA Input data ■ Input ALE VCC Internal ALE P-ch Output Output enable N-ch ■ RESET Input Reset WDTOUT Reset enable ■ Schmitt X1 and X2 Clock Oscillator X2 High-frequency o cillation enable P-ch N-ch X1 93PW20A-34 2004-02-10 TMP93PW20A 6. Package Dimensions P-LQFP144-1616-0.40 Unit: mm 93PW20A-35 2004-02-10 TMP93PW20A 93PW20A-36 2004-02-10