TOSHIBA TMP93CM40

TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L Series
TMP93CM40
Semiconductor Company
Preface
Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Points of Note and Restrictions”.
Especially, take care below cautions.
**CAUTION**
How to release the HALT mode
Usually, interrupts can release all halts status. However, the interrupts ( NMI ,
INT0), which can release the HALT mode may not be able to do so if they are
input during the period CPU is shifting to the HALT mode (for about 3 clocks of
fFPH) with IDLE1 or STOP mode (IDLE2, RUN is not applicable to this case). (In
this case, an interrupt request is kept on hold internally.)
If another interrupt is generated after it has shifted to HALT mode completely,
halt status can be released without difficultly. The priority of this interrupt is
compare with that of the interrupt kept on hold internally, and the interrupt with
higher priority is handled first followed by the other interrupt.
TMP93CM40
Low Voltage/Low Power
CMOS 16-Bit Microcontroller
TMP93CM40F
1.
Outline and Device Characteristics
The TMP93CM40 is high-speed, advanced 16-bit microcontroller developed for controlling
medium to large-scale equipment. They enable low voltage and low-power-consumption operation.
The TMP93CM40 is housed in 100-pin flat packages.
The device characteristics are as follows:
(1) Original 16-bit CPU (900/L CPU)
x
TLCS-90 instruction mnemonic upward compatible
x
16-Mbyte linear address space
x
General-purpose registers, register bank system
x
16-bit multiplication, 16-bit division, bit transfer and bit manipulation instructions
x
Micro DMA: 4 channels (1.6 Ps per 2 bytes at 20 MHz)
(2) Minimum instruction execution time: 200 ns at 20 MHz
(3) Internal RAM: 2 Kbytes
Internal ROM: 32 Kbytes
(4) External memory expansion
x
Can be expanded up to 16 Mbytes (for both programs and data).
x
AM8/ AM16 pin (select the external data bus width)
x
Can mix 8- and 16-bit external data buses. (Dynamic bus sizing)
(5) 8-bit timer:
2 channels
(6) 8-bit PWM timer:
2 channels
(7) 16-bit timer:
2 channels
(8) 4-bit pattern generator: 2 channels
(9) Serial interface:
2 channels
(10) 10-bit AD converter:
8 channels
030619EBP1
xThe information contained herein is subject to change without notice.
xThe information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of TOSHIBA or others.
xTOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
xThe TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made
at the customer’s own risk.
xThe products described in this document are subject to the foreign exchange and foreign trade laws.
xTOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law
and regulations.
xFor a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality
and Reliability Assurance/Handling Precautions.
93CM40-1
2004-02-10
TMP93CM40
(11) Watchdog timer
(12) Chip select and wait controller: 3 blocks
(13) Interrupt functions: 29
x
9 CPU interrupts (SWI instruction, and illegal instruction)
x
14 internal interrupts
x
6 external interrupts
7-level priority can be set.
(14) I/O ports: 79
(15) Standby function: 4 HALT modes (RUN, IDLE2, IDLE1, STOP)
(16) Clock gear function
x
Dual clock operation
x
Clock gear: High-frequency clock can be changed from fc to fc/16.
(17) Wide range of operating voltage
x
Vcc = 2.7 to 5.5 V
(18) Package
Type No.
Package
TMP93CM40F
P-QFP100-1414-0.50
93CM40-2
2004-02-10
TMP93CM40
PA0 to PA6
PA7 (SCOUT)
P50 to P57
(AN0 to AN7)
AVCC
AVSS
VREFH
VREFL
900/L CPU
10-bit
8-channel
AD
Converter
(TXD0) P90
(RXD0) P91
(SCLK0/ CTS0 ) P92
Serial I/O
(channel 0)
(TXD1) P93
(RXD1) P94
(SCLK1) P95
Serial I/O
(channel 1)
(PG 00) P60
(PG 01) P61
(PG 02) P62
(PG 03) P63
(PG 10) P64
(PG 11) P65
(PG 12) P66
(PG 13) P67
Pattern
generator
(channel 1)
8-bit timer
(Timer 0)
(TO1) P71
8-bit timer
(Timer 1)
(TO3) P73
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
W A
B C
D E
H L
IX
IY
IZ
SP
32 bits
F
SR
Highfrequency
OSC
2-Kbyte RAM
Lowfrequency
OSC
EA
RESET
ALE
TEST1
TEST2
Interrupt
controller
P87 (INT0)
Watchdog
timer
WDTOUT
Port 0
P00 to P07
(AD0 to AD7)
Port 1
P10 to P17
(AD8 to AD15/A8 to A15)
Port 2
P20 to P27
(A0 to A7/A16 to A23)
P30 ( RD )
P32 ( HWR )
Port 3
32-Kbyte ROM
(INT6/TI6) P84
(INT7/TI7) P85
(TO6) P86
16-bit timer
(Timer 5)
NMI
P31 ( WR )
8-bit PWM
(Timer 3)
16-bit timer
(Timer 4)
XT1
XT2
AM8/ AM16
8-bit PWM
(Timer 2)
(INT4/TI4) P80
(INT5/TI5) P81
(TO4) P82
(TO5) P83
X1
X2
CLK
P C
Pattern
generator
(channel 0)
(TI0) P70
(TO2) P72
VCC [3]
VSS [3]
Port A
P33 ( WAIT )
P34 ( BUSRQ )
P35 ( BUSAK )
P36 ( R / W )
P37 ( RAS )
CS/WAIT
controller
(3 block)
P40 ( CS0 / CAS0 )
P41 ( CS1 / CAS1 )
P42 ( CS2 / CAS2 )
Figure 1.1 TMP93CM40 Block Diagram
93CM40-3
2004-02-10
TMP93CM40
2.
Pin Assignment and Functions
The assignment of input and output pins for the TMP93CM40, their names and functions are
described below.
2.1
Pin Assignment
Figure 2.1.1 shows pin assignment of the TMP93CM40F.
ż
Timer
ADC
Clock, Mode
SIO
TMP93CM40
Programmable
Pull Pull
down up
88 P65/PG11
ż
P66/PG12
89
87 P64/PG10
ż
P67/PG13
90
86 P63/PG03
ż
VSS
91
85 P62/PG02
ż
P50/AN0
92
84 P61/PG01
ż
P51/AN1
93
83 P60/PG00
P52/AN2
94
82 P42/ CS2 / CAS2
P53/AN3
95
81 P41/ CS1 / CAS1
ż
P54/AN4
96
80 P40/ CS0 / CAS0
ż
P55/AN5
97
79 P37/ RAS
ż
P56/AN6
98
78 P36/ R / W
ż
P57/AN7
99
77 P35/ BUSAK
ż
VREFH
100
76 P34/ BUSRQ
ż
VREFL
AVSS
AVCC
1
2
3
75 P33/ WAIT
ż
74 P32/ HWR
ż
NMI
72 P30/ RD
P70/TI0
P71/TO1
P72/TO2
P73/TO3
P80/INT4/TI4
P81/INT5/TI5
5
6
7
8
9
10
ż
ż
ż
ż
ż
ż
ż
ż
P82/TO4
P83/TO5
P84/INT6/TI6
P85/INT7/TI7
P86/TO6
P87/INT0
P90/TXD0
P91/RXD0
11
12
13
14
15
16
17
18
71
70
69
68
67
66
65
64
63
ż
P92/ CTS0 /SCLK0 19
ż
ż
ż
P93/TXD1
P94/RXD1
P95/SCLK1
Top view
QFP100
23
CLK
24
P27/A7/A23
P26/A6/A22
P25/A5/A21
P24/A4/A20
P23/A3/A19
P22/A2/A18
P21/A1/A17
P20/A0/A16
VCC
ż
ż
ż
ż
ż
ż
ż
ż
62 VSS
61 WDTOUT
60
59
58
57
56
55
54
20
21
22
AM8/ AM16
ż
ż
73 P31/ WR
4
ż
ż
ż
ż
ż
ż
Stepping
motor control
ż
TMP93CM40
Pin
No.
Pin
No.
Memory interface
Programmable
Pull Pull
up down
P17/AD15/A15
P16/AD14/A14
P15/AD13/A13
P14/AD12/A12
P13/AD11/A11
P12/AD10/A10
P11/AD9/A9
VCC
25
53 P10/AD8/A8
52 P07/AD7
51 P06/AD6
VSS
26
50 P05/AD5
X1
27
49 P04/AD4
X2
28
48 P03/AD3
EA
29
47 P02/AD2
RESET
30
46 P01/AD1
P96/XT1
31
45 P00/AD0
P97/XT2
32
44 VCC
TEST1
33
43 ALE
TEST2
34
42 PA7/SCOUT
PA0
35
41 PA6
PA1
36
40 PA5
PA2
37
39 PA4
38 PA3
Figure 2.1.1 Pin Assignment (100-pin QFP)
93CM40-4
2004-02-10
TMP93CM40
2.2
Pin Names and Functions
The names of the input/output pins and their functions are described below.
Table 2.2.1 to Table 2.2.4 show pin names and functions.
Table 2.2.1 Pin Names and Functions (1/4)
Pin Names
Number
of Pins
I/O
Functions
P00 to P07
AD0 to AD7
8
I/O
3-state
Port 0: I/O port that allows I/O to be selected at the bit level.
Address and data (lower): Bits 0 to 7 for address and data bus.
P10 to P17
AD8 to AD15
A8 to A15
8
I/O
3-state
Output
Port 1: I/O port that allows I/O to be selected at the bit level.
Address and data (upper): Bits 8 to 15 for address and data bus.
Address: Bits 8 to 15 for address bus.
P20 to P27
8
I/O
Output
Output
Port 2: I/O port that allows to be selected at the bit level
(with pull-down resistor).
Address: Bits 0 to 7 for address bus.
Address: Bits 16 to 23 for address bus.
1
Output
Output
Port 30: Output port.
Read: Strobe signal for reading external memory.
1
Output
Output
Port 31: Output port.
Write: Strobe signal for writing data on pins AD0 to AD7.
1
I/O
Output
Port 32: I/O port (with pull-up resistor).
High write: Strobe signal for writing data on pins AD8 to AD15.
1
I/O
Input
Port 33: I/O port (with pull-up resistor).
Wait: Pin used to request CPU bus wait.
1
I/O
Input
Port 34: I/O port (with pull-up resistor).
Bus request: Signal used to request bus release.
1
I/O
Output
Port 35: I/O port (with pull-up resistor).
Bus acknowledge: Signal used to acknowledge bus release.
P36
R/ W
1
I/O
Output
Port 36: I/O port (with pull-up resistor).
Read/write: 1 represents read or dummy cycle; 0 represents write cycle.
P37
1
I/O
Output
Port 37: I/O port (with pull-up resistor).
Row address strobe: Outputs RAS strobe for DRAM.
1
I/O
Output
Output
Port 40: I/O port (with pull-up resistor).
Chip select 0: Outputs 0 when address is within specified address area.
Column address strobe 0: Outputs CAS strobe for DRAM when address is
within specified address area.
A0 to A7
A16 to A23
P30
RD
P31
WR
P32
HWR
P33
WAIT
P34
BUSRQ
P35
BUSAK
RAS
P40
CS0
CAS0
Note:
This device’s built-in memory or built-in I/O cannot be accessed by an external DMA controller,
using the BUSRQ and BUSAK signals.
93CM40-5
2004-02-10
TMP93CM40
Table 2.2.2 Pin Names and Functions (2/4)
Pin Names
P41
Number
of Pins
I/O
Output
Output
Port 41: I/O port (with pull-up resistor).
Chip select 1: Outputs 0 if address is within specified address area.
Column address strobe 1: Outputs CAS strobe for DRAM if address is within
specified address area.
1
I/O
Output
Output
Port 42: I/O port (with pull-down resistor).
Chip select 2: Outputs 0 if address is within specified address area.
Column address strobe 2: Outputs CAS strobe for DRAM if address is within
specified address area.
8
Input
Input
CAS1
CS2
CAS2
P50 to P57
AN0 to AN7
Functions
1
CS1 P42
I/O
Port 5: Pin used to input port.
Analog input: Pin used to input to AD converter.
VREFH
1
Input
Pin for reference voltage input to AD converter. (H)
VREFL
1
Input
Pin for reference voltage input to AD converter. (L)
P60 to P63
4
I/O
Output
PG00 to PG03
P64 to P67
4
I/O
Output
PG10 to PG13
Port 60 to 63: I/O ports that allow selection of I/O on a bit basis
(with pull-up resistor).
Pattern generator ports: 00 to 03.
Port 64 to 67: I/O ports that allow selection of I/O on a bit basis
(with pull-up resistor).
Pattern generator ports: 10 to 13.
P70
TI0
1
I/O
Input
Port 70: I/O port (with pull-up resistor).
Timer input 0: Timer 0 input.
P71
TO1
1
I/O
Output
Port 71: I/O port (with pull-up resistor).
Timer output 1: Timer 0 or 1 output.
P72
TO2
1
I/O
Output
Port 72: I/O port (with pull-up resistor).
PWM output 2: 8-bit PWM timer 2 output.
P73
TO3
1
I/O
Output
Port 73: I/O port (with pull-up resistor).
PWM output 3: 8-bit PWM timer 3 output.
P80
TI4
INT4
1
I/O
Input
Input
Port 80: I/O port (with pull-up resistor).
Timer input 4: Timer 4 count/capture trigger signal input.
Interrupt request pin 4: Interrupt request pin with programmable rising/falling
edge.
P81
TI5
INT5
1
I/O
Input
Input
Port 81: I/O port (with pull-up resistor).
Timer input 5: Timer 4 count/capture trigger signal input.
Interrupt request pin 5: Interrupt request pin with rising edge.
P82
TO4
1
I/O
Output
Port 82: I/O port (with pull-up resistor).
Timer output 4: Timer 4 output pin.
P83
TO5
1
I/O
Output
Port 83: I/O port (with pull-up resistor).
Timer output 5: Timer 4 output pin.
93CM40-6
2004-02-10
TMP93CM40
Table 2.2.3 Pin Names and Functions (3/4)
Pin Names
Number
of Pins
I/O
Functions
P84
TI6
INT6
1
I/O
Input
Input
Port 84: I/O port (with pull-up resistor).
Timer input 6: Timer 5 count/capture trigger signal input.
Interrupt request pin 6: Interrupt request pin with programmable rising/falling
edge.
P85
TI7
INT7
1
I/O
Input
Input
Port 85: I/O port (with pull-up resistor).
Timer input 7: Timer 5 count/capture trigger signal input.
Interrupt request pin 7: Interrupt request pin with rising edge.
P86
TO6
1
I/O
Output
P87
INT0
1
I/O
Input
P90
TXD0
1
I/O
Output
Port 90: I/O port (with pull-up resistor).
Serial send data 0.
P91
RXD0
1
I/O
Input
Port 91: I/O port (with pull-up resistor).
Serial receive data 0.
P92
1
I/O
Input
I/O
Port 92: I/O port (with pull-up resistor).
Serial data send enable 0. (Clear to send)
Serial Clock I/O 0.
P93
TXD1
1
I/O
Output
Port 93: I/O port (with pull-up resistor).
Serial send data 1.
P94
RXD1
1
I/O
Input
Port 94: I/O port (with pull-up resistor).
Serial receive data 1.
P95
SCLK1
1
I/O
I/O
Port 95: I/O port (with pull-up resistor).
Serial clock I/O 1.
CTS0 SCLK0
Port 86: I/O port (with pull-up resistor).
Timer output 6: Timer 5 output pin.
Port 87: I/O port (with pull-up resistor).
Interrupt request pin 0: Interrupt request pin with programmable level/rising
edge.
PA0 to PA6
7
I/O
PA7
SCOUT
1
I/O
Output
Port A7: I/O port.
System clock output: outputs fFPH or fSYS clock.
Port A0 to A6: I/O port.
WDTOUT 1
Output
Watchdog timer output pin.
NMI
1
Input
CLK
1
Output
EA
1
Input
Non-maskable interrupt request pin: Interrupt request pin with programmable
falling edge or both edges.
Clock output: Outputs [fSYS y 2] clock.
Pulled-up during reset.
Can be disabled for reducing noise.
External access: The VCC pin should be connected.
93CM40-7
2004-02-10
TMP93CM40
Table 2.2.4 Pin Names and Functions (4/4)
Pin Names
Number
of Pins
I/O
Functions
AM8/ AM16
1
Input
ALE
1
Output
Address mode: Selects external data bus width.
The VCC pin should be connected. The data bus width for
external access is set by the chip select/wait control register,
port 1 control register.
Address latch enable.
Can be disabled for reducing noise.
RESET
1
Input
X1/X2
2
Input/Output
Reset: Initializes TMP93CM40. (with pull-up resistor)
High frequency oscillator connecting pin.
P96
XT1
1
I/O
Input
Port 96: I/O port. (Open-drain output)
Low frequency oscillator connecting pin.
P97
XT2
1
I/O
Output
Port 97: I/O port. (Open-drain output)
Low-frequency oscillator connecting pin.
TEST1/TEST2
2
Output
/Input
TEST1 should be connected with TEST2 pin.
Do not connect to any other pins.
VCC
3
Power supply pin. (All VCC pins should be connected with the power supply
pin.)
VSS
3
GND pin (0 V). (All VSS pins should be connected with GND (0 V).)
AVCC
1
Power supply pin for AD converter.
AVSS
1
GND pin for AD converter (0 V).
Note:
All pins that have built-in pull-up/pull-down resistors (other than the RESET pin) can be
disconnected from the built-in pull-up/pull-down resistor by software.
93CM40-8
2004-02-10
TMP93CM40
3.
Operation
This section describes the functions and basic operation of all blocks of the TMP93CM40 devices.
3.1
CPU
The TMP93CM40 has a built-in high performance 16-bit CPU (900/L CPU). (For a
description of this CPU’s operation, see the sub section TLCS-900/L CPU in the previous
section.
3.2
Memory Map
Figure 3.2.1 is a memory map of the TMP93CM40.
000000H
000080H
000100H
000880H
Internal I/O
(128 Bytes)
256-byte direct
area (n)
Internal RAM
(2 KBytes)
64-Kbyte area
(nn)
External memory
008000H
008100H
Interrupt vector table area
(64 entries u 4 bytes)
32-Kbyte internal ROM
010000H
16-Mbyte area
(R)
(R)
(R )
(R R8/16)
(R d8/16)
(nnn)
External memory
FFFF00H
Reserved (256 bytes)
FFFFFFH
(
Internal area)
Note: The 256-byte area from FFFF00H to FFFFFFH cannot be used.
Figure 3.2.1 Memory Map
93CM40-9
2004-02-10
TMP93CM40
4.
4.1
Electrical Characteristics
“X” used in an expression shows a frequency for the clock fFPH selected by
SYSCR1<SYSCK>. The value of “X” changes according to whether a clock
gear or a low speed oscillator is selected. An example value is calculated
for fc, with gear 1/fc (SYSCR1<SYSCK, GEAR2:0> “0000”)
Maximum Ratings
(TMP93CM40F)
Parameter
Symbol
Rating
Unit
Power supply voltage
VCC
0.5 to 6.5
V
Input voltage
VIN
0.5 to VCC 0.5
V
Output current (total)
6IOL
120
mA
Output current (total)
6IOH
80
mA
mW
Power dissipation (Ta
PD
600
Soldering temperature (10 s)
85°C)
TSOLDER
260
°C
Storage temperature
TSTG
65 to 150
°C
Operating temperature
TOPR
40 to 85
°C
Note: The maximum ratings are rated values which must not be exceeded during
operation, even for an instant. Any one of the ratings must not be exceeded.
If any maximum rating is exceeded, a device may break down or its
performance may be degraded, causing it to catch fire or explode resulting
in injury to the user. Thus, when designing products which include this
device, ensure that no maximum rating value will ever be exceeded.
93CM40-10
2004-02-10
TMP93CM40
4.2
DC Characteristics (1/2)
Parameter
Input high voltage
Input low voltage
Power supply voltage
AVCC VCC
AVSS VSS 0 V
Symbol
VCC
AD0 to AD15
VIL
Port 2 to port A
(except P87)
VIL1
Condition
fc
fs
4 to 16 MHz
30 to 34 kHz
(Ta 40 to 85°C)
fc
fs
4 to 20 MHz
30 to 34 kHz
(Ta 20 to 70°C)
fc
fs
4 to 10 MHz
30 to 34 kHz
(Ta 40 to 85°C)
Min
Typ.
(Note 1)
Max
Unit
5.5
V
4.5
2.7
(Note 2)
VCC t 4.5 V
0.8
VCC 4.5 V
0.6
0.3
0.3 VCC
RESET , NMI , INT0
VIL2
EA , AM8/ AM16
VIL3
0.3
X1, Port 5
VIL4
0.2 VCC
AD0 to AD15
VIH
Port 2 to port A
(except P87)
VIH1
RESET , NMI , INT0
VIH2
EA , AM8/ AM16
VIH3
X1
VIH4
Output low voltage
VOL
VOH1
Output high voltage
VOH2
Note 1: Typical values are for Ta
VCC
0.25 VCC
2.7 to 5.5 V
VCC t 4.5 V
2.2
VCC 4.5 V
2.0
0.7 VCC
VCC
2.7 to 5.5 V
V
VCC 0.3
0.75 VCC
VCC 0.3
0.8 VCC
IOL
1.6 mA
(VCC 2.7 to 5.5 V)
IOH
400 PA
(VCC 3 V r 10%)
2.4
IOH
400 PA
(VCC 5 V r 10%)
4.2
25°C and VCC
0.45
V
5 V unless otherwise noted.
Note 2: The operation of the AD converter is guaranteed at 5 V r 10%.
93CM40-11
2004-02-10
TMP93CM40
4.2
DC Characteristics (2/2)
Typ.
(Note 1)
Parameter
Symbol
Condition
Min
Darlington drive current
(8 output pins max)
IDAR
(Note 2)
VEXT 1.5 V
REXT 1.1 k:
(only when
VCC 5 V r 10%)
1.0
Input leakage current
ILI
0.0 d VIN d VCC
0.02
r5
Output leakage current
ILO
0.2 d VIN d VCC 0.2
0.05
r10
Power down voltage
(at STOP, RAM back-up)
VSTOP
VIL2
VIL2
0.2 VCC,
0.8 VCC
2.0
6.0
RESET pull-up resistor
RRST
VCC
5 V r 10%
50
150
VCC
3 V r 10%
80
200
Pin capacitance
CIO
Schmitt width
RESET , NMI , INT0
VTH
Programmable
pull-down resistor
RKL
Programmable
pull-up resistor
RKH
NORMAL (Note 3)
ICC
NORMAL2 (Note 4)
fc
1 MHz
Max
Unit
3.5
mA
10
0.4
1.0
5 V r 10%
10
80
3 V r 10%
30
150
VCC
5 V r 10%
50
150
VCC
3 V r 10%
100
25
30
RUN
17
25
IDLE2
10
15
3.5
5
NORMAL2 (Note 4)
RUN
VCC 3 V r 10%
fc 10 MHz
(Typ: VCC 3.0 V)
IDLE2
IDLE1
SLOW (Note 3)
RUN
IDLE2
STOP
Note 1: Typical values are for Ta
8
8.5
11
4.0
7
2.5
4
0.7
1.2
20
35
16
30
10
20
5
15
VCC
0.2
10
2.7 to 5.5 V
25°C and VCC
mA
5.5
VCC 3 V r 10%
fs 32.768 kHz
(Typ: VCC 3.0 V)
IDLE1
k:
300
19
24
NORMAL (Note 3)
k:
V
VCC
IDLE1
V
pF
VCC
VCC 5 V r 10%
fc 20 MHz
PA
mA
PA
PA
5 V unless otherwise noted.
Note 2: IDAR is guaranteed for up to eight ports.
Note 3: ICC measurement conditions (NORMAL, SLOW): Only CPU is operational; output pins are open
and input pins are fixed.
Note 4: ICC measurement conditions (NORMAL 2): All functions are operational; output pins are open and
input pins are fixed.
93CM40-12
2004-02-10
TMP93CM40
4.3
AC Electrical Characteristics
(1) VCC
No.
5 V r 10%
Parameter
Symbol
Variable
16 MHz
Min
Max
Min
31250
Max
20 MHz
Min
Max
Unit
1
Osc. period ( x)
tOSC
50
62.5
50
2
CLK pulse width
tCLK
2x 40
85
60
ns
3
A0 to A23 fall o CLK hold
tAK
0.5x 20
11
5
ns
4
CLK valid o A0 to A 23 hold
tKA
1.5x 70
24
5
ns
5
A0 to A15 valid o ALE fall
tAL
0.5x 15
16
10
ns
6
ALE fall o A0 to A15 hold
tLA
0.5x 20
11
5
ns
7
ALE high pulse width
tLL
x 40
23
10
ns
8
ALE fall o RD / WR fall
tLC
0.5x 25
6
0
ns
9
RD / WR rise o ALE rise
A0 to A15 valid o RD / WR fall
tCL
0.5x 20
11
5
ns
tALC
x 25
38
25
ns
tACH
1.5x 50
44
25
ns
12
A0 to A23 valid o RD / WR fall
RD / WR rise o A0 to A23 hold
tCA
0.5x 25
13
A0 to A15 valid o D0 to D15 input
tADL
3.0x 55
133
95
ns
14
A0 to A23 valid o D0 to D15 input
tADH
3.5x 65
154
110
ns
15
RD fall o D0 to D15 input
tRD
2.0x 60
65
40
16
RD low pulse width
tRR
17
RD rise o D0 to D15 hold
tHR
0
0
0
ns
18
RD rise o A0 to A15 output
tRAE
x 15
48
35
ns
19
WR low pulse width
tWW
2.0x 40
85
60
ns
20
D0 to D15 valid o WR rise
tDW
2.0x 55
70
45
ns
tWD
0.5x 15
10
11
6
2.0x 40
ns
0
85
ns
60
ns
ns
21
WR rise o D0 to D15 hold
22
A0 to A23 valid o WAIT input
(1 N) WAIT
mode
tAWH
3.5x 90
129
85
ns
23
A0 to A15 valid o WAIT input
(1 N) WAIT
mode
tAWL
3.0x 80
108
70
ns
24
RD / WR fall o WAIT hold
(1 N) WAIT
mode
tCW
25
tAPH
5
ns
26
A0 to A23 valid o Port input
A0 to A23 valid o Port hold
27
WR rise o Port valid
tCP
200
ns
28
A0 to A23 valid o RAS fall
A0 to A15 valid o RAS fall
tASRH
1.0x 40
23
10
29
tASRL
0.5x 15
16
10
30
RAS fall o D0 to D15 input
tRAC
31
RAS fall o A0 to A15 hold
tRAH
0.5x 15
16
10
ns
32
RAS low pulse width
tRAS
2.0x 40
85
60
ns
33
RAS high pulse width
tRP
2.0x 40
85
60
ns
34
CAS fall o RAS rise
tRSH
1.0x 40
23
10
ns
35
RAS rise o CAS rise
tRSC
0.5x 25
6
0
ns
36
RAS fall o CAS fall
tRCD
1.0x 40
23
10
37
CAS fall o D0 to D15 input
tCAC
38
CAS low pulse width
tCAS
tAPH2
16
2.0x 0
10
125
2.5x 120
2.5x 50
100
36
206
200
86
1.5x 65
1.5x 30
ns
ns
ns
55
29
64
ns
175
200
2.5x 70
ns
ns
10
40
ns
ns
ns
AC measuring condition
x
Output level: High 2.2 V/Low 0.8 V, CL
50 pF
(However, CL 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , R/ W , CLK,
RAS , CAS0 to CAS2 )
x
Input level: High 2.4 V/Low 0.45 V (AD0 to AD15)
High 0.8 u VCC /Low 0.2 u VCC (except AD0 to AD15)
93CM40-13
2004-02-10
TMP93CM40
(2) VCC
No.
3 V r 10%
(TMP93CM40F is guaranteed up to 10 MHz operation.)
Parameter
Variable
Symbol
10 MHz
Min
Max
Min
31250
100
Unit
Max
1
Osc. period ( x)
tOSC
100
2
CLK pulse width
tCLK
2x 40
160
ns
ns
3
A0 to A23 fall o CLK hold
tAK
0.5x 30
20
ns
4
CLK valid o A0 to A 23 hold
tKA
1.5x 80
70
ns
5
A0 to A15 valid o ALE fall
tAL
0.5x 35
15
ns
6
ALE fall o A0 to A15 hold
tLA
0.5x 35
15
ns
7
ALE high pulse width
tLL
x 60
40
ns
8
ALE fall o RD / WR fall
tLC
0.5x 35
15
ns
9
RD / WR rise o ALE rise
A0 to A15 valid o RD / WR fall
tCL
0.5x 40
10
ns
10
tALC
x 50
50
ns
11
A0 to A23 valid o RD / WR fall
tACH
1.5x 50
100
ns
12
RD / WR rise o A0 to A23 hold
A0 to A15 valid o D0 to D15 input
tCA
0.5x 40
13
tADL
3.0x 110
190
ns
14
A0 to A23 valid o D0 to D15 input
tADH
3.5x 125
225
ns
15
RD fall o D0 to D15 input
tRD
16
RD low pulse width
tRR
17
RD rise o D0 to D15 hold
tHR
0
0
ns
18
RD rise o A0 to A15 output
tRAE
x 25
75
ns
10
2.0x 115
2.0x 40
ns
85
160
ns
ns
19
WR low pulse width
tWW
2.0x 40
160
ns
20
D0 to D15 valid o WR rise
tDW
2.0x 120
80
ns
tWD
0.5x 40
21
WR rise o D0 to D15 hold
22
A0 to A23 valid o WAIT input
(1 N) WAIT
mode
tAWH
3.5x 130
220
ns
23
A0 to A15 valid o WAIT input
(1 N) WAIT
mode
tAWL
3.0x 100
200
ns
24
RD / WR fall o WAIT hold
(1 N) WAIT
mode
tCW
25
A0 to A23 valid o Port input
tAPH
5
ns
26
A0 to A23 valid o Port hold
WR rise o Port valid
tAPH2
200
ns
A0 to A23 valid o RAS fall
A0 to A15 valid o RAS fall
tASRH
1.0x 60
40
29
tASRL
0.5x 40
10
30
RAS fall o D0 to D15 input
tRAC
31
RAS fall o A0 to A15 hold
tRAH
0.5x 25
25
ns
32
RAS low pulse width
tRAS
2.0x 40
160
ns
33
RAS high pulse width
tRP
2.0x 40
160
ns
34
CAS fall o RAS rise
tRSH
1.0x 55
45
ns
35
RAS rise o CAS rise
tRSC
0.5x 25
25
ns
36
RAS fall o CAS fall
tRCD
1.0x 40
60
ns
37
CAS fall o D0 to D15 input
tCAC
38
CAS low pulse width
tCAS
27
28
10
2.0x 0
200
2.5x 245
2.5x 50
tCP
ns
ns
300
200
2.5x 90
ns
ns
160
1.5x 120
1.5x 40
ns
30
110
ns
ns
ns
AC measuring condition
x
Output level: High 0.7 u VCC/Low 0.3 u VCC, CL
x
Input level: High 0.9 u VCC/Low 0.1 u VCC
93CM40-14
50 pF
2004-02-10
TMP93CM40
(1)
Read cycle
tOSC
X1
tCLK
CLK
tKA
tAK
A0 to A23
CS0 to CS2
R/ W
tAWH
tCW
tAWL
WAIT
tAPH
tAPH2
Port input (Note)
tASRH
tRP
tRSH
RAS
tRAS
tASRL
tRAC
tRAH
tRCD
CAS0 to CAS2
tCAS
tCAC
tCA
tADH
RD
tACH
tRR
tACL
tLC
tAL
ALE
Note:
tRD
tADL
A0 to A15
AD0 to AD15
tRSC
tRAE
tHR
D0 to D15
tLA
tCL
tLL
Since the CPU accesses the internal area to read data from a port, the control signals of external
pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be
regarded as depicting internal operation. Please also note that the timing and AC characteristics of
port input/output shown above are typical representation. For details, contact your local Toshiba
sales representative.
93CM40-15
2004-02-10
TMP93CM40
(2) Write cycle
X1
CLK
A0 to A23
CS0 to CS2
R/ W
WAIT
Port output (Note)
tCP
RAS
CAS0 to CAS2
WR , HWR
tWW
tWD
tDW
AD0 to AD15
A0 to A15
D0 to D15
ALE
Note:
Since the CPU accesses the internal area to write data to a port, the control signals of external pins
such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded
as depicting internal operation. Please also note that the timing and AC characteristics of port
input/output shown above are typical representation. For details, contact your local Toshiba sales
representative.
93CM40-16
2004-02-10
TMP93CM40
4.4
AD Conversion Characteristics
AVCC
Parameter
Symbol
Analog reference voltage ()
VREFH
Analog reference voltage ()
VREFL
Analog input voltage range
VAIN
Analog current for analog reference voltage
VCC 5 V r 10%
<VREFON> 1
VCC
5 V r 10%
<VREFON>
0
Error (not including quantizing errors)
Note 1: 1LSB
(VREFH VREFL) /2
Min
Typ.
Max
VCC 0.2 V
VCC
VCC
VSS
VSS
VSS 0.2 V
VREFL
IREF
(VREFL
0 V)
–
10
VCC, AVSS
VSS
Unit
V
VREFH
0.5
1.5
mA
0.02
5.0
PA
r3.0
r6
LSB
[V]
Note 2: The operation above is guaranteed for fFPH t 4 MHz.
Note 3: The value ICC includes the current which flows through the AVCC pin.
Note 4: The operation of this AD converter is guaranteed at 5 V r 10%.
93CM40-17
2004-02-10
TMP93CM40
4.5
Serial Channel Timing
(1) I/O interface mode
a. SCLK input mode
Parameter
Min
SCLK cycle
32.768 kHz
(Note 1)
Variable
Symbol
Max
Min
Max
10 MHz
Min
Max
20 MHz
Min
Unit
Max
16x
488 Ps
1600
800
ns
tOSS
tSCY/2 5x 50
91.5
Ps
250
100
ns
SCLK rising edge or falling edge (Note 2)
o Output data hold
tOHS
5x 100
152 Ps
400
150
ns
SCLK rising edge or falling edge (Note 2)
o Input data hold
tHSR
0
0
0
0
ns
SCLK rising edge or falling edge (Note 2)
o Effective data input
tSRD
tSCY
Output data o Rising edge or falling
edge (Note 2) of SCLK
tSCY 5x 100
336 Ps
1000
450
ns
Note 1: System clock is fs, or input clock to prescaler is divisor clock of fs.
Note 2: The rising edge is used in SCLK rising mode.
The falling edge is used SCLK falling mode.
b. SCLK output mode
Parameter
32.768 kHz
(Note)
Variable
Symbol
Min
Max
8192X
10 MHz
Min
Max
488
250 ms
Min
Max
1.6
819.2
20 MHz
Min
Max
0.8
409.6
Unit
Ps
SCLK cycle (Programmable)
tSCY
16X
Output data o SCLK rising edge
tOSS
tSCY 5X 150
427 Ps
1250
550
SCLK rising edge o Output data hold
tOHS
2x 80
60 Ps
120
20
ns
SCLK rising edge o Input data hold
tHSR
0
0
0
0
ns
SCLK rising edge o Effective data input
tSRD
tSCY 2x 150
428 Ps
ns
1250
550
ns
tSCY
SCLK
SCLK output mode (Only rising edge is used) or
SCLK input mode (SCLK rising edge mode)
SCLK
SCLK input mode (SCLK falling edge mode)
Output data
TxD
tOHS
tOSS
0
1
2
tSRD
Input data
RxD
3
tHSR
0
1
2
3
Valid
Valid
Valid
Valid
Note: System clock is fs, or input clock to prescaler is divisor clock of fs.
93CM40-18
2004-02-10
TMP93CM40
4.6
Timer/Counter Input Clock (TI0, TI4, TI5, TI6 and TI7)
Variable
Parameter
Symbol
Min
10 MHz
Max
Min
Max
20 MHz
Min
Max
Unit
Clock cycle
tVCK
8X 100
900
500
ns
Low level clock pulse width
tVCKL
4X 40
440
240
ns
High level clock pulse width
tVCKH
4X 40
440
240
ns
4.7
Interrupt and Capture
(1) NMI , INT0 interrupts
Variable
Parameter
Symbol
Min
10 MHz
Max
Min
Max
20 MHz
Min
Max
Unit
NMI , INT0 low level pulse width
tINTAL
4X
400
200
ns
NMI , INT0 high level pulse width
tINTAH
4X
400
200
ns
(2) INT4 to 7 interrupt, capture
The INT4 to 7 input pulse width depends on the CPU operation clock and timer
(9-bit prescaler). The following shows the pulse width for each clock.
System Clock Prescaler Clock tINTBL (INT4 to 7 low-level pulse width) tINTBH (INT4 to 7 high-level pulse width)
Unit
Selected
Selected
Variable
20 MHz
Variable
20 MHz
<SYSCK>
<PRCK1:0>
Min
Min
Min
Min
0 (fc)
1 (fs)
(Note 2)
00 (fIFPH)
8X 100
500
8X 100
500
01 (fs)
8XT 0.1
244.3
8XT 0.1
244.3
10 (fc/16)
128X 0.1
6.5
128X 0.1
6.5
8XT 0.1
244.3
8XT 0.1
244.3
00 (fIFPH)
01 (fs)
Note 1: XT represents the frequency of the low-frequency clock fs. It is calculated at fs
ns
Ps
32.768 kHz.
Note 2: When using fs as the system clock, fc/16 cannot be selected as the prescaler clock.
4.8
SCOUT Pin AC Characteristics
Variable
Parameter
High-level pulse width
VCC
Symbol
5 V r 10%
High-level pulse width
VCC
3 V r 10%
Low-level pulse width
VCC
5 V r 10%
Low-level pulse width
VCC
3 V r 10%
Min
10 MHz
Max
Min
Max
20 MHz
Min
0.5X 10
40
15
0.5X 20
30
0.5X 10
40
15
0.5X 20
30
Max
tSCH
Unit
ns
tSCL
ns
Measurement condition
x
Output level: High 2.2 V/Low 0.8 V, CL
10pF
tSCH
SCOUT
tSCL
93CM40-19
2004-02-10
TMP93CM40
4.9
Timing Chart for Bus Request ( BUSRQ )/Bus Acknowledge ( BUSAK )
(Note 1)
CLK
tBRC
BUSRQ
tBRC
tCBAL
tCBAH
BUSAK
tBAA
(Note 2)
tABA
AD0 to AD15, A0 to A23,
CS0 to CS2 , R/ W , RAS
CAS0 to CAS2
(Note 2)
RD , WR , HWR
ALE
Parameter
Variable
Symbol
Min
Max
Min
Max
120
20 MHz
Min
BUSRQ set-up time to CLK
tBRC
CLK o BUSAK falling edge
tCBAL
CLK o BUSAK rising edge
tCBAH
Output buffer off to BUSAK
tABA
0
80
0
80
0
BUSAK
tBAA
0
80
0
80
0
to output buffer on
120
10 MHz
0.5x 120
120
270
0.5x 40
Max
90
Unit
ns
195
ns
65
ns
80
ns
80
ns
Note 1: Even if the BUSRQ signal goes low, the bus will not be released while the WAIT signal is low. The
bus will only be released when BUSRQ goes low while WAIT is high.
Note 2: This line shows only that the output buffer is in the off state.
It does not indicate that the signal level is fixed.
Just after the bus is released, the signal level set before the bus was released is maintained
dynamically by the external capacitance. Therefore, to fix the signal level using an external resistor
during bus release, careful design is necessary, as fixing of the level is delayed.
The internal programmable pull-up/pull-down resistor is switched between the active and non-active
states by the internal signal.
93CM40-20
2004-02-10
TMP93CM40
4.10 Recommended Oscillator
The TMP93CM40 is evaluated with various resonators. The evaluation results are displayed
below to enable appropriate selection for any given application.
Note:
The load capacitance of the resonator consists of the load capacitors C1 and C2 which are
to be connected, and the floating capacitance of the target board.
Even if the specified values of C1 and C2 are used, there is a possibility that the oscillator
will malfunction due to varying load capacitance on the target boards. Hence the oscillator’s
wiring patterns on the board should be designed to be as short as possible.
It is recommended that evaluation of the resonators be conducted on the target board.
(1) Examples of resonator connection
X1
X2
XT1
XT2
Rd
Rd
C1
C2
C1
Figure 1: Example of High-frequency
Resonator Connection
C2
Figure 2: Example of Low-frequency
Resonator Connection
(2) Ceramic resonator: Murata Manufacturing. Co., Ltd. (Note 1)
Ta
Parameter
Frequency
(MHz)
Recommended Resonator
C1 [pF]
C2 [pF]
30
30
(30)
(Note 2)
(30)
(Note 2)
CSA10.00MTZ093
30
30
CST10.00MTW093
(30)
(Note 2)
(30)
(Note 2)
16.00
CSA16.00MXZ040
5
5
20.00
CSA20.00MXZ040
5
5
CSA4.00MGU
4.00
CST4.00MGWU
High-frequency
oscillation
20 to 80°C
Recommended Value
10.00
Rd [k:]
VCC [V]
2.7 to 5.5
0
4.5 to 5.5
Note 1: The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are
subject to change.
For up-to-date information, please refer to the following URL:
http://www.murata.com/
Note 2: For built-in condenser type
93CM40-21
2004-02-10
TMP93CM40
5.
Package Dimensions
P-QFP100-1414-0.50
Unit: mm
93CM40-22
2004-02-10