TOSHIBA TMP91CW12A

TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91CW12A
Preface
Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Points of Note and Restrictions”.
Especially, take care below cautions.
**CAUTION**
How to release the HALT mode
Usually, interrupts can release all halts status. However, the interrupts ( NMI ,
INT0 to 4, INTRTC) which can release the HALT mode may not be able to do so if
they are input during the period CPU is shifting to the HALT mode (for about 5
clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case).
(In this case, an interrupt request is kept on hold internally.)
If another interrupt is generated after it has shifted to HALT mode completely,
halt status can be released without difficultly. The priority of this interrupt is
compare with that of the interrupt kept on hold internally, and the interrupt with
higher priority is handled first followed by the other interrupt.
TMP91CW12A
CMOS 16-Bit Microcontrollers
TMP91CW12AF
1.
Outline and Features
TMP91CW12AF is a high-speed 16-bit microcontroller designed for the control of various mid- to
large-scale equipment.
TMP91CW12AF comes in a 100-pin flat package.
Listed below are the features.
(1) High-speed 16-bit CPU (900/L1 CPU)
x Instruction mnemonics are upward-compatible with TLCS-90/900
x 16 Mbytes of linear address space
x General-purpose registers and register banks
x 16-bit multiplication and division instructions; bit transfer and arithmetic instructions
x Micro DMA: 4 channels (1.0 Ps/2 bytes at 16 MHz)
(2) Minimum instruction execution time: 148 ns (at 27 MHz)
(3) Built-in RAM: 4 Kbytes
Built-in ROM: 128 Kbytes
(4) External memory expansion
x Expandable up to 16 Mbytes (shared program/data area)
x Can simultaneously support 8-/16-bit width external data bus
• • • Dynamic data bus sizing
(5) 8-bit timers: 8 channels
(6) 16-bit timer/event counter: 2 channels
(7) General-purpose serial interface: 2 channels
x
UART/Synchronous mode: 2 channels
x
IrDA ver 1.0 (115.2 kbps) supported: 1 channel
030519EBP1
xThe information contained herein is subject to change without notice.
xThe information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
xTOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
xThe TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made
at the customer’s own risk.
xThe products described in this document are subject to the foreign exchange and foreign trade laws.
xTOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law
and regulations.
xFor a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality
and Reliability Assurance/Handling Precautions.
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
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TMP91CW12A
(8) Serial bus interface: 1 channel
x I2C bus mode/clock synchronous select mode
(9) 10-bit AD converter (sample-hold circuit is built in): 8 channels
(10) Watchdog timer
(11) Timer for real-time clock (RTC)
(12) Chip Select/Wait controller: 4 channels
(13) Interrupts: 45 interrupts
x 9 CPU interrupts: Software interrupt instruction and illegal instruction
x 26 internal interrupts: 7-level priority can be set.
x 10 external interrupts: 7-level priority can be set.
(14) Input/output ports: 81 pins
(15) Standby function
Three Halt modes: Idle2 (programmable), Idle1, Stop
(16) Triple-clock controller
x Clock Doubler (DFM)
x Clock Gear (fc to fc/16)
x Slow mode (fs
32.768 kHz)
(17) Operating voltage
x VCC
2.7 V to 3.6 V (fc max
27 MHz)
x VCC
1.8 V to 3.6 V (fc max
10 MHz)
(18) Package
x 100-pin QFP: P-LQFP100-1414-0.50F
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TMP91CW12A
ADTRG (P53)
AN0 to AN7
(P50 to P57)
AVCC, AVSS
VREFH, VREFL
TXD0 (P90)
RXD0 (P91)
SCLK0/ CTS0 (P92)
TXD1 (P93)
RXD1 (P94)
SCLK1/ CTS1 (P95)
10-Bit 8CH
AD
Converter
SIO/UART/IrDA
(SIO0)
SIO/UART
(SIO1)
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
W A
B C
D E
H L
IX
IY
IZ
SP
32 bits
SR
F
PC
C
SCK (P60)
SO/SDA (P61)
SI / SCL (P62)
Serial Bus
Interface
(SBI)
TA0IN (P70)
8-Bit Timer
(TMRA0)
Real-Clock
Timer (RTC)
TA1OUT (P71)
8-Bit Timer
(TMRA1)
8-Bit Timer
(TMRA2)
TA3OUT (P72)
8-Bit Timer
(TMRA3)
TA4IN (P73)
8-Bit Timer
(TMRA4)
TA7OUT (P75)
Clock Gear
Clock doubler
L-OSC
RESET
Port 0
Port 2
Port 3
128-KB ROM
8-Bit Timer
(TMRA7)
(P00 to P07)
AD0 to AD7
(P10 to P17)
AD8/A8 to AD15/A15
(P20 to P27)
A0/A16 to A7/A23
RD (P30)
WR (P31)
HWR (P32)
BUSRQ (P34)
BUSAK (P35)
R/ W (P36)
P37
Port 6
(P64) SCOUT, P65, P66
Port A
PA4 to PA7
(P40 to P43)
Controller
(4-BLOCK)
Interrupt
Controller
8-Bit Timer
(TMRA5)
EMU0
EMU1
XT1 (P96)
XT2 (P97)
AM0
AM1
ALE
CS/WAIT
4-KB RAM
8-Bit Timer
(TMRA6)
H-OSC
Port 1
Watch-Dog
Timer
(WDT)
TA5OUT (P74)
DVCC [3]
DVSS [3]
X1
X2
CPU (TLCS-900/L1)
16-Bit Timer
(TMRB0)
16-Bit Timer
(TMRB1)
(
CS0 to CS3
WAIT (P33)
NMI
INT0 (P63)
INT1 to 4 (PA0 to 3)
TB0IN0/INT5 (P80)
TB0IN1/INT6 (P81)
TB0OUT0 (P82)
TB0OUT1 (P83)
TB1IN0/INT7 (P84)
TB1IN1/INT8 (P85)
TB1OUT0 (P86)
TB1OUT1 (P87)
): Initial function after reset
Figure 1.1 TMP91CW12AF Block Diagram
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TMP91CW12A
2.
Pin Assignment and Pin Functions
The assignment of input/output pins for the TMP91CW12AF, their names and functions are as
follows:
2.1
Pin Assignment Diagram
Figure 2.1.1 shows the pin assignment of the TMP91CW12AF.
88 P65
DVCC
89
87 P64/SCOUT
P66
90
86 P63/INT0
DVSS
91
85 P62/SI/SCL
P50/AN0
92
84 P61/SO/SDA
P51/AN1
93
83 P60/SCK
P52/AN2
94
82 P43/CS3
P53/AN3/ADTRG 95
81 P42/CS2
P54/AN4
96
80 P41/CS1
P55/AN5
97
79 P40/CS0
P56/AN6
98
78 P37
P57/AN7
99
77 P36/R/W
VREFH
100
76 P35/BUSAK
VREFL
1
75 P34/BUSRQ
AVSS
2
74 P33/WAIT
AVCC
3
73 P32/HWR
P70/TA0IN
4
72 P31/WR
P71/TA1OUT
5
71 P30/RD
P72/TA3OUT
6
P73/TA4IN
7
70 P27/A7/A23
69 P26/A6/A22
P74/TA5OUT
8
68 P25/A5/A21
P75/TA7OUT
9
67 P24/A4/A20
P80/TB0IN0/INT5 10
66 P23/A3/A19
65 P22/A2/A18
P81/TB0IN1/INT6 11
P82/TB0OUT0
12
P83/TB0OUT1
13
Top View
LQFP100
64 DVCC
63 NMI
P84/TB1IN0/INT7 14
62 DVSS
P85/TB1IN1/INT8 15
16
61 P21/A1/A17
60 P20/A0/A16
P87/TB1OUT1
17
59 P17/AD15/A15
P90/TXD0
18
58 P16/AD14/A14
P91/RXD0
19
57 P15/AD13/A13
P92/SCLK0/CTS0 20
56 P14/AD12/A12
P93/TXD1
21
55 P13/AD11/A11
P94/RX1
22
54 P12/AD10/A10
P86/TB1OUT0
P95/SCLK1/CTS1 23
AM0
24
53 P11/AD9/A9
52 P10/AD8/A8
DVCC
25
51 P07/AD7
X2
26
50 P06/AD6
DVSS
27
49 P05/AD5
X1
28
48 P04/AD4
AM1
29
47 P03/AD3
RESET
P96/XT1
30
31
46 P02/AD2
P97/XT2
32
44 P00/AD0
EMU0
33
43 ALE
EMU1
34
42 PA7
PA0/INT1
35
41 PA6
PA1/INT2
36
40 PA5
PA2/INT3
37
39 PA4
45 P01/AD1
38 PA3/INT4
Figure 2.1.1 Pin assignment diagram (100-pin LQFP)
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TMP91CW12A
2.2
Pin Names and Functions
The names of the input/output pins and their functions are described below.
Table 2.2.1 Pin names and functions.
Table 2.2.1 Pin Names and Functions (1/3)
Pin Name
Number
of Pins
I/O
Functions
P00 to P07
AD0 to AD7
8
I/O
Tri-state
Port 0: I/O port that allows I/O to be selected at the bit level
Address and data (lower): Bits 0 to 7 of address and data bus
P10 to P17
AD8 to AD15
A8 to A15
8
I/O
Tri-state
Output
Port 1: I/O port that allows I/O to be selected at the bit level
Address and data (upper): Bits 8 to 15 for address and data bus
Address: Bits 8 to 15 of address bus
P20 to P27
A0 to A7
A16 to A23
8
I/O
Output
Output
Port 2: I/O port that allows I/O to be selected at the bit level
Address: Bits 0 to 7 of address bus
Address: Bits 16 to 23 of address bus
P30
1
Output
Output
Port 30: Output port
Read: Strobe signal for reading external memory
1
Output
Output
Port 31: Output port
Write: Strobe signal for writing data to pins AD0 to AD7
1
I/O
Output
Port 32: I/O port (with pull-up resistor)
High Write: Strobe signal for writing data to pins AD8 to AD15
1
I/O
Input
Port 33: I/O port (with pull-up resistor)
Wait: Pin used to request CPU bus wait
1
I/O
Input
Port 34: I/O port (with pull-up resistor)
Bus Request: Signal used to request Bus Release
1
I/O
Output
Port 35: I/O port (with pull-up resistor)
Bus Acknowledge: Signal used to acknowledge Bus Release
P36
R/ W
1
I/O
Output
Port 36: I/O port (with pull-up resistor)
Read/Write: 1 represents Read or Dummy cycle; 0 represents Write cycle.
P37
1
I/O
P40
1
I/O
Output
Port 40: I/O port (with pull-up resistor)
Chip Select 0: Outputs 0 when address is within specified address area
1
I/O
Output
Port 41: I/O port (with pull-up resistor)
Chip Select 1: Outputs 0 if address is within specified address area
1
I/O
Output
Port 42: I/O port (with pull-up resistor)
Chip Select 2: Outputs 0 if address is within specified address area
1
I/O
Output
Port 43: I/O port (with pull-up resistor)
Chip Select 3: Outputs 0 if address is within specified address area
RD
P31
WR
P32
HWR
P33
WAIT
P34
BUSRQ
P35
BUSAK
CS0
P41
CS1
P42
CS2
P43
CS3
P50 to P57
AN0 to AN7
8
ADTRG
P60
SCK
P61
SO
SDA
P62
SI
SCL
1
1
1
Input
Input
Input
I/O
I/O
I/O
Output
I/O
Port 37: I/O port (with pull-up resistor)
Port 5: Pin used to input port
Analog input: Pin used to input to AD converter
AD Trigger: Signal used to request start of AD converter
Port 60: I/O port
Serial bus interface clock in SIO Mode
Port 61: I/O port
Serial bus interface output data in SIO Mode
Serial bus interface data in I2C bus Mode
I/O
Input
I/O
Port 62: I/O port
Serial bus interface input data in SIO Mode
Serial bus interface clock in I2C bus Mode
Port 63: I/O port
Interrupt Request Pin 0: Interrupt request pin with programmable
level / rising edge / falling edge
P63
INT0
1
I/O
Input
P64
SCOUT
1
I/O
Output
Port 64: I/O port
System Clock Output: Outputs fFPH or fs clock.
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TMP91CW12A
Table 2.2.1 Pin Names and Functions (2/3)
Pin Name
Number
of Pins
I/O
Functions
P65
1
I/O
Port 65: I/O port
P66
1
I/O
Port 66: I/O port
P70
TA0IN
1
I/O
Input
Port 70: I/O port
Timer A0 Input
P71
TA1OUT
1
I/O
Output
Port 71: I/O port
Timer A1 Output
P72
TA3OUT
1
I/O
Output
Port 72: I/O port
Timer A3 Output
P73
TA4IN
1
I/O
Input
Port 73: I/O port
Timer A4 Input
P74
TA5OUT
1
I/O
Output
Port 74: I/O port
Timer A5 Output
P75
TA7OUT
1
I/O
Output
Port 75: I/O port
Timer A7 Output
P80
TB0IN0
1
I/O
Input
Input
Port 80: I/O port
Timer B0 Input 0
Interrupt Request Pin 5: Interrupt request pin with programmable rising edge
/ falling edge.
P81
TB0IN1
INT6
1
I/O
Input
Input
Port 81: I/O port
Timer B0 Input 1
Interrupt Request Pin 6: Interrupt request on rising edge
P82
TB0OUT0
1
I/O
Output
Port 82: I/O port
Timer B0 Output 0
P83
TB0OUT1
1
I/O
Output
Port 83: I/O port
Timer B0 Output 1
P84
TB1IN0
INT7
1
I/O
Input
Input
Port 84: I/O port
Timer B1 Input 0
Interrupt Request Pin 7: Interrupt request pin with programmable rising edge
/ falling edge.
P85
TB1IN1
INT8
1
I/O
Input
Input
Port 85: I/O port
Timer B1 Input 1
Interrupt Request Pin 8: Interrupt request on rising edge
P86
TB1OUT0
1
I/O
Output
Port 86: I/O port
Timer B1 Output 0
P87
TB1OUT1
1
I/O
Output
Port 87: I/O port
Timer B1 Output 1
P90
TXD0
1
I/O
Output
Port 90: I/O port
Serial Send Data 0 (Programmable open-drain)
P91
RXD0
1
I/O
Input
Port 91: I/O port
Serial Receive Data 0
P92
SCLK0
1
I/O
I/O
Input
Port 92: I/O port
Serial Clock I/O 0
Serial Data Send Enable 0 (Clear to Send)
P93
TXD1
1
I/O
Output
P94
RXD1
1
I/O
Input
Port 94: I/O port (with pull-up resistor)
Serial Receive Data 1
P95
SCLK1
1
I/O
I/O
Input
Port 95: I/O port (with pull-up resistor)
Serial Clock I/O 1
Serial Data Send Enable 1 (Clear to Send)
1
I/O
Input
Port 96: I/O port (Open-drain output)
Low-frequency oscillator connection pin
INT5
CTS0
CTS1
P96
XT1
Port 93: I/O port
Serial Send Data 1 (Programmable open-drain)
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TMP91CW12A
Table 2.2.1 Pin Names and Functions (3/3)
Pin Name
Number
of Pins
I/O
Functions
P97
XT2
1
I/O
Output
PA0 to PA3
INT1 to INT4
4
I/O
Input
Port 97: I/O port (Open-drain output)
Low-frequency oscillator connection pin
Ports A0 to A3: I/O ports
Interrupt Request Pins 1 to 4: Interrupt request pins with programmable
rising edge / falling edge.
PA4 to PA7
4
I/O
ALE
1
Output
Ports A4 to A7: I/O ports
NMI
1
Input
Non-Maskable Interrupt Request Pin: Interrupt request pin with
programmable falling edge or both edge.
AM0 to 1
2
Input
Address Mode: The Vcc pin should be connected.
EMU0/EMU1
1
Output
RESET
1
Input
Address Latch Enable
Can be disabled to reduce noise.
Test Pins: Open pins
Reset: initializes TMP91CW12A. (With pull-up resistor)
VREFH
1
Input
Pin for reference voltage input to AD converter (H)
VREFL
1
Input
Pin for reference voltage input to AD converter (L)
AVCC
1
I/O
AVSS
1
Power supply pin for AD converter
X1/X2
2
GND pin for AD converter (0 V)
DVCC
3
Power supply pins (All VCC pins should be connected with the power supply
pin.)
DVSS
3
GND pins (0 V) (All VSS pins should be connected with the power supply
pin.)
High-frequency oscillator connection pins
Note: An external DMA controller cannot access the device’s built-in memory or built-in I/O devices using
the BUSRQ and BUSAK signal.
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TMP91CW12A
3.
Operation
This section describes the basic components, functions and operation of the TMP91CW12AF.
3.1 CPU
The TMP91CW12AF incorporates a high-performance 16-bit CPU (the 900/L1 CPU). For a
description of this CPU’s operation, please refer to the section of this data book which describes
the TLCS-900/L1 CPU.
The following sub-sections describe functions peculiar to the CPU used in the
TMP91CW12AF; these functions are not covered in the section devoted to the TLCS-900/L1
CPU.
3.1.1
Reset
When resetting the TMP91CW12AF microcontroller, ensure that the power supply
voltage is within the operating voltage range, and that the internal high-frequency
oscillator has stabilized. Then hold the RESET input Low for at least 10 system clocks (ten
states: 80 Ps at 4 MHz).
When the Reset has been accepted, the CPU performs the following:
x Sets the Program Counter (PC) as follows in accordance with the Reset Vector
stored at address FFFF00H to FFFF02H:
PC<0 to 7> m Data in location FFFF00H
PC<8 to 15> m Data in location FFFF01H
PC<16 to 23> m Data in location FFFF02H
x Sets the Stack Pointer (XSP) to 100H.
x Sets bits <IFF0 to IFF2> of the Status Register (SR) to 111 (thereby setting the
Interrupt Level Mask Register to level 7).
x Sets the <MAX> bit of the Status Register to 1 (MAX Mode).
x Clears bits <RFP0 to RFP2> of the Status Register to 000 (thereby selecting
Register Bank 0).
When the Reset is cleared, the CPU starts executing instructions according to the
Program Counter settings. CPU internal registers not mentioned above do not change
when the Reset is cleared.
When the Reset is accepted, the CPU sets internal I/O, ports and other pins as
follows.
x Initializes the internal I/O registers.
x Sets the port pins, including the pins that also act as internal I/O, to
General-Purpose Input or Output Port Mode.
x Sets the ALE pin to High-Z.
Note 1: Except PC,SR and XSP register of CPU and data of internal RAM are not change
by reset operation.
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TMP91CW12A
3.2 Memory Map
Figure 3.2.1 is a memory map of the TMP91CW12AF.
000000H
Internal I/O
(4 Kbytes)
Direct area (n)
000100H
001000H
64-Kbyte area
(nn)
Internal RAM
(4 Kbytes)
002000H
010000H
External memory
16-Mbyte area
(R)
(R)
(R)
(R R8/16)
(R d8/16)
(nnn)
FE0000H
Internal ROM
(128 Kbytes)
FFFF00H
FFFFFFH
Vector Table (256 Bytes)
(
Internal area)
Figure 3.2.1 Memory Map
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TMP91CW12A
3.3 Differences Between TMP91CW12AF and TMP91CW12F
(1) Outline
TMP91CW12AF is a high-speed and low-voltage products of TMP91CW12F.
The specification of function is added following item to TMP91CW12F.
The major difference points of A, C and D, C characteristics are operation voltage
(CW12F: 5 V/3 V, CW12AF: 3 V/2 V) and Fmax (CW12F: 16 MHz, CW12AF:27 MHz) at 3 V.
For the details, please refer to 4.Electrical Characteristics.
(2) Differences of Function
3.3.1
CS/WAIT controller
Wait operation setting is added in order to high-speed of operation frequency on
TMP91CW12AF. It is explained at Table 3.3.1.
Figure 3.3.1 shows SFR setting.
Table 3.3.1 Wait operation settings
<BxW2 to BxW0> No. of Waits
Wait Operation
2 waits
Inserts a wait of two states, irrespective of the WAIT pin state.
001
1 wait
Inserts a wait of one state, irrespective of the WAIT pin state.
010
1 wait N
011
0 waits
100
Reserved
101
3 waits
Inserts a wait of three states, irrespective of the WAIT pin state.
110
4 waits
Inserts a wait of four states, irrespective of the WAIT pin state.
111
8 waits
Inserts a wait of eight states, irrespective of the WAIT pin state.
000
Inserts one wait state, then continuously samples the state of the
WAIT pin. While the WAIT pin remains Low, the wait continues; the
the bus cycle is prolonged until the pin goes High.
Ends the bus cycle without a wait, regardless of the WAIT pin state.
Don’t setting
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TMP91CW12A
Chip Select/Wait Control Register
7
6
B0CS
(00C0H)
Bit symbol
B0E
Read/Write
W
ReadModifyWrite
instructions
are
prohibited.
After reset
0
B1CS
(00C1H)
Bit symbol
B1E
Read/Write
W
ReadModifyWrite
instructions
are
prohibited.
After reset
B2CS
(00C2H)
Bit symbol
ReadModifyWrite
instructions
are
prohibited.
After reset
1
0
Functions
Chip Select
Set up
0: Disable
1: Enable
CS2 area
selection
0: 16-Mbyte
area
1: CS area
B3CS
(00C3H)
Bit symbol
B3E
Read/Write
W
ReadModifyWrite
instructions
are
prohibited.
After reset
BEXCS
(00C7H)
Bit symbol
ReadModifyWrite
instructions
are
prohibited.
Function
Function
5
4
3
2
1
0
B0OM1
B0OM0
B0BUS
B0W2
B0W1
B0W0
0
0
0
0
0
0
W
Chip Select
Set up
0: Disable
1: Enable
Chip Select output
waveform selection
00: For ROM/SRAM
01:
10:
Reserved
11:
B1OM1
B1OM0
Number of Waits
000: 2 waits
001: 1 wait
010: 1 wait N
011: 0 waits
B1BUS
B1W2
B1W1
B1W0
0
0
Chip Select
Set up
0: Disable
1: Enable
B2E
0
Chip Select output
waveform selection
00: For ROM/SRAM
01:
10:
Reserved
11:
0
0
0
B2M
B2OM1
0
Data bus
width
0: 16 bits
1: 8 bits
B2OM0
Number of Waits
000: 2 waits
001: 1 wait
010: 1 wait N
011: 0 waits
B2BUS
0
0
Chip Select output
waveform selection
00: For ROM/SRAM
01:
10:
Reserved
11:
B2W2
B2W1
B2W0
0
0
0
B3OM1
0
Data bus
width
0: 16 bits
1: 8 bits
B3OM0
Number of waits
000: 2 waits
001: 1 wait
010: 1 wait N
011: 0 waits
B3BUS
0
0
Chip Select
Set up
0: Disable
1: Enable
0
Chip Select output
waveform selection
00: For ROM/SRAM
01:
10:
Reserved
11:
B3W2
B3W1
B3W0
0
0
0
0
Data bus
width
0: 16 bits
1: 8 bits
BEXBUS
Number of waits
000: 2 waits
001: 1 wait
010: 1 wait N
011: 0 waits
BEXW2
0
Data bus
width
0: 16 bits
1: 8 bits
Chip select output waveform
selection
Master enable bit
Prohibit
1
Permission
100: Reserved
101: 3 waits
110: 4 waits
111: 8 waits
BEXW1
BEXW0
0
0
0
Function
0
100: Reserved
101: 3 waits
110: 4 waits
111: 8 waits
W
After reset
0
Number of Waits
000: 2 waits
001: 1 waits
010: 1 wait N
011: 0 waits
01
10
11
16-Mbyte area
Reserved
Specified address area
100: Reserved
101: 3 waits
110: 4 waits
111: 8 waits
Number of address area waits
(See 3.3.1 Wait Control.)
00 For ROM/SRAM
CS2 area selection
1
100: Reserved
101: 3 waits
110: 4 waits
111: 8 waits
W
Read/Write
0
100: Reserved
101: 3 waits
110: 4 waits
111: 8 waits
W
Read/Write
Function
Data bus
width
0: 16 bits
1: 8 bits
Data bus width selection
0
16-bit data bus
1
8-bit data bus
Figure 3.3.1 Chip Select/Wait Control Registers
91CW12A-11
2003-05-21
TMP91CW12A
3.3.2
IrDA function
The SIRCR<RXSEL> register is added. This register can be the selection the logic of
recieving data from external IrDA module.
Figure 3.3.3 shows SFR setting.
Received pulse
<RXSEL>
0
Received pulse
<RXSEL>
1
Data after Demodulation
start
1
0
0
1
0
1
1
0
stop
Figure 3.3.2 Demodulation of Received data
SIRCR
(0207H)
Bit symbol
7
6
5
4
PLSEL
RXSEL
TXEN
RXEN
Read/Write
After reset
Function
3
2
1
0
SIRWD3
SIRWD2
SIRWD1
SIRWD0
0
0
0
R/W
0
Select
transmit
pulse width
0: 3/16
1: 1/16
0
0
Received
Data
0: H pulse
1: L
0
Transmit
0: disable
1: enable
Receive
0: disable
1: enable
0
Select receive pulse width
Set effective pulse width for equal or more than 2x u x
(value 1)
Values in the range 1 to 14 can be set
Select receive pulse width
Formula: Effective pulse width t 2x u x (value 1)
x 1/fFPH
0000
Cannot be set
0001
Equal or more than 4x 100 ns
to
1110
Equal or more than 30x 100 ns
1111
Can not be set
Receive operation
0
Disabled
1
Enabled
Transmit operation
0
Disabled
1
Enabled
Select transmit pulse width
0
3/16
1
1/16
Note: When the baud rate is slow and the IrDA1.0specified pulse width (minimum: 1.6 Ps) can be
secured, setting this bit to 1 enables infrared
light-up time to be decreased reducing power
consumption.
Figure 3.3.3 IrDA Control Register
91CW12A-12
2003-05-21
TMP91CW12A
3.3.3
Clock Doubler (DFM) function
Input frequency range to DFM (frequency of high-frequency oscillator) is different from
TMP91CW12.
Therefore, the DFMCR1 register is added to select frequency-range. (DFMCR1 register
don’t exist in TMP91CW12)
Write the following data according to the operating condition before starting lock-up.
DFMCR1
(00E9H)
7
6
5
4
0
0
0
1
3
2
1
0
0
0
1
1
Bit symbol
Read/Write
R/W
After reset
Function
Write 0BH when the fOSCH
4 to 6.75 MHz at Vcc = 3 V r10%
Write 1BH when the fOSCH
2 to 2.5 MHz at Vcc = 2 V r10%
Figure 3.3.4 DFM Control Register 1
3.3.4
Others
(1) Limitation of selecting drivability of High-frequency oscillator
The case of VCC 2.0 V r 10%, it is impossible to use selecting function of drivability
of High-frequency oscillator.
Do not write 0 to EMCCR0<DRVOSCH>.
91CW12A-13
2003-05-21
TMP91CW12A
4.
Electrical Characteristics
4.1 Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Power Supply Voltage
Vcc
0.5 to 4.0
V
Input Voltage
VIN
0.5 to Vcc 0.5
V
Output Current
IOL
2
mA
Output Current
IOH
2
mA
Output Current (total)
6IOL
80
mA
6IOH
80
mA
PD
600
mW
Output Current (total)
Power Dissipation (Ta
85°C)
Soldering Temperature (10 s)
TSOLDER
260
°C
Storage Temperature
TSTG
65 to 150
°C
Operating Temperature
TOPR
40 to 85
°C
Note:
The absolute maximum ratings are rated values which must not be exceeded during
operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute
maximum rating is exceeded, a device may break down or its performance may be
degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when
designing products which include this device, ensure that no absolute maximum rating
value will ever be exceeded.
91CW12A-14
2003-05-21
TMP91CW12A
4.2 DC Characteristics (1/2)
Parameter
Power Supply Voltage
(AVcc DVcc)
Input
High Voltage
Input
Low Voltage
(AVss
DVss
Symbol
Condition
fc
4 to 27 MHz
fc
2 to 10 MHz
VCC
0 V)
P00 to P17 (AD0 to 15)
VIL
P20 to PA7 (except P63)
VIL1
RESET , NMI , P63 (INT0)
VIL2
AM0, 1
VIL3
X1
VIL4
P00 to P17 (AD0 to 15)
VIH
P20 to PA7 (except P63)
VIH1
RESET , NMI , P63 (INT0)
VIH2
AM0, 1
VIH3
X1
VIH4
Output Low Voltage
VOL
Output High Voltage
VOH
Min
fs 30 to
34 kHz
Typ.
(Note1)
Max
Unit
3.6
V
2.7
1.8
Vcc t 2.7 V
0.6
Vcc 2.7 V
0.2 Vcc
Vcc t 2.7 V
0.3 Vcc
Vcc 2.7 V
0.2 Vcc
Vcc t 2.7 V
0.3
Vcc 2.7 V
0.25 Vcc
0.15 Vcc
Vcc t 2.7 V
0.3
Vcc 2.7 V
0.3
Vcc t 2.7 V
0.2 Vcc
Vcc 2.7 V
0.1 Vcc
Vcc t 2.7 V
2.0
Vcc 2.7 V
0.7 Vcc
Vcc t 2.7 V
0.7 Vcc
Vcc 2.7 V
0.8 Vcc
Vcc t 2.7 V
0.75 Vcc
Vcc 2.7 V
0.85 Vcc
Vcc t 2.7 V
Vcc0.3
Vcc 2.7 V
Vcc0.3
Vcc t 2.7 V
0.8 Vcc
Vcc 2.7 V
0.9 Vcc
Vcc 0.3
IOL
1.6mA
Vcc t 2.7 V
0.45
IOL
0.4mA
Vcc 2.7 V
0.15 Vcc
IOH
400 PA
Vcc t 2.7 V
2.4
IOH
200 PA
Vcc 2.7 V
0.8 Vcc
Note1: Typical values are for when Ta
25°C and Vcc
V
V
3.0 V unless otherwise noted.
91CW12A-15
2003-05-21
TMP91CW12A
4.2 DC Characteristics (2/2)
Parameter
Symbol
Condition
Min
Typ.
(Note1)
Max
Input Leakage Current
ILI
0.0 d VIN d Vcc
0.02
r5
Output Leakage Current
ILO
0.2 d VIN d Vcc 0.2
0.05
r10
Power Down Voltage
(at STOP, RAM back-up)
VSTOP
V IL2 0.2 Vcc,
V IH2 0.8 Vcc
RESET Pull-up Resistor
RRST
Pin Capacitance
CIO
Schmitt Width
RESET , NMI , INT0
VTH
Programmable
Pull-up Resistor
RKH
Normal (Note 2)
Icc
Idle2
Idle1
Normal (Note 2)
Idle2
Idle1
3.6
Vcc
3 V r 10%
100
400
Vcc
2 V r 10%
200
1000
fc
1 MHz
10
Vcc t 2.7 V
0.4
1.0
Vcc < 2.7 V
0.3
0.8
3 V r 10%
100
400
Vcc
2 V r 10%
200
1000
Vcc 3 V r 10%
fc 27 MHz
Vcc 2 V r 10%
fc 10 MHz
(Typ.: Vcc 2.0 V)
Vcc 3 V r 10%
fs 32.768 kHz
Idle1
Ta d 70°C
7.0
10.0
2.5
3.5
1.0
1.8
1.7
2.5
0.6
0.9
0.25
0.4
11.6
30
5.2
19
3.0
Ta d 85°C
8
7.7
20
3.5
13
Idle1
2.0
10
Stop
Vcc
0.1
10
Idle2
Note 1: Typical values are for when Ta
1.8 to 3.3V
25°C and Vcc
V
K:
PF
K:
mA
mA
PA
15
Vcc 2 V r 10%
fs 32.768 kHz
(Typ.: Vcc 2.0 V)
Slow (Note 2)
PA
V
Vcc
Idle2
Slow (Note 2)
1.8
Unit
PA
PA
3.0 V unless otherwise noted.
Note 2: Icc measurement conditions (Normal, Slow):
All functions are operating; output pins are open and input pins are fixed.
91CW12A-16
2003-05-21
TMP91CW12A
4.3 AC Characteristics
(1) Vcc
3.0 V r 10%
Variable
No. Symbol
fFPH
Parameter
27 MHz
Max
Unit
Min
Max
Min
37.0
31250
37.0
ns
12
ns
1
tFPH
fFPH Period ( x)
2
tAL
A0 to A15 Vaild o ALE Fall
0.5x 6
3
tLA
ALE Fall o A0 to A15 Hold
0.5x 16
2
ns
4
tLL
ALE High Width
x 20
17
ns
5
tLC
ALE Fall o RD / WR Fall
0.5x 14
4
ns
6
tCLR
RD Rise o ALE Rise
0.5x 10
8
ns
7
tCLW
WR Rise o ALE Rise
x 10
27
ns
8
tACL
A0 to A15 Valid o RD / WR Fall
x 23
14
ns
9
tACH
A0 to A23 Valid o RD / WR Fall
1.5x 26
29
ns
10
tCAR
RD Rise o A0 to A23 Hold
0.5x 13
5
ns
11
tCAW
WR Rise o A0 to A23 Hold
x 13
24
12
tADL
A0 to A15 Valid o D0 to D15 Input
3.0x 38
73
ns
13
tADH
A0 to A23 Valid o D0 to D15 Input
3.5x 41
88
ns
14
tRD
RD Fall o D0 to D15 Input
15
tRR
RD Low Width
16
tHR
RD Rise o D0 to A15 Hold
17
tRAE
RD Rise o A0 to A15 Output
18
tWW
WR Low Width
1.5x 15
40
ns
19
tDW
D0 to D15 Valid o WR Rise
1.5x 35
20
ns
20
tWD
WR Rise o D0 to D15 Hold
x 25
12
ns
2.0x 30
2.0x 15
21
tAWH
A0 to A23 Valid o WAIT Input
22
tAWL
A0 to A15 Valid o WAIT Input
1 WAIT
n Mode
1 WAIT
n Mode
23
tCW
RD / WR Fall o WAIT Hold
1 WAIT
n Mode
24
tAPH
A0 to A23 Valid o Port Input
25
tAPH2
A0 to A23 Valid o Port Hold
26
tAP
A0 to A23 Valid o Port Valid
ns
44
59
ns
ns
0
0
ns
x 15
22
ns
3.5x 60
69
ns
3.0x 50
61
ns
2.0x 0
74
3.5x 89
3.5x
ns
40
129
3.5x 80
AC Measuring Conditions
x Output Level: High 0.7 u Vcc, Low 0.3 u Vcc, CL
x Input Level: High 0.9 u Vcc, Low 0.1 u Vcc
ns
ns
209
ns
50 pF
Note: x used in an expression shows a frequency for the clock fFPH selected by
SYSCR1<SYSCK>.
The value of x changes according to whether a clock gear or a low-speed oscillator is
selected.
An example value is calculated for fc, with gear 1/fc (SYSCR1<SYSCK, GEAR2 to 0>
0000).
91CW12A-17
2003-05-21
TMP91CW12A
(2) Vcc
2.0 V r 10%
Variable
No. Symbol
fFPH
Parameter
x)
10 MHz
Max
Unit
Min
Max
Min
100
31250
100
ns
22
ns
1
tFPH
fFPH Period (
2
tAL
A0 to A15 o ALE Fall
0.5 x 28
3
tLA
ALE Fall o A0 to A15 Hold
0.5 x 35
4
tLL
ALE High Width
5
tLC
ALE Fall o RD / WR Fall
0.5x 28
22
ns
6
tCLR
RD Rise o ALE Rise
0.5x 20
30
ns
7
tACW
WR Rise o ALE Rise
x 20
80
ns
8
tACL
A0 to A15 Valid o RD / WR Fall
x 75
25
ns
9
TACH
A0 to A23 Valid o RD / WR Fall
1.5x 70
80
ns
10
tCAR
RD Rise o A0 to A23 Hold
0.5x 30
20
ns
11
TCAW
WR Rise o A0 to A23 Hold
x 30
70
ns
12
tADL
A0 to A15 Valid o D0 to D15 Input
3.0x 76
224
ns
13
tADH
A0 to A23 Valid o D0 to D15 Input
3.5x 82
268
ns
14
TRD
RD Fall o D0 to D15 Input
140
ns
15
tRR
RD Low Width
16
tHR
RD Rise o D0 to D15 Hold
17
tRAE
RD Rise o A0 to A15 Output
18
tWW
WR Low Width
19
tDW
D0 to D15 Valid o WR Rise
20
tWD
WR Rise oD0 to D15 Hold
x 40
21
tAWH
A0 to A23 Valid o WAIT Input
22
tAWL
A0 to A15 Valid o WAIT Input
1WAIT
n mode
1WAIT
n mode
tCW
RD / WR Fall o WAIT Hold
24
tAPH
A0 to A23 Valid o Port Input
25
tAPH2
A0 to A23 Valid o Port Hold
26
tAP
A0 to A23 Valid o Port Valid
ns
ns
2.0x 60
2.0x 30
1WAIT
n mode
23
15
60
170
ns
0
0
ns
x 30
70
ns
1.5 x 30
120
ns
1.5 x 70
80
ns
x 50
50
ns
3.5x 120
230
ns
3.0x 100
200
ns
180
ns
520
ns
2.0x 0
200
3.5x 170
3.5x
ns
350
3.5x 170
AC Measuring Conditions
x Output Level: High 0.7 u Vcc, Low 0.3 u Vcc, CL
x Input Level: High 0.9 u Vcc, Low 0.1 u Vcc
ns
50 pF
Note: x used in an expression shows a frequency for the clock fFPH selected by
SYSCR1<SYSCK>.
The value of x changes according to whether a clock gear or a low-speed oscillator is
selected.
An example value is calculated for fc, with gear 1/fc (SYSCR1<SYSCK, GEAR2 to 0>
0000).
91CW12A-18
2003-05-21
TMP91CW12A
(3) Read Cycle
tFPH
fFPH
A0 to A23
CS0 to CS3
R/ W
tAWH
tAWL
tCW
WAIT
tAPH
tAPH2
Port input
tADH
RD
tACH
tACL
tLC
A0 to A15
AD0 to AD15
tAL
ALE
tCAR
tRR
tRD
tADL
tRAE
tHR
D0 to D15
tLA
tCLR
tLL
91CW12A-19
2003-05-21
TMP91CW12A
(4) Write Cycle
fFPH
A0 to 23
CS0 to CS3
R/ W
WAIT
tAP
Port Output
tCAW
tWW
WR , HWR
tDW
AD0 to 15
A0 to 15
tWD
D0 to 15
tCLW
ALE
91CW12A-20
2003-05-21
TMP91CW12A
4.4 AD Conversion Characteristics
AVcc
Parameter
Symbol
Analog Reference Voltage ()
VREFH
Analog Reference Voltage ()
VREFL
Analog Input Voltage Range
Analog Current for Analog
Reference Voltage
<VREFON> 1
VAIN
<VREFON>
Typ.
Max
IREF
(VREFL
0V)
Vss
Unit
VCC
3 V r 10%
VCC 0.2 V
Vcc
Vcc
VCC
2 V r 10%
VCC
Vcc
Vcc
VCC
3 V r 10%
VSS
Vss
Vss 0.2 V
VCC
2 V r 10%
VSS
Vss
V
Vss
VREFH
VCC
3 V r 10%
0.94
1.20
VCC
2 V r 10%
0.65
0.90
1.8 V to 3.3 V
0.02
5.0
VCC
3 V r 10%
r1.0
r4.0
VCC
2 V r 10%
r1.0
r4.0
VCC
Error
(not including quantizing errors)
Min
VREFL
0
Note 1: 1 LSB
Condition
Vcc, AVss
mA
PA
LSB
(VREFH VREFL)/1024 [V]
Note 2: The operation above is guaranteed for fFPH t 4 MHz.
Note 3: The value for ICC includes the current which flows through the AVCC pin.
91CW12A-21
2003-05-21
TMP91CW12A
4.5 Serial Channel Timing (I/O Interface Mode)
(1) SCLK Input Mode
Parameter
Symbol
SCLK Period
tSCY
Output Data
oSCLK
Rising/Falling
Edge*
Vcc 3V r
10%
Variable
10 MHz
Min
Max
Min
27 MHz
Max
Min
Max
Unit
16X
1.6
0.59
Ps
tSCY/2 4X 110
290
38
ns
tSCY/2 4X 180
220
ns
tOSS
Vcc 2V r
10%
SCLK Rising/Falling Edge*
o Output Data Hold
tOHS
tSCY/2 2X 0
1000
370
ns
SCLK Rising/Falling Edge*
o Input Data Hold
tHSR
3X 10
310
121
ns
SCLK Rising/Falling Edge*
o Valid Data Input
tSRD
Valid Data Input o
SCLK Rising/Falling Edge*
tRDS
tSCY 0
1600
0
592
0
0
ns
ns
(2) SCLK Output Mode
Parameter
Symbol
Variable
10 MHz
27 MHz
Min
Max
Min
Max
Min
Max
8192X
1.6
819
0.59
303
Unit
Ps
SCLK Period
tSCY
16X
Output Data o SCLK Rising
/Falling Edge*
tOSS
tSCY/2 40
760
256
ns
SCLK Rising/Falling Edge*
o Output Data Hold
tOHS
tSCY/2 40
760
256
ns
SCLK Rising/Falling Edge*
o Input Data Hold
tHSR
0
0
0
ns
SCLK Rising/Falling Edge*
o Valid Data Input
tSRD
Valid Data Input o
SCLK Rising/Falling Edge*
tRDS
Note:
tSCY 1X 180
1X 180
1320
280
375
217
ns
ns
SCLK Rinsing/Falling Edge: The rising edge is used in SCLK Rising Mode.
The falling edge is used in SCLK Falling Mode.
27 MHz and 10 MHz values are calculated from tSCY 16X case.
tSCY
SCLK
Output Mode/
Input Mode
SCLK
(Input Mode)
OUTPUT DATA
TxD
tOHS
tOSS
1
0
2
3
tRDS
tSRD
INPUT DATA
RxD
tHSR
0
1
2
3
Valid
Valid
Valid
Valid
91CW12A-22
2003-05-21
TMP91CW12A
4.6 Event Counter (TA0IN, TA4IN, TB0IN0, TB0IN1, TB1IN0, TB1IN1)
Parameter
Variable
Symbol
Min
10 MHz
Max
Min
Max
27 MHz
Min
Max
Unit
Clock Perild
tVCK
8X 100
900
396
ns
Clock Low Level Width
tVCKL
4X 40
440
188
ns
Clock High Level Width
tVCKH
4X 40
440
188
ns
4.7 Interrupt and Capture
(1) NMI , INT0 to INT4 Interrupts
Symbol
Variable
Parameter
Min
10 MHz
Max
Min
Max
27 MHz
Min
Unit
Max
tINTAL
NMI , INT0 to INT4 Low level width
4X 40
440
188
ns
tINTAH
NMI , INT0 to INT4 High level width
4X 40
440
188
ns
(2) INT5 to INT8 Interrupts, Capture
The INT5 to INT8 input width depends on the system clock and prescaler clock settings.
System Clock
Selected
<SYSCK>
0 (fc)
1 (fs)
Note: Xc
tINTBH
tINTBL
Prescaler Clock
(INT5 to INT8 Low level Width) (INT5 to INT8 High Level Width) Unit
Selected
<PRCK1,
Variable
fFPH 27 MHz
Variable
fFPH 27 MHz
PRCK0>
Min
Min
Min
Min
00 (fFPH)
8X 100
396
8X 100
396
10 (fc/16)
128Xc 0.1
4.8
128Xc 0.1
4.8
00 (fFPH)
8X 0.1
244.3
8X 0.1
244.3
ns
Ps
Period of Clock fc
4.8 SCOUT Pin AC Characteristics
Parameter
Symbol
Low level Width
tSCH
High level Width
tSCL
Note: T
Variable
Min
10 MHz
Max
Min
27 MHz
Max
Min
Max
Condition
0.5T 13
37
5
Vcc t 2.7 V
0.5T 25
25
Vcc < 2.7 V
0.5T 13
37
5
Vcc t 2.7 V
0.5T 25
25
Vcc < 2.7 V
Unit
ns
ns
Period of SCOUT
Measrement Condition
x
Output Level: High 0.7 Vcc/Low 0.3 Vcc, CL
10pF
tSCH
tSCL
SCOUT
91CW12A-23
2003-05-21
TMP91CW12A
4.9 Bus Request/Bus Acknowledge
BUSRQ
(Note 1)
tCBAL
BUSAK
tBA
(Note 2)
tABA
AD0 to AD15
A0 to A23,
RD , WR
(Note 2)
CS0 to CS3 ,
R/ W , HWR
ALE
Paramter
Symbol
Variable
Min
Output Buffer Off to BUSAK Low
BUSAK High to Output Buffer On
tABA
tBAA
Max
fFPH
Min
10 MHz
Max
fFPH
Min
27 MHz
Condition
Unit
Max
0
80
0
80
0
80
Vcc t 2.7 V
0
300
0
300
0
300
Vcc < 2.7 V
0
80
0
80
0
80
Vcc t 2.7 V
0
300
0
300
0
300
Vcc < 2.7 V
ns
ns
Note 1: Even if the BUSRQ Signal goes Low, the bus will not be released while the WAIT signal is Low. The
bus will only be released when BUSRQ goes Low while WAIT is High.
Note 2: This line shows only that the output buffer is in the Off state.
It does not indicate that the signal level is fixed.
Just after the bus is released, the signal level set before the bus was released is maintained
dynamically by the external capacitance. Therefore, to fix the signal level using an external resister
during bus release, careful design is necessary, since fixing of the level is delayed.
The internal programmable pull-up/pull-down resistor is switched between the Active and Non-Active
states by the internal signal.
91CW12A-24
2003-05-21
TMP91CW12A
4.10 Recommended Oscillation Circuit
The TMP91CW12AF has been evaluated by the following resonator manufacturer. The
evaluation results are shown below for your information.
Note:
The load capacitance of the oscillation terminal is the sum of the load capacitances of C1 and
C2 to be connected and the stray capacitance on the board. Even if the ratings of C1 and C2
are used, the load capacitance varies with each board and the oscillator may malfunction.
Therefore, when designing a board, make the pattern around the oscillation circuit shortest. It
is recommended that final evaluation of the resonator be performed on the board.
(1) Examples of resonator connection
X1
XT1
X2
XT2
Rd
Rd
C1
C2
C1
C2
Figure 4.10.1 High-frequency
Oscillator Connection
Figure 4.10.2 Low-frequency
Oscillator Connection
(2) Recommended ceramic resonators for the TMP91CW12AF: Murata Manufacturing Co.,
Ltd.
40 to 85°C
Ta
Item
Oscillation Recommended
frequency
resonator
[MHz]
2.0
2.5
4.0
High-frequ
ency
oscillator
6.75
10.0
12.5
20.0
27.0
CSA2.00MG042
CST2.00MG042
CSA2.50MG042
CST2.50MGW042
CSA4.00MG040
CST4.00MGW040
CSTS0400MG06
CSA4.00MGU040
CST4.00MGWU040
CSA6.75MTZ040
CST6.75MTW040
CSTS0675MG06
CSA6.75MTZ093
CST6.75MTW093
CSA10.0MTZ
CST10.0MTW
CSA10.0MTZ093
CST10.0MTW093
CSA12.5MTZ
CST12.5MTW
CSA20.00MXZ040
CSA27.00MXZ040
CST27.00MXW040
Recommended rating
C1[pF]
C2[pF]
100
(100)
100
(100)
100
(100)
(47)
100
(100)
100
(100)
(47)
30
(30)
30
(30)
30
(30)
30
(30)
7
5
(5)
100
(100)
100
(100)
100
(100)
(47)
100
(100)
100
(100)
(47)
30
(30)
30
(30)
30
(30)
30
(30)
7
5
(5)
Rd[kǡ]
VCC[V]
Remarks
1.8 to 2.2
2.7 to 3.3
1.8 to 2.2
2.7 to 3.3
0
1.8 to 2.2
2.7 to 3.3
1.8 to 2.2
2.7 to 3.3
x The values enclosed in brackets in the C1 and C2 columns apply to the condenser
built-in type.
x The product numbers and specifications of the resonators by Murata
Manufacturing Co., Ltd. are subject to change. For up-to-date information, please
refer to the following URL;
http://www.murata.co.jp/search/index.html
91CW12A-25
2003-05-21
TMP91CW12A
91CW12A-26
2003-05-21