IDT IDT54FCT646A Fast cmos octal transceiver/register Datasheet


IDT54/74FCT646
IDT54/74FCT646A
IDT54/74FCT646C
FAST CMOS OCTAL
TRANSCEIVER/REGISTER
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
•
•
•
•
The IDT54/74FCT646/A/C consists of a bus transceiver
with 3-state D-type flip-flops and control circuitry arranged for
multiplexed transmission of data directly from the data bus or
from the internal storage registers.
The IDT54/74FCT646/A/C utilizes the enable control (G)
and direction (DIR) pins to control the transceiver functions.
SAB and SBA control pins are provided to select either real
time or stored data transfer. The circuitry used for select
control will eliminate the typical decoding glitch that occurs in
a multiplexer during the transition between stored and realtime data. A LOW input level selects real-time data and a
HIGH selects stored data.
Data on the A or B data bus or both can be stored in the
internal D flip flops by LOW-to-HIGH transitions at the
appropriate clock pins (CPAB or CPBA) regardless of the
select or enable control pins.
IDT54/74FCT646 equivalent to FAST speed;
IDT54/74FCT646A 30% faster than FAST
IDT54/74FCT646C 40% faster than FAST
Independent registers for A and B buses
Multiplexed real-time and stored data
IOL = 64mA (commercial) and 48mA (military)
CMOS power levels (1mW typical static)
TTL input and output level compatible
CMOS output level compatible
Available in 24-pin (300 mil) CERDIP, plastic DIP, SOIC,
CERPACK and 28-pin LCC
• Product available in Radiation Tolerant and Radiation
Enhanced Versions
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
G
DIR
CPBA
SBA
CPAB
SAB
B REG
1 OF 8 CHANNELS
1D
C1
A1
A REG
B1
1D
C1
TO 7 OTHER CHANNELS
2536 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1992 Integrated Device Technology, Inc.
7.18
MAY 1992
DSC-4626/2
1
IDT54/74FCT646/A/C
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DIR
SAB
CPAB
NC
Vcc
CPBA
SBA
PIN CONFIGURATIONS
INDEX
1
24
2
23
3
22
P24-1,
D24-1,
S024-2
&
E24-1
4
5
6
7
21
20
19
18
8
17
9
16
10
15
11
14
12
13
Vcc
CPBA
SBA
G
B1
B2
B3
B4
B5
B6
B7
B8
4
A1
A2
A3
NC
A4
A5
A6
5
2
28 27 26
1
6
8
25
24
7
23
L28-1
22
9
21
10
20
11
19
12 13 14 15 16 17 18
DIP/SOIC/CERPACK
TOP VIEW
G
B1
B2
NC
B3
B4
B5
2536 drw 02
LCC
TOP VIEW
PIN DESCRIPTION
LOGIC SYMBOL
Pin Names
Description
A1–A8
Data Register A Inputs
Data Register B Outputs
B1–B8
Data Register B Inputs
Data Register A Outputs
CPAB, CPBA
Clock Pulse Inputs
SAB, SBA
Output Data Source Select Inputs
DIR, G
3
A7
A8
GND
NC
B8
B7
B6
CPAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
CPAB
SAB
DIR
CPBA
SBA
G
Output Enable Inputs
A 1 A 2 A3 A 4 A5 A 6 A 7 A8
B 1 B 2 B3 B 4 B5 B 6 B 7 B8
2536 tbl 01
2536 drw 06
FUNCTION TABLE(2)
Data I/O(1)
Inputs
Operation or Function
G
DIR
CPAB
CPBA
SAB
SBA
A1–A8
B1–B8
H
H
X
X
H or L
↑
H or L
↑
X
X
X
X
Input
Input
Isolation
Store A and B Data
L
L
L
L
X
X
X
H or L
X
X
L
H
Output
Input
Real-Time B Data to A Bus
Stored B Data to A Bus
L
L
H
H
X
H or L
X
X
L
H
X
X
Input
Output
Real-Time A Data to B Bus
Stored A Data to B Bus
IDT54/74FCT646
NOTES:
2536 tbl 02
1. The data output functions may be enabled or disabled by various signals at the G or DIR inputs. Data input functions are always enabled, i.e., data at
the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
2. H = HIGH, L = LOW, X = Don’t Care, ↑ = LOW-to-HIGH Transition.
7.18
2
IDT54/74FCT646/A/C
FAST CMOS OCTAL TRANSCEIVER/REGISTER
BUS
A
DIR
L
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUS
A
BUS
B
G
L
CPAB
X
CPBA
X
SAB
X
DIR
H
SBA
L
DIR
H
L
X
CPAB
CPBA
X
X
SAB
X
X
X
CPAB
X
CPBA
X
SAB
L
BUS
A
BUS
B
G
L
L
H
G
L
REAL–TIME TRANSFER
BUS A TO BUS B
REAL–TIME TRANSFER
BUS B TO BUS A
BUS
A
BUS
B
DIR
L
H
SBA
X
X
X
2536 drw 03
BUS
B
(1)
G
L
L
CPAB
X
H or L
CPBA
H or L
X
SAB
X
H
TRANSFER STORED
DATA TO A AND/OR B
STORAGE FROM
A AND/OR B
SBA
X
SBA
H
X
2536 drw 04
NOTE:
1. Cannot transfer data to A bus and B bus simultaneously.
7.18
3
IDT54/74FCT646/A/C
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
to GND
VTERM(3) Terminal Voltage
with Respect
to GND
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
TSTG
Storage
Temperature
PT
Power Dissipation
IOUT
DC Output Current
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Commercial
Military
Unit
–0.5 to +7.0 –0.5 to +7.0
V
–0.5 to VCC
–0.5 to VCC
V
0 to +70
–55 to +125
°C
–55 to +125
–65 to +135
°C
–55 to +125
–65 to +150
°C
0.5
120
0.5
120
W
mA
Symbol
Parameter(1)
Conditions
Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
6
10
pF
CI/O
I/O Capacitance
VOUT = 0V
8
12
pF
NOTE:
2536
1. This parameter is measured at characterization but not tested.
tbl 04
NOTES:
2536 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed VCC by +0.5V unless otherwise noted.
2. Inputs and VCC terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
VIK
IOS
VOH
Input HIGH Level
Input LOW Level
Input HIGH Current
(Except I/O pins)
Input LOW Current
(Except I/O pins)
Input HIGH Current
(I/O pins only)
Input LOW Current
(I/O pins only)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
VIL
IIH
IIL
IIH
IIL
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
VCC = Max.
VI = VCC
VI = 2.7V
VI = 0.5V
VI = GND
VCC = Max.
VI = VCC
VI = 2.7V
VI = 0.5V
VI = GND
VCC = Min., IN = –18mA
VCC = Max.(3), VO = GND
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
IOH = –300µA
VCC = Min.
IOH = –12mA MIL.
VIN = VIH or VIL
IOH = –15mA COM’L.
VCC = 3V, VIN = VLC or VHC, IOL = 300µA
IOL = 300µA
VCC = Min.
VIN = VIH or VIL
IOL = 48mA MIL.
IOL = 64mA COM’L.
2.0
—
—
—
—
—
—
—
—
—
—
–60
VHC
VHC
2.4
2.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–0.7
–120
VCC
VCC
4.0
4.0
GND
GND
0.3
0.3
—
0.8
5
5(4)
–5(4)
–5
15
15(4)
–15(4)
–15
–1.2
—
—
—
—
—
VLC
VLC(4)
0.55
0.55
V
V
µA
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.18
µA
V
mA
V
V
2536 tbl 05
4
IDT54/74FCT646/A/C
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
Symbol
Parameter
Test Conditions(1)
VCC = Max.
VIN ≥ VHC; VIN ≤ VLC
VCC = Max.
VIN = 3.4V(3)
Min.
Typ.(2)
Max.
Unit
—
0.2
1.5
mA
—
0.5
2.0
mA
ICC
Quiescent Power Supply Current
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
ICCD
Dynamic Power Supply Current(4)
VCC = Max.
Outputs Open
G = DIR = GND
One Input Toggling
50% Duty Cycle
VIN ≥ VHC
VIN ≤ VLC
—
0.15
0.25
mA/MHz
IC
Total Power Supply Current(6)
VCC = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
G = DIR = GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
1.7
4.0
mA
VIN = 3.4V
VIN = GND
—
2.2
6.0
VCC = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
G = DIR = GND
Eight Bits Toggling
at fi = 5MHz
50% Duty Cycle
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
7.0
12.8(5)
VIN = 3.4V
VIN = GND
—
9.2
21.8(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
7.18
2536 tbl 06
5
IDT54/74FCT646/A/C
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
54/74FCT646
Com’l.
Symbol
Parameter
tPLH
tPHL
Propagation
Delay
Bus to Bus
tPZH
tPZL
(1)
Condition
CL = 50 pF
RL = 500Ω
(2)
Min.
54/74FCT646A
Mil.
(2)
Max. Min.
Com’l.
(2)
Max. Min.
54/74FCT646C
Mil.
(2)
Max. Min.
Com’l.
(2)
Max.
Min.
Mil.
Max. Min.
(2)
Max. Unit
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
1.5
5.4
1.5
6.0
ns
Output Enable
Time G, DIR to
Bus
2.0
14.0
2.0
15.0
2.0
9.8
2.0
10.5
1.5
7.8
1.5
8.9
ns
tPHZ
tPLZ
Output Disable
Time G, DIR to
Bus
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
1.5
6.3
1.5
7.7
ns
tPLH
tPHL
Propagation
Delay Clock
to Bus
2.0
9.0
2.0
10.0
2.0
6.3
2.0
7.0
1.5
5.7
1.5
6.3
ns
tPLH
tPHL
Propagation
Delay SBA or
SAB to Bus
2.0
11.0
2.0
12.0
2.0
7.7
2.0
8.4
1.5
6.2
1.5
7.0
ns
tSU
Set-up Time
HIGH or LOW
Bus to Clock
4.0
—
4.5
—
2.0
—
2.0
—
2.0
—
2.0
—
ns
tH
Hold Time
HIGH or LOW
Bus to Clock
2.0
—
2.0
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tW
Clock Pulse
Width HIGH or
LOW
6.0
—
6.0
—
5.0
—
5.0
—
5.0
—
5.0
—
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2536 tbl 07
7.18
6
IDT54/74FCT646/A/C
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
VCC
7.0V
500Ω
V OUT
VIN
Pulse
Generator
D.U.T.
50pF
RT
500Ω
SET-UP, HOLD AND RELEASE TIMES
Closed
All Other Tests
Open
3V
1.5V
0V
tH
TIMING
INPUT
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
tW
t REM
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
Open Drain
Disable Low
Enable Low
PULSE WIDTH
DATA
INPUT
ASYNCHRONOUS CONTROL
Switch
DEFINITIONS:
2536 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
CL
t SU
Test
t SU
1.5V
3V
1.5V
0V
tH
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
3V
1.5V
SAME PHASE
INPUT TRANSITION
t PLH
t PHL
CONTROL
INPUT
OUTPUT
NORMALLY SWITCH
LOW CLOSED
t PZH
VOL
t PLH
t PHL
OUTPUT SWITCH
NORMALLY OPEN
HIGH
3V
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
t PLZ
t PZL
0V
VOH
1.5V
OUTPUT
1.5V
3.5V
1.5V
3.5V
0.3V
V OL
t PHZ
0.3V
1.5V
0V
V OH
0V
0V
NOTES
2536 drw 07
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.18
7
IDT54/74FCT646/A/C
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
Temperature
Range
FCT
XXXX
XX
X
Device
Type
Package
Process/
Temperature
Range
Blank
B
Commercial
MIL-STD-883, Class B
P
D
SO
L
E
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
646
646A
646C
Non-inverting Octal Transceiver/Register
Fast Non-inverting Octal Transceiver/Register
Super Fast Non-inverting Octal Transceiver/Register
54
75
–55°C to +125°C
0°C to +70°C
7.18
2536 drw 05
8
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