TOSHIBA TMP89FM46

8 Bit Microcontroller
TLCS-870/C1 Series
TMP89FM46
The information contained herein is subject to change without notice. 021023_D
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and
vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards
of safety in making a safe design for the entire system, and to avoid situations in which a malfunction
or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating
ranges as set forth in the most recent TOSHIBA products specifications.
Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
The TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.).
These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of
human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, medical instruments, all types of safety devices, etc. Unintended
Usage of TOSHIBA products listed in this document shall be made at the customer's own risk.
021023_B
The products described in this document shall not be used or embedded to any downstream products of
which manufacture, use and/or sale are prohibited under any applicable laws and regulations.
060106_Q
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any
patents or other rights of TOSHIBA or the third parties. 070122_C
The products described in this document are subject to foreign exchange and foreign trade control
laws. 060925_E
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3
of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S
© 2007 TOSHIBA CORPORATION
All Rights Reserved
Revision History
Date
Revision
2007/10/25
1
First Release
2007/11/1
2
Contents Revised
Table of Contents
TMP89FM46
1.1
1.2
1.3
1.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
3
4
5
2. CPU Core
2.1
2.2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.1
RAM
BOOTROM
Flash
2.2.2.1
2.2.2.2
2.2.2.3
2.2.2.4
SFR
RAM
BOOTROM
Flash
2.2.2
2.3
Data area ................................................................................................................................................ 12
System clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1
2.3.2
2.3.3
Configuration .......................................................................................................................................... 15
Control .................................................................................................................................................... 15
Functions ................................................................................................................................................ 17
2.3.3.1
2.3.3.2
2.3.3.3
Clock generator
Clock gear
Timing generator
2.3.4.1
2.3.4.2
Warm-up counter operation when the oscillation is enabled by the hardware
Warm-up counter operation when the oscillation is enabled by the software
2.3.5.1
2.3.5.2
2.3.5.3
2.3.5.4
Single-clock mode
Dual-clock mode
STOP mode
Transition of operation modes
2.3.6.1
2.3.6.2
2.3.6.3
2.3.6.4
STOP mode
IDLE1/2 and SLEEP1 modes
IDLE0 and SLEEP0 modes
SLOW mode
2.3.4
2.3.5
2.3.6
2.4
Code area ................................................................................................................................................. 9
2.2.1.1
2.2.1.2
2.2.1.3
Warm-up counter .................................................................................................................................... 20
Operation mode control circuit ................................................................................................................ 22
Operation Mode Control ......................................................................................................................... 27
Reset Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.4.1
2.4.2
2.4.3
2.4.4
Configuration ..........................................................................................................................................
Control ....................................................................................................................................................
Functions ................................................................................................................................................
Reset Signal Generating Factors............................................................................................................
2.4.4.1
2.4.4.2
2.4.4.3
2.4.4.4
2.4.4.5
2.4.4.6
2.4.4.7
2.4.4.8
2.4.4.9
38
38
40
41
External reset input (RESET pin input)
Power-on reset
Voltage detection reset
Watchdog timer reset
System clock reset
Trimming data reset
Flash standby reset
Internal factor reset detection status register
How to use the external reset input pin as a port
i
3. Interrupt Control Circuit
3.1
3.2
3.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Interrupt Latches (IL25 to IL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Interrupt Enable Register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3.1
3.3.2
Interrupt master enable flag (IMF) .......................................................................................................... 49
Individual interrupt enable flags (EF25 to EF4) ...................................................................................... 49
3.5.1
3.5.2
3.5.3
Initial Setting ........................................................................................................................................... 54
Interrupt acceptance processing............................................................................................................. 54
Saving/restoring general-purpose registers ............................................................................................ 55
3.4
3.5
Maskable Interrupt Priority Change Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.5.3.1
3.5.3.2
3.5.3.3
Using PUSH and POP instructions
Using data transfer instructions
Using a register bank to save/restore general-purpose registers
3.5.4
Interrupt return ........................................................................................................................................ 57
3.6.1
3.6.2
Address error detection .......................................................................................................................... 58
Debugging .............................................................................................................................................. 58
3.6
3.7
Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4. External Interrupt control circuit
4.1
4.2
4.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.3.1
4.3.2
4.3.3
Low power consumption function ........................................................................................................... 63
External interrupt 0 ................................................................................................................................. 64
External interrupts 1/2/3.......................................................................................................................... 64
4.3.3.1
4.3.3.2
4.3.3.3
Interrupt request signal generating condition detection function
A noise canceller pass signal monitoring function when interrupt request signals are generated
Noise cancel time selection function
4.3.4.1
4.3.4.2
4.3.4.3
Interrupt request signal generating condition detection function
A noise canceller pass signal monitoring function when interrupt request signals are generated
Noise cancel time selection function
4.3.4
4.3.5
External interrupt 4 ................................................................................................................................. 65
External interrupt 5 ................................................................................................................................. 67
5. Watchdog Timer (WDT)
5.1
5.2
5.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
Setting of enabling/disabling the watchdog timer operation ...................................................................
Setting the clear time of the 8-bit up counter ..........................................................................................
Setting the overflow time of the 8-bit up counter ....................................................................................
Setting an overflow detection signal of the 8-bit up counter ...................................................................
Writing the watchdog timer control codes ...............................................................................................
Reading the 8-bit up counter ..................................................................................................................
Reading the watchdog timer status ........................................................................................................
71
72
72
73
73
74
74
6. Power-on Reset Circuit
6.1
6.2
ii
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7. Voltage Detection Circuit
7.1
7.2
7.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
Enabling/disabling the voltage detection operation ................................................................................
Selecting the voltage detection operation mode .....................................................................................
Selecting the detection voltage level ......................................................................................................
Voltage detection flag and voltage detection status flag.........................................................................
Selecting the STOP mode release signal ...............................................................................................
7.4.1
7.4.2
Setting procedure when the operation mode is set to generate voltage detection interrupt request signals 81
Setting procedure when the operation mode is set to generate voltage detection reset signals ............ 81
7.4
79
79
79
79
80
Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8. I/O Ports
8.1
8.2
8.3
I/O Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
List of I/O Port Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
I/O Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.4
8.5
Port P0 (P03 to P00)............................................................................................................................... 88
Port P1 (P13 to P10)............................................................................................................................... 92
Port P2 (P27 to P20)............................................................................................................................... 95
Port P4 (P47 to P40)............................................................................................................................... 99
Port P7 (P77 to P70)............................................................................................................................. 102
Port P8 (P83 to P80)............................................................................................................................. 104
Port P9 (P91 to P90)............................................................................................................................. 106
Port PB (PB7 to PB4) ........................................................................................................................... 109
Serial Interface Selecting Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9. Special Function Registers
9.1
9.2
9.3
SFR1 (0x0000 to 0x003F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SFR2 (0x0F00 to 0x0FFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SFR3 (0x0E40 to 0x0EFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10. Low Power Consumption Function for Peripherals
10.1
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
11. Divider Output (DVO)
11.1
11.2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.2.1
Function .............................................................................................................................................. 125
12. Time Base Timer (TBT)
12.1
Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
iii
12.1.1
12.1.2
12.1.3
Configuration ...................................................................................................................................... 127
Control ................................................................................................................................................ 127
Functions ............................................................................................................................................ 128
13. 16-bit Timer Counter (TCA)
13.1
13.2
13.3
13.4
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Power Consumption Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.1
Setting
Operation
Auto capture
Register buffer configuration
13.4.2.1
13.4.2.2
13.4.2.3
13.4.2.4
Setting
Operation
Auto capture
Register buffer configuration
13.4.3.1
13.4.3.2
13.4.3.3
13.4.3.4
Setting
Operation
Auto capture
Register buffer configuration
13.4.4.1
13.4.4.2
13.4.4.3
13.4.4.4
Setting
Operation
Auto capture
Register buffer configuration
13.4.5.1
13.4.5.2
Setting
Operation
13.4.6.1
13.4.6.2
13.4.6.3
Setting
Operation
Register buffer configuration
13.4.3
13.4.4
13.4.5
13.4.6
13.5
Timer mode......................................................................................................................................... 138
13.4.1.1
13.4.1.2
13.4.1.3
13.4.1.4
13.4.2
132
133
137
138
External trigger timer mode ................................................................................................................ 142
Event counter mode............................................................................................................................ 144
Window mode ..................................................................................................................................... 146
Pulse width measurement mode ........................................................................................................ 148
Programmable pulse generate (PPG) mode ...................................................................................... 150
Noise Canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
13.5.1
Setting................................................................................................................................................. 153
14. 8-bit Timer Counter (TC0)
14.1
14.2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
14.2.1
14.2.2
14.2.3
14.2.4
Timer counter 00.................................................................................................................................
Timer counter 01.................................................................................................................................
Common to timer counters 00 and 01 ................................................................................................
Operation modes and usable source clocks .......................................................................................
14.4.1
8-bit timer mode .................................................................................................................................. 165
14.3
14.4
Low Power Consumption Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
14.4.1.1
14.4.1.2
14.4.1.3
Setting
Operation
Double buffer
14.4.2.1
14.4.2.2
14.4.2.3
Setting
Operation
Double buffer
14.4.3.1
14.4.3.2
14.4.3.3
Setting
Operations
Double buffer
14.4.4.1
14.4.4.2
Setting
Operation
14.4.2
14.4.3
14.4.4
iv
157
159
161
163
8-bit event counter mode .................................................................................................................... 168
8-bit pulse width modulation (PWM) output mode .............................................................................. 170
8-bit programmable pulse generate (PPG) output mode .................................................................... 175
14.4.4.3
Double buffer
14.4.5.1
14.4.5.2
14.4.5.3
Setting
Operations
Double buffer
14.4.6.1
14.4.6.2
14.4.6.3
Setting
Operations
Double buffer
14.4.7.1
14.4.7.2
14.4.7.3
Setting
Operations
Double buffer
14.4.8.1
14.4.8.2
14.4.8.3
Setting
Operations
Double buffer
14.4.5
16-bit timer mode ................................................................................................................................ 178
14.4.6
16-bit event counter mode .................................................................................................................. 182
14.4.7
12-bit pulse width modulation (PWM) output mode ............................................................................ 184
14.4.8
16-bit programmable pulse generate (PPG) output mode .................................................................. 190
15. Real Time Clock (RTC)
15.1
15.2
15.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.3.1
15.3.2
15.3.3
Low Power Consumption Function ..................................................................................................... 194
Enabling/disabling the real time clock operation................................................................................. 194
Selecting the interrupt generation interval .......................................................................................... 194
15.4.1
15.4.2
Enabling the real time clock operation ................................................................................................ 195
Disabling the real time clock operation ............................................................................................... 195
15.4
Real Time Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
16. Asynchronous Serial Interface (UART)
16.1
16.2
16.3
16.4
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Low Power Consumption Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Protection to Prevent UART0CR1 and UART0CR2 Registers from Being Changed
204
Activation of STOP, IDLE0 or SLEEP0 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 205
16.5
16.5.1
16.5.2
Transition of register status ................................................................................................................ 205
Transition of TXD pin status ............................................................................................................... 205
16.8.1
Transfer baud rate calculation method ............................................................................................... 208
16.6
16.7
16.8
Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Infrared Data Format Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Transfer Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
16.8.1.1
16.8.1.2
Bit width adjustment using UART0CR2<RTSEL>
Calculation of set values of UART0CR2<RTSEL> and UART0DR
16.9 Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
16.10 Received Data Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
16.11 Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
16.11.1
16.11.2
Data transmit operation .................................................................................................................... 214
Data receive operation...................................................................................................................... 214
16.12.1
16.12.2
16.12.3
16.12.4
16.12.5
16.12.6
Parity error ........................................................................................................................................
Framing Error....................................................................................................................................
Overrun error ....................................................................................................................................
Receive Data Buffer Full...................................................................................................................
Transmit busy flag ...........................................................................................................................
Transmit Buffer Full ..........................................................................................................................
16.12
16.13
Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
215
216
217
220
221
221
Receiving Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
v
16.14
AC Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
16.14.1
IrDA properties.................................................................................................................................. 224
17. Synchronous Serial Interface (SIO)
17.1
17.2
17.3
17.4
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Power Consumption Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.1
17.4.2
17.4.3
Transfer format ................................................................................................................................... 231
Serial clock ......................................................................................................................................... 231
Transfer edge selection ...................................................................................................................... 231
17.5.1
8-bit transmit mode ............................................................................................................................. 233
17.5
Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
17.5.1.1
17.5.1.2
17.5.1.3
17.5.1.4
17.5.1.5
Setting
Starting the transmit operation
Transmit buffer and shift operation
Operation on completion of transmission
Stopping the transmit operation
17.5.2.1
17.5.2.2
17.5.2.3
17.5.2.4
Setting
Starting the receive operation
Operation on completion of reception
Stopping the receive operation
17.5.3.1
17.5.3.2
17.5.3.3
17.5.3.4
17.5.3.5
Setting
Starting the transmit/receive operation
Transmit buffer and shift operation
Operation on completion of transmission/reception
Stopping the transmit/receive operation
17.5.2
17.5.3
17.6
226
227
230
231
8-bit Receive Mode ............................................................................................................................. 238
8-bit transmit/receive mode ................................................................................................................ 242
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
18. Serial Bus Interface (SBI)
18.1
Communication Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
18.1.1
18.1.2
18.2
18.3
18.4
I2C bus ............................................................................................................................................... 249
Free data format ................................................................................................................................. 250
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
18.4.1 Low Power Consumption Function ..................................................................................................... 255
18.4.2 Selecting the slave address match detection and the GENERAL CALL detection............................. 256
18.4.3 Selecting the number of clocks for data transfer and selecting the acknowledgement or non-acknowledgment
mode ........................................................................................................................................................... 256
18.4.3.1
18.4.3.2
Number of clocks for data transfer
Output of an acknowledge signal
18.4.4.1
18.4.4.2
Clock source
Clock synchronization
18.4.4
18.4.5
18.4.6
18.4.7
18.4.8
18.4.9
18.4.10
18.4.11
18.4.12
18.4.13
18.4.14
18.4.15
18.5
vi
Serial clock ......................................................................................................................................... 258
Master/slave selection ........................................................................................................................
Transmitter/receiver selection.............................................................................................................
Start/stop condition generation ...........................................................................................................
Interrupt service request and release .................................................................................................
Setting of serial bus interface mode ...................................................................................................
Software reset...................................................................................................................................
Arbitration lost detection monitor ......................................................................................................
Slave address match detection monitor............................................................................................
GENERAL CALL detection monitor ..................................................................................................
Last received bit monitor...................................................................................................................
Slave address and address recognition mode specification .............................................................
260
260
261
262
262
262
263
264
265
265
265
Data Transfer of I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
18.5.1
18.5.2
18.5.3
Device initialization ............................................................................................................................. 266
Start condition and slave address generation..................................................................................... 266
1-word data transfer............................................................................................................................ 267
18.5.3.1
18.5.3.2
18.5.4
18.5.5
18.6
When SBI0SR2<MST> is "1" (Master mode)
When SBI0SR2<MST> is "0" (Slave mode)
Stop condition generation ................................................................................................................... 271
Restart ................................................................................................................................................ 271
AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
19. Key-on Wakeup (KWU)
19.1
19.2
19.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
20. 10-bit AD Converter (ADC)
20.1
20.2
20.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
20.3.1
20.3.2
20.3.3
Single mode........................................................................................................................................ 284
Repeat mode ...................................................................................................................................... 284
AD operation disable and forced stop of AD operation....................................................................... 285
20.7.1
20.7.2
20.7.3
Analog input pin voltage range ........................................................................................................... 288
Analog input pins used as input/output ports ...................................................................................... 288
Noise countermeasure........................................................................................................................ 288
20.4
20.5
20.6
20.7
Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Starting STOP/IDLE0/SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . .
Precautions about the AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
286
286
287
288
21. Flash Memory
21.1
21.2
Flash Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
21.2.1
21.2.2
21.2.3
21.2.4
21.2.5
21.2.6
Flash memory command sequence execution and toggle control (FLSCR1 <FLSMD>) ...................
Flash memory area switching (FLSCR1<FAREA>)............................................................................
RAM area switching (SYSCR3<RAREA>)..........................................................................................
BOOTROM area switching (FLSCR1<BAREA>)................................................................................
Flash memory standby control (FLSSTB<FSTB>) .............................................................................
Port input control register (SPCR<PIN0, PIN1>) ................................................................................
293
294
295
295
296
297
21.3.1
21.3.2
21.3.3
21.3.4
21.3.5
21.3.6
Byte program ......................................................................................................................................
Sector erase (4-kbyte partial erase) ...................................................................................................
Chip erase (all erase) .........................................................................................................................
Product ID entry ..................................................................................................................................
Product ID exit ....................................................................................................................................
Security program ................................................................................................................................
298
299
299
300
300
300
21.5.1
Flash memory control in serial PROM mode ...................................................................................... 301
21.3
21.4
21.5
Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Toggle Bit (D6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Access to the Flash Memory Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
21.5.1.1
How to transfer and write a control program to the RAM area in RAM loader mode of the serial PROM mode
21.5.2.1
21.5.2.2
How to write to the flash memory by transferring a control program to the RAM area
How to write to the flash memory by using a support program (API) of BOOTROM
21.5.2
Flash memory control in MCU mode .................................................................................................. 304
vii
22. Serial PROM Mode
22.1
22.2
22.3
Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Serial PROM Mode Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
22.3.1
Serial PROM mode control pins ......................................................................................................... 310
22.6.1
22.6.2
SIO communication ............................................................................................................................ 314
UART communication ......................................................................................................................... 314
22.8.1
Flash memory erase command (0xF0) ............................................................................................... 319
22.4
22.5
22.6
Example Connection for On-board Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Activating the Serial PROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
22.7
22.8
Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Operation Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
22.8.1.1
22.8.2
22.8.3
22.8.4
22.8.5
22.8.6
22.8.7
Specifying the erase area
Flash memory write command (operation command: 0x30)...............................................................
Flash memory read command (operation command: 0x40) ...............................................................
RAM loader command (operation command: 0x60) ...........................................................................
Flash memory SUM output command (operation command: 0x90) ...................................................
Product ID code output command (operation command: 0xC0).........................................................
Flash memory status output command (0xC3) ...................................................................................
22.8.7.1
322
324
326
328
329
331
Flash memory status code
22.8.8
22.8.9
Mask ROM emulation setting command (0xD0) ................................................................................. 334
Flash memory security setting command (0xFA)................................................................................ 335
22.10.1
22.10.2
Calculation method ........................................................................................................................... 337
Calculation data ................................................................................................................................ 337
22.12.1
Passwords ........................................................................................................................................ 339
22.9 Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
22.10 Checksum (SUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
22.11
22.12
Intel Hex Format (Binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
22.12.1.1
22.12.1.2
22.12.1.3
22.12.1.4
How a password can be specified
Password structure
Password setting, cancellation and authentication
Password values and setting range
22.12.2.1
22.12.2.2
How the security program functions
Enabling or disabling the security program
22.12.2
Security program .............................................................................................................................. 343
22.12.3
22.12.4
Option codes..................................................................................................................................... 344
Recommended settings .................................................................................................................... 346
22.14.1
22.14.2
22.14.3
22.14.4
22.14.5
22.14.6
22.14.7
22.14.8
22.14.9
22.14.10
Reset timing ......................................................................................................................................
Flash memory erase command (0xF0) .............................................................................................
Flash memory write command (0x30)...............................................................................................
Flash memory read command (0x40) ...............................................................................................
RAM loader command (0x60) ...........................................................................................................
Flash memory SUM output command (0x90) ...................................................................................
Product ID code output command (0xC0) ........................................................................................
Flash memory status output command (0xC3) .................................................................................
Mask ROM emulation setting command (0xD0) ...............................................................................
Flash memory security setting command (0xFA)............................................................................
22.13
22.14
Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
AC Characteristics (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
349
349
350
350
351
351
351
352
352
352
23. On-chip Debug Function (OCD)
23.1
23.2
23.3
viii
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
How to Connect the On-chip Debug Emulator to a Target System . . . . . . . . . . 354
23.4
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
24. Input/Output Circuit
24.1
Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
25. Electrical Characteristics
25.1
25.2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
25.2.1
25.2.2
25.2.3
25.3
25.4
25.5
25.6
25.7
MCU mode (Flash Programming or erasing) ...................................................................................... 358
MCU mode (Except Flash Programming or erasing) .......................................................................... 359
Serial PROM mode ............................................................................................................................. 360
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-on Reset Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Detecting Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.7.1
25.7.2
25.7.3
MCU mode (Flash programming or erasing) ...................................................................................... 367
MCU mode (Except Flash Programming or erasing) .......................................................................... 367
Serial PROM mode ............................................................................................................................. 368
25.8.1
Write characteristics ........................................................................................................................... 368
25.8
361
364
365
366
367
Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
25.9 Recommended Oscillating Condition- 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
25.10 Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
25.11 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
26. Package Dimensions
ix
x
TMP89FM46
CMOS 8-Bit Microcontroller
TMP89FM46
The TMP89FM46 is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 32768
bytes of Flash Memory. It is pin-compatible with the TMP89CM46 (Mask ROM version). The TMP89FM46 can
realize operations equivalent to those of the TMP89CM46 by programming the on-chip Flash Memory.
Product No.
ROM
(Flash)
RAM
Package
Flash MCU
Emulation Chip
TMP89FM46DUG
32768 bytes
2048 bytes
LQFP48-P-0707-0.50D
* TMP89CM46DUG
* TMP89C900XBG
Note :
* ; Under development
1.1 Features
1. 8-bit single chip microcomputer TLCS-870/C1 series
- Instruction execution time :
100 ns (at 10 MHz)
122 µs (at 32.768 kHz)
- 133 types & 732 basic instructions
2. 25 interrupt sources (External : 6 Internal : 19 , Except reset)
3. Input / Output ports (42 pins)
Note : Two of above pins can not be used for the I/O port, because they should be connected with the high frequency OSC input.
Large current output: 8 pins (Typ. 20mA)
4. Watchdog timer
- Interrupt or reset can be selected by the program.
5. Power-on reset circuit
6. Voltage detection circuit
7. Divider output function
8. Time base timer
9. 16-bit timer counter : 2 ch
- Timer, External trigger, Event Counter, Window, Pulse width measurement, PPG OUTPUT modes
This product uses the Super Flash® technology under the licence of Silicon Storage Technology, Inc. Super Flash® is registered trademark of Silicon Storage
Technology, Inc.
• The information contained herein is subject to change without notice. 021023_D
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when
utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations
in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither
intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of
which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's
own risk. 021023_B
• The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or
sale are prohibited under any applicable laws and regulations. 060106_Q
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C
• The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and
Reliability Assurance/Handling Precautions. 030619_S
RA000
Page 1
1.1 Features
TMP89FM46
10. 8-bit timer counter: 4 ch
- Timer, Event Counter, PWM, PPG OUTPUT modes
- Usable as a 16-bit timer, 12-bit PWM output and 16-bit PPG output by the cascade connection of two
channels.
11. Real time clock
12. UART : 1ch
13. UART/SIO : 1ch Note : One SIO channel can be used at the same time.
14. I2C/SIO : 1ch
15. Key-on wake-up : 8 ch
16. 10-bit successive approximation type AD converter
- Analog input : 8ch
17. On-chip debug function
- Break/Event
- Trace
- RAM monitor
- Flash memory writing
18. Clock operation mode control circuit : 2 circuit
Single clock mode / Dual clock mode
19. Low power consumption operation (8 mode)
- STOP mode:
Oscillation stops. (Battery/Capacitor back-up.)
- SLOW1 mode:
Low power consumption operation using low-frequency clock.(High-frequency clock stop.)
- SLOW2 mode:
Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.)
- IDLE0 mode:
CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock.
Released when the reference time set to TBT has elapsed.
- IDLE1 mode:
The CPU stops, and peripherals operate using high frequency clock. Release by interruputs(CPU
restarts).
- IDLE2 mode:
CPU stops and peripherals operate using high and low frequency clock. Release by interruputs. (CPU
restarts).
- SLEEP0 mode:
CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low frequency clock.
Released when the reference time set to TBT has elapsed.
- SLEEP1 mode:
CPU stops, and peripherals operate using low frequency clock. Release by interruput.(CPU restarts).
20. Wide operation voltage:
4.3 V to 5.5 V at 10MHz /32.768 kHz
2.7 V to 5.5 V at 4.2 MHz /32.768 kHz
2.2 V to 5.5 V at 2MHz /32.768 kHz
RA000
Page 2
TMP89FM46
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
37
38
39
40
41
42
43
44
45
46
47
48
P41 (AIN1/KWI1)
P40 (AIN0/KWI0)
VAREF
AVDD
AVSS
P27
P26
P25 (SCLK0)
P24 (SCL0/SI0)
P23 (SDA0/SO0)
P22 (SCLK0)
P21 (RXD0/TXD0/SI0/OCDIO)
VSS
(XIN) P00
(XOUT) P01
MODE
VDD
(XTIN) P02
(XTOUT) P03
(RESET) P10
(STOP/INT5) P11
(INT0) P12
(INT1) P13
(OCDCK/SO0/RXD0/TXD0) P20
(PWM02/PPG02/TC02) P80
(PWM03/PPG03/TC03) P81
P82
P83
(PWM00/PPG00/TC00) P70
(PWM01/PPG01/TC01) P71
(PPGA0/TCA0) P72
(PPGA1/TCA1) P73
(SO0/RXD0/TXD0) PB4
(SI0/TXD0/RXD0) PB5
(SCLK0) PB6
PB7
36
35
34
33
32
31
30
29
28
27
26
25
P91 (RXD1/TXD1)
P90 (TXD1/RXD1)
P77 (INT4)
P76 (INT3)
P75 (INT2)
P74 (DVO)
P47 (AIN7/KWI7)
P46 (AIN6/KWI6)
P45 (AIN5/KWI5)
P44 (AIN4/KWI4)
P43 (AIN3/KWI3)
P42 (AIN2/KWI2)
1.2 Pin Assignment
Figure 1-1 Pin Assignment
RA000
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1.3 Block Diagram
TMP89FM46
1.3 Block Diagram
Figure 1-2 Block Diagram
RA000
Page 4
TMP89FM46
1.4 Pin Names and Functions
The TMP89FM46 has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pin functions in MCU mode. The serial PROM mode is explained later in a separate chapter.
Table 1-1 Pin Names and Functions(1/3)
Pin Name
Functions
P03
XTOUT
IO
O
PORT03
Low frequency OSC output
P02
XTIN
IO
I
PORT02
Low frequency OSC input
P01
XOUT
IO
O
PORT01
High frequency OSC output
P00
XIN
IO
I
PORT00
High frequency OSC input
P13
INT1
IO
I
PORT13
External interrupt 1 input
P12
IO
I
PORT12
External interrupt 0 input
IO
I
I
PORT11
External interrupt 5 input
STOP mode release input
RESET
IO
I
PORT10
Reset signal input
P27
IO
PORT27
P26
IO
PORT26
P25
SCLK0
IO
IO
PORT25
Serial clock input/output 0
P24
SCL0
SI0
IO
IO
I
PORT24
I2C bus clock input/output 0
Serial data input 0
P23
SDA0
SO0
IO
IO
O
PORT23
I2C bus data input/output 0
Serial data output 0
P22
SCLK0
IO
IO
PORT22
Serial clock input/output 0
P21
RXD0
TXD0
SI0
OCDIO
IO
I
O
I
IO
PORT21
UART data input 0
UART data output 0
Serial data input 0
OCD data input/output
P20
TXD0
RXD0
SO0
OCDCK
IO
O
I
O
I
PORT20
UART data output 0
UART data input 0
Serial data output 0
OCD clock input
P47
AIN7
KWI7
IO
I
I
PORT47
Analog input 7
Key-on wake-up input 7
P46
AIN6
KWI6
IO
I
I
PORT46
Analog input 6
Key-on wake-up input 6
INT0
P11
INT5
STOP
P10
RA000
Input/Output
Page 5
1.4 Pin Names and Functions
TMP89FM46
Table 1-1 Pin Names and Functions(2/3)
Pin Name
Functions
P45
AIN5
KWI5
IO
I
I
PORT45
Analog input 5
Key-on wake-up input 5
P44
AIN4
KWI4
IO
I
I
PORT44
Analog input 4
Key-on wake-up input 4
P43
AIN3
KWI3
IO
I
I
PORT43
Analog input 3
Key-on wake-up input 3
P42
AIN2
KWI2
IO
I
I
PORT42
Analog input 2
Key-on wake-up input 2
P41
AIN1
KWI1
IO
I
I
PORT41
Analog input 1
Key-on wake-up input 1
P40
AIN0
KWI0
IO
I
I
PORT40
Analog input 0
Key-on wake-up input 0
P77
INT4
IO
I
PORT77
External interrupt 4 input
P76
INT3
IO
I
PORT76
External interrupt 3 input
P75
INT2
IO
I
PORT75
External interrupt 2 input
P74
IO
O
PORT74
Divider output
IO
I
O
PORT73
TCA1 input
PPGA1 output
IO
I
O
PORT72
TCA0 input
PPGA0 output
IO
I
O
O
PORT71
TC01 input
PPG01 output
PWM01 output
PWM00
IO
I
O
O
PORT70
TC00 input
PPG00 output
PWM00 output
P83
IO
PORT83
P82
IO
PORT82
P81
TC03
IO
I
O
O
PORT81
TC03 input
PPG03 output
PWM03 output
IO
I
O
O
PORT80
TC02 input
PPG02 output
PWM02 output
DVO
P73
TCA1
PPGA1
P72
TCA0
PPGA0
P71
TC01
PPG01
PWM01
P70
TC00
PPG00
PPG03
PWM03
P80
TC02
PPG02
PWM02
RA000
Input/Output
Page 6
TMP89FM46
Table 1-1 Pin Names and Functions(3/3)
Pin Name
RA000
Input/Output
Functions
P91
RXD1
TXD1
IO
I
O
PORT91
UART data input 1
UART data output 1
P90
TXD1
RXD1
IO
O
I
PORT90
UART data output 1
UART data input 1
PB7
IO
PORTB7
PB6
SCLK0
IO
IO
PORTB6
Serial clock input/output 0
PB5
RXD0
TXD0
SI0
IO
I
O
I
PORTB5
UART data input 0
UART data output 0
Serial data input 0
PB4
TXD0
RXD0
SO0
IO
O
I
O
PORTB4
UART data output 0
UART data input 0
Serial data output 0
MODE
I
Test pin for out-going test (fix to Low level).
VAREF
I
Analog reference voltage input pin for A/D conversion.
AVDD
I
Analog power supply pin.
AVSS
I
Analog GND pin
VDD
I
VDD pin
VSS
I
GND pin
Page 7
1.4 Pin Names and Functions
RA000
TMP89FM46
Page 8
TMP89FM46
2. CPU Core
2.1 Configuration
The CPU core consists of a CPU, a system clock controller and a reset circuit.
This chapter describes the CPU core address space, the system clock controller and the reset circuit.
2.2 Memory space
The 870/C1 CPU memory space consists of a code area to be accessed as instruction operation codes and operands
and a data area to be accessed as sources and destinations of transfer and calculation instructions.
Both the code and data areas have independent 64-Kbyte address spaces.
2.2.1
Code area
The code area stores operation codes, operands, vector tables for vector call instructions and interrupt vector
tables.
The RAM, the BOOTROM and the Flash are mapped in the code area.
0x0000
SWI instruction
(0xFF) is fetched.
0x003F
0x0040
RAM
(2048 bytes)
0x083F
SWI instruction
(0xFF) is fetched.
0x17FF
0x1800
0xFFA0
0xFFBF
0xFFCC
0xFFFF
SWI instruction
(0xFF) is fetched.
SWI instruction
(0xFF) is fetched.
0x1000
0x7FFF
0x8000
SWI instruction
(0xFF) is fetched.
RAM
(2048 bytes)
SWI instruction
(0xFF) is fetched.
BOOTROM
(2048 bytes)
BOOTROM
(2048 bytes)
Flash
(32768 bytes)
Flash
(32768 bytes)
Flash
(32768 bytes)
Flash
(32768 bytes)
Vector table for vector call instructions
(32 bytes)
Vector table for vector call instructions
(32 bytes)
Vector table for vector call instructions
(32 bytes)
Vector table for vector call instructions
(32 bytes)
Interrupt vector
table
(52 bytes)
Interrupt vector
table
(52 bytes)
Interrupt vector
table
(52 bytes)
Interrupt vector
table
(52 bytes)
Immediately after reset release
When the RAM is
mapped in the code
area
When the
BOOTROM is
mapped in the code
area
When the RAM and
the BOOTROM are
mapped in the code
area
Note: Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM mode.
Figure 2-1 Memory Map in the Code Area
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Page 9
2. CPU Core
2.2 Memory space
TMP89FM46
2.2.1.1
RAM
The RAM is mapped in the data area immediately after reset release.
By setting SYSCR3<RAREA> to "1" and writing 0xD4 to SYSCR4, RAM can be mapped to 0x0040to
0x083F in the code area to execute the program.
At this time, by setting SYSCR<RVCTR> to "1" and writing 0xD4 to SYSCR4, vector table for vector
call instructions and interrupt except reset can be mapped to RAM.
In the serial PROM mode, the RAM is mapped to 0x0040 to 0x083F in the code area, regardless of the
value of SYSCR3<RAREA>. The program can be executed on the RAM using the RAM loader function.
Note 1: When the RAM is not mapped in the code area, the SWI instruction is fetched from 0x0040 to 0x083F.
Note2:
The contents of the RAM become unstable when the power is turned on and immediately after a reset
is released. To execute the program by using the RAM, transfer the program to be executed in the
initialization routine.
System control register 3
SYSCR3
(0x0FDE)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
-
RVCTR
RAREA
(RSTDIS)
Read/Write
R
R
R
R
R
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
RAREA
RVCTR
Specifies mapping of the RAM in
the code area
Specifies mapping of the vector
table for vector call instructions
and interrupts
0:
The RAM is not mapped from 0x0040 to 0x083F in the code area.
1:
The RAM is mapped from 0x0040 to 0x083F in the code area.
0:
1:
Vector table for vector call instructions
Vector table for interrupt
0xFFA0 to 0xFFBF in the code area
0xFFC8 to 0xFFFF in the code
area
0x01A0 to 0x01BF in the code area
0x01C8 to 0x01FD in the code area
Note 1: The value of SYSCR3<RAREA> is invalid until 0xD4 is written into SYSCR4.
Note 2: To assign vector address areas to RAM, set SYSCR3<RVCTR> to "1" and SYSCR3<RAREA> to "1".
Note 3: Do not set SYSCR3<RVCTR> to "0" by using the RAM loader program. If an interrupt occurs with SYSCR3<RVCTR> set
to "0", the BOOTROM area is referenced as a vector address and, therefore, the program will not function properly.
Note 4: Bits 7 to 3 of SYSCR3 are read as "0".
System control register 4
SYSCR4
(0x0FDF)
7
6
5
4
Bit Symbol
Read/Write
After reset
SYSCR4
3
2
1
0
0
0
0
0
SYSCR4
W
0
0
Writes the SYSCR3 data control
code.
0
0xB2 :
0xD4 :
0x71 :
0
Enables the contents of SYSCR3<RSTDIS>.
Enables the contents of SYSCR3<RAREA> and SYSCR3 <RVCTR>.
Enables the contents of IRSTSR<FCLR>
Others : Invalid
Note 1: SYSCR4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit operation.
Note 2: After SYSCR3<RSTDIS> is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3<RSTDIS>) in NORMAL
mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, SYSCR3<RSTDIS> may be enabled at unexpected timing.
Note 3: After IRSTSR<FCLR> is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR<FCLR> in NORMAL mode
when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> may be enabled at unexpected timing.
RA001
Page 10
TMP89FM46
System control status register 4
SYSSR4
(0x0FDF)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
-
RVCTRS
RAREAS
(RSTDIS)
Read/Write
R
R
R
R
R
R
R
R
After reset
0
0
0
0
0
0
0
0
RAREAS
Status of mapping of the RAM in the
code area
0:
1:
The enabled SYSCR3<RAREA> data is "0".
The enabled SYSCR3<RAREA> data is "1".
RVCTRS
Status of mapping of the vector
address in the area
0:
1:
The enabled SYSCR3<RVCTR> data is "0".
The enabled SYSCR3<RVCTR> data is "1".
Note: Bits 7 to 3 of SYSSR4 are read as "0".
Example: Program transfer (Transfer the program saved in the data area to the RAM.)
TRANS_RAM:
2.2.1.2
LD
HL, TRANSFER_START_ADDRESS
; Destination RAM address
LD
DE, PROGRAM_START_ADDRESS
; Source ROM address
LD
BC, BYTE_OF_PROGRAM
; Number of bytes of the program to be executed -1
LD
A, (DE)
; Reading the program to be transferred
LD
(HL), A
; Writing the program to be transferred
INC
HL
; Destination address increment
INC
DE
; Source address increment
DEC
BC
; Have all the programs been transferred?
JRS
F, TRANS_RAM
BOOTROM
The BOOTROM is not mapped in the code area or the data area after reset release.
Setting FLSMD<BAREA> to "1" maps the BOOTROM to 0x1000 to 0x17FF in the code area and to
0x1000 to 0x17FF in the data area. The BOOTROM can be easily written into the Flash by using the Application Programming Interface (API) integrated in the BOOTROM.
Note 1: When the BOOTROM is not mapped in the code area, an instruction is fetched from the Flash or an
SWI instruction is fetched, depending on the capacity of the internal Flash.
Note 2: Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM
mode.
Flash memory control register 1
FLSCR1
(0x0FD0)
7
Bit Symbol
Read/Write
After reset
BAREA
6
5
4
(FLSMD)
R/W
0
1
Specifies mapping of the
BOOTROM in the code and data
areas
3
BAREA
R/W
0
0
0:
1:
2
1
(FAREA)
R/W
0
0
(ROMSEL)
R/W
0
0
0
The BOOTROM is not mapped to 0x1000 to 0x17FF in the code area and
to 0x1000 to 0x17FF in the data area.
The BOOTROM is mapped to 0x1000 to 0x17FF in the code area and to
0x1000 to 0x17FF in the data area.
Note: The flash memory control register 1 has a double-buffer structure comprised of the register FLSCR1 and a shift register.
Writing "0xD5" to the register FLSCR2 allows a register setting to be reflected and take effect in the shift register. This
means that a register setting value does not take effect until "0xD5" is written to the register FLSCR2. The value of the shift
register can be checked by reading the register FLSCRM.
RA001
Page 11
2. CPU Core
2.2 Memory space
TMP89FM46
Flash memory control register 2
FLSCR2
7
(0x0FD1)
5
4
Bit Symbol
CR1EN
Read/Write
W
After reset
CR1EN
2.2.1.3
6
*
*
FLSCR1 register
enable/disable control
*
*
0xD5
Others
3
2
1
0
*
*
*
*
Enable a change in the FLSCR1 setting
Reserved
Flash
The Flash is mapped to 0x8000 to 0xFFFF in the code area after reset release.
2.2.2
Data area
The data area stores the data to be accessed as sources and destinations of transfer and calculation instructions.
The SFR, the RAM, the BOOTROM and the FLASH are mapped in the data area.
0x0000
0x003F
0x0040
0x083F
0x0E40
0x0EFF
0x0F00
0x0FFF
0x1000
SFR1
(64 bytes)
SFR1
(64 bytes)
RAM
(2048 bytes)
RAM
(2048 bytes)
0xFF is read
0xFF is read
SFR3
(192 bytes)
SFR3
(192 bytes)
SFR2
(256 bytes)
SFR2
(256 bytes)
BOOTROM
(2048 bytes)
0x17FF
0x1800
0x7FFF
0x8000
0xFF is read
0xFF is read
Flash
(32768 bytes)
Flash
(32768 bytes)
Immediately after reset release
When the
BOOTROM is
mapped in the data
area
0xFFFF
Note: Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM mode.
Figure 2-2 Memory Map in the Data Area
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Page 12
TMP89FM46
2.2.2.1
SFR
The SFR is mapped to 0x0000 to 0x003F (SFR1), 0x0F00 to 0x0FFF (SFR2) and 0x0E40 to 0x0EFF
(SFR3) in the data area after reset release.
Note: Don't access the reserved SFR.
2.2.2.2
RAM
The RAM is mapped to 0x0040 to 0x083F in the data area after reset release.
Note: The contents of the RAM become unstable when the power is turned on and immediately after a reset
is released. To execute the program by using the RAM, transfer the program to be executed in the initialization routine.
Example: RAM initialization program
CLR_RAM:
2.2.2.3
LD
HL, RAM_TOP_ADDRESS
; Head of address of the RAM to be initialized
LD
A, 0x00
; Initialization data
LD
BC, BYTE_OF_CLEAR_BYTES
; Number of bytes of RAM to be initialized -1
LD
(HL), A
; Initialization of the RAM
INC
HL
; Initialization address increment
DEC
BC
; Have all the RAMs been initialized?
JRS
F, CLR_RAM
BOOTROM
The BOOTROM is not mapped in the code area or the data area after reset release.
Setting FLSMD<BAREA> to "1" maps the BOOTROM to 0x1000 to 0x17FF in the code area and to
0x1000 to 0x17FF in the data area. The BOOTROM can be easily written into the Flash by using the Application Programming Interface (API) integrated in the BOOTROM.
Note 1: When the BOOTROM is not mapped in the data area, 0xFF is read from 0x1000 to 0x17FF.
Note2:
Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM
mode.
Flash memory control register 1
FLSCR1
(0x0FD0)
7
6
5
4
3
2
1
0
Bit Symbol
(FLSMD)
BAREA
(FAREA)
(ROMSEL)
Read/Write
R/W
R/W
R/W
R/W
After reset
BAREA
0
1
0
0
0:
Specifies mapping of the
BOOTROM in the code and data
areas
1:
0
0
0
0
The BOOTROM is not mapped to 0x1000 to 0x17FF in the code area and
to 0x1000 to 0x17FF in the data area.
The BOOTROM is mapped to 0x1000 to 0x17FF in the code area and to
0x1000 to 0x17FF in the data area.
Note: The flash memory control register 1 has a double-buffer structure comprised of the register FLSCR1 and a shift register.
Writing "0xD5" to the register FLSCR2 allows a register setting to be reflected and take effect in the shift register. This
means that a register setting value does not take effect until "0xD5" is written to the register FLSCR2. The value of the shift
register can be checked by reading the register FLSCRM.
Flash memory control register 2
FLSCR2
(0x0FD1)
7
6
5
4
Bit Symbol
Read/Write
After reset
RA001
3
2
1
0
*
*
*
*
CR1EN
W
*
*
*
*
Page 13
2. CPU Core
2.2 Memory space
TMP89FM46
CR1EN
2.2.2.4
FLSCR1 register
enable/disable control
0xD5
Others
Enable a change in the FLSCR1 setting
Reserved
Flash
The Flash is mapped to 0x8000 to 0xFFFF in the data area after reset release.
RA001
Page 14
TMP89FM46
2.3 System clock controller
2.3.1
Configuration
The system clock controller consists of a clock generator, a clock gear, a timing generator, a warm-up
counter and an operation mode control circuit.
WUCCR
WUCDR
Warm-up counter
INTWUC interrupt
XEN/XTEN
STOP
TBTCR
Clock generator
SYSCR1
SYSCR2
DV9CK
XIN
fc
High-frequency
clock oscillation
circuit
fcgck
Clock gear
(x1/4,x1/2,x1)
Operation mode
control circuit
Timing
generator
XOUT
FCGCKSEL
System control register
Clock gear control register
XTIN
System clock
fs
Low-frequency clock
oscillation circuit
1/4
XTOUT
Oscillation/stop control
Figure 2-3 System Clock Controller
2.3.2
Control
The system clock controller is controlled by system control register 1 (SYSCR1), system control register 2
(SYSCR2), the warm-up counter control register (WUCCR), the warm-up counter data register (WUCDR) and
the clock gear control register (CGCR).
System control register 1
SYSCR1
(0x0FDC)
7
6
5
4
2
1
0
Bit Symbol
STOP
RELM
OUTEN
DV9CK
-
-
-
-
Read/Write
R/W
R/W
R/W
R/W
R
R
R
R
After reset
0
0
0
0
1
0
0
0
0:
1:
Operate the CPU and the peripheral circuits
Stop the CPU and the peripheral circuits (activate the STOP mode)
0:
Edge-sensitive release mode (Release the STOP mode at the rising edge
of the STOP mode release signal)
Level-sensitive release mode (Release the STOP mode at the "H" level of
the STOP mode release signal)
STOP
Activates the STOP mode
RELM
Selects the STOP mode release
method
1:
OUTEN
Selects the port output state in the
STOP mode
0:
1:
High impedance
Output hold
DV9CK
Selects the input clock to stage 9 of
the divider
0:
1:
fcgck/29
fs/4
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Bits 2, 1 and 0 of SYSCR1 are read as "0". Bit 3 is read as "1".
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3
Page 15
2. CPU Core
2.3 System clock controller
TMP89FM46
Note 3: If the STOP mode is activated with SYSCR1<OUTEN> set at "0", the port internal input is fixed to "0". Therefore, an external interrupt may be set at the falling edge, depending on the pin state when the STOP mode is activated.
Note 4: The P11 pin is also used as the STOP pin. When the STOP mode is activated, the pin reverts to high impedance state and
is put in input mode, regardless of the state of SYSCR1<OUTEN>.
Note 5: Writing of the second byte data will be executed improperly if the operation is switched to the STOP state by an instruction, such as LDW, which executes 2-byte data transfer at a time.
Note 6: Don't set SYSCK1<DV9CK> to "1" before the oscillation of the low-frequency clock oscillation circuit becomes stable.
Note 7: In the SLOW1/2 or SLEEP1 mode, fs/4 is input to stage 9 of the divider, regardless of the state of SYSCR1< DV9CK >.
System control register 2
SYSCR2
(0x0FDD)
7
6
5
4
3
2
1
0
Bit Symbol
-
XEN
XTEN
SYSCK
IDLE
TGHALT
-
-
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R
R
After reset
0
1
0
0
0
0
0
0
XEN
Controls the high-frequency clock
oscillation circuit
0:
1:
Stop oscillation
Continue or start oscillation
XTEN
Controls the low-frequency clock
oscillation circuit
0:
1:
Stop oscillation
Continue or start oscillation
Selects a system clock
0:
1:
Gear clock (fcgck) (NORMAL1/2 or IDLE1/2 mode)
Low-frequency clock (fs/4) (SLOW1/2 or SLEEP1 mode)
CPU and WDT control
(IDLE1/2 or SLEEP1 mode)
0:
1:
Operate the CPU and the WDT
Stop the CPU and the WDT (Activate IDLE1/2 or SLEEP1 mode)
0:
1:
Enable the clock supply from the TG to all the peripheral circuits
Disable the clock supply from the TG to the peripheral circuits except the
TBT (Activate IDLE0 or SLEEP0 mode)
SYSCK
IDLE
TGHALT
TG control
(IDLE0 or SLEEP0 mode)
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: WDT: Watchdog timer, TG: Timing generator
Note 3: Don't set both SYSCR2<IDLE> and SYSCR2<TGHALT> to "1" simultaneously.
Note 4: Writing of the second byte data will be executed improperly if the operation is switched to the IDLE state by an instruction,
such as LDW, which executes 2-byte data transfer at a time.
Note 5: When the IDLE1/2 or SLEEP1 mode is released, SYSCR2<IDLE> is cleared to "0" automatically.
Note 6: When the IDLE0 or SLEEP0 mode is released, SYSCR2<TGHALT> is cleared to "0" automatically.
Note 7: Bits 7, 1 and 0 of SYSCR2 are read as "0".
Warm-up counter control register
WUCCR
(0x0FCD)
7
6
5
4
Bit Symbol
WUCRST
-
-
-
Read/Write
W
R
R
R
After reset
0
0
0
0
WUCRST
Resets and stops the warm-up
counter
WUCDIV
Selects the frequency division of the
warm-up counter source clock
WUCSEL
Selects the warm-up counter
source clock
0:
1:
00 :
01 :
10 :
11 :
0:
1:
3
2
WUCDIV
R/W
1
1
1
0
WUCSEL
-
R/W
R
0
1
Clear and stop the counter
Source clock
Source clock / 2
Source clock / 22
Source clock / 23
Select the high-frequency clock (fc)
Select the low-frequency clock (fs)
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz]
Note 2: WUCCR<WUCRST> is cleared to "0" automatically, and need not be cleared to "0" after being set to "1".
Note 3: Bits 7 to 4 of WUCCR are read as "0". Bit 0 is read as "1".
Note 4: Before starting the warm-up counter operation, set the source clock and the frequency division rate at WUCCR and set
the warm-up time at WUCDR.
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TMP89FM46
Warm-up counter data register
7
WUCDR
(0x0FCE)
6
5
4
Bit Symbol
WUCDR
Read/Write
R/W
After reset
0
1
1
0
WUCDR
3
2
1
0
0
1
1
0
1
Warm-up time setting
Note 1: Don't start the warm-up counter operation with WUCDR set at "0x00".
Clock gear control register
CGCR
(0x0FCF)
7
6
5
4
3
2
Bit Symbol
-
-
-
-
-
-
Read/Write
R
R
R
R
R
R
After reset
0
0
0
0
0
0
FCGCKSEL
Clock gear setting
00 :
01 :
10 :
11 :
0
FCGCKSEL
R/W
0
0
fcgck = fc / 4
fcgck = fc / 2
fcgck = fc
Reserved
Note 1: fcgck: Gear clock [Hz], fc: High-frequency clock [Hz]
Note 2: Don't change CGCR<FCGCKSEL> in the SLOW mode.
Note 3: Bits 7 to 2 of CGCR are read as "0".
2.3.3
Functions
2.3.3.1
Clock generator
The clock generator generates the basic clock for the system clocks to be supplied to the CPU core and
peripheral circuits.
It contains two oscillation circuits: one for the high-frequency clock and the other for the low-frequency
clock.
The oscillation circuit pins are also used as ports P0. For the setting to use them as ports, refer to the
chapter of I/O Ports.
To use ports P00 and P01 as the high-frequency clock oscillation circuits (the XIN and XOUT pins), set
P0FC0 to "1" and then set SYSCR2<XEN> to "1".
To use ports P02 and P03 as the low-frequency clock oscillation circuits (the XTIN and XTOUT pins),
set P0FC2 to "1" and then set SYSCR2<XTEN> to "1".
The high-frequency (fc) clock and the low-frequency (fs) clock can easily be obtained by connecting an
oscillator between the XIN and XOUT pins and between the XTIN and XTOUT pins respectively.
Clock input from an external oscillator is also possible. In this case, external clocks are applied to the
XIN/XTIN pins and the XOUT/XTOUT pins are kept open.
Enabling/disabling the oscillation of the high-frequency clock oscillation circuit and the low-frequency
clock oscillation circuit and switching the pin function to ports are controlled by the software and hardware.
The software control is executed by SYSCR2<XEN>, SYSCR2<XTEN> and the P0 port function control register P0FC.
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2. CPU Core
2.3 System clock controller
TMP89FM46
The hardware control is executed by reset release and the operation mode control circuit when the operation is switched to the STOP mode as described in "2.3.5 Operation mode control circuit".
Note: No hardware function is available for external direct monitoring of the basic clock. The oscillation frequency can be adjusted by programming the system to output pulses at a certain frequency to a port
(for example, a clock output) with interrupts disabled and the watchdog timer disabled and monitoring
the output. An adjustment program must be created in advance for a system that requires adjustment of
the oscillation frequency.
To prevent the dead lock of the CPU core due to the software-controlled enabling/disabling of the oscillation, an internal factor reset is generated depending on the combination of values of the clock selected as
the main system clock, SYSCR2<XEN>, SYSCR2<XTEN> and the P0 port function control register
P0FC0.
Table 2-1 Prohibited Combinations of Oscillation Enable Register Conditions
P0FC0
SYSCR2
<XEN>
SYSCR2
<XTEN>
SYSCR2
<SYSCK>
Don't Care
0
0
Don’t Care
Don’t Care
Don’t Care
0
1
The low-frequency clock (fs) is selected as the main system
clock, but the low-frequency clock oscillation circuit is
stopped.
Don’t Care
0
Don’t Care
0
The high-frequency clock (fc) is selected as the main system
clock, but the high-frequency clock oscillation circuit is
stopped.
0
1
Don’t Care
Don’t Care
State
All the oscillation circuits are stopped.
The high-frequency clock oscillation circuit is allowed to
oscillate, but the port is set as a general-purpose port.
Note: It takes a certain period of time after SYSCR2<SYSCK> is changed before the main system clock is
switched. If the currently operating oscillation circuit is stopped before the main system clock is
switched, the internal condition becomes as shown in Table 2-1 and a system clock reset occurs. For
details of clock switching, refer to "2.3.6 Operation Mode Control".
High-frequency clock
XIN
XOUT
XIN
Low-frequency clock
XOUT
XTIN
XTOUT
(Open)
(a) Crystal or ceramic
oscillator
XTIN
XTOUT
(Open)
(b) External oscillator
(c) Crystal oscillator
(d) External oscillator
Figure 2-4 Examples of Oscillator Connection
2.3.3.2
Clock gear
The clock gear is a circuit that selects a gear clock (fcgck) obtained by dividing the high-frequency
clock (fc) and inputs it to the timing generator.
Selects a divided clock at CGCR<FCGCKSEL>.
Two machine cycles are needed after CGCR<FCGCKSEL> is changed before the gear clock (fcgck) is
changed.
The gear clock (fcgck) may be longer than the set clock width, immediately after CGCR<FCGCKSEL>
is changed.
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TMP89FM46
Immediately after reset release, the gear clock (fcgck) becomes the clock that is a quarter of the highfrequency clock (fc).
Table 2-2 Gear Clock (fcgck)
CGCR<FCGCKSEL>
fcgck
00
fc / 4
01
fc / 2
10
fc
11
Reserved
Note: Don't change CGCR<FCGCKSEL> in the SLOW mode. This may stop the gear clock (fcgck) from
being changed.
2.3.3.3
Timing generator
The timing generator is a circuit that generates system clocks to be supplied to the CPU core and the
peripheral circuits, from the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock
(fs). The timing generator has the following functions:
1. Generation of the main system clock (fm)
2. Generation of clocks for the timer counter, the time base timer and other peripheral circuits
Main system clock
fm
Main system clock generator
Machine cycle counter
SYSCR2<SYSCK>
SYSCR1<DV9CK>
Prescaler
Divider
A
Gear clock fcgck
S
Divider
Y
B
Multiplexer
A quarter of the basic clock
for the low-frequency clock
Timer counter, time base timer and other peripheral circuits
Figure 2-5 Configuration of Timing Generator
(1)
Configuration of timing generator
The timing generator consists of a main system clock generator, a prescaler, a 21-stage divider and
a machine cycle counter.
1. Main system clock generator
This circuit selects the gear clock (fcgck) or the clock that is a quarter of the low-frequency
clock (fs) for the main system clock (fm) to operate the CPU core.
Clearing SYSCR2<SYSCK> to "0" selects the gear clock (fcgck). Setting it to "1" selects
the clock that is a quarter of the low-frequency clock (fs).
It takes a certain period of time after SYSCR2<SYSCK> is changed before the main system clock is switched. If the currently operating oscillation circuit is stopped before the main
system clock is switched, the internal condition becomes as shown in Table 2-1 and a system
clock reset occurs. For details of clock switching, refer to "2.3.6 Operation Mode Control".
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2. CPU Core
2.3 System clock controller
TMP89FM46
2. Prescaler and divider
These circuits divide fcgck. The divided clocks are supplied to the timer counter, the time
base timer and other peripheral circuits.
When both SYSCR1<DV9CK> and SYSCR2<SYSCK> are "0", the input clock to stage 9
of the divider becomes the output of stage 8 of the divider.
When SYSCR1<DV9CK> or SYSCR2<SYSCK> is "1", the input clock to stage 9 of the
divider becomes fs/4. When SYSCR2<SYSCK> is "1", the outputs of stages 1 to 8 of the
divider and prescaler are stopped.
The prescaler and divider are cleared to "0" at a reset and at the end of the warm-up operation that follows the release of STOP mode.
3. Machine cycle
Instruction execution is synchronized with the main system clock (fm).
The minimum instruction execution unit is called a "machine cycle". One machine cycle
corresponds to one main system clock.
There are a total of 11 different types of instructions for the TLCS-870/C1 Series: 10 types
ranging from 1-cycle instructions, which require one machine cycle for execution, to 10cycle instructions, which require 10 machine cycles for execution, and 13-cycle instructions,
which require 13 machine cycles for execution.
2.3.4
Warm-up counter
The warm-up counter is a circuit that counts the high-frequency clock (fc) and the low-frequency clock (fs),
and it consists of a source clock selection circuit, a 3-stage frequency division circuit and a 14-stage counter.
The warm-up counter is used to secure the time after a power-on reset is released before the supply voltage
becomes stable and secure the time after the STOP mode is released or the operation mode is changed before
the oscillation by the oscillation circuit becomes stable.
WUCCR
WUCSEL
WUCDIV
SYSCR2
WUCRST
SYSCR1
XEN XTEN
STOP
INTWUC interrupt
Warm-up counter
controller
Enable/disable counting up
S
Clock for high-frequency clock
oscillation circuit (fc)
Clock for low-frequency clock
oscillation circuit (fs)
A Z
B
1 2 3
S
D
CZ
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Comparator
0 1 2 3 4 5 6 7
WUCDR
Figure 2-6 Warm-up Counter Circuit
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Enable CPU operation
TMP89FM46
2.3.4.1
Warm-up counter operation when the oscillation is enabled by the hardware
(1)
When a power-on reset is released or a reset is released
The warm-up counter serves to secure the time after a power-on reset is released before the supply
voltage becomes stable and the time after a reset is released before the oscillation by the high-frequency clock oscillation circuit becomes stable.
When the power is turned on and the supply voltage exceeds the power-on reset release voltage,
the warm-up counter reset signal is released. At this time, the CPU and the peripheral circuits are
held in the reset state.
A reset signal initializes WUCCR<WUCSEL> to "0" and WUCCR<WUCDIV> to "11", which
selects the high-frequency clock (fc) as the input clock to the warm-up counter.
When a reset is released for the warm-up counter, the high-frequency clock (fc) is input to the
warm-up counter, and the 14-stage counter starts counting the high-frequency clock (fc).
When the upper 8 bits of the warm-up counter become equal to WUCDR, counting is stopped and
a reset is released for the CPU and the peripheral circuits.
WUCDR is initialized to 0x66 after reset release, which makes the warm-up time 0x66 × 29/fc[s].
Note: The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The
warm-up time contains errors because the oscillation frequency is unstable until the oscillation circuit becomes stable.
(2)
When the STOP mode is released
The warm-up counter serves to secure the time after the oscillation is enabled by the hardware
before the oscillation becomes stable at the release of the STOP mode.
The high-frequency clock (fc) or the low-frequency clock (fs), which generates the main system
clock when the STOP mode is activated, is selected as the input clock for frequency division circuit,
regardless of WUCCR<WUCSEL>.
Before the STOP mode is activated, select the division rate of the input clock to the warm-up
counter at WUCCR<WUCDIV> and set the warm-up time at WUCDR.
When the STOP mode is released, the 14-stage counter starts counting the input clock selected in
the frequency division circuit.
When the upper 8 bits of the warm-up counter become equal to WUCDR, counting is stopped and
the operation is restarted by an instruction that follows the STOP mode activation instruction.
Clock that generates the main system
clock when the STOP mode is activated
fc
fs
WUCCR<WUCSEL>
WUCCR<WUCDIV>
Counter input clock
Warm-up time
00
fc
26 / fc to 255 x 26 / fc
01
fc / 2
27 / fc to 255 x 27 / fc
10
fc / 22
28 / fc to 255 x 28 / fc
11
23
29 / fc to 255 x 29 / fc
Don’t Care
fc /
00
fs
26 / fs to 255 x 26 / fs
01
fs / 2
27 / fs to 255 x 27 / fs
10
fs / 22
28 / fs to 255 x 28 / fs
11
fs / 23
29 / fs to 255 x 29 / fs
Don't Care
Note 1: When the operation is switched to the STOP mode during the warm-up for the oscillation enabled by the software, the
warm-up counter holds the value at the time, and restarts counting after the STOP mode is released. In this case, the
warm-up time at the release of the STOP mode becomes insufficient. Don't switch the operation to the STOP mode during
the warm-up for the oscillation enabled by the software.
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2. CPU Core
2.3 System clock controller
TMP89FM46
Note 2: The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The warm-up time contains
errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. Set the sufficient time for
the oscillation start property of the oscillator.
2.3.4.2
Warm-up counter operation when the oscillation is enabled by the software
The warm-up counter serves to secure the time after the oscillation is enabled by the software before the
oscillation becomes stable, at a mode change from NORMAL1 to NORMAL2 or from SLOW1 to
SLOW2.
Select the input clock to the frequency division circuit at WUCCR<WUCSEL>.
Select the input clock to the 14-stage counter at WUCCR<WUCDIV>.
After the warm-up time is set at WUCDR, setting SYSCR2<XEN> or SYSCR2<XTEN> to "1" allows
the stopped oscillation circuit to start oscillation and the 14-stage counter to start counting the selected
input clock.
When the upper 8 bits of the counter become equal to WUCDR, an INTWUC interrupt occurs, counting
is stopped and the counter is cleared.
Set WUCCR<WUCRST> to "1" to discontinue the warm-up operation.
By setting it to "1", the count-up operation is stopped, the warm-up counter is cleared, and
WUCCR<WUCRST> is cleared to "0".
SYSCR2<XEN> and SYSCR2<XTEN> hold the values when WUCCR<WUCRST> is set to "1". To
restart the warm-up operation, SYSCR2<XEN> or SYSCR2<XTEN> must be cleared to "0".
Note: The warm-up counter starts counting when SYSCR2<XEN> or SYSCR2<XTEN> is changed from "0"
to "1". The counter will not start counting by writing "1" to SYSCR2<XEN> or SYSCR2<XTEN> when it
is in the state of "1".
WUCCR<WUCSEL>
WUCCR<WUCDIV>
Counter input clock
Warm-up time
26
/ fc to 255 x 26 / fc
00
fc
01
fc / 2
27 / fc to 255 x 27 / fc
10
fc / 22
28 / fc to 255 x 28 / fc
11
fc / 23
29 / fc to 255 x 29 / fc
00
fs
26 / fs to 255 x 26 / fs
01
fs / 2
27 / fs to 255 x 27 / fs
10
fs / 22
28 / fs to 255 x 28 / fs
11
fs / 23
29 / fs to 255 x 29 / fs
0
1
Note: The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The
warm-up time contains errors because the oscillation frequency is unstable until the oscillation circuit
becomes stable. Set the sufficient time for the oscillation start property of the oscillator.
2.3.5
Operation mode control circuit
The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock (fm).
There are three operating modes: the single-clock mode, the dual-clock mode and the STOP mode. These
modes are controlled by the system control registers (SYSCR1 and SYSCR2).
Figure 2-7 shows the operating mode transition diagram.
2.3.5.1
Single-clock mode
Only the gear clock (fcgck) is used for the operation in the single-clock mode.
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TMP89FM46
The main system clock (fm) is generated from the gear clock (fcgck). Therefore, the machine cycle time
is 1/fcgck [s].
The gear clock (fcgck) is generated from the high-frequency clock (fc).
In the single-clock mode, the low-frequency clock generation circuit pins P03 (XTIN) and P04
(XTOUT) can be used as the I/O ports.
(1)
NORMAL1 mode
In this mode, the CPU core and the peripheral circuits operate using the gear clock (fcgck).
The NORMAL1 mode becomes active after reset release.
(2)
IDLE1 mode
In this mode, the CPU and the watchdog timer stop and the peripheral circuits operate using the
gear clock (fcgck).
The IDLE1 mode is activated by setting SYSCR2<IDLE> to "1" in the NORMAL1 mode.
When the IDLE1 mode is activated, the CPU and the watchdog timer stop.
When the interrupt latch enabled by the interrupt enable register EFR becomes "1", the IDLE1
mode is released to the NORMAL1 mode.
When the IMF (interrupt master enable flag) is "1" (interrupts enabled), the operation returns normal after the interrupt processing is completed.
When the IMF is "0" (interrupts disabled), the operation is restarted by the instruction that follows
the IDLE1 mode activation instruction.
(3)
IDLE0 mode
In this mode, the CPU and the peripheral circuits stop, except the oscillation circuits and the time
base timer.
In the IDLE0 mode, the peripheral circuits stop in the states when the IDLE0 mode is activated or
become the same as the states when a reset is released. For operations of the peripheral circuits in the
IDLE0 mode, refer to the section of each peripheral circuit.
The IDLE0 mode is activated by setting SYSCR2<TGHALT> to "1" in the NORMAL1 mode.
When the IDLE0 mode is activated, the CPU stops and the timing generator stops the clock supply
to the peripheral circuits except the time base timer.
When the falling edge of the source clock selected at TBTCR<TBTCK> is detected, the IDLE0
mode is released, the timing generator starts the clock supply to all the peripheral circuits and the
NORMAL1 mode is restored.
Note that the IDLE0 mode is activated and restarted, regardless of the setting of
TBTCR<TBTEN>.
When the IDLE0 mode is activated with TBTCR<TBTEN> set at "1", the INTTBT interrupt latch
is set after the NORMAL mode is restored.
When the IMF is "1" and the EF5 (the individual interrupt enable flag for the time base timer) is
"1", the operation returns normal after the interrupt processing is completed.
When the IMF is "0" or when the IMF is "1" and the EF5 (the individual interrupt enable flag for
the time base timer) is "0", the operation is restarted by the instruction that follows the IDLE0 mode
activation instruction.
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2. CPU Core
2.3 System clock controller
2.3.5.2
TMP89FM46
Dual-clock mode
The gear clock (fcgck) and the low-frequency clock (fs) are used for the operation in the dual-clock
mode.
The main system clock (fm) is generated from the gear clock (fcgck) in the NORMAL2 or IDLE2
mode, and generated from the clock that is a quarter of the low-frequency clock (fs) in the SLOW1/2 or
SLEEP0/1 mode. Therefore, the machine cycle time is 1/fcgck [s] in the NORMAL2 or IDLE2 mode and
is 4/fs [s] in the SLOW1/2 or SLEEP0/1 mode.
P03 (XTIN) and P04 (XTOUT) are used as the low-frequency clock oscillation circuit pins. (These pins
cannot be used as I/O ports in the dual-clock mode.)
The operation of the TLCS-870/C1 Series becomes the single-clock mode after reset release. To operate
it in the dual-clock mode, allow the low-frequency clock to oscillate at the beginning of the program.
(1)
NORMAL2 mode
In this mode, the CPU core operates using the gear clock (fcgck), and the peripheral circuits operate using the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs).
(2)
SLOW2 mode
In this mode, the CPU core and the peripheral circuits operate using the clock that is a quarter of
the low-frequency clock (fs).
In the SLOW mode, some peripheral circuits become the same as the states when a reset is
released. For operations of the peripheral circuits in the SLOW mode, refer to the section of each
peripheral circuit.
Set SYSCR2<SYSCK> to switch the operation mode from NORMAL2 to SLOW2 or from
SLOW2 to NORMAL2.
In the SLOW2 mode, outputs of the prescaler and stages 1 to 8 of the divider stop.
(3)
SLOW1 mode
In this mode, the high-frequency clock oscillation circuit stops operation and the CPU core and the
peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs).
This mode requires less power to operate the high-frequency clock oscillation circuit than in the
SLOW2 mode.
In the SLOW mode, some peripheral circuits become the same as the states when a reset is
released. For operations of the peripheral circuits in the SLOW mode, refer to the section of each
peripheral circuit.
Set SYSCR2<XEN> to switch the operation between the SLOW1 and SLOW2 modes.
In the SLOW1 or SLEEP1 mode, outputs of the prescaler and stages 1 to 8 of the divider stop.
(4)
IDLE2 mode
In this mode, the CPU and the watchdog timer stop and the peripheral circuits operate using the
gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs).
The IDLE2 mode can be activated and released in the same way as for the IDLE1 mode. The operation returns to the NORMAL2 mode after this mode is released.
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TMP89FM46
(5)
SLEEP1 mode
In this mode, the high-frequency clock oscillation circuit stops operation, the CPU and the watchdog timer stop, and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs).
In the SLEEP1 mode, some peripheral circuits become the same as the states when a reset is
released. For operations of the peripheral circuits in the SLEEP1 mode, refer to the section of each
peripheral circuit.
The SLEEP1 mode can be activated and released in the same way as for the IDLE1 mode. The
operation returns to the SLOW1 mode after this mode is released.
In the SLOW1 or SLEEP1 mode, outputs of the prescaler and stages 1 to 8 of the divider stop.
(6)
SLEEP0 mode
In this mode, the high-frequency clock oscillation circuit stops operation, the time base timer operates using the clock that is a quarter of the low-frequency clock (fs), and the core and the peripheral
circuits stop.
In the SLEEP0 mode, the peripheral circuits stop in the states when the SLEEP0 mode is activated
or become the same as the states when a reset is released. For operations of the peripheral circuits in
the SLEEP0 mode, refer to the section of each peripheral circuit.
The SLEEP0 mode can be activated and released in the same way as for the IDLE0 mode. The
operation returns to the SLOW1 mode after this mode is released.
In the SLEEP0 mode, the CPU stops and the timing generator stops the clock supply to the peripheral circuits except the time base timer.
2.3.5.3
STOP mode
In this mode, all the operations in the system, including the oscillation circuits, are stopped and the
internal states in effect before the system was stopped are held with low power consumption.
In the STOP mode, the peripheral circuits stop in the states when the STOP mode is activated or become
the same as the states when a reset is released. For operations of the peripheral circuits in the STOP mode,
refer to the section of each peripheral circuit.
The STOP mode is activated by setting SYSCR1<STOP> to "1".
The STOP mode is released by the STOP mode release signals. After the warm-up time has elapsed, the
operation returns to the mode that was active before the STOP mode, and the operation is restarted by the
instruction that follows the STOP mode activation instruction.
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2. CPU Core
2.3 System clock controller
2.3.5.4
TMP89FM46
Transition of operation modes
RESET
Reset release
IDLE0
mode
Warm-up that
follows reset
release
Warm-up completed
SYSCR2<TGHA LT> = "1" (Note 2)
SYSCR2<IDLE> = "1"
IDLE0
mode
SYSCR1<STOP> = "1"
NORMAL1
mode
STOP mode release
signal
Interrupt
(a) Single-clock mode
SYSCR2<XTEN> = "1"
SYSCR2<XTEN> = "0"
SYSCR2<IDLE> = "1"
IDLE2
mode
SYSCR1<STOP> = "1"
NORMAL2
mode
STOP mode release
signal
Interrupt
SYSCR2<SYSCK> = "1"
STOP
SYSCR2<SYSCK> = "0"
SLOW2
mode
SYSCR2<XEN> = "1"
SYSCR2<XEN> = "0"
SYSCR2<IDLE> = "1"
SLEEP1
mode
SYSCR1<STOP> = "1"
SLOW1
mode
Interrupt
STOP mode release
(Note 2) SYSCR2<TGHALT> = "1" signal
(b) Dual-clock mode
SLEEP0
mode
Note 1: The NORMAL1 and NORMAL2 modes are generically called the NORMAL mode; the SLOW1 and SLOW2 modes are
called the SLOW mode; the IDLE0, IDLE1 and IDLE2 modes are called the IDLE mode; and the SLEEP0 and SLEEP1
are called the SLEEP mode.
Note 2: The mode is released by the falling edge of the source clock selected at TBTCR<TBTCK>.
Figure 2-7 Operation Mode Transition Diagram
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TMP89FM46
Table 2-3 Operation Modes and Conditions
Oscillation circuit
Operation mode
High-frequency
Low-frequency
RESET
NORMAL1
CPU core
Watchdog
timer
Time base
timer
Other peripheral circuits
Reset
Reset
Reset
Reset
Operate
Operate
Oscillation
Single clock
IDLE1
Operate
Stop
IDLE0
Machine cycle time
1 / fcgck [s]
Operate
Stop
Stop
Stop
STOP
Stop
Stop
NORMAL2
IDLE2
Oscillation
SLOW2
Oscillation
Dual clock
SLOW1
SLEEP1
Operate with
the high frequency
Operate with
the high/low
frequency
Stop
Stop
Operate with
the low frequency
Operate with
the low frequency
Operate with
the low frequency
Operate with
the low frequency
Stop
Stop
Å|
1 / fcgck [s]
Operate
Operate
4/ fs [s]
Stop
SLEEP0
Stop
STOP
2.3.6
Stop
Stop
Å|
Operation Mode Control
2.3.6.1
STOP mode
The STOP mode is controlled by system control register 1 (SYSCR1) and the STOP mode release signals.
(1)
Start the STOP mode
The STOP mode is started by setting SYSCR1<STOP> to "1". In the STOP mode, the following
states are maintained:
1. Both the high-frequency and low-frequency clock oscillation circuits stop oscillation and all
internal operations are stopped.
2. The data memory, the registers and the program status word are all held in the states in
effect before STOP mode was started. The port output latch is determined by the value of
SYSCR1<OUTEN>.
3. The prescaler and the divider of the timing generator are cleared to "0".
4. The program counter holds the address of the instruction 2 ahead of the instruction (e.g.,
[SET (SYSCR1).7]) which started the STOP mode.
(2)
Release the STOP mode
The STOP mode is released by the following STOP mode release signals. It is also released by a
reset by the RESET pin, a power-on reset and a reset by the voltage detection circuits. When a reset is
released, the warm-up starts. After the warm-up is completed, the NORMAL1 mode becomes active.
1. Release by the STOP pin
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2. CPU Core
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TMP89FM46
2. Release by key-on wakeup
3. Release by the voltage detection circuits
Note: During the STOP period (from the start of the STOP mode to the end of the warm-up), due to
changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may
be accepted immediately after the STOP mode is released. Before starting the STOP mode,
therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear
unnecessary interrupt latches.
1. Release by the STOP pin
Release the STOP mode by using the STOP pin.
To release the STOP mode by using the STOP pin, set VDCR2<VDSS> to "00" or "10".
(For details of VDCR2, refer to the section of voltage detection circuits.)
The STOP mode release by the STOP pin includes the level-sensitive release mode and the
edge-sensitive release mode, either of which can be selected at SYSCR1<RELM>.
The STOP pin is also used as the P11 port and the INT5 (external interrupt input 5) pin.
- Level-sensitive release mode
The STOP mode is released by setting the STOP pin high.
Setting SYSCR1<RELM> to "1" selects the level-sensitive release mode.
This mode is used for the capacitor backup when the main power supply is cut off and
the long term battery backup.
Even if an instruction for starting the STOP mode is executed while the STOP pin input is high, the STOP mode does not start. Thus, to start the STOP mode in the levelsensitive release mode, it is necessary for the program to first confirm that the STOP pin
input is low.
This can be confirmed by testing the port by the software or using interrupts
Note:
When the STOP mode is released, the warm-up counter source clock automatically changes
to the clock that generated the main system clock when the STOP mode was started, regardless of WUCCR<WUCSEL>.
Example: Starting the STOP mode from the SLOW mode with an INT5 interrupt
(Warm-up time at release of the STOP mode is about 450ms at fs=32.768 KHz.)
PINT5:
TEST
(P0PRD).5
JRS
F, SINT5
; To reject noise, the STOP mode does not start
; if the STOP pin input is high.
LD
(SYSCR1), 0x40
; Sets up the level-sensitive release mode
LD
(WUCCR), 0x03
; WUCCR<WUCDIV> = 00 (No division) (Note)
LD
(WUCDR),0xE8
; Sets the warm-up time
; 450 ms/1.953 ms = 230.4 → round up to 0xE8
DI
SET
SINT5:
; IMF = 0
(SYSCR1).7
; Starts the STOP mode
RETI
Note: When the STOP mode is released, the warm-up counter source clock automatically changes to the clock that generated the
main system clock when the STOP mode was started, regardless of WUCCR<WUCSEL>.
VIH
STOP pin
XOUT pin
NORMAL mode
STOP mode
Warm-up
Confirm by program that
the STOP pin input is low
and start the STOP mode.
RA001
NORMAL mode
The STOP mode is released by the hardware.
Always released if the
STOP pin input is high.
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TMP89FM46
Even if the STOP pin input returns to low after the warm-up starts, the STOP mode is not restarted.
Figure 2-8 Level-sensitive Release Mode (Example when the high-frequency clock oscillation
circuit is selected)
- Edge-sensitive release mode
In this mode, the STOP mode is released at the rising edge of the STOP pin input.
Setting SYSCR1<RELM> to "0" selects the edge-sensitive release mode.
This is used in applications where a relatively short program is executed repeatedly at
periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, the
STOP mode is started even when the STOP pin input is high
Example: Starting the STOP mode from the NORMAL mode
(Warm-up time at release of the STOP mode is about 200ms at fc=10 MHz.)
LD
(WUCCR),0x01
; WUCCR<WUCDIV> = 00 (No division) (Note)
LD
(WUCDR),0x20
; Sets the warm-up time
; 200ms / 6.4µs = 31.25 → round up to 0x20
DI
LD
; IMF = 0
(SYSCR1) , 0x80
; Starts the STOP mode with the edge-sensitive release mode selected
Note: When the STOP mode is released, the warm-up counter source clock automatically changes to the clock that generated the
main system clock when the STOP mode was started, regardless of WUCCR<WUCSEL>.
VIH
STOP pin
XOUT pin
NORMAL mode
The STOP mode
is started
by the program.
STOP mode
Warm-up
NORMAL
mode
STOP mode
The STOP mode is released by the hardware
at the rising edge of the STOP pin input.
Note: If the rising edge is input to the STOP pin within 1 machine cycle after SYSCR1<STOP> is set to "1", the STOP mode will not
be released.
Figure 2-9 Edge-sensitive Release Mode (Example when the high-frequency clock oscillation
circuit is selected)
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2. CPU Core
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TMP89FM46
2. Release by the key-on wakeup
The STOP mode is released by inputting the prescribed level to the key-on wakeup pin.
The level to release the STOP mode can be selected from "H" and "L".
For release by the key-on wakeup, refer to section "Key-on Wakeup".
Note:
If the key-on wakeup pin input becomes the opposite level to the release level after the
warm-up starts, the STOP mode is not restarted.
3. Release by the voltage detection circuits
The STOP mode is released by the supply voltage detection by the voltage detection circuits.
To release the STOP mode by using the voltage detection circuits, set VDCR2<VDSS> to
"01" or "10".
If the voltage detection operation mode of the voltage detection circuits is set to generate
reset signals (when VDCR2<VDxMOD> is 1 (x=1 to 2)), the STOP mode is released and a
reset is applied as soon as the supply voltage becomes lower than the detection voltage.
When the supply voltage becomes equal to or higher than the detection voltage of the voltage detection circuits, the reset is released and the warm-up starts. After the warm-up is completed, the NORMAL1 mode becomes active.
If the voltage detection operation mode of the voltage detection circuits is set to generate
interrupt request signals (when VDCR2<VDxMOD> is 0 (x=1 to 2)), the STOP mode is
released when the supply voltage becomes equal to or higher than the detection voltage.
For details, refer to the section of the voltage detection circuits.
Note:
(3)
If the supply voltage becomes equal to or higher than the detection voltage within 1 machine cycle after SYSCR1<STOP> is set to "1", the STOP mode will not be released.
STOP mode release operation
The STOP mode is released in the following sequence:
1. Oscillation starts. For the oscillation start operation in each mode, refer to "Table 2-4 Oscillation Start Operation at Release of the STOP Mode".
2. Warm-up is executed to secure the time required to stabilize oscillation. The internal operations remain stopped during warm-up. The warm-up time is set by the warm-up counter,
depending on the oscillator characteristics.
3. After the warm-up time has elapsed, the normal operation is restarted by the instruction that
follows the STOP mode start instruction. At this time, the prescaler and the divider of the
timing generator are cleared to "0".
Note: When the STOP mode is released with a low hold voltage, the following cautions must be
observed.
The supply voltage must be at the operating voltage level before releasing the STOP mode. The
RESET pin input must also be "H" level, rising together with the supply voltage. In this case, if an
external time constant circuit has been connected, the RESET pin input voltage will increase at a
slower pace than the power supply voltage. At this time, there is a danger that a reset may occur
if the input voltage level of the RESET pin drops below the non-inverting high-level input voltage
(Hysteresis input).
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TMP89FM46
Table 2-4 Oscillation Start Operation at Release of the STOP Mode
Operation mode before the STOP
mode is started
Single-clock
mode
High-frequency
clock
Low-frequency
clock
Oscillation start operation after release
NORMAL1
High-frequency
clock oscillation
circuit
-
The high-frequency clock oscillation circuit starts
oscillation.
The low-frequency clock oscillation circuit stops
oscillation.
NORMAL2
High-frequency
clock oscillation
circuit
Low-frequency
clock oscillation circuit
The high-frequency clock oscillation circuit starts
oscillation.
The low-frequency clock oscillation circuit starts
oscillation.
-
Low-frequency
clock oscillation circuit
The high-frequency clock oscillation circuit stops
oscillation.
The low-frequency clock oscillation circuit starts
oscillation.
Dual-clock mode
SLOW1
Note: When the operation returns to the NORMAL2 mode, fc is input to the frequency division circuit of the warm-up counter.
2.3.6.2
IDLE1/2 and SLEEP1 modes
The IDLE1/2 and SLEEP1 modes are controlled by the system control register 2 (SYSCR2) and
maskable interrupts. The following states are maintained during these modes.
1. The CPU and the watchdog timer stop their operations. The peripheral circuits continue to operate.
2. The data memory, the registers, the program status word and the port output latches are all held
in the status in effect before IDLE1/2 or SLEEP1 mode was started.
3. The program counter holds the address of the instruction 2 ahead of the instruction which starts
the IDLE1/2 or SLEEP1 mode.
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2. CPU Core
2.3 System clock controller
TMP89FM46
Starting IDLE1/2 mode or
SLEEP1 mode by an
instruction
CPU and WDT stop
Yes
Reset input
Reset
No
No
Interrupt
request
Yes
No
(Normal release mode)
IMF = "1"
Yes
(Interrupt release mode)
Interrupt processing
Execution of the instruction
which follows the IDLE1/2 mode
or SLEEP1 mode start
instruction
Figure 2-10 IDLE1/2 and SLEEP 1 Modes
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TMP89FM46
(1)
Start the IDLE1/2 and SLEEP1 modes
After the interrupt master enable flag (IMF) is set to "0", set the individual interrupt enable flag
(EF) to "1", which releases IDLE1/2 and SLEEP1 modes.
To start the IDLE1/2 or SLEEP1 mode, set SYSCR2<IDLE> to "1".
If the release condition is satisfied when it is attempted to start the IDLE1/2 or SLEEP1 mode,
SYSCR2<IDLE> remains cleared and the IDLE1/2 or SLEEP1 mode will not be started.
Note 1: When a watchdog timer interrupt is generated immediately before the IDLE1/2 or SLEEP1 mode
is started, the watchdog timer interrupt will be processed but the IDLE1/2 or SLEEP1 mode will
not be started.
Note 2: Before starting the IDLE1/2 or SLEEP1 mode, enable the interrupt request signals to be generated to release the IDLE1/2 or SLEEP1 mode and set the individual interrupt enable flag.
(2)
Release the IDLE1/2 and SLEEP1 modes
The IDLE1/2 and SLEEP1 modes include a normal release mode and an interrupt release mode.
These modes are selected at the interrupt master enable flag (IMF). After releasing IDLE1/2 or
SLEEP1 mode, SYSCR2<IDLE> is automatically cleared to "0" and the operation mode is returned
to the mode preceding the IDLE1/2 or SLEEP1 mode.
The IDLE1/2 and SLEEP1 modes are also released by a reset by the RESET pin, a power-on reset
and a reset by the voltage detection circuits. After releasing the reset, the warm-up starts. After the
warm-up is completed, the NORMAL1 mode becomes active.
• Normal release mode (IMF = "0")
The IDLE1/2 or SLEEP1 mode is released when the interrupt latch enabled by the individual interrupt enable flag (EF) is "1". The operation is restarted by the instruction that follows
the IDLE1/2 or SLEEP1 mode start instruction. Normally, the interrupt latch (IL) of the interrupt source used for releasing must be cleared to "0" by load instructions.
• Interrupt release mode (IMF = "1")
The IDLE1/2 or SLEEP1 mode is released when the interrupt latch enabled by the individual interrupt enable flag (EF) is "1". After the interrupt is processed, the operation is restarted
by the instruction that follows the IDLE1/2 or SLEEP1 mode start instruction.
2.3.6.3
IDLE0 and SLEEP0 modes
The IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time
base timer control register (TBTCR). The following states are maintained during the IDLE0 and SLEEP0
modes:
• The timing generator stops the clock supply to the peripheral circuits except the time base timer.
• The data memory, the registers, the program status word and the port output latches are all held in
the states in effect before the IDLE0 or SLEEP0 mode was started.
• The program counter holds the address of the instruction 2 ahead of the instruction which starts
the IDLE0 or SLEEP0 mode.
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2. CPU Core
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TMP89FM46
Stopping peripherals by
instructions
Starting IDLE0 or SLEEP0
mode by an instruction
CPU and WDT stop
Yes
Reset input
Reset
No
No
TBT source clock
falling edge
Yes
"0"
TBTCR<TBTEN>
"1"
No
TBT interrupt
enabled
(Normal release mode)
Yes
No
IMF = "1"
Yes
(Interrupt release mode)
Interrupt processing
Execution of the instruction
which follows the IDLE0 or
SLEEP0 mode start
instruction
Figure 2-11 IDLE0 and SLEEP0 Modes
• Start the IDLE0 and SLEEP0 modes
Stop (disable) the peripherals such as a timer counter.
To start the IDLE0 or SLEEP0 mode, set SYSCR2<TGHALT> to "1".
• Release the IDLE0 and SLEEP0 modes
The IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release
mode. These modes are selected at the interrupt master enable flag (IMF), the individual interrupt enable flag (EF5) for the time base timer and TBTCR<TBTEN>. After releasing the
IDLE0 or SLEEP0 mode, SYSCR2<TGHALT> is automatically cleared to "0" and the operation mode is returned to the mode preceding the IDLE0 or SLEEP0 mode. If
TBTCR<TBTEN> has been set at "1", the INTTBT interrupt latch is set.
The IDLE0 and SLEEP0 modes are also released by a reset by the RESET pin, a power-on
reset and a reset by the voltage detection circuits. When a reset is released, the warm-up starts.
After the warm-up is completed, the NORMAL1 mode becomes active.
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TMP89FM46
(1)
Normal release mode (IMF, EF5, TBTCR<TBTEN> = "0")
The IDLE0 or SLEEP0 mode is released when the falling edge of the source clock selected at
TBTCR<TBTCK> is detected. After the IDLE0 or SLEEP0 mode is released, the operation is
restarted by the instruction that follows the IDLE0 or SLEEP0 mode start instruction.
When TBTCR<TBTEN> is "1", the time base timer interrupt latch is set.
(2)
Interrupt release mode (IMF, EF5, TBTCR<TBTEN> = "1")
The IDLE0 or SLEEP0 mode is released when the falling edge of the source clock selected at
TBTCR<TBTCK> is detected. After the release, the INTTBT interrupt processing is started.
Note 1: The IDLE0 or SLEEP0 mode is released to the NORMAL1 or SLOW1 mode by the asynchronous internal clock selected at TBTCR<TBTCK>. Therefore, the period from the start to the
release of the mode may be shorter than the time specified at TBTCR<TBTCK>.
Note 2: When a watchdog timer interrupt is generated immediately before the IDLE0 or SLEEP0 mode
is started, the watchdog timer interrupt will be processed but the IDLE0 or SLEEP0 mode will
not be started.
2.3.6.4
SLOW mode
The SLOW mode is controlled by system control register 2 (SYSCR2).
(1)
Switching from the NORMAL2 mode to the SLOW1 mode
Set SYSCR2<SYSCK> to "1".
When a maximum of 2/fcgck + 10/fs [s] has elapsed since SYSCR2<SYSCK> is set to "1", the
main system clock (fm) is switched to fs/4.
After switching, wait for 2 machine cycles or longer, and then clear SYSCR2<XEN> to "0" to turn
off the high-frequency clock oscillator.
If the oscillation of the low-frequency clock (fs) is unstable, confirm the stable oscillation at the
warm-up counter before implementing the procedure described above.
Note 1: Be sure to follow this procedure to switch the operation from the NORMAL2 mode to the
SLOW1 mode.
Note 2: It is also possible to allow the basic clock for the high-frequency clock to oscillate continuously to
return to NORMAL2 mode. However, be sure to turn off the oscillation of the basic clock for the
high-frequency clock when the STOP mode is started from the SLOW mode.
Note 3: After switching SYSCR2<SYSCK>, be sure to wait for 2 machine cycles or longer before clearing SYSCR2<XEN> to "0". Clearing it within 2 machine cycles causes a system clock reset.
Note 4: When the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the
clock that is a quarter of the basic clock (fs) for the low-frequency clock. For the synchronization,
fm is stopped for a period of 10/fs or shorter.
Quarter of the low-frequency clock
(fs/4)
Gear clock (fcgck)
SYSCR2<SYSCK>
Main system clock
10/fs (max.)
When the rising edge of fcgck is
When the rising edge of fs/4 is detected
detected twice after SYSCR2<SYSCK> twice after fm is stopped, fm is switched to fs.
is changed from 0 to 1, f is stopped
for synchronization.
Figure 2-12 Switching of the Main System Clock (fm) (Switching from fcgck to fs/4)
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2. CPU Core
2.3 System clock controller
TMP89FM46
Example 1: Switching from the NORMAL2 mode to the SLOW1 mode (when fc is used as the basic clock for the high-frequency clock)
SET
(SYSCR2).4
; SYSCR2<SYSCK> = 1
; (Switches the main system clock to the basic clock for the low-frequency clock for the SLOW2 mode)
NOP
; Waits for 2 machine cycles
NOP
CLR
(SYSCR2).6
; SYSCR2<XEN> = 0
(Turns off the high-frequency clock oscillation circuit)
Example 2: Switching to the SLOW1 mode after the stable oscillation of the low-frequency clock oscillation circuit is confirmed at the warm-up counter (fs=32.768KHz, warm-up time = about 100 ms)
; #### Initialize routine ####
SET
(P0FC).2
; P0FC2 = 1
(Uses P02/03 as oscillators)
LD
(WUCCR), 0x02
; WUCCR<WUCDIV> = 00 (No division)
WUCCR<WUCSEL> = 1 (Selects fs as the source clock)
LD
(WUCDR), 0x33
; Sets the warm-up time
(Determines the time depending on the oscillator characteristics)
100 ms/1.95 ms = 51.2 → round up to 0x33
SET
(EIRL).4
; Enables INTWUC interrupts
SET
(SYSCR2).5
; SYSCR2<XTEN> = 1
(Starts the low-frequency clock oscillation and starts the warm-up
counter)
¦
¦
¦
; #### Interrupt service routine of warm-up counter interrupts ####
PINTWUC:
SET
(SYSCR2).4
; SYSCR2<SYSCK> = 1
(Switches the main system clock to the low-frequency clock)
NOP
; Waits for 2 machine cycles
NOP
CLR
(SYSCR2).6
; SYSCR2<XEN> = 0 (Turns off the high-frequency clock oscillation circuit)
PINTWUC
; INTWUC vector table
RETI
¦
VINTWUC:
(2)
DW
Switching from the SLOW1 mode to the NORMAL1 mode
Set SYSCR2<XEN> to "1" to enable the high-frequency clock (fc) to oscillate. Confirm at the
warm-up counter that the oscillation of the basic clock for the high-frequency clock has stabilized,
and then clear SYSCR2<SYSCK> to "0".
When a maximum of 8/fs + 2.5/fcgck [s] has elapsed since SYSCR2<SYSCK> is cleared to "0",
the main system clock (fm) is switched to fcgck.
After switching, wait for 2 machine cycles or longer, and then clear SYSCR2<XTEN> to "0" to
turn off the low-frequency clock oscillator.
The SLOW mode is also released by a reset by the RESET pin, a power-on reset and a reset by the
voltage detection circuits. When a reset is released, the warm-up starts. After the warm-up is completed, the NORMAL1 mode becomes active.
Note 1: Be sure to follow this procedure to switch the operation from the SLOW1 mode to the
NORMAL1 mode.
Note 2: After switching SYSCR2<SYSCK>, be sure to wait for 2 machine cycles or longer before clearing SYSCR2<XTEN> to "0". Clearing it within 2 machine cycles causes a system clock reset.
Note 3: When the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the
clock that is a quarter of the basic clock (fs) for the low-frequency clock. For the synchronization,
fm is stopped for a period of 2.5/fcgck [s] or shorter.
Note 4: When P0FC0 is "0", setting SYSCR2<XEN> to "1" causes a system clock reset.
Note 5: When SYSCR2<XEN> is set at "1", writing "1" to SYSCR2<XEN> does not cause the warm-up
counter to start counting the source clock.
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TMP89FM46
Quarter of the low-frequency clock
(fs/4)
Gear clock (fcgck)
2.5/fcgck(max.)
SYSCR2<SYSCK>
Main system clock
When the rising edge of fs/4 is
When the rising edge of fcgck is detected
detected twice after SYSCR2<SYSCK> twice after fm is stopped, fm is switched to fcgck.
is changed from 1 to 0, f is stopped
for synchronization.
Figure 2-13 Switching the Main System Clock (fm) (Switching from fs/4 to fcgck)
Example : Switching from the SLOW1 mode to the NORMAL1 mode after the stability of the high-frequency clock oscillation circuit is confirmed at the warm-up counter (fc = 10 MHz, warm-up time = 4.0 ms)
; #### Initialize routine ####
SET
(P0FC).2
; P0FC2 = 1
(Uses P02/03 as oscillators)
LD
(WUCCR), 0x09
; WUCCR<WUCDIV> = 10 (Divided by 2)
WUCCR<WUCSEL> = 0 (Selects fc as the source clock)
LD
(WUCDR), 0x9D
; Sets the warm-up time
(Determine the time depending on the frequency and the oscillator
characteristics)
4ms / 25.6us = 156.25 → round up to 0x9D
SET
(EIRL). 4
; Enables INTWUC interrupts
SET
(SYSCR2) .6
; SYSCR2<XEN> = 1
(Starts the oscillation of the high-frequency clock oscillation circuit)
¦
¦
¦
; #### Interrupt service routine of warm-up counter interrupts ####
PINTWUC:
CLR
(SYSCR2). 4
; SYSCR2<SYSCK> = 0
(Switches the main system clock to the gear clock)
NOP
; Waits for 2 machine cycles
NOP
CLR
(SYSCR2). 5
; SYSCR2<XTEN> = 0
(Turns off the low-frequency clock oscillation circuit)
PINTWUC
; INTWUC vector table
RETI
¦
VINTWUC:
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2. CPU Core
2.4 Reset Control Circuit
TMP89FM46
2.4 Reset Control Circuit
The reset circuit controls the external and internal factor resets and initializes the system.
2.4.1
Configuration
The reset control circuit consists of the following reset signal generation circuits:
1. External reset input (external factor)
2. Power-on reset (internal factor)
3. Voltage detection reset 1 (internal factor)
4. Voltage detection reset 2 (internal factor)
5. Watchdog timer reset (internal factor)
6. System clock reset (internal factor)
7. Trimming data reset (internal factor)
8. Flash standby reset (internal factor)
P10(RESET)
P10 port
Internal factor reset detection status register,
Voltage detection circuit reset signal
External reset input enable reset signal
Power-on reset signal
Voltage detection reset 1 signal
Voltage detection reset 2 signal
CPU/peripheral
circuits reset signal
Warm-up counter
Watchdog timer reset signal
Warm-up
counter reset
signal
System clock reset signal
System clock control circuit
Trimming data reset signal
Flash standby reset signal
Figure 2-14 Reset Control Circuit
2.4.2
Control
The reset control circuit is controlled by system control register 3 (SYSCR3), system control register 4
(SYSCR4), system control status register (SYSSR4) and the internal factor reset detection status register
(IRSTSR).
System control register 3
SYSCR3
(0x0FDE)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
-
(RVCTR)
(RAREA)
RSTDIS
Read/Write
R
R
R
R
R
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
RSTDIS
External reset input enable register
0 : Enables the external reset input.
1 : Disables the external reset input.
Note 1: The enabled SYSCR3<RSTDIS> is initialized by a power-on reset only, and cannot be initialized by an external reset input
or internal factor reset. The value written in SYSCR3 is reset by a power-on reset, external reset input or internal factor
reset.
Note 2: The value of SYSCR3<RSTDIS> is invalid until 0xB2 is written into SYSCR4.
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TMP89FM46
Note 3: After SYSCR3<RSTDIS> is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3<RSTDIS>) in
NORMAL1 mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, SYSCR3<RSTDIS> may be enabled at unexpected timing.
Note 4: Bits 7 to 3 of SYSCR3 are read as "0".
System control register 4
SYSCR4
(0x0FDF)
7
6
5
4
Bit Symbol
SYSCR4
Read/Write
W
After reset
SYSCR4
0
0
0
0
3
2
1
0
0
0
0
0
0xB2 : Enables the contents of SYSCR3<RSTDIS>.
0xD4 : Enables the contents of SYSCR3<RAREA> and SYSCR3
<RVCTR>.
0x71 : Enables the contents of IRSTSR<FCLR>
Others : Invalid
Writes the SYSCR3 data control code.
Note 1: SYSCR4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit operation.
Note 2: After SYSCR3<RSTDIS> is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3<RSTDIS>) in NORMAL
mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, SYSCR3<RSTDIS> may be enabled at unexpected timing.
Note 3: After IRSTSR<FCLR> is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR<FCLR> in NORMAL mode
when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> may be enabled at unexpected timing.
System control status register 4
SYSSR4
(0x0FDF)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
-
(RVCTRS)
(RAREAS)
RSTDISS
Read/Write
R
R
R
R
R
R
R
R
After reset
0
0
0
0
0
0
0
0
RSTDISS
0 : The enabled SYSCR3<RSTDIS> data is "0".
1 : The enabled SYSCR3<RSTDIS> data is "1".
External reset input enable status
Note 1: The enabled SYSCR3<RSTDIS> is initialized by a power-on reset only, and cannot be initialized by any other reset signals. The value written in SYSCR3 is reset by a power-on reset and other reset signals.
Note 2: Bits 7 to 3 of SYSCR4 are read as "0".
Internal factor reset detection status register
IRSTSR
(0x0FCC)
RA001
7
6
5
4
3
2
1
0
Bit Symbol
FCLR
FLSRF
TRMDS
TRMRF
LVD2RF
LVD1RF
SYSRF
WDTRF
Read/Write
W
R
R
R
R
R
R
R
After reset
0
0
0
0
0
0
0
0
Page 39
2. CPU Core
2.4 Reset Control Circuit
TMP89FM46
FCLR
Flag initialization control
0 :1 : Clears the internal factor reset flag to "0".
FLSRF
Flash standby reset detection flag
0 :1 : Detects the flash standby reset.
TRMDS
Trimming data status
0 :1 : Detect state of abnormal trimming data
0 :1 : Detects the trimming data reset.
TRMRF
Trimming data reset detection flag
LVD2RF
Voltage detection reset 2 detection flag
0 :1 : Detects the voltage detection 2 reset.
LVD1RF
Voltage detection reset 1 detection flag
0 :1 : Detects the voltage detection 1 reset.
SYSRF
System clock reset detection flag
0 :1 : Detects the system clock reset.
WDTRF
Watchdog timer reset detection flag
0 :1 : Detects the watchdog timer reset.
Note 1: IRSTSR is initialized by an external reset input or power-on reset.
Note 2: Care must be taken in system designing since the IRSTSR may not fulfill its functions due to disturbing noise and other
effects.
Note 3: IRSTSR<FCLR> is initialized by a power-on reset, an external reset input or an internal reset factor.
Note 4: Set IRSTSR<FCLR> to "1" and write 0x71 to SYSCR4. This enables IRSTSR<FCLR> and the internal factor reset detection status register is clear to "0". IRSTSR<FCLR> is cleared to "0" automatically after initializing the internal factor reset
detection status register.
Note 5: After IRSTSR<FCLR> is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR<FCLR> in NORMAL mode
when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> may be enabled at unexpected timing.
Note 6: Bit 7 of IRSTSR is read as "0".
2.4.3
Functions
The power-on reset, external reset input and internal factor reset signals are input to the warm-up circuit of
the clock generator.
During reset, the warm-up counter circuit is reset, and the CPU and the peripheral circuits are reset.
After reset is released, the warm-up counter starts counting the high frequency clock (fc), and executes the
warm-up operation that follows reset release.
During the warm-up operation that follows reset release, the trimming data is loaded from the non-volatile
exclusive use memory for adjustment of the ladder resistor that generates the comparison voltage for the
power-on reset and the voltage detection circuits.
When the warm-up operation that follows reset release is finished, the CPU starts execution of the program
from the reset vector address stored in addresses 0xFFFE to 0xFFFF.
When a reset signal is input during the warm-up operation that follows reset release, the warm-up counter
circuit is reset.
The reset operation is common to the power-on reset, external reset input and internal factor resets, except
for the initialization of some special function registers and the initialization of the voltage detection circuits.
When a reset is applied, the peripheral circuits become the states as shown in Table 2-5.
RA001
Page 40
TMP89FM46
Table 2-5 Initialization of Built-in Hardware by Reset Operation and Its Status after Release
During reset
During the warm-up operation that follows reset
release
Immediately after the
warm-up operation that follows reset release
MCU mode:
0xFFFE
Serial PROM
mode:0x01FF
MCU mode:
0xFFFE
Serial PROM
mode:0x01FF
MCU mode:
0xFFFE
Serial PROM
mode:0x01FF
0x00FF
0x00FF
0x00FF
RAM
Indeterminate
Indeterminate
Indeterminate
General-purpose registers (W, A, B, C, D, E, H, L, IX and
IY)
Indeterminate
Indeterminate
Indeterminate
0
0
0
Jump status flag (JF)
Indeterminate
Indeterminate
Indeterminate
Zero flag (ZF)
Indeterminate
Indeterminate
Indeterminate
Carry flag (CF)
Indeterminate
Indeterminate
Indeterminate
Half carry flag (HF)
Indeterminate
Indeterminate
Indeterminate
Sign flag (SF)
Indeterminate
Indeterminate
Indeterminate
Overflow flag (VF)
Indeterminate
Indeterminate
Indeterminate
Interrupt master enable flag (IMF)
0
0
0
Individual interrupt enable flag (EF)
0
0
0
Interrupt latch (IL)
0
0
0
High-frequency clock oscillation circuit
Oscillation enabled
Oscillation enabled
Oscillation enabled
Low-frequency clock oscillation circuit
Oscillation disabled
Oscillation disabled
Oscillation disabled
Reset
Start
Stop
0
0
0
Disabled
Disabled
Enabled
Disabled or enabled
Disabled or enabled
Disabled or enabled
HiZ
HiZ
HiZ
Refer to the SFR map.
Refer to the SFR map.
Refer to the SFR map.
Built-in hardware
Program counter (PC)
Stack pointer (SP)
Register bank selector (RBS)
Warm-up counter
Timing generator prescaler and divider
Watchdog timer
Voltage detection circuit
I/O port pin status
Special function register
Note: The voltage detection circuits are disabled by an external reset input or power-on reset only.
2.4.4
Reset Signal Generating Factors
Reset signals are generated by each factor as follows:
2.4.4.1
External reset input (RESET pin input)
Port P10 is also used as the RESET pin, and it serves as the RESET pin after the power is turned on.
If the supply voltage is lower than the recommended operating voltage range, for example, when the
power is turned on, the supply voltage is raised to the operating voltage range with the RESET pin kept at
the "L" level, and a reset is applied 5 µs after the oscillation is stabilized.
If the supply voltage is within the recommended operating voltage range, the RESET pin is kept at the
"L" level for 5 µs with the stabilized oscillation, and then a reset is applied.
In each case, after a reset is applied, it is released by turning the RESET pin to "H" and the warm-up
operation that follows reset release gets started.
RA001
Page 41
2. CPU Core
2.4 Reset Control Circuit
TMP89FM46
Note: When the supply voltage is equal to or lower than the detection voltage of the power-on reset circuit,
the power-on reset remains active, even if the RESET pin is turned to "H".
Operating voltage
Reset time
RESET pin
CPU/peripheral
circuits reset
Warm-up operation
During reset
CPU and peripheral circuits
start operation
Figure 2-15 External Reset Input (when the power is turned on)
Operating voltage
Reset time
RESET pin
During reset
Warm-up operation
Reset signal
CPU and peripheral circuits
start operation
Figure 2-16 External Reset Input (when the power is stabilized)
RA001
Page 42
TMP89FM46
2.4.4.2
Power-on reset
The power-on reset is an internal factor reset that occurs when the power is turned on.
When power supply voltage goes on, if the supply voltage is equal to or lower than the releasing voltage
of the power-on reset circuit, a reset signal is generated and if it is higher than the releasing voltage of the
power-on reset circuit, a reset signal is released.
When power supply voltage goes down, if the supply voltage is equal to or lower than the detecting
voltage of the power-on reset circuit, a reset signal is generated.
Refer to "Power-on Reset circuit".
2.4.4.3
Voltage detection reset
The voltage detection reset is an internal factor reset that occurs when it is detected that the supply voltage has reached a predetermined detection voltage.
Refer to "Voltage Detection Circuit".
2.4.4.4
Watchdog timer reset
The watchdog timer reset is an internal factor reset that occurs when an overflow of the watchdog timer
is detected.
Refer to "Watchdog Timer".
2.4.4.5
System clock reset
The system clock reset is an internal factor reset that occurs when it is detected that the oscillation
enable register is set to a combination that puts the CPU into deadlock.
Refer to "Clock Control Circuit".
2.4.4.6
Trimming data reset
The trimming data reset is an internal factor reset that occurs when the trimming data latched in the
internal circuit is broken down during operation due to noise or other factors.
The trimming data is a data bit provided for adjustment of the ladder resistor that generates the comparison voltage for the power-on reset and the voltage detection circuits.
This bit is loaded from the non-volatile exclusive use memory during the warm-up time that follows
reset release (tPWUP) and latched into the internal circuit.
If the trimming data loaded from the non-volatile exclusive use memory during the warm-up operation
that follows reset release is abnormal, IRSTSR<TRMDS> is set to "1".
When IRSTSR<TRMDS> is read as "1" in the initialize routine immediately after reset release, the
trimming data need to be reloaded by generating an internal factor reset, such as a system clock reset, and
activating the warm-up operation again.
If IRSTSR<TRMDS> is still set to "1" after repeated reading, the detection voltage of the voltage detection circuit and power-on reset circuit does not satisfy the characteristic specified in the electric characteristics. Design the system so that the system will not be damaged in such a case.
2.4.4.7
Flash standby reset
The flash standby reset is an internal factor reset generated by the reading or writing of data of the flash
memory while it is on standby.
Refer to "Flash Memory".
RA001
Page 43
2. CPU Core
2.4 Reset Control Circuit
2.4.4.8
TMP89FM46
Internal factor reset detection status register
By reading the internal factor reset detection status register IRSTSR after the release of an internal factor reset, except the power-on reset, the factor which causes a reset can be detected.
The internal factor reset detection status register is initialized by an external reset input or power-on
reset.
Set IRSTSR<FCLR> to "1" and write 0x71 to SYSCR4. This enables IRSTSR<FCLR> and the internal
factor reset detection status register is clear to "0". IRSTSR<FCLR> is cleared to "0" automatically after
initializing the internal factor reset detection status register.
Note 1: Care must be taken in system designing since the IRSTSR may not fulfill its functions due to disturbing noise and other effects.
Note 2: After IRSTSR<FCLR> is modified, SYSCR4 should be written 0x71 (Enable code for
IRSTSR<FCLR> in NORMAL mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise,
IRSTSR<FCLR> may be enabled at unexpected timing.
2.4.4.9
How to use the external reset input pin as a port
To use the external reset input pin as a port, keep the external reset input pin at the "H" level until the
power is turned on and the warm-up operation that follows reset release is finished.
After the warm-up operation that follows reset release is finished, set P1PU0 to "1" and P1CR0 to "0",
and connect a pull-up resistor for a port. Then set SYSCR3<RSTDIS> to "1" and write 0xB2 to SYSCR4.
This disables the external reset function and makes the external reset input pin usable as a normal port.
To use the pin as an external reset pin when it is used as a port, set P1PU0 to "1" and P1CR0 to "0" and
connect the pull-up resistor to put the pin to the input mode. Then clear SYSCR3<RSTDIS> to "0" and
write 0xB2 to SYSCR4. This enables the external reset function and makes the pin usable as the external
reset input pin.
Note 1: If you switch the external reset input pin to a port or switch the pin used as a port to the external reset
input pin, do it when the pin is stabilized at the "H" level. Switching the pin function when the "L" level
is input may cause a reset.
Note 2: If the external reset input is used as a port, the statement which clears SYSCR3<RSTDIS> to "0" is
not written in a program. By the abnormal execution of program, the external reset input set as a port
may be changed as the external reset input at unexpected timing.
Note 3: After SYSCR3<RSTDIS> is modified, SYSCR4 should be written 0xB2 (Enable code for
SYSCR3<RSTDIS>) in NORMAL1 mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise,
SYSCR3<RSTDIS> may be enabled at unexpected timing.
RA001
Page 44
TMP89FM46
3. Interrupt Control Circuit
The TMP89FM46 has a total of 25 interrupt sources excluding reset. Interrupts can be nested with priorities. Three
of the internal interrupt sources are non-maskable while the rest are maskable.
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and have independent vector addresses. When a request for an interrupt is generated, its interrupt latch is set to "1", which requests the CPU to
accept the interrupt. Acceptance of interrupts is enabled or disabled by software using the interrupt master enable
flag (IMF) and individual enable flag (EF) for each interrupt source. If multiple maskable interrupts are generated
simultaneously, the interrupts are accepted in order of descending priority. The priorities are determined by the interrupt priority change control register (ILPRS1-ILPRS6) as Levels and determined by the hardware as the basic priorities.
However, there are no prioritized interrupt sources among non-maskable interrupts.
Interrupt sources
Enable condition
Interrupt
latch
Vector Address
(MCU mode)
RVCTR=0
enabled
RVCTR=1
enabled
Basic
priority
Internal/
External
(Reset)
Non-maskable
-
0xFFFE
-
1
Internal
INTSWI
Non-maskable
-
0xFFFC
0x01FC
2
Internal
INTUNDEF
Non-maskable
-
0xFFFC
0x01FC
2
Internal
INTWDT
Non-maskable
ILL<IL3>
0xFFF8
0x01F8
2
Internal
INTWUC
IMF AND EIRL<EF4> = 1
ILL<IL4>
0xFFF6
0x01F6
5
Internal
INTTBT
IMF AND EIRL<EF5> = 1
ILL<IL5>
0xFFF4
0x01F4
6
Internal
INTRXD0 / INTSIO0
IMF AND EIRL<EF6> = 1
ILL<IL6>
0xFFF2
0x01F2
7
Internal
INTTXD0
IMF AND EIRL<EF7> = 1
ILL<IL7>
0xFFF0
0x01F0
8
External
INT5
IMF AND EIRH<EF8> = 1
ILH<IL8>
0xFFEE
0x01EE
9
Internal
INTVLTD
IMF AND EIRH<EF9> = 1
ILH<IL9>
0xFFEC
0x01EC
10
Internal
INTADC
IMF AND EIRH<EF10> = 1
ILH<IL10>
0xFFEA
0x01EA
11
Internal
INTRTC
IMF AND EIRH<EF11> = 1
ILH<IL11>
0xFFE8
0x01E8
12
Internal
INTTC00
IMF AND EIRH<EF12> = 1
ILH<IL12>
0xFFE6
0x01E6
13
Internal
INTTC01
IMF AND EIRH<EF13> = 1
ILH<IL13>
0xFFE4
0x01E4
14
Internal
INTTCA0
IMF AND EIRH<EF14> = 1
ILH<IL14>
0xFFE2
0x01E2
15
Internal
INTSBI0/INTSIO0
IMF AND EIRH<EF15> = 1
ILH<IL15>
0xFFE0
0x01E0
16
External
INT0
IMF AND EIRE<EF16> = 1
ILE<IL16>
0xFFDE
0x01DE
17
External
INT1
IMF AND EIRE<EF17> = 1
ILE<IL17>
0xFFDC
0x01DC
18
External
INT2
IMF AND EIRE<EF18> = 1
ILE<IL18>
0xFFDA
0x01DA
19
External
INT3
IMF AND EIRE<EF19> = 1
ILE<IL19>
0xFFD8
0x01D8
20
External
INT4
IMF AND EIRE<EF20> = 1
ILE<IL20>
0xFFD6
0x01D6
21
Internal
INTTCA1
IMF AND EIRE<EF21> = 1
ILE<IL21>
0xFFD4
0x01D4
22
Internal
INTRXD1
IMF AND EIRE<EF22> = 1
ILE<IL22>
0xFFD2
0x01D2
23
Internal
INTTXD1
IMF AND EIRE<EF23> = 1
ILE<IL23>
0xFFD0
0x01D0
24
Internal
INTTC02
IMF AND EIRD<EF24> = 1
ILD<IL24>
0xFFCE
0x01CE
25
Internal
INTTC03
IMF AND EIRD<EF25> = 1
ILD<IL25>
0xFFCC
0x01CC
26
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note 1: To use the watchdog timer interrupt (INTWDT), clear WDCTR<WDTOUT> to "0" (It is set for the "Reset request" after
reset is released). For details, see "Watchdog Timer".
Note 2: 0xFFFA and 0xFFFB function not as interrupt vectors but as option codes in the serial PROM mode. For details, see
"Serial PROM Mode".
Note 3: Vector address areas can be changed by the SYSCR3<RVCTR> setting. To assign vector address areas to RAM, set
SYSCR3<RVCTR> to "1" and SYSCR3<RAREA> to "1".
RA003
Page 45
3. Interrupt Control Circuit
TMP89FM46
Note 4: Do not set SYSCR3<RVCTR> to "0" in the serial PROM mode. If an interrupt is generated with SYSCR3<RVCTR> ="0",
the software refers to the vector area in the BOOTROM and the user cannot use it.
RA003
Page 46
Page 47
Figure 3-1 Interrupt Control Circuit
Interrupt source25
Interrupt source 20
Interrupt source 19
Interrupt source 18
Interrupt source 17
Interrupt source 16
Interrupt source 15
Interrupt source 14
Interrupt source 13
Interrupt source 12
Interrupt source 11
Interrupt source 10
Interrupt source 9
Interrupt source 8
Interrupt source 7
Interrupt source 6
Interrupt source 5
Interrupt source 4
INTWDT
INTSWI
INTUNDEF
ILPRS1
ILPRS2
ILPRS3
ILPRS4
ILPRS6
IL4 clear signal
IL4 vector read signal
IL3 vector read signal
Internal factor reset
R
S
R
S
IL4
IL3
Q
Q
IL25 to IL4 reading
Data bus
EF25 to EF4
IL25
IL21
IL20
IL19
IL18
IL17
IL16
IL15
IL14
IL13
IL12
IL11
IL10
IL9
IL8
IL7
IL6
IL5
IL4
A 3
2
B 1
0
EN
Decoder
IL3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Maskable interrupt priority change circuit
Address bus
25
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
1
IMF
Q
Interrupt request
IDLE1/2,SLEEP1/2
Mode clear request
[RETN] instruction
(only when the IMF is set to “1”
before interrupt acceptance)
Instruction to write “1” to IMF
[EI] instruction
[RET1]1 instruction
(only when the IMF is set to “1”
before interrupt acceptance)
Instruction to write
“0” to IMF
DI instruction
Internal factor reset
Interrupt accept
IMF (Interrupt master enable flag)
R
S
Vector address generation
Maskable interrupts
RA003
Non-maskable interrupts
Priority encoder
TMP89FM46
3.1 Configuration
3. Interrupt Control Circuit
3.2 Interrupt Latches (IL25 to IL3)
TMP89FM46
3.2 Interrupt Latches (IL25 to IL3)
An interrupt latch is provided for each interrupt source, except for a software interrupt and an undefined instruction execution interrupt. When an interrupt request is generated, the latch is set to "1", and the CPU is requested to
accept the interrupt if its acceptance is enabled. The interrupt latch is cleared to "0" immediately after the interrupt is
accepted. All interrupt latches are initialized to "0" during reset.
The interrupt latches are located at addresses 0x0FE0, 0x0FE1, 0x0FE2, 0x0FE3 in SFR area. Each latch can be
cleared to "0" individually by an instruction. However, IL2 and IL3 interrupt latches cannot be cleared by instructions.
Do not use any read-modify-write instruction, such as a bit manipulation or operation instruction, because it may
clear interrupt requests generated while the instruction is executed.
Interrupt latches cannot be set to "1" by using an instruction. Writing "1" to an interrupt latch is equivalent to denying clearing of the interrupt latch, and not setting the interrupt latch.
Since interrupt latches can be read by instructions, the status of interrupt requests can be monitored by software.
Note: In the main program, before manipulating an interrupt latch (IL), be sure to clear the master enable flag (IMF) to "0"
(Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the IL (Enable interrupt by EI
instruction).
In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. However, if using multiple interrupt in the interrupt service routine, manipulate the IL before setting the IMF to "1".
Example 1: Clears interrupt latches
; IMF ← 0
DI
LD
(ILL), 0y00111111
LD
(ILH), 0y11101000
; IL7 to IL6 ← 0
; IL12, IL10 to IL8 ← 0
; IMF ← 1
EI
Example 2: Reads interrupt latches
LD
; W ← ILH, A ← ILL
WA, (ILL)
Example 3: Tests interrupt latches
RA003
TEST
(ILL). 7
; if IL7=1 then jump
JR
F, SSET
;
Page 48
TMP89FM46
3.3 Interrupt Enable Register (EIR)
The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable
interrupts (software interrupt, undefined instruction interrupt and watchdog interrupt). Non-maskable interrupts are
accepted regardless of the contents of the EIR.
The EIR consists of the interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These
registers are located at addresses 0x003A, 0x003B, 0x003C, 0x003D in the SFR area, and they can be read and written by instructions (including read-modify-write instructions such as bit manipulation or operation instructions).
3.3.1
Interrupt master enable flag (IMF)
The interrupt master enable flag (IMF) enables and disables the acceptance of all maskable interrupts. Clearing the IMF to "0" disables the acceptance of all maskable interrupts. Setting the IMF to "1" enables the acceptance of the interrupts that are specified by the individual interrupt enable flags.
When an interrupt is accepted, the IMF is stacked and then cleared to "0", which temporarily disables the
subsequent maskable interrupts. After the interrupt service routine is executed, the stacked data, which was the
status before interrupt acceptance, reloaded on the IMF by return interrupt instruction [RETI]/[RETN].
The IMF is located on bit 0 in EIRL (Address: 0x03A in SFR), and can be read and written by instructions.
The IMF is normally set and cleared by [EI] and [DI] instructions respectively. During reset, the IMF is initialized to "0".
3.3.2
Individual interrupt enable flags (EF25 to EF4)
Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding
bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance.
During reset, all the individual interrupt enable flags are initialized to "0" and no maskable interrupts are
accepted until the flags are set to "1".
Note:In the main program, before manipulating the interrupt enable flag (EF), be sure to clear the master enable
flag (IMF) to "0" (Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the EF
(Enable interrupt by EI instruction).
In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally.
However, if using multiple interrupt in the interrupt service routine, manipulate the EF before setting the IMF to
"1".
Example: Enables interrupts individually and sets IMF
; IMF ← 0
DI
LDW
:
(EIRL), 0y1110100010100000
; EF15 to EF13, EF11, EF7, EF5 ← 1
; Note: IMF should not be set.
:
; IMF ← 1
EI
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Page 49
3. Interrupt Control Circuit
3.3 Interrupt Enable Register (EIR)
TMP89FM46
Interrupt latch (ILL)
ILL
(0x0FE0)
7
6
5
4
3
2
1
0
Bit Symbol
IL7
IL6
IL5
IL4
IL3
-
-
-
Read/Write
R/W
R/W
R/W
R/W
R
R
R
R
0
0
0
2
1
0
After reset
Function
0
0
0
0
0
INTTXD0
INTRXD0 /
INTSIO0
INTTBT
INTWUC
INTWDT
7
6
5
4
3
Interrupt latch (ILH)
ILH
(0x0FE1)
Bit Symbol
IL15
IL14
IL13
IL12
IL11
IL10
IL9
IL8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
Function
INTSBI0/
INTSIO0
INTTCA0
INTTC01
INTTC00
INTRTC
INTADC
INTVLTD
INT5
7
6
5
4
3
2
1
0
Interrupt latch (ILE)
ILE
(0x0FE2)
Bit Symbol
IL23
IL22
IL21
IL20
IL19
IL18
IL17
IL16
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
Function
INTTXD1
INTRXD1
INTTCA1
INT4
INT3
INT2
INT1
INT0
Interrupt latch (ILD)
ILD
(0x0FE3)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
-
-
IL25
IL24
Read/Write
R
R
R
R
R
R
R/W
R/W
After reset
0
0
0
0
0
0
0
0
INTTC03
INTTC02
Function
Read
IL25 to IL4
0:
1:
No interrupt request
Interrupt request
0:
1:
No interrupt request
Interrupt request
Interrupt latch
IL3
Write
Clears the interrupt request
(Notes 2 and 3)
Does not clear the interrupt
request
(Interrupt is not set by writing "1".)
-
Note 1: IL3 is a read-only register. Writing the register does not affect interrupt latch.
Note 2: In the main program, before manipulating an interrupt latch (IL), be sure to clear the interrupt master enable flag (IMF) to
"0" (Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the IL (Enable interrupt by EI
instruction).
In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. However, if
using multiple interrupt in the interrupt service routine, manipulate the IL before setting the IMF to "1".
Note 3: Do not clear IL with read-modify-write instructions such as bit operations.
Note 4: When a read instruction is executed on ILL, bits 0 to 2 are read as "0". Other unused bits are read as "0".
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TMP89FM46
Interrupt enable register (EIRL)
EIRL
(0x003A)
7
6
5
4
3
2
1
0
Bit Symbol
EF7
EF6
EF5
EF4
-
-
-
IMF
Read/Write
R/W
R/W
R/W
R/W
R
R
R
R/W
0
0
0
After reset
0
0
0
0
INTTXD0
INTRXD0 /
INTSIO0
INTTBT
INTWUC
Function
0
Interrupt
master enable flag
Interrupt enable register (EIRH)
EIRH
(0x003B)
7
6
5
4
3
2
1
0
Bit Symbol
EF15
EF14
EF13
EF12
EF11
EF10
EF9
EF8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
Function
INTSBI0/
INTSIO0
INTTCA0
INTTC01
INTTC00
INTRTC
INTADC
INTVLTD
INT5
Interrupt enable register (EIRE)
EIRE
(0x003C)
7
6
5
4
3
2
1
0
Bit Symbol
EF23
EF22
EF21
EF20
EF19
EF18
EF17
EF16
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
Function
INTTXD1
INTRXD1
INTTCA1
INT4
INT3
INT2
INT1
INT0
6
5
4
3
2
1
0
Interrupt enable register (EIRD)
EIRD
(0x003D)
7
Bit Symbol
-
-
-
-
-
-
EF25
EF24
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
Function
EF25 to
EF4
IMF
0
0
INTTC03
INTTC02
Individual interrupt enable flag
(Specified for each bit)
0:
1:
Disables the acceptance of each maskable interrupt.
Enables the acceptance of each maskable interrupt.
Interrupt master enable flag
0:
1:
Disables the acceptance of all maskable interrupts.
Enables the acceptance of all maskable interrupts.
Note 1: Do not set the IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time.
Note 2: In the main program, before manipulating the interrupt enable flag (EF), be sure to clear the master enable flag (IMF) to
"0" (Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the EF (Enable interrupt by EI
instruction)
In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. However, if
using multiple interrupt in the interrupt service routine, manipulate the EF before setting the IMF to "1".
Note 3: When a read instruction is executed on EIRL, bits 3 to 1 are read as "0". Other unused bits are read as "0".
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3. Interrupt Control Circuit
3.4 Maskable Interrupt Priority Change Function
TMP89FM46
3.4 Maskable Interrupt Priority Change Function
The priority of maskable interrupts (IL4 to IL25) can be changed to four levels, Levels 0 to 3, regardless of the
basic priorities 5 to 26. Interrupt priorities can be changed by the interrupt priority change control register (ILPRS1
to ILPRS6). To raise the interrupt priority, set the Level to a larger number. To lower the interrupt priority, set the
Level to a smaller number. When different maskable interrupts are generated simultaneously at the same level, the
interrupt with higher basic priority is processed preferentially. For example, when the ILPRS1 register is set to 0xC0
and interrupts IL4 and IL7 are generated at the same time, IL7 is preferentially processed (provided that EF4 and
EF7 have been enabled).
After reset is released, all maskable interrupts are set to priority level 0 (the lowest priority).
Note: In the main program, before manipulating the interrupt priority change control register (ILPRS1 to 6), be sure to
clear the master enable flag (IMF) to "0" (Disable interrupt by DI instruction).
Set the IMF to "1" as required after operating ILPRS1 to 6 (Enable interrupt by EI instruction).
In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. However, if using multiple interrupt in the interrupt service routine, manipulate ILPRS1 to 6 before setting the IMF to "1".
Interrupt priority change control register 1
ILPRS1
(0x0FF0)
7
6
5
4
3
2
1
0
Bit Symbol
IL07P
IL06P
IL05P
IL04P
Read/Write
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
IL07P
Sets the interrupt priority of IL7.
00:
Level 0 (lower priority)
IL06P
Sets the interrupt priority of IL6.
01:
Level 1
IL05P
Sets the interrupt priority of IL5.
10:
Level 2
IL04P
Sets the interrupt priority of IL4.
11:
Level 3 (higher priority)
0
0
2
1
0
Interrupt priority change control register 2
ILPRS2
(0x0FF1)
7
Bit Symbol
Read/Write
After reset
6
5
IL11P
R/W
0
4
3
IL10P
IL09P
R/W
0
0
R/W
0
0
IL11P
Sets the interrupt priority of IL11.
00:
Level 0 (lower priority)
IL10P
Sets the interrupt priority of IL10.
01:
Level 1
IL09P
Sets the interrupt priority of IL9.
10:
Level 2
IL08P
Sets the interrupt priority of IL8.
11:
Level 3 (higher priority)
0
IL08P
R/W
0
0
2
1
0
Interrupt priority change control register 3
ILPRS3
(0x0FF2)
7
Bit Symbol
Read/Write
After reset
RA003
6
5
IL15P
R/W
0
4
3
IL14P
IL13P
R/W
0
0
R/W
0
0
IL15P
Sets the interrupt priority of IL15.
00:
Level 0 (lower priority)
IL14P
Sets the interrupt priority of IL14.
01:
Level 1
IL13P
Sets the interrupt priority of IL13.
10:
Level 2
IL12P
Sets the interrupt priority of IL12.
11:
Level 3 (higher priority)
Page 52
0
IL12P
R/W
0
0
0
TMP89FM46
Interrupt priority change control register 4
ILPRS4
(0x0FF3)
7
6
5
4
3
2
1
0
Bit Symbol
IL19P
IL18P
IL17P
IL16P
Read/Write
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
IL19P
Sets the interrupt priority of IL19.
00:
Level 0 (lower priority)
IL18P
Sets the interrupt priority of IL18.
01:
Level 1
IL17P
Sets the interrupt priority of IL17.
10:
Level 2
IL16P
Sets the interrupt priority of IL16.
11:
Level 3 (higher priority)
0
0
2
1
0
Interrupt priority change control register 5
ILPRS5
(0x0FF4)
7
Bit Symbol
6
5
IL23P
Read/Write
R/W
After reset
0
4
3
IL22P
IL21P
R/W
0
0
R/W
0
0
IL23P
Sets the interrupt priority of IL23.
00:
Level 0 (lower priority)
IL22P
Sets the interrupt priority of IL22.
01:
Level 1
IL21P
Sets the interrupt priority of IL21.
10:
Level 2
IL20P
Sets the interrupt priority of IL20.
11:
Level 3 (higher priority)
0
IL20P
R/W
0
0
2
1
0
Interrupt priority change control register 6
ILPRS6
(0x0FF5)
7
Bit Symbol
Read/Write
5
4
0
3
-
R/W
After reset
RA003
6
-
IL25P
R/W
0
0
R/W
0
0
-
-
00:
Level 0 (lower priority)
-
-
01:
Level 1
IL25P
Sets the interrupt priority of IL25.
10:
Level 2
IL24P
Sets the interrupt priority of IL24.
11:
Level 3 (higher priority)
Page 53
0
IL24P
R/W
0
0
0
3. Interrupt Control Circuit
3.5 Interrupt Sequence
TMP89FM46
3.5 Interrupt Sequence
An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to
by resetting or an instruction. Interrupt acceptance sequence requires 8-machine cycles after the completion of
the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI]
(for maskable interrupts) or [RETN] (for non-maskable interrupts).
“0”
3.5.1
Initial Setting
Using an interrupt requires specifying an SP (stack pointer) for it in advance. The SP is a 16-bit register
pointing at the start address of a stack. The SP is post-decremented when a subroutine call or a push instruction
is executed or when an interrupt request is accepted. It is pre-incremented when a return or pop instruction is
executed. Therefore, the stack becomes deeper toward lower stack location addresses. Be sure to reserve a
stack area having an appropriate size based on the SP setting.
The SP is initialized to 00FFH after a reset. If you need to change the SP, do so right after a reset or when the
interrupt master enable flag (IMF) is “0”.
Example :SP setting
3.5.2
LD
SP, 023FH
; SP = 023FH
LD
SP, SP+04H
; SP = SP + 04H
ADD
SP, 0010H
; SP = SP + 0010H
Interrupt acceptance processing
Interrupt acceptance processing is packaged as follows.
1. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any following interrupt.
2. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
3. The contents of the program counter (PC) and the program status word, including the interrupt master
enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3.
4. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the
vector table, is transferred to the program counter.
5. The instruction stored at the entry address of the interrupt service program is executed.
Note:When the contents of PSW are saved on the stack, the contents of register bank and IMF are also saved.
Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt
service program
Vector table address
Vector table address
0xFFF4
0x03
0xD203
0x0F
0xFFF5
0xD2
0xD204
0x06
Figure 3-2 Vector table address and Entry address
RA003
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TMP89FM46
A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt is requested in
the interrupt service routine.
In order to utilize nested interrupt service, the IMF must be set to “1” in the interrupt service program. In this
case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced,
before setting IMF to “1”. As for non-maskable interrupt, keep interrupt service shorter compared with length
between interrupt requests.
3.5.3
Saving/restoring general-purpose registers
During interrupt acceptance processing, the program counter (PC) and the program status word (PSW,
includes IMF) are automatically saved on the stack, but the general purpose registers are not. These registers
must be saved by software if necessary. When multiple interrupt services are nested, it is also necessary to
avoid using the same data memory area for saving registers. The following methods are used to save/restore the
general-purpose registers.
3.5.3.1
Using PUSH and POP instructions
To save only a specific register, PUSH and POP instructions are available.
Example :Using PUSH and POP instructions
PINTxx
PUSH
WA
; Save WA register
Interrupt processing
POP
WA
; Restore WA register
RETI
; RETURN
Address
(Example)
SP
A
SP
W
b-4
SP
b-3
PCL
PCL
PCL
b-2
PCH
PCH
PCH
b-1
PSW
PSW
PSW
At Acceptance of
an Interrupt
At execution of
PUSH instruction
At execution of
POP instruction
SP
b
At execution of
an RETI instruction
Figure 3-3 Saving/restoring general-purpose registers
RA003
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3. Interrupt Control Circuit
3.5 Interrupt Sequence
TMP89FM46
3.5.3.2
Using data transfer instructions
To save only a specific register without nested interrupts, data transfer instructions are available.
Example :Save/store register using data transfer instructions
PINTxx:
LD
(GSAVA), A
; Save A register
A, (GSAVA)
; Restore A register
Interrupt processing
LD
RETI
; RETURN
Main task
Interrupt acceptance Interrupt
service task
Saving
registers
Restoring
registers
Interrupt return
Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing
3.5.3.3
Using a register bank to save/restore general-purpose registers
In non-multiple interrupt handling, the register bank function can be used to save/restore the generalpurpose registers at a time. The register bank function saves (switches) the general-purpose registers by
executing a register bank manipulation instruction (such as LD RBS,1) at the beginning of an interrupt
service task. It is unnecessary to re-execute the register bank manipulation instruction at the end of the
interrupt service task because executing the RETI instruction makes a return automatically to the register
bank that was being used by the main task according to the content of the PSW.
Note: Two register banks (BANK0 and BANK1) are available. Each bank consists of 8-bit general-purpose
registers (W, A, B, C, D, E, H, and L) and 16-bit general-purpose registers (IX and IY).
Example :Saving/restoring registers, using an instruction for transfer with data memory (with the main task using the register bank BANK0)
PINTxx:
LD
RBS, 1
; Switches to the register bank BANK1
Interrupt processing
RETI
; RETURN
(Makes a return automatically to BANK0 that
was being used by the main task when the
PSW is restored)
RA003
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TMP89FM46
Main task
Interrupt acceptance Interrupt
service task
The register bank
BANK0 is in use.
LD (RBS),1
Switching occurs to
the register bank BANK1.
Interrupt return
A return is made automatically to
the register bank BANK0.
Figure 3-5 Saving/Restoring General-purpose Registers under Interrupt Processing
3.5.4
Interrupt return
Interrupt return instructions [RETI]/[RETN] perform as follows.
[RETI]/[RETN] Interrupt Return
1. Program counter (PC) and program status word (register bank) are
restored from tha stack.
2. Stack pointer (SP) is incremented by 3.
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3. Interrupt Control Circuit
3.6 Software Interrupt (INTSW)
TMP89FM46
3.6 Software Interrupt (INTSW)
Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW
is the top-priority interrupt).
Use the SWI instruction only for address error detection or for debugging described below.
3.6.1
Address error detection
0xFF is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent
memory address. Code 0xFF is an SWI instruction, so a software interrupt is generated and an address error is
detected. The address error detection range can be further expanded by writing 0xFF to unused areas in the program memory.
3.6.2
Debugging
Debugging efficiency can be increased by placing the SWI instruction at the software break point setting
address.
3.7 Undefined Instruction Interrupt (INTUNDEF)
When the CPU tries to fetch and execute an instruction that is not defined, INTUNDEF is generated and starts the
interrupt processing. INTUNDEF is accepted even if another non-maskable interrupt is in process. The current process is discontinued and the INTUNDEF interrupt process starts soon after it is requested.
Note: The undefined instruction interrupt (INTUNDEF) forces the CPU to jump into the interrupt vector address, as software interrupt (SWI) does.
RA003
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TMP89FM46
4. External Interrupt control circuit
External interrupts detects the change of the input signal and generates an interrupt request. Noise can be removed
by the built-in digital noise canceller.
4.1 Configuration
The external interrupt control circuit consists of a noise canceller, an edge detection circuit, a level detection circuit and an interrupt signal generation circuit.
Externally input signals are input to the rising edge or falling edge or level detection circuit for each external interrupt, after noise is removed by the noise canceller.
INTj pin
Falling edge
detection circuit
Noise canceller
Interrupt request signal
generation circuit
INTj interr
request
j=0,5
fcgck
fs/4
Figure 4-1 External Interrupts 0/5
INTi pin
Noise canceller
fs/4
Z
A B C DS
Rising edge
detection circuit
Falling edge
detection circuit
Interrupt request
signal generation
circuit
INTi interrupt
request
i=1 to 3
INTiES
INTiLVL
fcgck
1 2 3 4
EINTCRi
Figure 4-2 External Interrupts 1/2/3
Rising edge
detection circuit
INT4 pin
Noise canceller
fs
Z
Falling edge
detection circuit
Level detection
circuit
Interrupt request
signal generation
circuit
A B C DS
INT4ES
INT4LVL
fcgck
1 2 3 4
EINTCR4
Figure 4-3 External Interrupt 4
RA000
Page 59
INT4 interrupt
request
4. External Interrupt control circuit
4.2 Control
TMP89FM46
4.2 Control
External interrupts are controlled by the following registers:
Low power consumption register 3
POFFCR3
(0x0F77)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
INT5EN
INT4EN
INT3EN
INT2EN
INT1EN
INT0EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
INT5EN
INT5 control
0
1
Disable
Enable
INT4EN
INT4 control
0
1
Disable
Enable
INT3EN
INT3 control
0
1
Disable
Enable
INT2EN
INT2 control
0
1
Disable
Enable
INT1EN
INT1 control
0
1
Disable
Enable
INT0EN
INT0 control
0
1
Disable
Enable
Note 1: Clearing INTxEN(x=0 to 5) to "0" stops the clock supply to the external interrupts. This invalidates the data written
in the control register for each external interrupt. When using the external interrupts, set INTxEN to "1" and then
write data into the control register for each external interrupt.
Note 2: Interrupt request signals may be generated when INTxEN is changed. Before changing INTxEN, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is
changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed
and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/
2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
Note 3: Bits 7 and 6 of POFFSET3 are read as "0".
External interrupt control register 1
EINTCR1
(0x0FD8)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
INT1LVL
INT1ES
INT1NC
Read/Write
R
R
R
R
R/W
R/W
After reset
0
0
0
0
0
0
INI1LVL
Noise canceller pass signal level
when the interrupt request signal is
generated for external interrupt 1
0:
1:
00 :
INT1ES
Selects the interrupt request generating condition for external interrupt
1
01 :
10 :
11 :
Initial state or signal level "L"
Signal level "H"
An interrupt request is generated at the rising edge of the noise canceller
pass signal
An interrupt request is generated at the falling edge of the noise canceller
pass signal
An interrupt request is generated at both edges of the noise canceller
pass signal
Reserved
NORMAL1/2, IDLE1/2
INT1NC
Sets the noise canceller sampling
interval for external interrupt 1
00 :
01 :
10 :
11 :
fcgck [Hz]
fcgck / 22 [Hz]
fcgck / 23 [Hz]
fcgck / 24 [Hz]
SLOW1/2, SLEEP1
00 :
01 :
10 :
11 :
fs/4
fs/4
fs/4
fs/4
[Hz]
[Hz]
[Hz]
[Hz]
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear
the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is
changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and
RA000
Page 60
TMP89FM46
clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2,
wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
Note 3: Interrupt requests may be generated when EINTCR1 is changed. Before doing such operation, clear the corresponding
interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from
NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/
fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
Note 4: Bits 7 to 5 of EINTCR1 are read as "0".
External interrupt control register 2
EINTCR1
(0x0FD9)
7
6
5
4
Bit Symbol
-
-
-
INT2LVL
INT2ES
INT2NC
Read/Write
R
R
R
R
R/W
R/W
After reset
0
0
0
0
0
0
INI2LVL
Noise canceller pass signal level
when the interrupt request signal is
generated for external interrupt 2
0:
1:
00 :
INT2ES
Selects the interrupt request generating condition for external interrupt
2
01 :
10 :
11 :
3
2
1
Initial state or signal level "L"
Signal level "H"
An interrupt request is generated at the rising edge of the noise canceller
pass signal
An interrupt request is generated at the falling edge of the noise canceller
pass signal
An interrupt request is generated at both edges of the noise canceller
pass signal
Reserved
NORMAL1/2, IDLE1/2
INT2NC
Sets the noise canceller sampling
interval for external interrupt 2
00 :
01 :
10 :
11 :
0
SLOW1/2, SLEEP1
fcgck [Hz]
00 :
01 :
10 :
11 :
fcgck / 22 [Hz]
fcgck / 23 [Hz]
fcgck / 24 [Hz]
fs/4
fs/4
fs/4
fs/4
[Hz]
[Hz]
[Hz]
[Hz]
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear
the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is
changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and
clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2,
wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
Note 3: Interrupt requests may be generated when EINTCR2 is changed. Before doing such operation, clear the corresponding
interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from
NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/
fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
Note 4: Bits 7 to 5 of EINTCR2 are read as "0".
External interrupt control register 3
EINTCR3
(0x0FDA)
RA000
7
6
5
4
Bit Symbol
-
-
-
INT3LVL
INT3ES
INT3NC
Read/Write
R
R
R
R
R/W
R/W
After reset
0
0
0
0
0
0
Page 61
3
2
1
0
4. External Interrupt control circuit
4.2 Control
TMP89FM46
INI3LVL
Noise canceller pass signal level
when the interrupt request signal is
generated for external interrupt 3
0:
1:
00 :
INT3ES
Selects the interrupt request generating condition for external interrupt
3
01 :
10 :
11 :
Initial state or signal level "L"
Signal level "H"
An interrupt request is generated at the rising edge of the noise canceller
pass signal
An interrupt request is generated at the falling edge of the noise canceller
pass signal
An interrupt request is generated at both edges of the noise canceller
pass signal
Reserved
NORMAL1/2, IDLE1/2
INT3NC
Sets the noise canceller sampling
interval for external interrupt 3
00 :
01 :
10 :
11 :
SLOW1/2, SLEEP1
fcgck [Hz]
00 :
01 :
10 :
11 :
fcgck / 22 [Hz]
fcgck / 23 [Hz]
fcgck / 24 [Hz]
fs/4
fs/4
fs/4
fs/4
[Hz]
[Hz]
[Hz]
[Hz]
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear
the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is
changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and
clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2,
wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
Note 3: Interrupt requests may be generated when EINTCR3 is changed. Before doing such operation, clear the corresponding
interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from
NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/
fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
Note 4: Bits 7 to 5 of EINTCR3 are read as "0".
External interrupt control register 4
EINTCR4
(0x0FDB)
7
6
5
4
Bit Symbol
-
-
-
INT4LVL
INT4ES
INT4NC
Read/Write
R
R
R
R
R/W
R/W
After reset
0
0
0
0
0
0
INI4LVL
Noise canceller pass signal level
when the interrupt request signal is
generated for external interrupt 4
0:
1:
00 :
INT4ES
Selects the interrupt request generating condition for external interrupt
4
01 :
10 :
11 :
3
2
1
Initial state or signal level "L"
Signal level "H"
An interrupt request is generated at the rising edge of the noise canceller
pass signal
An interrupt request is generated at the falling edge of the noise canceller
pass signal
An interrupt request is generated at both edges of the noise canceller
pass signal
An interrupt request is generated at "H" of the noise canceller pass signal
NORMAL1/2, IDLE1/2
INT4NC
Sets the noise canceller sampling
interval for external interrupt 4
00 :
01 :
10 :
11 :
0
fcgck [Hz]
fcgck / 22 [Hz]
fcgck / 23 [Hz]
fcgck / 24 [Hz]
SLOW1/2, SLEEP1
00 :
01 :
10 :
11 :
fs/4
fs/4
fs/4
fs/4
[Hz]
[Hz]
[Hz]
[Hz]
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear
the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is
changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and
clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2,
wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
Note 3: Interrupt requests may be generated when EINTCR4 is changed. Before doing such operation, clear the corresponding
interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from
NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/
fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
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TMP89FM46
Note 4: The contents of EINTCRx<INTxLVL> are updated each time an interrupt request signal is generated.
Note 5: Bits 7 to 5 of EINTCR4 are read as "0".
4.3 Function
The condition for generating interrupt request signals and the noise cancel time can be set for external interrupts 1
to 4.
The condition for generating interrupt request signals and the noise cancel time are fixed for external interrupts 0
and 5.
Table 4-1 External Interrupts
Source
Pin
Enable conditions
External interrupt pin input signal width and noise removal
Interrupt request
signal generated at
NORMAL1/2, IDLE1/2
SLOW1/2, SLEEP1
INT0
IMF AND EF16 =
1
Falling edge
Less than 1/fcgck: Noise
More than 1/fcgck and less than 2/
fcgck: Indeterminate
More than 2/fcgck: Signal
Less than 4/fs: Noise
More than 4/fs and less than 8/fs: Indeterminate
More than 8/fs: Signal
INT1
INT1
IMF AND EF17 =
1
Falling edge
Rising edge
Both edges
Less than 2/fspl: Noise
More than 2/fspl and less than 3/fspl+1/
fcgck: Indeterminate
More than 3/fspl+1/fcgck: Signal
Less than 4/fs: Noise
More than 4/fs and less than 8/fs: Indeterminate
More than 8/fs: Signal
INT2
INT2
IMF AND EF18 =
1
Falling edge
Rising edge
Both edges
Less than 2/fspl: Noise
More than 2/fspl and less than 3/fspl+1/
fcgck: Indeterminate
More than 3/fspl+1/fcgck: Signal
Less than 4/fs: Noise
More than 4/fs and less than 8/fs: Indeterminate
More than 8/fs: Signal
INT3
INT3
IMF AND EF19 =
1
Falling edge
Rising edge
Both edges
Less than 2/fspl: Noise
More than 2/fspl and less than 3/fspl+1/
fcgck: Indeterminate
More than 3/fspl+1/fcgck: Signal
Less than 4/fs: Noise
More than 4/fs and less than 8/fs: Indeterminate
More than 8/fs: Signal
INT4
INT4
IMF AND EF20 =
1
Falling edge
Rising edge
Both edges
"H" level
Less than 2/fspl: Noise
More than 2/fspl and less than 3/fspl+1/
fcgck: Indeterminate
More than 3/fspl+1/fcgck: Signal
Less than 4/fs: Noise
More than 4/fs and less than 8/fs: Indeterminate
More than 8/fs: Signal
Falling edge
Less than 1/fcgck: Noise
More than 1/fcgck and less than 2/
fcgck: Indeterminate
More than 2/fcgck: Signal
Less than 4/fs: Noise
More than 4/fs and less than 8/fs: Indeterminate
More than 8/fs: Signal
INT0
INT5
INT5
IMF AND EF8 = 1
Note 1: fcgck, Gear clock [Hz]; fs, low frequency clock [Hz]; fspl, Sampling interval [Hz]
4.3.1
Low power consumption function
External interrupts have a function that saves power by using the low power consumption register
(POFFCR3) when they are not used.
Setting POFFCR3<INTxEN> to "0" stops (disables) the basic clock for external interrupts and helps save
power. Note that this makes external interrupts unavailable. Setting POFFCR3<INTxEN> to "1" supplies
(enables) the basic clock for external interrupts and makes external interrupts available.
After reset, POFFCR3<INTxEN> is initialized to "0" and external interrupts become unavailable. When
using the external interrupt function for the first time, be sure to set POFFCR3<INTxEN> to "1" in the initial
setting of software (before operating the external interrupt control registers).
Note:Interrupt request signals may be generated when INTxEN is changed. Before changing INTxEN, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is
changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is
changed and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to
NORMAL1/2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt
latch.
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4. External Interrupt control circuit
4.3 Function
TMP89FM46
4.3.2
External interrupt 0
External interrupt 0 detects the falling edge of the INT0 pin and generates interrupt request signals.
In NORMAL1/2 or IDLE1/2 mode, pulses of less than 1/fcgck are removed as noise and pulses of 2/fcgck or
more are recognized as signals.
In SLOW/SLEEP mode, pulses of less than 4/fs are removed as noise and pulses of 8/fs or more are recognized as signals.
4.3.3
External interrupts 1/2/3
External interrupts 1/2/3 detect the falling edge, the rising edge or both edges of the INT1, INT2 and INT3
pins and generate interrupt request signals.
4.3.3.1
Interrupt request signal generating condition detection function
Select interrupt request signal generating conditions at EINTCRx<INTxES> for external interrupts 1/2/
3.
Table 4-2 Selection of Interrupt Request Generation Edge
EINTCRx<INTxES>
Detected at
00
Rising edge
01
Falling edge
10
Both edges
11
Reserved
Note: x=1 to 3
4.3.3.2
A noise canceller pass signal monitoring function when interrupt request signals are
generated
The level of a signal that has passed through the noise canceller when an interrupt request is generated
can be read by using EINTCRx<INTxLVL>. When both edges are selected as detection edges, the edge
where an interrupt is generated can be detected by reading EINTCRx<INTxLVL>.
INTi pin
Signal that has passed through
the noise canceller
Interrupt request signal
(detected at the falling edge)
INT LVL
Interrupt request signal
(detected at the rising edge)
INT LVL
Interrupt request signal
(detected at both edges)
INT LVL
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TMP89FM46
Note: The contents of EINTCRx<INTxLVL> are updated each time an interrupt request signal is generated.
Figure 4-4 Interrupt Request Generation and EINTCRx<INTxLVL>
4.3.3.3
Noise cancel time selection function
In NORMAL1/2 or IDLE1/2 mode, a signal that has been sampled by fcgck is sampled at the sampling
interval selected at EINTCRx<INTxNC>. If the same level is detected three consecutive times, the signal
is recognized as a signal. If not, the signal is removed as noise.
Table 4-3 Noise Canceller Sampling Lock
EINTCRx<INTxNC>
Sampling interval
00
fcgck
01
fcgck/22
10
fcgck/23
11
fcgck/24
INTi pin
i=1 to 3
Signal
Noise
Signal after noise removal
Figure 4-5 Noise Cancel Operation
In SLOW1/2 or SLEEP1 mode, a signal is sampled by the low frequency clock divided by 4. If the same
level is detected twice consecutively, the signal is recognized as a signal.
In IDLE0, SLEEP0 or STOP mode, the noise canceller sampling operation is stopped and an external
interrupts are unavailable. When operation returns to NORMAL1/2, IDLE1/2, SLOW1/2 or SLEEP1
mode, sampling operation restarts.
Note 1: If noise is input consecutively during sampling of external interrupt pins, the noise cancel function
does not work properly. Set EINTCRx<INTxNC> according to the cycle of externally input noise.
Note 2: If an external interrupt pin is used as an output port, the input signal to the port is fixed to "L" when the
mode is switched to the output mode, and thus an interrupt request occurs. To use the pin as an output port, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt.
Note 3: Interrupt requests may be generated during transition of the operation mode. Before changing the
operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of
interrupt. When the operation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or
SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when
the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/
fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
4.3.4
External interrupt 4
External interrupt 4 detects the falling edge, the rising edge, both edges or "H" level of the INT4 pin and generates interrupt request signals.
4.3.4.1
Interrupt request signal generating condition detection function
Select an interrupt request signal generating condition at EINTCR4<INT4ES> for external interrupt 4.
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4. External Interrupt control circuit
4.3 Function
TMP89FM46
Table 4-4 Selection of Interrupt Request Generation Edge
4.3.4.2
EINTCR4<INT4ES>
Detected at
00
Rising edge
01
Falling edge
10
Both edges
11
"H" level interrupt
A noise canceller pass signal monitoring function when interrupt request signals are
generated
The level of a signal that has passed through the noise canceller when an interrupt request is generated
can be read by using EINTCR4<INT4LVL>. When both edges are selected as detection edges, the edge
where an interrupt is generated can be detected by reading EINTCR4<INT4LVL>.
INT4 pin
Signal that has passed through
the noise canceller
Interrupt request signal
(detected at the falling edge)
INT4LVL
Interrupt request signal
(detected at the rising edge)
INT4LVL
Interrupt request signal
(detected at both edges)
INT4LVL
Interrupt request signal
(level detection)
INT4LVL
Figure 4-6 Interrupt Request Generation and EINTCR4<INT4LVL>
4.3.4.3
Noise cancel time selection function
In NORMAL1/2 or IDLE1/2 mode, a signal that has been sampled by fcgck is sampled at the sampling
interval selected at EINTCRx<INT4NC>. If the same level is detected three consecutive times, the signal
is recognized as a signal. If not, the signal is removed as noise.
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TMP89FM46
Table 4-5 Noise Canceller Sampling Lock
EINTCR4<INT4NC>
Sampling interval
00
fcgck
01
fcgck/22
10
fcgck/23
11
fcgck/24
Signal
INT4 pin
Noise
Signal after noise removal
Figure 4-7 Noise Cancel Operation
In SLOW1/2 or SLEEP1 mode, a signal is sampled by the low frequency clock divided by 4. If the same
level is detected twice consecutively, the signal is recognized as a signal.
In IDLE0, SLEEP0 or STOP mode, the noise canceller sampling operation is stopped and an external
interrupts are unavailable. When operation returns to NORMAL1/2, IDLE1/2, SLOW1/2 or SLEEP1
mode, sampling operation restarts.
Note 1: When noise is input consecutively during sampling external interrupt pins, the noise cancel function
does not work properly. Set EINTCRx<INTxNC> according to the cycle of externally input noise.
Note 2: When an external interrupt pin is used as an output port, the input signal to the port is fixed to "L"
when the mode is switched to the output mode, and thus an interrupt request occurs. To use the pin
as an output port, clear the corresponding interrupt enable register to "0" to disable the generation of
interrupt.
Note 3: Interrupt requests may be generated during transition of the operation mode. Before changing the
operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of
interrupt. When the operation mode is changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or
SLEEP1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. And when
the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/2 or IDLE1/2, wait 2/
fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.
4.3.5
External interrupt 5
External interrupt 5 detects the falling edge of the INT5 pin and generates interrupt request signals.
In NORMAL1/2 or IDLE1/2 mode, pulses of less than 1/fcgck are removed as noise and pulses of 2/fcgck or
more are recognized as signals.
In SLOW/SLEEP mode, pulses of less than 4/fs are removed as noise and pulses of 8/fs or more are recognized as signals.
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4. External Interrupt control circuit
4.3 Function
RA000
TMP89FM46
Page 68
TMP89FM46
5. Watchdog Timer (WDT)
The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine.
The watchdog timer signals used for detecting malfunctions can be programmed as watchdog interrupt request signals or watchdog timer reset signals.
Note: Care must be taken in system designing since the watchdog timer may not fulfill its functions due to disturbing noise
and other effects.
5.1 Configuration
10
Selector
fcgck/2 or fs/23
12
fcgck/2 or fs/25
14
fcgck/2 or fs/27
16
fcgck/2 or fs/29
Source clock
2
8-bit up counter
3 4 5 6 7
8
Watchdog timer interrupt requestl
Interrupt
request/reset
signal control
circuit
Overflow
Clear
Watchdog timer reset signal
2
8
CPU/peripheral circuits reset
Clear time control circuit
Disable
control circuit
Disable code
(0xB1)
Clear code
(0x4E)
WDTST
WINTST2
WINTST1
WDTT
WDTOUT
WDCDR
WDTW
WDCNT
WDTEN
Control code
decoder
WDST
WDCTR
Figure 5-1 Watchdog Timer Configuration
5.2 Control
The watchdog timer is controlled by the watchdog timer control register (WDCTR), the watchdog timer control
code register (WDCDR), the watchdog timer counter monitor (WDCNT) and the watchdog timer status (WDST).
The watchdog timer is enabled automatically just after the warm-up operation that follows reset is finished.
Watchdog timer control register
WDCTR
(0x0FD4)
RA000
7
6
5
4
3
2
1
0
Bit Symbol
-
-
WDTEN
WDTW
WDTT
WDTOUT
Read/Write
R
R
R/W
R/W
R/W
R/W
After reset
1
0
1
Page 69
0
0
1
1
0
5. Watchdog Timer (WDT)
5.2 Control
TMP89FM46
WDTEN
Enables/disables the watchdog
timer operation.
0:
1:
00 :
01 :
WDTW
Sets the clear time of the 8-bit up
counter.
10 :
11 :
Disable
Enable
The 8-bit up counter is cleared by writing the clear code at any point within
the overflow time of the 8-bit up counter.
A watchdog timer interrupt request is generated by writing the clear code
at a point within the first quarter of the overflow time of the 8-bit up
counter. The 8-bit up counter is cleared by writing the clear code after the
first quarter of the overflow time has elapsed.
A watchdog timer interrupt request is generated by writing the clear code
at a point within the first half of the overflow time of the 8-bit up counter.
The 8-bit up counter is cleared by writing the clear code after the first half
of the overflow time has elapsed.
A watchdog timer interrupt request is generated by writing the clear code
at a point within the first three quarters of the overflow time of the 8-bit up
counter. The 8-bit up counter is cleared by writing the clear code after the
first three quarters of the overflow time have elapsed.
NORMAL mode
SLOW mode
WDTT
WDTOUT
Sets the overflow time of the 8-bit
up counter.
DV9CK=0
DV9CK=1
00 :
218/fcgck
211/fs
211/fs
01:
220/fcgck
213/fs
213/fs
10:
222/fcgck
215/fs
215/fs
11:
224/fcgck
217/fs
217/fs
Selects an overflow detection signal
of the 8-bit up counter.
0:
1:
Watchdog timer interrupt request signal
Watchdog timer reset request signal
Note 1: fcgck, Gear clock [Hz]; fs, Low frequency clock [Hz]
Note 2: WDCTR<WDTW>, WDCTR<WDTT> and WDCTR<WDTOUT> cannot be changed when WDCTR<WDTEN> is "1". If
WDCTR<WDTEN> is "1", clear WDCTR<WDTEN> to "0" and write the disable code (0xB1) into WDCDR to disable the
watchdog timer operation. Note that WDCTR<WDTW>, WDCTR<WDTT> and WDCTR<WDTOUT> can be changed at
the same time as setting WDCTR<WDTEN> to "1".
Note 3: Bit 7 and bit 6 of WDCTR are read as "1" and "0" respectively.
Watchdog timer control code register
WDCDR
(0x0FD5)
7
6
5
4
Bit Symbol
Read/Write
2
1
0
0
0
0
0
W
After reset
WDTCR2
3
WDTCR2
0
0
0
0
0x4E :
0xB1 :
Writes watchdog timer control
codes.
Others :
Clears the watchdog timer. (Clear code)
Disables the watchdog timer operation and clears the 8-bit up
counter when WDCTR<WDTEN> is "0". (Disable code)
Invalid
Note: WDCDR is a write-only register and must not be accessed by using a read-modify-write instruction, such as a bit operation.
8-bit up counter monitor
WDCNT
(0x0FD6)
7
5
4
Bit Symbol
WDCNT
Read/Write
R
After reset
WDCNT
RA000
6
0
0
Monitors the count value of the 8-bit
up counter
0
0
3
2
1
0
0
0
0
0
The count value of the 8-bit up counter is read.
Page 70
TMP89FM46
Watchdog timer status
WDST
(0x0FD7)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
-
WINTST2
WINTST1
WDTST
Read/Write
R
R
R
R
R
R
R
R
After reset
0
1
0
1
1
0
0
1
WINTST2
Watchdog timer interrupt request
signal factor status 2
WINTST1
Watchdog timer interrupt request
signal factor status 1
WDTST
Watchdog timer operating state status
0:
1:
No watchdog timer interrupt request signal has occurred.
A watchdog timer interrupt request signal has occurred due to the overflow of the 8-bit up counter.
0:
1:
No watchdog timer interrupt request signal has occurred.
A watchdog timer interrupt request signal has occurred due to releasing of
the 8-bit up counter outside the clear time.
0:
1:
Operation disabled
Operation enabled
Note 1: WDST<WINTST2> and WDST<WINTST1> are cleared to "0" by reading WDST.
Note 2: Values after reset are read from bits 7 to 3 of WDST.
5.3 Functions
The watchdog timer can detect the CPU malfunctions and deadlock by detecting the overflow of the 8-bit up
counter and detecting releasing of the 8-bit up counter outside the clear time.
The watchdog timer stoppage and other abnormalities can be detected by reading the count value of the 8-bit up
counter at random times and comparing the value to the last read value.
5.3.1
Setting of enabling/disabling the watchdog timer operation
Setting WDCTR<WDTEN> to "1" enables the watchdog timer operation, and the 8-bit up counter starts
counting the source clock.
WDCTR<WDTEN> is initialized to "1" after the warm-up operation that follows reset is released. This
means that the watchdog timer is enabled.
To disable the watchdog timer operation, clear WDCTR<WDTEN> to "0" and write 0xB1 into WDCDR.
Disabling the watchdog timer operation clears the 8-bit up counter to "0".
Note:If the overflow of the 8-bit up counter occurs at the same time as 0xB1 (disable code) is written into WDCDR
with WDCTR<WDTEN> set at "1", the watchdog timer operation is disabled preferentially and the overflow
detection is not executed.
To re-enable the watchdog timer operation, set WDCTR<WDTEN> to "1". There is no need to write a control code into WDCDR.
Watchdog timer source clock
8-bit up counter value
00H
FFH
01H
WDCTR<WDTEN>
Overflow time
WDCTR<WDTEN>
Overflow time
Interrupt request signal
1 clock (max.)
Figure 5-2 WDCTR<WDTEN> Set Timing and Overflow Time
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00H
5. Watchdog Timer (WDT)
5.3 Functions
TMP89FM46
Note:The 8-bit up counter source clock operates out of synchronization with WDCTR<WDTEN>. Therefore, the first
overflow time of the 8-bit up counter after WDCTR<WDTEN> is set to "1" may get shorter by a maximum of 1
source clock. The 8-bit up counter must be cleared within the period of the overflow time minus 1 source clock
cycle.
5.3.2
Setting the clear time of the 8-bit up counter
WDCTR<WDTW> sets the clear time of the 8-bit up counter.
When WDCTR<WDTW> is "00", the clear time is equal to the overflow time of the 8-bit up counter, and the
8-bit up counter can be cleared at any time.
When WDCTR<WDTW> is not "00", the clear time is fixed to only a certain period within the overflow
time of the 8-bit up counter. If the operation for releasing the 8-bit up counter is attempted outside the clear
time, a watchdog timer interrupt request signal occurs.
At this time, the watchdog timer is not cleared but continues counting. If the 8-bit up counter is not cleared
within the clear time, a watchdog timer reset request signal or a watchdog timer interrupt request signal occurs
due to the overflow, depending on the WDCTR<WDTOUT> setting.
8-bit up counter value FFH 00H 01H
3FH 40H
When WDCTR<WDTW> is 00
When WDCTR<WDTW> is 01
When WDCTR<WDTW> is 10
7FH 80H
BFH C0H
FFH 00H
Clear time
Outside the clear time
Clear time
Outside the clear time
When WDCTR<WDTW> is 11
Clear time
Outside the clear time
Clear time
Figure 5-3 WDCTR<WDTW> and the 8-bit up Counter Clear Time
5.3.3
Setting the overflow time of the 8-bit up counter
WDCTR<WDTT> sets the overflow time of the 8-bit up counter.
When the 8-bit up counter overflows, a watchdog timer reset request signal or a watchdog timer interrupt
request signal occurs, depending on the WDCTR<WDTOUT> setting.
If the watchdog timer interrupt request signal is selected as the malfunction detection signal, the watchdog
counter continues counting, even after the overflow has occurred.
The watchdog timer temporarily stops counting up in the STOP mode (including warm-up) or in the IDLE/
SLEEP mode, and restarts counting up after the STOP/IDLE/SLEEP mode is released. To prevent the 8-bit up
counter from overflowing immediately after the STOP/IDLE/SLEEP mode is released, it is recommended to
clear the 8-bit up counter before the operation mode is changed.
Table 5-1 Watchdog Timer Overflow Time (fcgck=10.0 MHz; fs=32.768 kHz)
Watchdog timer overflow time [s]
WDTT
RA000
NORMAL mode
DV9CK = 0
DV9CK = 1
SLOW
mode
00
26.21 m
62.50 m
62.50 m
01
104.86 m
250.00 m
250.00 m
10
419.43 m
1.000
1.000
11
1.678
4.000
4.000
Page 72
TMP89FM46
Note:The 8-bit up counter source clock operates out of synchronization with WDCTR<WDTEN>. Therefore, the first
overflow time of the 8-bit up counter after WDCTR<WDTEN> is set to "1" may get shorter by a maximum of 1
source clock. The 8-bit up counter must be cleared within a period of the overflow time minus 1 source clock
cycle.
5.3.4
Setting an overflow detection signal of the 8-bit up counter
WDCTR<WDTOUT> selects a signal to be generated when the overflow of the 8-bit up counter is detected.
1. When the watchdog timer interrupt request signal is selected (when WDCTR<WDTOUT> is "0")
Releasing WDCTR<WDTOUT> to "0" causes a watchdog timer interrupt request signal to occur
when the 8-bit up counter overflows.
A watchdog timer interrupt is a non-maskable interrupt, and its request is always accepted, regardless of the interrupt master enable flag (IMF) setting.
Note: When a watchdog timer interrupt is generated while another interrupt, including a watchdog timer interrupt, is already
accepted, the new watchdog timer interrupt is processed immediately and the preceding interrupt is put on hold. Therefore,
if watchdog timer interrupts are generated continuously without execution of the RETN instruction, too many levels of nesting may cause a malfunction of the microcontroller.
2. When the watchdog timer reset request signal is selected (when WDCTR<WDTOUT> is "1")
Setting WDCTR<WDTOUT> to "1" causes a watchdog timer reset request signal to occur when
the 8-bit up counter overflows.
This watchdog timer reset request signal resets the TMP89FM46 and starts the warm-up operation.
5.3.5
Writing the watchdog timer control codes
The watchdog timer control codes are written into WDCDR.
By writing 0x4E (clear code) into WDCDR, the 8-bit up counter is cleared to "0" and continues counting the
source clock.
When WDCTR<WDTEN> is "0", writing 0xB1 (disable code) into WDCDR disables the watchdog timer
operation.
To prevent the 8-bit up counter from overflowing, clear the 8-bit up counter in a period shorter than the overflow time of the 8-bit up counter and within the clear time.
By designing the program so that no overflow will occur, the program malfunctions and deadlock can be
detected through interrupts generated by watchdog timer interrupt request signals.
By applying a reset to the microcomputer using watchdog timer reset request signals, the CPU can be
restored from malfunctions and deadlock.
Example: When WDCTR<WDTEN> is "0", set the watchdog timer detection time to 220/fcgck [s], set the counter clear
time to half of the overflow time, and allow a watchdog timer reset request signal to occur if a malfunction is
detected.
LD
(WDCTR), 0y00110011
; WDTW←10, WDTT←01, WDTOUT←1
Clear the 8-bit up counter at a point after
half of its overflow time and within a period of the overflow time minus 1 source
clock cycle.
LD
(WDCDR), 0x4E
; Clear the 8-bit up counter
Clear the 8-bit up counter at a point after
half of its overflow time and within a period of the overflow time minus 1 source
clock cycle.
LD
(WDCDR), 0x4E
; Clear the 8-bit up counter
Note:If the overflow of the 8-bit up counter and writing of 0x4E (clear code) into WDCDR occur simultaneously, the
8-bit up counter is cleared preferentially and the overflow detection is not executed.
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5. Watchdog Timer (WDT)
5.3 Functions
TMP89FM46
5.3.6
Reading the 8-bit up counter
The counter value of the 8-bit up counter can be read by reading WDCNT.
The stoppage of the 8-bit up counter can be detected by reading WDCNT at random times and comparing the
value to the last read value.
5.3.7
Reading the watchdog timer status
The watchdog timer status can be read at WDST.
WDST<WDTST> is set to "1" when the watchdog timer operation is enabled, and it is cleared to "0" when
the watchdog timer operation is disabled.
WDST<WINTST2> is set to "1" when a watchdog timer interrupt request signal occurs due to the overflow
of the 8-bit up counter.
WDST<WINTST1> is set to "1" when a watchdog timer interrupt request signal occurs due to the operation
for releasing the 8-bit up counter outside the clear time.
You can know which factor has caused a watchdog timer interrupt request signal by reading
WDST<WINTST2> and WDST<WINTST1> in the watchdog timer interrupt service routine.
WDST<WINTST2> and WDST<WINTST1> are cleared to "0" when WDST is read. If WDST is read at the
same time as the condition for turning WDST<WINTST2> or WDST<WINTST1> to "1" is satisfied,
WDST<WINTST2> or WDST<WINTST1> is set to "1", rather than being cleared.
8-bit up counter value
FFH 00H 01H
When WDCTR<WDTW> is 10
3FH 40H
7FH 80H
Outside the clear time
BFH C0H
FFH 00H 01H
Clear time
Writing of 4EH (clear code)
Reading of WDST
Interrupt request signal generated by clearing
the 8-bit up counter outside the clear time
Interrupt request signal generated by the
overflow of the 8-bit up counter
Watchdog timer interrupt request signal
WDST<WINTST1>
WDST<WINTST2>
Figure 5-4 Changes in the Watchdog Timer Status
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TMP89FM46
6. Power-on Reset Circuit
The power-on reset circuit generates a reset when the power is turned on. When the supply voltage is lower than
the detection voltage of the power-on reset circuit, a power-on reset signal is generated.
6.1 Configuration
The power-on reset circuit consists of a reference voltage generation circuit and a comparator.
The supply voltage divided by ladder resistor is compared with the voltage generated by the reference voltage generation circuit by the comparator.
VDD
Comparator
Power-on reset signal
Reference voltage
generation circuit
Figure 6-1 Power-on Reset Circuit
6.2 Function
When power supply voltage goes on, if the supply voltage is equal to or lower than the releasing voltage of the
power-on reset circuit, a power-on reset signal is generated and if it is higher than the releasing voltage of the poweron reset circuit, a power-on reset signal is released.
When power supply voltage goes down, if the supply voltage is equal to or lower than the detecting voltage of the
power-on reset circuit, a power-on reset signal is generated.
Until the power-on reset signal is generated, a warm-up circuit and a CPU is reset.
When the power-on reset signal is released, the warm-up circuit is activated. The reset of the CPU and peripheral
circuits is released after the warm-up time that follows reset release has elapsed.
Increase the supply voltage into the operating range during the period from detection of the power-on reset release
voltage until the end of the warm-up time that follows reset release. If the supply voltage has not reached the operating range by the end of the warm-up time that follows reset release, the TMP89FM46 cannot operate properly.
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6. Power-on Reset Circuit
6.2 Function
TMP89FM46
Supply voltage (VDD)
Operating voltage
VPROFF
VPRON
PPW
VDD
Power-on
reset signal
PRON
PROFF
Warm-up counter start
Warm-up
counter clock
PWUP
CPU/peripheral circuits
reset signal
Note 1: The power-on reset circuit may operate improperly, depending on fluctuations in the supply voltage (VDD). Refer to the
electrical characteristics and take them into consideration when designing equipment.
Note 2: For the AC timing, refer to the electrical characteristics.
Figure 6-2 Operation Timing of Power-on Reset
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TMP89FM46
7. Voltage Detection Circuit
The voltage detection circuit detects any decrease in the supply voltage and generates voltage detection interrupt
request signals and voltage detection reset signals.
Note: The voltage detection circuit may operate improperly, depending on fluctuations in the supply voltage (VDD). Refer
to the electrical characteristics and take them into consideration when designing equipment.
7.1 Configuration
The voltage detection circuit consists of a reference voltage generation circuit, a detection voltage level selection
circuit, a comparator and control registers.
The supply voltage (VDD) is divided by the ladder resistor and input to the detection voltage selection circuit. A
voltage is selected in the detection voltage selection circuit, depending on the detection voltage (VDxLVL), and
compared to the reference voltage in the comparator. When the supply voltage (VDD) becomes lower than the detection voltage (VDxLVL), a voltage detection interrupt request signal or a voltage detection reset signal is generated.
Either the voltage detection interrupt request signal or the voltage detection reset signal can be selected by programming the software.
Detection voltage 1
level selection circuit
F/F
Detection voltage 2
level selection circuit
VDD
F/F
Voltage detection reset signal 1
Interrupt request signal
generation circuit
Voltage detection interrupt
request signal
Voltage detection reset signal 2
VDCR1
VD1MOD
V D1 E N
V D2 E N
VD2MOD
VD2F
VD2SF
VD1F
VD1LVL
Reference voltage
generation circuit
VD1SF
VD2LVL
Voltage detection STOP mode
release signal
VDCR2
Figure 7-1 Voltage Detection Circuit
7.2 Control
The voltage detection circuit is controlled by voltage detection control registers 1,2 and 3.
Voltage detection control register 1
VDCR1
(0x0FC6)
RA002
7
6
Bit Symbol
VD2F
VD2SF
Read/Write
R/W
Read Only
After reset
0
0
5
4
VD2LVL
R/W
0
Page 77
0
3
2
VD1F
VD1SF
R/W
Read Only
0
0
1
0
VD1LVL
R/W
0
0
7. Voltage Detection Circuit
7.3 Function
TMP89FM46
VD2F
Voltage detection 2 flag (Retains
the state when VDD<VD2LVL is
detected)
0 : VDD ≥ VD2LVL
1 : VDD < VD2LVL
VD2SF
Voltage detection 2 status flag
(Magnitude relation of VDD and
VD2LVL when they are read)
0 : VDD ≥ VD2LVL
1 : VDD < VD2LVL
VD2LVL
Selection for detection voltage 2
00 : 2.35 +0.15 / -0.15V
01 : 3.15 +0.15 / -0.15V
10 : 2.85 +0.15 / -0.15V
11 : 2.65 +0.15 / -0.15V
VD1F
Voltage detection 1 flag (Retains
the state when VDD<VD1LVL is
detected)
0 : VDD ≥ VD1LVL
1 : VDD < VD1LVL
VD1SF
Voltage detection 1 status flag
(Magnitude relation of VDD and
VD1LVL when they are read)
0 : VDD ≥ VD1LVL
1 : VDD < VD1LVL
Selection for detection voltage 1
00 : 4.50 +0.2 / -0.2V
01 : 4.20 +0.2 / -0.2V
10 : 3.70 +0.2 / -0.2V
11 : 3.15 +0.15 / -0.15V
VD1LVL
Note 1: VDCR1 is initialized by a power-on reset or an external reset input.
Note 2: When VD2F or VD1F is cleared by the software and is set due to voltage detection at the same time, the setting due to
voltage detection is given priority.
Note 3: VD2F and VD1F cannot be programmed to "1" by the software.
Voltage detection control register 2
VDCR2
(0x0FC7)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
SRSS
VD2MOD
VD2EN
VD1MOD
VD1EN
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
00:
01:
SRSS
Selection for the STOP mode
release source
10:
11:
VD2MOD
VD2EN
VD1MOD
VD1EN
Release STOP mode depending on the state of the STOP pin
Release STOP mode when the supply voltage (VDD) becomes higher
than the detection voltage (VDxLVL)
Release STOP mode depending on the state of the STOP pin or when the
supply voltage (VDD) becomes higher than the detection voltage (VDxLVL)
Reserved
Selects the operation mode of voltage detection 2
0:
1:
Generate a voltage detection interrupt request signal
Generate a voltage detection reset 2 signal
Enables/disables the operation of
voltage detection 2
0:
1:
Disables the operation of voltage detection 2
Enables the operation of voltage detection 2
Selects the operation mode of voltage detection 1
0:
1:
Generates a voltage detection interrupt request signal
Generates a voltage detection reset signal
Enables/disables the operation of
voltage detection 1
0:
1:
Disables the operation of voltage detection 1
Enables the operation of voltage detection 1
Note 1: VDCR2 is initialized by a power-on reset or an external reset input.
Note 2: Bits 7 and 6 of VDCR2 are read as "0".
7.3 Function
Two detection voltages (VDxLVL, x=1-2) can be set in the voltage detection circuit. For each voltage, enabling/
disabling the voltage detection and the operation to be executed when the supply voltage (VDD) becomes lower than
the detection voltage (VDxLVL) can be programmed.
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TMP89FM46
7.3.1
Enabling/disabling the voltage detection operation
Setting VDCR2<VDxEN> to "1" enables the voltage detection operation. Setting it to "0" disables the operation.
VDCR2<VDxEN> is cleared to "0" immediately after a power-on reset or a reset by an external reset input is
released.
Note:When the supply voltage (VDD) is lower than the detection voltage (VDxLVL), setting VDCR2<VDxEN> to "1"
generates a voltage detection interrupt request signal or a voltage detection reset signal at the time.
7.3.2
Selecting the voltage detection operation mode
If the voltage detection operation mode is set to generate voltage detection interrupt request signals
(VDCR1<VDxMOD>="0") and VDCR2<VDxEN> is set to "1", a voltage detection interrupt request signal is
generated when the supply voltage (VDD) becomes lower than the detection voltage (VDxLVL).
If the voltage detection operation mode is set to generate voltage detection reset signals (VDCR1<VDxMOD>="1") and VDCR2<VDxEN> is set to "1", a voltage detection reset signal is generated when the supply
voltage (VDD) becomes lower than the detection voltage (VDxLVL).
VDCR1 and VDCR2 are initialized by a power-on reset or an external reset input only. Therefore, the voltage detection reset signals are generated continuously, as long as the supply voltage (VDD) is lower than the
detection voltage (VDxLVL).
Note:If the voltage detection mode is set to generate voltage detection interrupt request signals and the supply voltage (VDD) becomes lower than the detection voltage (VDxLVL) in the STOP, IDLE0 or SLEEP0 mode, a voltage detection interrupt request signal is generated after the operation mode is released and returned to
NORMAL or SLOW mode.
VDD level
Detection voltage level
VDCR2<VDxEN>
Voltage detection interrupt
request signal
Voltage detection reset signal
Figure 7-2 Voltage Detection Interrupt Request Signal and Voltage Detection Reset Signal
7.3.3
Selecting the detection voltage level
Select a detection voltage at VDCR1<VDxLVL>.
7.3.4
Voltage detection flag and voltage detection status flag
The magnitude relation between the supply voltage (VDD) and the detection voltage (VDxLVL) can be
checked by reading VDCR1<VDxF> and VDCR1<VDxSF>.
If VDCR2<VDxEN> is set at "1", when the supply voltage (VDD) becomes lower than the detection voltage
(VDxLVL), VDCR1<VDxF> is set to "1" and is held in this state. VDCR1<VDxF> is not cleared to "0" when
the supply voltage (VDD) becomes equal to or higher than the detection voltage (VDxLVL).
When VDCR2<VDxEN> is cleared to "0" after VDCR1<VDxF> is set to "1", the previous state is still held.
To clear VDCR1<VDxF>, "0" must be written to it.
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7. Voltage Detection Circuit
7.3 Function
TMP89FM46
If VDCR2<VDxEN> is set at "1", when the supply voltage (VDD) becomes lower than the detection voltage
(VDxLVL), VDCR1<VDxSF> is set to "1". When the supply voltage (VDD) becomes equal to or higher than
the detection voltage (VDxLVL), VDCR1<VDxSF> is cleared to "0".
Unlike VDCR1<VDxF>, VDCR1<VDxSF> does not hold the set state.
Note 1: When the supply voltage (VDD) becomes lower than the detection voltage (VDxLVL) in the STOP, IDLE0 or
SLEEP0 mode, the voltage detection flag and the voltage detection status flag are changed after the operation mode is returned to NORMAL or SLOW mode.
Note 2: Depending on the voltage detection timing, the voltage detection status flag (VDxSF) may be changed earlier than the voltage detection flag (VDxF) by a maximum of 2/fcgck[s].
VDD level
Detection voltage level
VDCR2<VDxEN>
Write 0 to VDCR1<VDxF>
VDCR1<VDxF>
VDCR1<VDxSF>
The flag is not set because VDCR2<VDxEN> is 0 .
Figure 7-3 Changes in the Voltage Detection Flag and the Voltage Detection Status Flag
7.3.5
Selecting the STOP mode release signal
By setting VDCR2<SRSS> to select the voltage detection STOP mode release signal as the STOP mode
release signal, STOP mode can be released when the supply voltage (VDD) becomes equal to or higher than
the detection voltage (VDxLVL).
To use this function, set VDCR2<VDxMOD> to "0" and set the operation mode to generate voltage detection interrupt request signals. In addition, before the operation is switched to STOP mode, clear SYSCR1
<RELM> to "0" and select the edge release mode.
If the level release mode is selected and the supply voltage (VDD) is equal to or higher than the detection
voltage (VDxLVL), STOP mode cannot be activated.
Setting VDCR2<SRSS> to "00" allows STOP mode to be released depending on the state of the STOP pin.
Setting it to "01" allows STOP mode to be released when the supply voltage (VDD) becomes equal to or
higher than the detection voltage (VDxLVL).
Setting it to "10" allows STOP mode to be released depending on the state of the STOP pin or when the supply voltage (VDD) becomes equal to or higher than the detection voltage (VDxLVL).
Refer to Section 2 "CPU" for settings to activate or release STOP mode.
Note 1: After STOP mode is released by a voltage detection STOP mode release signal, the interrupt latch
becomes "1". If it is undesirable to accept an interrupt after STOP mode is released, disable interrupts
before STOP mode is activated. In addition, clear the interrupt latch before enabling interrupts after STOP
mode is released.
Note 2: If the supply voltage (VDD) becomes equal to or higher than the detection voltage (VDxLVL) within 1
machine cycle after SYSCR1<STOP> is set to "1" and STOP mode is activated, STOP mode is not
released.
Note 3: When the voltage detection interrupt request signal of the voltage detection circuit is used as the STOP
mode release signal, take into account sudden fluctuations in the supply voltage (VDD) and changes near
the detection voltage (VDxLVL) in setting the detection voltage (VDxLVL) and the warm-up time.
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TMP89FM46
VDD level
Detection voltage level
VDCR1<VDxSF>
Voltage detection interrupt
request signal
NORMAL mode
STOP mode
STOP mode is
activated by
Warm-up
NORMAL mode
STOP mode is released at the falling
edge of VDCR1<VDxSF>
programming.
STOP mode
STOP mode is
activated by
Warm-up
NORMAL mode
STOP mode is released at the falling
edge of VDCR1<VDxSF>
programming.
Figure 7-4 STOP Mode Release by VDCR1<VDxSF>
7.4 Register Settings
7.4.1
Setting procedure when the operation mode is set to generate voltage detection
interrupt request signals
When the operation mode is set to generate voltage detection interrupt request signal, make the following
setting:
In this case, setting VDCR2<SRSS> allows STOP mode to be released when the supply voltage (VDD)
becomes equal to or higher than the detection voltage (VDxLVL).
1. Clear the voltage detection circuit interrupt enable flag to "0".
2. Set the detection voltage at VDCR1<VDxLVL>(x=1 to 2).
3. Clear VDCR2<VDxMOD> to "0" to set the operation mode to generate voltage detection interrupt
request signals.
4. Set VDCR2<VDxEN> to "1" to enable the voltage detection operation.
5. Wait for 5 [us] or more until the voltage detection circuit becomes stable.
6. Make sure that VDCR1<VDxSF> is "0".
7. Clear the voltage detection circuit interrupt latch to "0" and set the interrupt enable flag to "1" to
enable interrupts.
Note:If the set value of detection voltage (VDxLVL) is close to the supply voltage (VDD), voltage detection request
signals may be generated frequently. At the return from the voltage detection interrupt processing, execute
appropriate wait processing depending on fluctuations in the system power supply and clear the interrupt
latch.
7.4.2
Setting procedure when the operation mode is set to generate voltage detection
reset signals
When the operation mode is set to generate voltage detection reset signals, make the following setting:
1. Clear the voltage detection circuit interrupt enable flag to "0".
2. Set the detection voltage at VDCR1<VDxLVL>(x=1 to 2).
3. Clear VDCR2<VDxMOD> to "0" to set the operation mode to generate voltage detection interrupt
request signals.
4. Set VDCR2<VDxEN> to "1" to enable the voltage detection operation.
5. Wait for 5 [us] or more until the voltage detection circuit becomes stable.
6. Make sure that VDCR1<VDxSF> is "0".
7. Set VDCR2<VDxMOD> to "1" to set the operation mode to generate voltage detection reset signals.
Note 1: VDCR1 and VDCR2 are initialized by a power-on reset or an external reset input only. If the supply voltage
(VDD) becomes lower than the detection voltage (VDxLVL) in the period from release of the voltage detection reset until clearing of VDCR2<VDxEN> to "0", a voltage detection reset signal is generated immediately.
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7. Voltage Detection Circuit
7.4 Register Settings
TMP89FM46
Note 2: The voltage detection reset signals are generated continuously as long as the supply voltage (VDD) is
lower than the detection voltage (VDxLVL).
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TMP89FM46
8. I/O Ports
Table 8-1 List of I/O Ports
Port name
Pin name
Number of pins
Input/output
Secondary functions
Port P0
P03 to P00
(Note)
4
(Note)
Input/output
Also used as the high-frequency oscillator connection pin and the
low-frequency oscillator connection pin
Port P1
P13 to P10
4
Input/output
Also used as the external reset input, the external interrupt input and
the STOP mode release signal input
Port P2
P27 to P20
8
Input/output
Also used as the UART input/output, the serial interface input/output
and the serial bus interface input/output
Port P4
P47 to P40
8
Input/output
Also used as the analog input and the key-on wakeup input
Port P7
P77 to P70
8
Input/output
Also used as the timer counter input/output, the divider output and
the external interrupt input
Port P8
P83 to P80
4
Input/output
Also used as the timer counter input/output
Port P9
P91 to P90
2
Input/output
Also used as the UART input/output
Port PB
PB7 to PB4
4
Input/output
Also used as the UART input/output and the serial interface input/output
Note: P00 and P01 pins can not be used for the I/O port, because they should be connected with the high frequency OSC
input.
Each output port contains a latch, which holds the output data. No input port has a latch, so the external input data
should be externally held until the input data is read from outside or reading should be performed several times
before processing. Figure 8-1 shows input/output timing examples.
External data is read from an I/O port in the read cycle during execution of the read instruction. This timing cannot
be recognized from outside, so that transient input such as chattering must be processed by the program. Data is output to an I/O port in the next cycle of the write cycle during execution of the write instruction.
Fetch cycle
Fetch cycle
Read cycle
System clock
Example: LD A, (x)
Instruction
execution cycle
Internal read
signal
Data input
(a) Input timing
Fetch cycle
Fetch cycle
Write cycle
System clock
Instruction
execution cycle
Example: LD (x), A
Internal write
signal
Data input
(b) Input timing
Figure 8-1 Input/Output Timing (Example)
Note: The positions of the read and write cycles may vary, depending on the instruction.
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8. I/O Ports
8.1 I/O Port Control Registers
TMP89FM46
8.1 I/O Port Control Registers
The following control registers are used for I/O ports. (The port number is indicated in place of x.) Registers that
can be set vary depending on the port. For details, refer to the description of each port.
• PxDR register
This is the register for setting output data. When a port is set to the "output mode", the value specified at
PxDR is output from the port.
• PxPRD register
This is the register for reading input data. When a port is set to the "input mode", the current port input
status can be read by reading PxPRD.
• PxCR register
This register switches a port between input and output. A port can be switched between the "input
mode" and the "output mode".
• PxFC register
This register enables the secondary function output of each port. The secondary function output of each
port can be enabled or disabled.
• PxOUTCR register
This register switches the port output between the C-MOS output and the open drain output.
• PxPU register
This register determines whether or not the built-in pull-up resistor is connected when a port is used in
the input mode or as the open drain output.
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TMP89FM46
8.2 List of I/O Port Settings
For the setting methods for individual I/O ports, refer to the following table.
Table 8-2
List of I/O Port Settings
Register set value
Port name
Pin name
Function
PxCR
Port P0
PxOUTCR
PxFC
Port input
0
0
Port output
1
0
XTOUT
*
Other required settings
P03 to P00
P03
Without
register
Without
register
P02
XTIN
*
P01
XOUT
*
Without
register
P00
XIN
*
1
Port input
0
Port output
1
P10
Port input
0
P10
Port output
1
Port P1
1
P13 to P11
Note 1
Note 1
Without
register
Without
register
P13
INT1 input
0
P12
INT0 input
0
P11
INT5 input
0
P11
STOP input
0
P10
RESET input
*
Port input
0
*
*
Port output
1
*
0
SCLK0 input
0
*
*
SERSEL<SRSEL0>="01"
SCLK0 output
1
*
1
SERSEL<SRSEL0>="01"
SCL0 input/output
1
1
SERSEL<SRSEL0>="*0"
SI input
0
Without
register
*
SERSEL<SRSEL0>="01"
SDA0 input/output
1
1
SERSEL<SRSEL0>="*0"
SO output
1
Without
register
1
SERSEL<SRSEL0>="01"
SCLK0 input
0
*
*
SERSEL<SRSEL0>="10"
SERSEL<SRSEL2>="0"
SCLK0 output
1
*
1
SERSEL<SRSEL0>="10"
SERSEL<SRSEL2>="0"
RXD0 input
0
*
*
SERSEL<SRSEL0>="0*"
SERSEL<SRSEL2>="0"
UATCNG<UAT0IO>="0"
TXD0 output
1
*
1
SERSEL<SRSEL0>="0*"
SERSEL<SRSEL2>="0"
UATCNG<UAT0IO>="1"
SI0 input
0
*
*
SERSEL<SRSEL0>="10"
SERSEL<SRSEL2>="0"
Port P2
Note 1
P27 to P20
P25
P24
P23
P22
P21
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8. I/O Ports
8.2 List of I/O Port Settings
Table 8-2
TMP89FM46
List of I/O Port Settings
Register set value
Port name
Pin name
P20
Port P4
P47 to P40
Function
PxCR
PxOUTCR
PxFC
Other required settings
TXD0 output
1
*
1
SERSEL<SRSEL0>="0*"
SERSEL<SRSEL2>="0"
UATCNG<UAT0IO>="0"
RXD0 input
0
*
*
SERSEL<SRSEL0>="0*"
SERSEL<SRSEL2>="0"
UATCNG<UAT0IO>="1"
SO0 output
1
*
1
SERSEL<SRSEL0>="10"
SERSEL<SRSEL2>="0"
Port input
0
Port output
1
*
0
Without
register
AIN7 to AIN0
0
KWI7 to KWI4
*
*
KWUCR1
KWI3 to KWI0
*
*
KWUCR0
Port input
0
*
Port output
1
0
P77
INT4 input
0
Without
register
P76
INT3 input
0
Without
register
P75
INT2 input
0
Without
register
P74
DVO output
1
TCA1 input
0
PPGA1 output
1
1
TCA0 input
0
*
PPGA0 output
1
1
TC01 input
0
*
PPG01 / PWM01 output
1
1
TC00 input
0
*
PPG00 / PWM00 output
1
1
Port P7
1
P77 to P70
Without
register
1
*
P73
P72
P71
P70
RA005
Page 86
SERSEL<TCA0SEL>="00"
TMP89FM46
Table 8-2
List of I/O Port Settings
Register set value
Port name
Pin name
Function
PxCR
Port P8
PxOUTCR
PxFC
Other required settings
Port input
0
*
Port output
1
0
TC03 input
0
PPG03 / PWM03 output
1
TC02 input
0
*
PPG02 / PWM02 output
1
1
Port input
0
*
*
Port output
1
*
0
RXD1 input
0
*
0
UATCNG<UAT1IO>="0"
TXD1 output
1
*
1
UATCNG<UAT1IO>="1"
TXD1 output
1
*
1
UATCNG<UAT1IO>="0"
RXD1 input
0
*
0
UATCNG<UAT1IO>="1"
Port input
0
*
*
Port output
1
*
0
SCLK0 input
0
*
*
SERSEL<SRSEL0>="10"
SERSEL<SRSEL2>="1"
SCLK0 output
1
*
1
SERSEL<SRSEL0>="10"
SERSEL<SRSEL2>="1"
RXD0 input
0
*
*
SERSEL<SRSEL0>="0*"
SERSEL<SRSEL2>="1"
UATCNG<UAT0IO>="0"
TXD0 output
1
*
1
SERSEL<SRSEL0>="0*"
SERSEL<SRSEL2>="1"
UATCNG<UAT0IO>="1"
SI0 input
0
*
*
SERSEL<SRSEL0>="10"
SERSEL<SRSEL2>="1"
TXD0 output
1
*
1
SERSEL<SRSEL0>="0*"
SERSEL<SRSEL2>="1"
UATCNG<UAT0IO>="0"
RXD0 input
0
*
*
SERSEL<SRSEL0>="0*"
SERSEL<SRSEL2>="1"
UATCNG<UAT0IO>="1"
SO0 output
1
*
1
SERSEL<SRSEL0>="10"
SERSEL<SRSEL2>="1"
P83 to P80
P81
Without
register
*
1
P80
Port P9
P92 to P90
P91
P90
Port PB
PB7 to PB4
PB6
PB5
PB4
Note 1: After the power is turned on, pin P10 serves as an external reset input. To use pin P10 as a port, refer to "How to
use the external reset input pin as a port".
Note 2: About SERSEL, please refer to "8.4 Serial Interface Selecting Function".
Note 3: The symbol and numeric characters in the table have the following meanings:
RA005
Symbol and
numeric characters
Meaning
0
Set "0".
1
Set "1".
*
Don’t care
(Operation is the same whether "1" or "0" is selected.)
Without register
There is no register that corresponds to the bit.
Page 87
8. I/O Ports
8.3 I/O Port Registers
TMP89FM46
8.3 I/O Port Registers
8.3.1
Port P0 (P03 to P00)
Port P0 is a 4-bit input/output port that can be set to input or output for each bit individually, and it is also
used as the high-frequency oscillation connection pin and the low-frequency oscillation connection pin.
Port P0 contains a programmable pull-up resistor on the VDD side. This pull-up resistor can be used when
the port is used in the input mode.
Table 8-3 Port P0
Secondary
function
-
-
-
-
P03
P02
P01
P00
-
-
-
-
XTOUT
XTIN
XOUT
XIN
VDD
Pull-up control
(for each bit)
Programmable
pull-up resistor
P0PU0 write
RIN3
Input/output control
(for each bit)
P0CR0 write
VDD
Function control
(for each bit)
P0FC0 write
P00
(XIN)
Internal data bus
Output latch
(for each bit)
R
P0DR0 write
P0PRD0 read
VDD
Pull-up control
(for each bit)
Rf
Programmable
pull-up resistor
P0PU1 write
RIN3
Input/output control
(for each bit)
P0CR1 write
VDD
System clock reset
(internal factor reset)
Ro
P01
(XOUT)
Output latch
(for each bit)
R
P0DR1 write
P0PRD1 read
SYSCR2<XEN>
Note1 : R = 100Ω (typ.)
Note2 : Rf = 1.2MΩ (typ.)
Note3 : Ro = 0.5kΩ (typ.)
Note4 : RIN3 = 50kΩ (typ.)
SYSCR1<STOP>
SYSCR1<OUTEN>
Reset signal
Figure 8-2 Port P0 (P00, P01)
RA005
Page 88
TMP89FM46
VDD
Pull-up control
(for each bit)
Programmable
pull-up resistor
P0PU2 write
RIN3
Input/output control
(for each bit)
P0CR2 write
VDD
Function control
(for each bit)
P0FC2 write
P02
(XTIN)
Internal data bus
Output latch
(for each bit)
R
P0DR2 write
P0PRD2 read
VDD
Pull-up control
(for each bit)
Rf
Programmable
pull-up resistor
P0PU3 write
RIN3
Input/output control
(for each bit)
P0CR3 write
VDD
Ro
P03
(XTOUT)
Output latch
(for each bit)
R
P0DR3 write
P0PRD3 read
SYSCR2<XTEN>
Note1 : R = 100Ω (typ.)
Note2 : Rf = 6MΩ (typ.)
Note3 : Ro = 220kΩ (typ.)
Note4 : RIN3 = 50kΩ (typ.)
SYSCR1<STOP>
SYSCR1<OUTEN>
Reset signal
Figure 8-3 Port P0 (P02, P03)
RA005
Page 89
8. I/O Ports
8.3 I/O Port Registers
TMP89FM46
Port P0 output latch
P0DR
(0x0000)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
P03
P02
P01
P00
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
After reset
0:
Outputs L level when the output mode is selected.
1:
Outputs H level when the output mode is selected.
Function
Port P0 input/output control
P0CR
(0x0F1A)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
P0CR3
P0CR2
P0CR1
P0CR0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
After reset
0:
Input mode (port input)
1:
Output mode (port output)
Function
Note: P0CR1 and P0CR0 must be clear to "0".
Port P0 function control
P0FC
(0x0F34)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
-
P0FC2
-
P0FC0
Read/Write
R
R
R
R
R
R/W
R
R/W
After reset
0
0
0
0
0
0
0
1
0:
Port function
Port function
1:
XTIN (I)
XIN (I)
Function
Note 1: When SYSCR2<XEN> is "1", setting P0FC0 to "0" generates a system clock (internal factor) reset. Normally, ports P00 or
P01 are not used as ports, so P0FC0 must be set to "1".
Note 2: Symbol "I" means secondary function input
Port P0 built-in pull-up resistor control
P0PU
(0x0F27)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
P0PU2
P0PU2
P0PU1
P0PU0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
0:
The built-in pull-up resistor is not connected.
1:
The built-in pull-up resistor is connected. (The resistor is
connected in the input mode only. Under any other conditions, setting to "1" does not make the resistor connected.)
Function
Port P0 input data
P0PRD
(0x000D)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
P0PRD3
P0PRD2
P0PRD1
P0PRD0
Read/Write
R
R
R
R
R
R
R
R
After reset
0
0
0
0
*
*
*
*
If the port is in the input mode, the contents of the port
are read. If not, "0" is read.
Function
RA005
Page 90
TMP89FM46
Table 8-4 P0PRD Read Value (P00 to P01)
Set condition
P0PRDi read value
P0FC0
P0CRi
*
1
"0"
1
*
"0"
0
0
Contents of port
Note 1: * : Don’t care
Note 2: i = 0, 1
Table 8-5 P0PRD Read Value (P02 to P03)
Set condition
P0PRDj read value
P0FC2
P0CRj
*
1
"0"
1
*
"0"
0
0
Contents of port
Note 1: * : Don’t care
Note 2: j = 2, 3
RA005
Page 91
8. I/O Ports
8.3 I/O Port Registers
8.3.2
TMP89FM46
Port P1 (P13 to P10)
Port P1 is a 4-bit input/output port that can be set to input or output for each bit individually, and is also used
as the external interrupt input, the STOP mode release signal input and the external reset input.
Port P1 contains a programmable pull-up resistor on the VDD side. This pull-up resistor can be used when
the port is used in the input mode.
After reset, pin P10 serves as the external reset input. To use pin P10 as a port, refer to "How to use external
reset input pin as a port".
Table 8-6 Port P1
Secondary
function
RA005
-
-
-
-
P13
P12
-
-
-
-
INT1
INT0
P11
P10
INT5
RESET
STOP
Page 92
TMP89FM46
VDD
VDD
Reset
pull-up resistor
Pull-up control
(for each bit)
Internal data bus
RIN2
Programmable
pull-up resistor
P1PU write
VDD
Input/output control
(for each bit)
RIN3
P1CR write
P10
Output latch
(for each bit)
R
P1DR write
P1PRD read
Note1 : R = 100Ω (typ.)
Note2 : RIN2 = 220kΩ (typ.)
Note3 : RIN3 = 50kΩ (typ.)
SYSCR3<RSTDIS>
EN
B2H write
SYSCR4
Power-on reset signal
Reset 1
Reset 2
Low-voltage detection reset 1 signal
Low-voltage detection reset 2 signal
Watchdog timer reset signal
System clock reset signal
Trimming data reset signal
Flash standby reset signal
VDD
Pull-up control
(for each bit)
Programmable
pull-up resistor
Internal data bus
P1PU write
RIN3
VDD
Input/output control
(for each bit)
P1CR write
P1i
Output latch
(for each bit)
R
P1DR write
Peripheral
functions
P1PRD read
Interrupt
STOP
control
INT0, INT1, INT5, STOP
SYSCR1<STOP>
SYSCR1<OUTEN>
In case of P12
and P13
Reset signal
Reset signal
In case of P11
Figure 8-4 Port P1
RA005
Page 93
Note1 : R = 100Ω (typ.)
Note2 : RIN3 = 50kΩ (typ.)
Note3 : i = 1 ~ 3
8. I/O Ports
8.3 I/O Port Registers
TMP89FM46
Port P1 output latch
P1DR
(0x0001)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
P13
P12
P11
P10
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
After reset
0:
Outputs L level when the output mode is selected.
1:
Outputs H level when the output mode is selected.
Function
Port P1 input/output control
P1CR
(0x0F1B)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
P1CR3
P1CR2
P1CR1
P1CR0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
Input mode (port input)
0:
INT1 (I)
Function
INT0 (I)
INT5 (I)
STOP (I)
1:
-
Output mode (port output)
Note: Symbol "I" means secondary function input
Port P1 built-in pull-up resistor control
P1PU
(0x0F28)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
P1PU4
P1PU2
P1PU1
P1PU0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
0:
The built-in pull-up resistor is not connected.
1:
The built-in pull-up resistor is connected. (The resistor is
connected only when the port is used in the input mode
or as the open drain output. Under any other conditions,
setting to "1" does not make the resistor connected.)
Function
Port P1 input data
P1PRD
(0x000E)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
P1PRD3
P1PRD2
P1PRD1
P1PRD0
Read/Write
R
R
R
R
R
R
R
R
After reset
0
0
0
0
*
*
*
*
If the port is in the input mode, the contents of the port
are read. If not, "0" is read.
Function
Table 8-7 P1PRD Read Value
Set condition
P1PRDi read value
P1CRi
0
Contents of port
1
"0"
Note 1: * : Don’t care
Note 2: i = 0 to 3
RA005
Page 94
TMP89FM46
8.3.3
Port P2 (P27 to P20)
Port P2 is an 8-bit input/output port that can be set to input or output for each bit individually, and it is also
used as the serial bus interface input/output, the serial interface input/output, the UART input/output and the
on-chip debug function.
The output circuit has the P-channel output control function and either the sink open drain output or the CMOS output can be selected. Port P2 contains a programmable pull-up resistor on the VDD side. This pull-up
resistor can be used when the port is used in the input mode or as a sink open drain output.
When this port is used as the serial bus interface, the serial interface or the UART, setting for serial interface
selecting function is also needed. For details, refer to "8.4 Serial Interface Selecting Function".
For the on-chip debug function, refer to the chapter of "On-chip Debug Function (OCD)".
Table 8-8 Port P2
Secondary
function
RA005
P27
P26
P25
P24
P23
P22
P21
P20
-
-
SCLK0
SI0
SCL0
SO0
SDA0
SCLK0
SI0
RXD0
TXD0
OCDIO
SO0
TXD0
RXD0
OCDCK
Page 95
8. I/O Ports
8.3 I/O Port Registers
TMP89FM46
VDD
Pull-up control
(for each bit)
Programmable
pull-up resistor
P2PU write
RIN3
Output control
(for each bit)
Internal data bus
P2OUTCR write
Input/output control
(for each bit)
P2CR write
VDD
Function control
(for each bit)
P2FC write
P2i
Output latch
(for each bit)
0 S
1
Peripheral
functions
P2DR write
SCLK0, SO0, TXD0
SIO0
UART0
P2PRD read
Functions enclosed by the
dotted line are for P20,
P21,P22 and P25 only.
SCLK0, SI0, RXD0
SYSCR1<STOP>
R
Note1 : R = 100Ω (typ.)
Note2 : RIN3 = 50kΩ (typ.)
Note3 : i = 0 to 2, 5 to 7
SYSCR1<OUTEN>
Reset signal
Input/output control
(for each bit)
P2CR write
Internal data bus
Peripheral
functions
Function control
(for each bit)
P2FC write
P2j
Output latch
(for each bit)
0 S
1
P2DR write
R
SCL0, SDA0, SO0
SIO0
I2C0
P2PRD read
SCL0, SDA0, SI0
SYSCR1<STOP>
SYSCR1<OUTEN>
Reset signal
Figure 8-5 Port P2
RA005
Page 96
Note1 : R = 100Ω (typ.)
Note2 : j = 3, 4
TMP89FM46
Port P2 output latch
P2DR
(0x0002)
7
6
5
4
3
2
1
0
Bit Symbol
P27
P26
P25
P24
P23
P22
P21
P20
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
After reset
0:
Outputs L level when the output mode is selected.
1:
Outputs H level when the output mode is selected. (Serves as Hi-Z or pull-up depending on settings of P2OUTCR
and P2PU.)
Function
Port P2 input/output control
P2CR
(0x0F1C)
7
6
5
4
3
2
1
0
Bit Symbol
P2CR7
P2CR6
P2CR5
P2CR4
P2CR3
P2CR2
P2CR1
P2CR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
SCLK0 (I)
SI0 (I)
-
SCLK0 (I)
RXD0 (I)
SI0 (I)
RXD0 (I)
SCLK0 (O)
SCL0 (I/O)
SDA0 (I/O)
SO (O)
SCLK0 (O)
TXD0(O)
TXD0 (O)
SO0 (O)
Input mode (port input)
0:
-
-
Function
Output mode (port output)
1:
-
-
Note: Symbol "I" means secondary function input. Symbol "O" means secondary function output. Symbol "I/O" means secondary
function input/output
Port P2 function control
P2FC
(0x0F36)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
P2FC5
P2FC4
P2FC3
P2FC2
P2FC1
P2FC0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
SCLK0 (O)
SCL0 (I/O)
SDA0 (I/O)
SO0 (O)
SCLK0 (O)
TXD0 (O)
TXD0 (O)
SO0 (O)
4
3
2
1
0
0:
Port function
Function
1:
Port P2 output control
P2OUTCR
(0x0F43)
7
6
5
Bit Symbol
P2OUT7
P2OUT6
P2OUT5
-
-
P2OUT2
P2OUT1
P2OUT0
Read/Write
R/W
R/W
R/W
R
R
R/W
R/W
R/W
0
0
0
0
0
0
0
0
After reset
0:
C-MOS output
C-MOS output
1:
Open drain output
Open drain output
Function
RA005
Page 97
8. I/O Ports
8.3 I/O Port Registers
TMP89FM46
Port P2 built-in pull-up resistor control
P2PU
(0x0F29)
7
6
5
Bit Symbol
P2PU7
P2PU6
P2PU5
Read/Write
R/W
R/W
R/W
0
0
0
0
0
After reset
4
3
2
1
0
-
-
P2PU2
P2PU1
P2PU0
R
R
R/W
R/W
R/W
0
0
0
0:
The built-in pull-up resistor is not connected.
The built-in pull-up resistor is not connected.
1:
The built-in pull-up resistor is connected.
(The resistor is connected only when the
port is used in the input mode or as the
open drain output. Under any other conditions, setting to "1" does not make the
resistor connected.)
The built-in pull-up resistor is connected.
(The resistor is connected only when the
port is used in the input mode or as the
open drain output. Under any other conditions, setting to "1" does not make the
resistor connected.)
Function
Port P2 input data
P2PRD
(0x000F)
7
6
5
4
3
2
1
0
Bit Symbol
P2PRD7
P2PRD6
P2PRD5
P2PRD4
P2PRD3
P2PRD2
P2PRD1
P2PRD0
Read/Write
R
R
R
R
R
R
R
R
*
*
*
*
*
*
*
*
After reset
Function
If the port is used in the input mode or as
the open drain output, the contents of the
port are read. If not, "0" is read.
The contents of the port
are read without condition.
If the port is used in the input mode or as
the open drain output, the contents of the
port are read. If not, "0" is read.
Table 8-9 P2PRD Read Value (P20 to P22, P25 to P27)
Set condition
P2PRDi read value
P2CRi
P2OUTCRi
0
*
Contents of port
1
0
"0"
1
1
Contents of port
Note: * : Don’t care
Note: i = 0 to 2, 5 to 7
RA005
Page 98
TMP89FM46
8.3.4
Port P4 (P47 to P40)
Port P4 is an 8-bit input/output port that can be set to input or output for each bit individually, and it is also
used as the analog input and the key-on wakeup input.
Port P4 contains a programmable pull-up resistor on the VDD side. This pull-up resistor can be used when
the port is used in the input mode.
Table 8-10 Port P4
Secondary
function
P47
P46
P45
P44
P43
P42
P41
P40
AIN7
KWI7
AIN6
KWI6
AIN5
KWI5
AIN4
KWI4
AIN3
KWI3
AIN2
KWI2
AIN1
KWI1
AIN0
KWI0
SYSCR1<STOP>
SYSCR1<OUTEN>
VDD
Pull-up control
(for each bit)
Programmable
pull-up resistor
P4PU write
RIN3
Internal data bus
Input/output control
(for each bit)
P4CR write
VDD
Function control
(for each bit)
P4FC write
P4i
Output latch
(for each bit)
Peripheral
functions
P4DR write
KWIi enable signal
Key-on
wakeup
P4PRD read
AINi enable signal
AD
R
KWIi
Note1 : R = 100Ω (typ.)
Note2 : RIN3 = 50kΩ (typ.)
Note3 : i = 0 to 7
Reset signal
ADCCR1<AINEN>
AINi
Figure 8-6 Port P4
RA005
Page 99
8. I/O Ports
8.3 I/O Port Registers
TMP89FM46
Port P4 output latch
P4DR
(0x0004)
7
6
5
4
3
2
1
0
Bit Symbol
P47
P46
P45
P44
P43
P42
P41
P40
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
After reset
0:
Outputs L level when the output mode is selected.
1:
Outputs H level when the output mode is selected.
Function
Port P4 input/output control
P4CR
(0x0F1E)
7
6
5
4
3
2
1
0
Bit Symbol
P4CR7
P4CR6
P4CR5
P4CR4
P4CR3
P4CR2
P4CR1
P4CR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
AIN5 (I)
AIN4 (I)
AIN3 (I)
AIN2 (I)
AIN1 (I)
AIN0 (I)
After reset
Input mode (port input)
0:
Function
AIN7 (I)
1:
AIN6 (I)
Output mode (port output)
Note 1: Symbol "I" means secondary function input.
Note 2: When the key-on wakeup input (KWIi) is enabled (KWUCRm<KWnEN>="1"), there is no need to set P4CRi. (i=7 to 0,
m=1 to 0, n=3 to 0)
Port P4 function control
P4FC
(0x0F38)
7
6
5
4
3
2
1
0
Bit Symbol
P4FC7
P4FC6
P4FC5
P4FC4
P4FC3
P4FC2
P4FC1
P4FC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
AIN6 (I)
AIN5 (I)
AIN4 (I)
AIN3 (I)
AIN2 (I)
AIN1 (I)
AIN0 (I)
0:
Port function
1:
AIN7 (I)
Function
Note 1: When the key-on wakeup input (KWIi) is enabled, there is no need to set P4FCi.
Port P4 built-in pull-up resistor control
P4PU
(0x0F2B)
7
6
5
4
3
2
1
0
Bit Symbol
P4PU7
P4PU6
P4PU5
P4PU4
P4PU3
P4PU2
P4PU1
P4PU0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
0:
The built-in pull-up resistor is not connected.
1:
The built-in pull-up resistor is connected.
(The resistor is connected only when the key-on wakeup input (KWIi) is enabled or the port is used in the input
mode (P4FCi="0" and P4CRi="0"). Under any other conditions, setting to "1" does not make the resistor connected.)
Function
Port P4 input data
P4PRD
(0x0011)
7
6
5
4
3
2
1
0
Bit Symbol
P4PRD7
P4PRD6
P4PRD5
P4PRD4
P4PRD3
P4PRD2
P4PRD1
P4PRD0
Read/Write
R
R
R
R
R
R
R
R
After reset
*
*
*
*
*
*
*
*
Function
RA005
If the port is in the input mode, the contents of the port are read. If not, "0" is read.
Page 100
TMP89FM46
Table 8-11 P4PRD Read Value
Set condition
P4PRDi read value
P4CRi
P4FCi
0
0
Contents of port
*
1
"0"
1
*
"0"
Note 1: * : Don’t care
Note 2: i = 0 to 7
RA005
Page 101
8. I/O Ports
8.3 I/O Port Registers
8.3.5
TMP89FM46
Port P7 (P77 to P70)
Port P7 is an 8-bit input/output port that can be set to input or output for each bit individually, and it is also
used as the external interrupt input, the divider output and the timer counter input/output.
Table 8-12 Port P7
Secondary
function
P77
P76
P75
P74
P73
P72
P71
P70
INT4
INT3
INT2
DVO
PPGA1
PPGA0
PPG01
PPG00
TCA1
TCA0
PWM01
PWM00
TC01
TC00
Input/output control
(for each bit)
Peripheral
functions
Divider
output
Internal data bus
P7CR write
VDD
Function control
(for each bit)
P7FC write
P7i
Output latch
(for each bit)
0 S
(Note3)
1
P7DR write
DVO, PPGA1, PPGA0, PPG01,
PPG00, PWM01, PWM00
Functions enclosed by
the dotted line are for
P74 to P70 only.
R
External
interrupt
P7PRD read
TCA0
TCA1
TC00
TC01
INT4, INT3, INT2,
TCA1, TCA0, TC01, TC00
SYSCR1<STOP>
SYSCR1<OUTEN>
Reset signal
Figure 8-7 Port P7
RA005
Page 102
Note1 : R = 100Ω (typ.)
Note2 : i = 0 to 7
Note3 : Nch large current
(Only P70 to P73)
TMP89FM46
Port P7 output latch
P7DR
(0x0007)
7
6
5
4
3
2
1
0
Bit Symbol
P77
P76
P75
P74
P73
P72
P71
P70
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
After reset
0:
Outputs L level when the output mode is selected
1:
Outputs H level when the output mode is selected
Function
Port P7 input/output control
P7CR
(0x0F21)
7
6
5
4
3
2
1
0
Bit Symbol
P7CR7
P7CR6
P7CR5
P7CR4
P7CR3
P7CR2
P7CR1
P7CR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
INT2 (I)
-
TCA1 (I)
TCA0 (I)
TC01 (I)
TC00 (I)
-
DVO (O)
PPGA1 (O)
PPGA0 (O)
After reset
Input mode (port input)
0:
INT4 (I)
Function
INT3 (I)
Output mode (port output)
1:
-
-
PPG01 (O)
PPG00 (O)
PWM01 (O)
PWM00 (O)
Note: Symbol "I" means secondary function input. Symbol "O" means secondary function output.
Port P7 function control
P7FC
(0x0F3B)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
P7FC3
P7FC3
P7FC2
P7FC1
P7FC0
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
After reset
0:
Port function
Function
DVO (O)
1:
PPGA1 (O)
PPGA0 (O)
PPG01 (O)
PPG00 (O)
PWM01 (O)
PWM00 (O)
Port P7 input data
P7PRD
(0x0014)
7
6
5
4
3
2
1
0
Bit Symbol
P7PRD7
P7PRD6
P7PRD5
P7PRD4
P7PRD3
P7PRD2
P7PRD1
P7PRD0
Read/Write
R
R
R
R
R
R
R
R
After reset
*
*
*
*
*
*
*
*
Function
If the port is used in the input mode, the contents of the port are read. If not, "0" is read.
Table 8-13 P7PRD Read Value
Set condition
P7PRDi read value
P7CRi
0
Contents of port
1
"0"
Note 1: * : Don’t care
Note 2: i = 0 to 7
RA005
Page 103
8. I/O Ports
8.3 I/O Port Registers
8.3.6
TMP89FM46
Port P8 (P83 to P80)
Port P8 is a 4-bit input/output port that can be set to input or output for each bit individually, and it is also used
as the timer counter input/output.
Table 8-14 Port P8
Secondary
function
-
-
-
-
P83
P82
-
-
P81
P80
PPG03
PPG02
PWM03
PWM02
TC03
TC02
Input/output control
(for each bit)
Peripheral
functions
Internal data bus
P8CR write
VDD
Function control
(for each bit)
P8FC write
P8i
Output latch
(for each bit)
0 S
1
P8DR write
TC03
TC02
Functions enclosed by
the dotted line are for
P81 and P80 only.
R
PPG03, PPG02, PWM03, PWM02
P8PRD read
TC03, TC02
Note1 : R = 100Ω (typ.)
Note2 : i = 0 to 3
SYSCR1<STOP>
SYSCR1<OUTEN>
Reset signal
Figure 8-8 Port P8
RA005
Page 104
TMP89FM46
Port P8 output latch
P8DR
(0x0008)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
P83
P82
P81
P80
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
After reset
0:
Outputs L level when the output mode is selected.
1:
Outputs H level when the output mode is selected.
Function
Port P8 input/output control
P8CR
(0x0F22)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
P8CR3
P8CR2
P8CR1
P8CR0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
TC03 (I)
TC02 (I)
Input mode (port input)
0:
Function
-
Output mode (port output)
1:
-
PPG03 (O)
PPG02 (O)
PWM03 (O)
PWM02 (O)
2
1
0
-
Note: Symbol "I" means secondary function input. Symbol "O" means secondary function output.
Port P8 function control
P8FC
(0x0F3C)
7
6
5
4
3
Bit Symbol
-
-
-
-
-
-
P8FC1
P8FC0
Read/Write
R
R
R
R
R
R
R/W
R/W
0
0
0
0
0
0
0
0
After reset
0:
Port function
Function
1:
PPG03 (O)
PPG02 (O)
PWM03 (O)
PWM02 (O)
Port P8 input data
P8PRD
(0x0015)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
P8PRD3
P8PRD2
P8PRD1
P8PRD0
Read/Write
R
R
R
R
R
R
R
R
After reset
0
0
0
0
*
*
*
*
If the port is used in the input mode, the contents of the
port are read. If not, "0" is read.
Function
Table 8-15 P8PRD Read Value
Set condition
P8PRDi read value
P8CRi
0
Contents of port
1
"0"
Note 1: * : Don’t care
Note 2: i = 0 to 3
RA005
Page 105
8. I/O Ports
8.3 I/O Port Registers
8.3.7
TMP89FM46
Port P9 (P91 to P90)
Port P9 is a 2-bit input/output port that can be set to input or output for each bit individually, and it is also
used as the UART.
The output circuit has the P-channel output control function and either the sink open drain output or the CMOS output can be selected. Port P9 contains a programmable pull-up resistor on the VDD side. This pull-up
resistor can be used when the port is used in the input mode or as a sink open drain output.
When this port is used as the UART, setting for the serial interface selecting function is also needed. For
details, refer to "8.4 Serial Interface Selecting Function".
Table 8-16 Port P9
Secondary
function
-
-
-
-
-
-
P91
P90
RXD1
TXD1
TXD1
RXD1
VDD
Pull-up control
(for each bit)
Programmable
pull-up resistor
P9PU write
RIN3
Output control
(for each bit)
Internal data bus
P9OUTCR write
Input/output control
(for each bit)
P9CR write
VDD
Function control
(for each bit)
P9FC write
P9i
Output latch
(for each bit)
0 S
1
P9DR write
Peripheral
functions
UART1
R
TXD1
P9PRD read
RXD1
SYSCR1<STOP>
SYSCR1<OUTEN>
Reset signal
Figure 8-9 Port P9
RA005
Page 106
Note1 : R = 100Ω (typ.)
Note2 : RIN3 = 50kΩ (typ.)
Note3 : i = 0 to 1
TMP89FM46
Port P9 output latch
P9DR
(0x0009)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
-
-
P91
P90
Read/Write
R
R
R
R
R
R
R/W
R/W
After reset
0
0
0
0
0
0
0
0
0:
Outputs L level when the
output mode is selected.
1:
Outputs H level when the
output mode is selected.
(Serves as Hi-Z or pull-up
depending on settings of
P9OUTCR and P9PU.)
Function
Port P9 input/output control
P9CR
(0x0F23)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
-
-
P9CR1
P9CR0
Read/Write
R
R
R
R
R
R
R/W
R/W
After reset
0
0
0
0
0
0
0
0
Input mode (port input)
0:
RXD1 (I)
RXD1 (I)
Function
Output mode (port output)
1:
TXD1 (O)
TXD1 (O)
2
1
0
Note: Symbol "I" means secondary function input. Symbol "O" means secondary function output.
Port P9 function control
P9FC
(0x0F3D)
7
6
5
4
3
Bit Symbol
-
-
-
-
-
-
P9FC1
P9FC0
Read/Write
R
R
R
R
R
R
R/W
R/W
0
0
0
0
0
0
0
0
After reset
0:
Port function
1:
TXD1 (O)
TXD1 (O)
2
1
0
Function
Port P9 output control
P9OUTCR
(0x0F4A)
7
6
5
4
3
Bit Symbol
-
-
-
-
-
-
P9OUT1
P9OUT0
Read/Write
R
R
R
R
R
R
R/W
R/W
0
0
0
0
0
0
0
0
After reset
0:
C-MOS output
1:
Open drain output
Function
Port P9 built-in pull-up resistor control
P9PU
(0x0F30)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
-
-
P9PU1
P9PU0
Read/Write
R
R
R
R
R
R
R/W
R/W
After reset
0
0
0
0
0
0
0
0
0:
The built-in pull-up resistor
is not connected.
1:
Note 1
Function
Note 1: The built-in pull-up resistor is connected. (The resistor is connected only when the port is used in the input mode or as the
open drain output. Under any other conditions, setting to "1" does not make the resistor connected.)
RA005
Page 107
8. I/O Ports
8.3 I/O Port Registers
TMP89FM46
Port P9 input data
P9PRD
(0x0016)
7
6
5
4
3
1
0
Bit Symbol
-
-
-
-
-
-
P9PRD1
P9PRD0
Read/Write
R
R
R
R
R
R
R
R
After reset
0
0
0
0
0
0
*
*
If the port is used in the
input mode or as the sink
open drain output, the
contents of the port are
read. If not, "0" is read.
Function
Table 8-17 P9PRD Read Value
Set condition
P9PRDi read value
P9CRi
P9OUTCRi
0
*
Contents of port
1
0
"0"
1
1
Contents of port
Note 1: * : Don’t care
Note 2: i = 0 to 1
RA005
2
Page 108
TMP89FM46
8.3.8
Port PB (PB7 to PB4)
Port PB is an 4-bit input/output port that can be set to input or output for each bit individually, and it is also
used as the serial interface input/output and the UART input/output.
The output circuit has the P-channel output control function and either the sink open drain output or the CMOS output can be selected.
When this port is used as the serial interface or the UART, setting for serial interface selecting function is
also needed. For details, refer to "8.4 Serial Interface Selecting Function".
Table 8-18 Port PB
Secondary
function
PB7
PB6
PB5
PB4
-
-
-
-
-
SCLK0
SI0
RXD0
TXD0
SO0
TXD0
RXD0
-
-
-
-
Output control
(for each bit)
Internal data bus
PBOUTCR write
Input/output control
(for each bit)
PBCR write
Function control
(for each bit)
PBFC write
PBi
Output latch
(for each bit)
0 S
1
Peripheral
functions
PBDR write
SCLK0, SO0, TXD0
SIO0
UART0
PBPRD read
Functions enclosed by
the dotted line are for
PB6 to PB4 only.
SCLK0, SI0, RXD0
SYSCR1<STOP>
SYSCR1<OUTEN>
Reset signal
Figure 8-10 Port PB
RA005
Page 109
(Note2)
R
Note1 : R = 100Ω (typ.)
Note2 : Nch large current
Note3 : i = 4 to 7
8. I/O Ports
8.3 I/O Port Registers
TMP89FM46
Port PB output latch
PBDR
(0x000B)
7
6
5
4
3
2
1
0
Bit Symbol
PB7
PB6
PB5
PB4
-
-
-
-
Read/Write
R/W
R/W
R/W
R/W
R
R
R
R
0
0
0
0
0
0
0
0
3
2
1
0
After reset
0:
Outputs L level when the output mode is selected.
1:
Outputs H level when the output mode is selected.
Function
Port PB input/output control
PBCR
(0x0F25)
7
6
5
4
Bit Symbol
PBCR7
PBCR6
PBCR5
PBCR4
-
-
-
-
Read/Write
R/W
R/W
R/W
R/W
R
R
R
R
0
0
0
0
0
0
0
0
After reset
0:
Input mode (port input)
1:
Output mode (port output)
Function
Port PB function control
PBFC
(0x0F3F)
7
6
5
4
3
2
1
0
Bit Symbol
-
PBFC6
PBFC5
PBFC4
-
-
-
-
Read/Write
R
R/W
R/W
R/W
R
R
R
R
After reset
0
0
0
0
0
0
0
0
SCLK0 (O)
TXD0 (O)
TXD0 (O)
SO0 (O)
7
6
5
4
3
2
1
0
Bit Symbol
PBOUT7
PBOUT6
PBOUT5
PBOUT4
-
-
-
-
Read/Write
R/W
R/W
R/W
R/W
R
R
R
R
0
0
0
0
0
0
0
0
3
2
1
0
0:
Port function
Function
1:
Port PB output control
PBOUTCR
(0x0F4C)
After reset
0:
C-MOS output
1:
Open drain output
Function
Port PB input data
PBPRD
(0x0018)
7
6
5
4
Bit Symbol
PBPRD7
PBPRD6
PBPRD5
PBPRD4
Read/Write
R
R
R
R
R
R
R
R
After reset
*
*
*
*
*
*
*
*
Function
RA005
If the port is used in the input mode or as the open drain
output, the contents of the port are read. If not, "0" is
read.
Page 110
TMP89FM46
Table 8-19 PBPRD Read Value
Set condition
PBPRDi read value
PBCRi
PBOUTCRi
0
*
Contents of port
1
0
"0"
1
1
Contents of port
Note 1: * : Don’t care
Note 2: i = 4 to 7
RA005
Page 111
8. I/O Ports
8.4 Serial Interface Selecting Function
TMP89FM46
8.4 Serial Interface Selecting Function
On the TMP89FM46, the built-in serial interface (SIO, UART and I2C) communication pins and interrupt source
assignment can be changed. Two out of three functions, SIO0, UART0 and I2C0, can be used at the same time by
using this selecting function.
The input pins of the 16-bit timer counter A0 input (TCA0 input) can be changed by using this selecting function.
UART1
Port
P90 (TXD1)
P91 (RXD1)
Port
PB4 (TXD0 / SO0)
PB5 (RXD0 / SI0)
Selector
Selector
UART0
PB6 (SCLK0)
1
0
0*
10
Port
S
P21 (RXD0 / SI0)
P22 (SCLK0)
S
SIO0
Selector
SERSEL
<SRSEL2>
01
*0
I2C0
P20 (TXD0 / SO0)
Port
P23 (SDA0 / SO0)
P24 (SCL0 / SI0)
P25 (SCLK0)
Port
P72 (TCA0)
S
SERSEL<SRSEL0>
Selector
TCA0
00
01
10
P21 (RXD0)
P91 (RXD1)
S
SERSEL<TCA0SEL>
Figure 8-11 Serial Interface Selecting Function
Serial interface selection control register
SERSEL
(0x0FCB)
7
Bit Symbol
6
5
4
TCA0SEL
3
2
1
SRSEL2
0
SRSEL0
Read/Write
R/W
R/W
R
R/W
R
R
R/W
R/W
After reset
0
0
0
0
0
0
0
0
TCA0SEL
SRSEL2
SRSEL0
16-bit timer counter A0 input switching
Select UART0/SIO0 input/output
port
Serial interface selection 0
00:
01:
10:
11:
0:
1:
00:
01:
10:
11:
P72 input (TCA0)
P21 input (also used as RXD0)
P91 input (also used as RXD1)
Reserved
Select P20, P21, P22
Select PB4, PB5, PB6
Select UART0, I2C0
Select UART0, SIO0
Select SIO0, I2C0
Reserved
Note 1: The operation for changing SERSEL must be executed while the applicable serial interface and timer counter operations
are stopped. If SERSEL is switched during operation of these peripheral functions, each peripheral function may receive
(transmit) unexpected data and operate improperly.
RA005
Page 112
TMP89FM46
Note 2: It is recommended to clear the interrupt latch for the applicable serial interface immediately after changing SERSEL. Interrupt latches are common to INTRXD and INTSIO and to INTSBI and INTSIO. Therefore, if an interrupt occurs before or
after SERSEL is switched, it is difficult to tell which function has caused the interrupt.
UART input/output change control register
UATCNG
(0x0F57)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
-
-
UAT1IO
UAT0IO
Read/Write
R
R
R
R
R
R
R/W
R/W
After reset
0
0
0
0
0
0
0
0
RXD pin
UAT1IO
UAT0IO
0:
1:
Select UART1 input/ output port
TXD pin
P91
P90
P90
P91
SERSEL
<SERSEL2>="0"
SERSEL
<SERSEL2>="1"
SERSEL
<SERSEL2>="0"
SERSEL
<SERSEL2>="1"
P21
P20
PB5
PB4
P20
P21
PB4
PB5
Select UART0 input/ output port
0:
1:
Note 1: The operation for changing UATCNG must be executed while the applicable serial interface operations are stopped.
Table 8-20 Select input/output port and interrupt
SERSEL
<SRSEL0
>
SERSEL
<SRSEL2
>
UATCNG
<UAT0IO
>
Port
Interrupt
UART0/SIO0
I2C0/SIO0
PB4
PB5
PB6
P20
P21
P22
Note
1
Note
1
TXD0
RXD0
1:
Note
1
RXD0
TXD0
Note
1
0:
TXD0
RXD0
1:
RXD0
0:
0:
0:
00:
TXD0
Note
1
Note
1
Note
1
Note
1
Note
1
Note
1
TXD0
RXD0
1:
Note
1
RXD0
TXD0
Note
1
0:
TXD0
RXD0
1:
RXD0
0 or 1:
Note
1
1:
0:
01:
TXD0
Note
1
Note
1
Note
1
Note
1
Note
1
Note
1
SO0
SI0
SCLK
0
1:
0:
10:
11:
1:
0 or 1:
0 or 1:
0 or 1:
SO0
SI0
SCLK
0
Note
1
Note
1
P24
P25
IL7
IL6
IL15
SDA0
SCL0
Note
1
INTTXD0
INTRXD0
INTSBI0
SO0
SI0
SCLK
0
INTTXD0
INTRXD0
INTSIO0
SDA0
SCL0
Note
1
-
INTSIO0
INTSBI0
Note
1
Reserved
Note 1: Can be used as a port. (Set the function register (PxFC) to "0".)
RA005
P23
Page 113
8. I/O Ports
8.5 Revision History
TMP89FM46
8.5 Revision History
Rev
RA005
RA005
Description
"Figure 8-4 Port P1" Revised reset control signal.
Page 114
TMP89FM46
9. Special Function Registers
The TMP89FM46 adopts the memory mapped I/O system, and all peripheral hardware data control and transfer
operations are performed through the special function registers (SFR). SFR1 is mapped on addresses 0x0000 to
0x003F, SFR2 is mapped on addresses 0x0F00 to 0x0FFF, and SFR3 is mapped on addresses 0x0E40 to 0x0EBF.
9.1 SFR1 (0x0000 to 0x003F)
Table 9-1 SFR1 (0x0000 to 0x003F)
Address
Register Name
Address
Register Name
0x0000
P0DR
0x0020
SIO0SR
0x0001
P1DR
0x0021
SIO0BUF
0x0002
P2DR
0x0022
SBI0CR1
0x0003
Reserved
0x0023
SBI0CR2/SBI0SR2
0x0004
P4DR
0x0024
I2C0AR
0x0005
Reserved
0x0025
SBI0DBR
0x0006
Reserved
0x0026
T00REG
0x0007
P7DR
0x0027
T01REG
0x0008
P8DR
0x0028
T00PWM
0x0009
P9DR
0x0029
T01PWM
0x000A
Reserved
0x002A
T00MOD
0x000B
PBDR
0x002B
T01MOD
0x000C
Reserved
0x002C
T001CR
0x000D
P0PRD
0x002D
TA0DRAL
0x000E
P1PRD
0x002E
TA0DRAH
0x000F
P2PRD
0x002F
TA0DRBL
0x0010
Reserved
0x0030
TA0DRBH
0x0011
P4PRD
0x0031
TA0MOD
0x0012
Reserved
0x0032
TA0CR
0x0013
Reserved
0x0033
TA0SR
0x0014
P7PRD
0x0034
ADCCR1
0x0015
P8PRD
0x0035
ADCCR2
0x0016
P9PRD
0x0036
ADCDRL
0x0017
Reserved
0x0037
ADCDRH
0x0018
PBPRD
0x0038
DVOCR
0x0019
Reserved
0x0039
TBTCR
0x001A
UART0CR1
0x003A
EIRL
0x001B
UART0CR2
0x003B
EIRH
0x001C
UART0DR
0x003C
EIRE
0x001D
UART0SR
0x003D
EIRD
0x001E
TD0BUF/RD0BUF
0x003E
Reserved
0x001F
SIO0CR
0x003F
PSW
Note 1: Do not access reserved addresses by the program.
RA001
Page 115
9. Special Function Registers
9.2 SFR2 (0x0F00 to 0x0FFF)
TMP89FM46
9.2 SFR2 (0x0F00 to 0x0FFF)
Table 9-2
SFR2 (0x0F00 to 0x0F7F)
Address
Register Name
Address
Register Name
Address
Register Name
Address
Register Name
0x0F00
Reserved
0x0F20
Reserved
0x0F40
Reserved
0x0F60
Reserved
0x0F01
Reserved
0x0F21
P7CR
0x0F41
Reserved
0x0F61
Reserved
0x0F02
Reserved
0x0F22
P8CR
0x0F42
Reserved
0x0F62
Reserved
0x0F03
Reserved
0x0F23
P9CR
0x0F43
P2OUTCR
0x0F63
Reserved
0x0F04
Reserved
0x0F24
Reserved
0x0F44
Reserved
0x0F64
Reserved
0x0F05
Reserved
0x0F25
PBCR
0x0F45
Reserved
0x0F65
Reserved
0x0F06
Reserved
0x0F26
Reserved
0x0F46
Reserved
0x0F66
Reserved
0x0F07
Reserved
0x0F27
P0PU
0x0F47
Reserved
0x0F67
Reserved
0x0F08
Reserved
0x0F28
P1PU
0x0F48
Reserved
0x0F68
Reserved
0x0F09
Reserved
0x0F29
P2PU
0x0F49
Reserved
0x0F69
Reserved
0x0F0A
Reserved
0x0F2A
Reserved
0x0F4A
P9OUTCR
0x0F6A
Reserved
0x0F0B
Reserved
0x0F2B
P4PU
0x0F4B
Reserved
0x0F6B
Reserved
0x0F0C
Reserved
0x0F2C
Reserved
0x0F4C
PBOUTCR
0x0F6C
Reserved
0x0F0D
Reserved
0x0F2D
Reserved
0x0F4D
Reserved
0x0F6D
Reserved
0x0F0E
Reserved
0x0F2E
Reserved
0x0F4E
Reserved
0x0F6E
Reserved
0x0F0F
Reserved
0x0F2F
Reserved
0x0F4F
Reserved
0x0F6F
Reserved
0x0F10
Reserved
0x0F30
P9PU
0x0F50
Reserved
0x0F70
Reserved
0x0F11
Reserved
0x0F31
Reserved
0x0F51
Reserved
0x0F71
Reserved
0x0F12
Reserved
0x0F32
Reserved
0x0F52
Reserved
0x0F72
Reserved
0x0F13
Reserved
0x0F33
Reserved
0x0F53
Reserved
0x0F73
Reserved
0x0F14
Reserved
0x0F34
P0FC
0x0F54
UART1CR1
0x0F74
POFFCR0
0x0F15
Reserved
0x0F35
Reserved
0x0F55
UART1CR2
0x0F75
POFFCR1
0x0F16
Reserved
0x0F36
P2FC
0x0F56
UART1DR
0x0F76
POFFCR2
0x0F17
Reserved
0x0F37
Reserved
0x0F57
UART1SR
0x0F77
POFFCR3
0x0F18
Reserved
0x0F38
P4FC
0x0F58
TD1BUF/RD1BUF
0x0F78
Reserved
0x0F19
Reserved
0x0F39
Reserved
0x0F59
Reserved
0x0F79
Reserved
0x0F1A
P0CR
0x0F3A
Reserved
0x0F5A
Reserved
0x0F7A
Reserved
0x0F1B
P1CR
0x0F3B
P7FC
0x0F5B
Reserved
0x0F7B
Reserved
0x0F1C
P2CR
0x0F3C
P8FC
0x0F5C
Reserved
0x0F7C
Reserved
0x0F1D
Reserved
0x0F3D
P9FC
0x0F5D
Reserved
0x0F7D
Reserved
0x0F1E
P4CR
0x0F3E
Reserved
0x0F5E
Reserved
0x0F7E
Reserved
0x0F1F
Reserved
0x0F3F
PBFC
0x0F5F
Reserved
0x0F7F
Reserved
Note 1: Do not access reserved addresses by the program.
RA001
Page 116
TMP89FM46
Table 9-3
SFR2 (0x0F80 to 0x0FFF)
Address
Register Name
Address
Register Name
Address
Register Name
Address
Register Name
0x0F80
Reserved
0x0FA0
Reserved
0x0FC0
Reserved
0x0FE0
ILL
0x0F81
Reserved
0x0FA1
Reserved
0x0FC1
Reserved
0x0FE1
ILH
0x0F82
Reserved
0x0FA2
Reserved
0x0FC2
Reserved
0x0FE2
ILE
0x0F83
Reserved
0x0FA3
Reserved
0x0FC3
Reserved
0x0FE3
ILD
0x0F84
Reserved
0x0FA4
Reserved
0x0FC4
KWUCR0
0x0FE4
Reserved
0x0F85
Reserved
0x0FA5
Reserved
0x0FC5
KWUCR1
0x0FE5
Reserved
0x0F86
Reserved
0x0FA6
Reserved
0x0FC6
VDCR1
0x0FE6
Reserved
0x0F87
Reserved
0x0FA7
Reserved
0x0FC7
VDCR2
0x0FE7
Reserved
0x0F88
T02REG
0x0FA8
TA1DRAL
0x0FC8
RTCCR
0x0FE8
Reserved
0x0F89
T03REG
0x0FA9
TA1DRAH
0x0FC9
Reserved
0x0FE9
Reserved
0x0F8A
T02PWM
0x0FAA
TA1DRBL
0x0FCA
Reserved
0x0FEA
Reserved
0x0F8B
T03PWM
0x0FAB
TA1DRBH
0x0FCB
SERSEL
0x0FEB
Reserved
0x0F8C
T02MOD
0x0FAC
TA1MOD
0x0FCC
IRSTSR
0x0FEC
Reserved
0x0F8D
T03MOD
0x0FAD
TA1CR
0x0FCD
WUCCR
0x0FED
Reserved
0x0F8E
T023CR
0x0FAE
TA1SR
0x0FCE
WUCDR
0x0FEE
Reserved
0x0F8F
Reserved
0x0FAF
Reserved
0x0FCF
CGCR
0x0FEF
Reserved
0x0F90
Reserved
0x0FB0
Reserved
0x0FD0
FLSCR1
0x0FF0
ILPRS1
0x0F91
Reserved
0x0FB1
Reserved
0x0FD1
FLSCR2/FLSCRM
0x0FF1
ILPRS2
0x0F92
Reserved
0x0FB2
Reserved
0x0FD2
FLSSTB
0x0FF2
ILPRS3
0x0F93
Reserved
0x0FB3
Reserved
0x0FD3
SPCR
0x0FF3
ILPRS4
0x0F94
Reserved
0x0FB4
Reserved
0x0FD4
WDCTR
0x0FF4
ILPRS5
0x0F95
Reserved
0x0FB5
Reserved
0x0FD5
WDCDR
0x0FF5
ILPRS6
0x0F96
Reserved
0x0FB6
Reserved
0x0FD6
WDCNT
0x0FF6
Reserved
0x0F97
Reserved
0x0FB7
Reserved
0x0FD7
WDST
0x0FF7
Reserved
0x0F98
Reserved
0x0FB8
Reserved
0x0FD8
EINTCR1
0x0FF8
Reserved
0x0F99
Reserved
0x0FB9
Reserved
0x0FD9
EINTCR2
0x0FF9
Reserved
0x0F9A
Reserved
0x0FBA
Reserved
0x0FDA
EINTCR3
0x0FFA
Reserved
0x0F9B
Reserved
0x0FBB
Reserved
0x0FDB
EINTCR4
0x0FFB
Reserved
0x0F9C
Reserved
0x0FBC
Reserved
0x0FDC
SYSCR1
0x0FFC
Reserved
0x0F9D
Reserved
0x0FBD
Reserved
0x0FDD
SYSCR2
0x0FFD
Reserved
0x0F9E
Reserved
0x0FBE
Reserved
0x0FDE
SYSCR3
0x0FFE
Reserved
0x0F9F
Reserved
0x0FBF
Reserved
0x0FDF
SYSCR4/SYSSR4
0x0FFF
Reserved
Note 1: Do not access reserved addresses by the program.
RA001
Page 117
9. Special Function Registers
9.3 SFR3 (0x0E40 to 0x0EFF)
TMP89FM46
9.3 SFR3 (0x0E40 to 0x0EFF)
Table 9-4
SFR3 (0x0E40 to 0x0EBF)
Address
Register Name
Address
Register Name
Address
Register Name
Address
Register Name
0x0E40
Reserved
0x0E60
Reserved
0x0E80
Reserved
0x0EA0
Reserved
0x0E41
Reserved
0x0E61
Reserved
0x0E81
Reserved
0x0EA1
Reserved
0x0E42
Reserved
0x0E62
Reserved
0x0E82
Reserved
0x0EA2
Reserved
0x0E43
Reserved
0x0E63
Reserved
0x0E83
Reserved
0x0EA3
Reserved
0x0E44
Reserved
0x0E64
Reserved
0x0E84
Reserved
0x0EA4
Reserved
0x0E45
Reserved
0x0E65
Reserved
0x0E85
Reserved
0x0EA5
Reserved
0x0E46
Reserved
0x0E66
Reserved
0x0E86
Reserved
0x0EA6
Reserved
0x0E47
Reserved
0x0E67
Reserved
0x0E87
Reserved
0x0EA7
Reserved
0x0E48
Reserved
0x0E68
Reserved
0x0E88
Reserved
0x0EA8
Reserved
0x0E49
Reserved
0x0E69
Reserved
0x0E89
Reserved
0x0EA9
Reserved
0x0E4A
Reserved
0x0E6A
Reserved
0x0E8A
Reserved
0x0EAA
Reserved
0x0E4B
Reserved
0x0E6B
Reserved
0x0E8B
Reserved
0x0EAB
Reserved
0x0E4C
Reserved
0x0E6C
Reserved
0x0E8C
Reserved
0x0EAC
Reserved
0x0E4D
Reserved
0x0E6D
Reserved
0x0E8D
Reserved
0x0EAD
Reserved
0x0E4E
Reserved
0x0E6E
Reserved
0x0E8E
Reserved
0x0EAE
Reserved
0x0E4F
Reserved
0x0E6F
Reserved
0x0E8F
Reserved
0x0EAF
Reserved
0x0E50
Reserved
0x0E70
Reserved
0x0E90
Reserved
0x0EB0
Reserved
0x0E51
Reserved
0x0E71
Reserved
0x0E91
Reserved
0x0EB1
Reserved
0x0E52
Reserved
0x0E72
Reserved
0x0E92
Reserved
0x0EB2
Reserved
0x0E53
Reserved
0x0E73
Reserved
0x0E93
Reserved
0x0EB3
Reserved
0x0E54
Reserved
0x0E74
Reserved
0x0E94
Reserved
0x0EB4
Reserved
0x0E55
Reserved
0x0E75
Reserved
0x0E95
Reserved
0x0EB5
Reserved
0x0E56
Reserved
0x0E76
Reserved
0x0E96
Reserved
0x0EB6
Reserved
0x0E57
UATCNG
0x0E77
Reserved
0x0E97
Reserved
0x0EB7
Reserved
0x0E58
Reserved
0x0E78
Reserved
0x0E98
Reserved
0x0EB8
Reserved
0x0E59
Reserved
0x0E79
Reserved
0x0E99
Reserved
0x0EB9
Reserved
0x0E5A
Reserved
0x0E7A
Reserved
0x0E9A
Reserved
0x0EBA
Reserved
0x0E5B
Reserved
0x0E7B
Reserved
0x0E9B
Reserved
0x0EBB
Reserved
0x0E5C
Reserved
0x0E7C
Reserved
0x0E9C
Reserved
0x0EBC
Reserved
0x0E5D
Reserved
0x0E7D
Reserved
0x0E9D
Reserved
0x0EBD
Reserved
0x0E5E
Reserved
0x0E7E
Reserved
0x0E9E
Reserved
0x0EBE
Reserved
0x0E5F
Reserved
0x0E7F
Reserved
0x0E9F
Reserved
0x0EBF
Reserved
Note 1: Do not access reserved addresses by the program.
RA001
Page 118
TMP89FM46
Table 9-5
SFR3 (0x0EC0 to 0x0EFF)
Address
Register Name
Address
Register Name
Address
Register Name
Address
Register Name
0x0EC0
Reserved
0x0ED0
Reserved
0x0EE0
Reserved
0x0EF0
Reserved
0x0EC1
Reserved
0x0ED1
Reserved
0x0EE1
Reserved
0x0EF1
Reserved
0x0EC2
Reserved
0x0ED2
Reserved
0x0EE2
Reserved
0x0EF2
Reserved
0x0EC3
Reserved
0x0ED3
Reserved
0x0EE3
Reserved
0x0EF3
Reserved
0x0EC4
Reserved
0x0ED4
Reserved
0x0EE4
Reserved
0x0EF4
Reserved
0x0EC5
Reserved
0x0ED5
Reserved
0x0EE5
Reserved
0x0EF5
Reserved
0x0EC6
Reserved
0x0ED6
Reserved
0x0EE6
Reserved
0x0EF6
Reserved
0x0EC7
Reserved
0x0ED7
Reserved
0x0EE7
Reserved
0x0EF7
Reserved
0x0EC8
Reserved
0x0ED8
Reserved
0x0EE8
Reserved
0x0EF8
Reserved
0x0EC9
Reserved
0x0ED9
Reserved
0x0EE9
Reserved
0x0EF9
Reserved
0x0ECA
Reserved
0x0EDA
Reserved
0x0EEA
Reserved
0x0EFA
Reserved
0x0ECB
Reserved
0x0EDB
Reserved
0x0EEB
Reserved
0x0EFB
Reserved
0x0ECC
Reserved
0x0EDC
Reserved
0x0EEC
Reserved
0x0EFC
Reserved
0x0ECD
Reserved
0x0EDD
Reserved
0x0EED
Reserved
0x0EFD
Reserved
0x0ECE
Reserved
0x0EDE
Reserved
0x0EEE
Reserved
0x0EFE
Reserved
0x0ECF
Reserved
0x0EDF
Reserved
0x0EEF
Reserved
0x0EFF
Reserved
Note 1: Do not access reserved addresses by the program.
RA001
Page 119
9. Special Function Registers
9.3 SFR3 (0x0E40 to 0x0EFF)
RA001
TMP89FM46
Page 120
TMP89FM46
10. Low Power Consumption Function for Peripherals
The TMP89FM46 has low power consumption registers (POFFCRn) that save power when specific peripheral
functions are unused. Each bit of the low power consumption registers can be set to enable or disable each peripheral
function. (n = 0, 1, 2, 3)
The basic clock supply to each peripheral function is disabled for power saving, by setting the corresponding bit of
the low power consumption registers (POFFCRn) to "0". (The disabled peripheral functions become unavailable.)
The basic clock supply to each peripheral function is enabled and the function becomes available by setting the corresponding bit of the low power consumption registers (POFFCRn) to "1".
After reset, the low power consumption registers (POFFCRn) are initialized to "0", and thus the peripheral functions are unavailable. When each peripheral function is used for the first time, be sure to set the corresponding bit of
the low power consumption registers (POFFCRn) to "1" in the initial settings of the program (before operating the
control register for the peripheral function).
When a peripheral function is operating, the corresponding bit of the low power consumption registers
(POFFCRn) must not be changed to "0". If it is changed, the peripheral function may operate unexpectedly.
RA001
Page 121
10. Low Power Consumption Function for Peripherals
TMP89FM46
10.1 Control
The low power consumption function is controlled by the low power consumption registers (POFFCRn). (n = 0, 1,
2, 3)
Low power consumption register 0
POFFCR0
(0x0F74)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
TC023EN
TC001EN
-
-
TCA1EN
TCA0EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
3
2
1
0
TC023EN
TC02,03 control
0
1
Disable
Enable
TC001EN
TC00,01 control
0
1
Disable
Enable
TCA1EN
TCA1 control
0
1
Disable
Enable
TCA0EN
TCA0 control
0
1
Disable
Enable
Low power consumption register 1
POFFCR1
(0x0F75)
7
6
5
4
Bit Symbol
-
-
-
SBI0EN
-
-
UART1EN
UART0EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
I2C0 control
0
1
Disable
Enable
UART1EN
UART1 control
0
1
Disable
Enable
UART0EN
UART0 control
0
1
Disable
Enable
SBI0EN
Low power consumption register 2
POFFCR2
(0x0F76)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
RTCEN
-
-
-
-
SIO0EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
RTCEN
RTC control
0
1
Disable
Enable
SIO0EN
SIO0 control
0
1
Disable
Enable
Low power consumption register 3
POFFCR3
(0x0F77)
RA001
7
6
5
4
3
2
1
0
Bit Symbol
-
-
INT5EN
INT4EN
INT3EN
INT2EN
INT1EN
INT0EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
Page 122
TMP89FM46
RA001
INT5EN
INT5 control
0
1
Disable
Enable
INT4EN
INT4 control
0
1
Disable
Enable
INT3EN
INT3 control
0
1
Disable
Enable
INT2EN
INT2 control
0
1
Disable
Enable
INT1EN
INT1 control
0
1
Disable
Enable
INT0EN
INT0 control
0
1
Disable
Enable
Page 123
10. Low Power Consumption Function for Peripherals
TMP89FM46
RA001
Page 124
TMP89FM46
11. Divider Output (DVO)
This function outputs approximately 50% duty pulses that can be used to drive the piezoelectric buzzer or other
device.
11.1 Configuration
fcgck/212 or fs/25
fcgck/211 or fs/24
fcgck/210 or fs/23
fcgck/29
Selector
A
B
C Y
D
S
2
DVOCK
DVO pin
DVOEN
DVOCR
Figure 11-1 Divider Output
11.2 Control
The divider output is controlled by the divider output control register (DVOCR).
Divider output control register
DVOCR
(0x0038)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
-
DV0EN
DVOCK
Read/Write
R
R
R
R
R
R/W
R/W
After reset
0
0
0
0
0
0
DVOEN
Enables/disables
the divider output
Selects the divider output frequency
Unit: [Hz]
0
0: Disable the divider output
1: Enable the divider output
DV9CK=0
DV9CK=1
SLOW1/2
SLEEP1
mode
00
fcgck/212
fs/25
fs/25
01
fcgck/211
fs/24
fs/24
10
fcgck/210
fs/23
fs/23
11
fcgck/29
Reserved
Reserved
NORMAL 1/2, IDLE 1/2 mode
DVOCK
0
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: DVOCR<DVOEN> is cleared to "0" when the operation is switched to STOP or IDLE0/SLEEP0 mode. DVOCR<DVOCK>
holds the value.
Note 3: When SYSCR1<DV9CK> is "1" in the NORMAL 1/2 or IDLE 1/2 mode, the DVO frequency is subject to some fluctuations
to synchronize fs and fcgck.
Note 4: Bits 7 to 3 of DVOCR are read as "0".
11.2.1 Function
Select the divider output frequency at DVOCR<DVOCK>.
RA001
Page 125
11. Divider Output (DVO)
11.2 Control
TMP89FM46
The divider output is enabled by setting DVOCR<DVOEN> to "1". Then, The rectangular waves selected by
DVOCR<DVOCK> is output from DVO pin.
It is disabled by clearing DVOVR<DVOEN> to "0". And DVO pin keeps "H" level.
When the operation is changed to STOP or IDLE0/SLEEP0 mode, DVOCR<DVOEN> is cleared to "0" and
the DVO pin outputs the "H" level.
The divider output source clock operates, regardless of the value of DVOCR<DVOEN>.
Therefore, the frequency of the first divider output after DVOCR<DVOEN> is set to "1" is not the frequency
set at DVOCR<DVOCK>.
When the operation is changed to the software, STOP or IDLE0/SLEEP0 mode is activated and
DVOCR<DVOEN> is cleared to "0", the frequency of the divider output is not the frequency set at
DVOCR<DVOCK>.
TBTCR<DVOEN>
DVO output
Divider output timing chart
Figure 11-2 Divider Output Timing
When the operation is changed from NORMAL mode to SLOW mode or from SLOW mode to NORMAL
mode, the divider output frequency does not reach the expected value due to synchronization of the gear clock
(fcgck) and the low-frequency clock (fs).
Example: 2.441 kHz pulse output (fcgck = 10.0 MHz)
LD
; DVOCK ← "00", DVOEN ← "1"
(DVOCR), 00000100B
Table 11-1 Divider Output Frequency (Example: fcgck = 10.0 MHz, fs = 32.768 kHz)
Divider output frequency [Hz]
DVOCK
RA001
NORMAL 1/2, IDLE 1/2 mode
DV9CK = 0
DV9CK = 1
SLOW1/2, SLEEP1
mode
00
2.441 k
1.024 k
1.024 k
01
4.883 k
2.048 k
2.048 k
10
9.766 k
4.096 k
4.096 k
11
19.531 k
Reserved
Reserved
Page 126
TMP89FM46
12. Time Base Timer (TBT)
The time base timer generates the time base for key scanning, dynamic display and other processes. It also provides a time base timer interrupt (INTTBT) in a certain cycle.
12.1 Time Base Timer
12.1.1 Configuration
Selector
fcgck/222 or fs/215
fcgck/220 or fs/213
fcgck/215 or fs/28
fcgck/213 or fs/26
fcgck/212 or fs/25
fcgck/211 or fs/24
fcgck/210 or fs/23
fcgck/28
Source clock
IDLE0, SLEEP0
Release request
Falling edge
detector
INTTBT
Interrupt request
3
TBTCK
TBTEN
TBTCR
Figure 12-1 Time Base Timer Configuration
12.1.2 Control
The time base timer is controlled by the time base timer control register (TBTCR).
Time base timer control register
TBTCR
(0x0039)
7
6
5
4
3
2
1
Bit Symbol
-
-
-
-
TBTEN
TBTCK
Read/Write
R
R
R
R
R/W
R/W
After reset
0
0
0
0
0
TBTEN
Enables/disables the time base
timer interrupt requests
0
0
NORMAL 1/2, IDLE 1/2 mode
Selects the time base timer interrupt
frequency
Unit: [Hz]
0
0: Disables generation of interrupt request signals
1: Enables generation of interrupt request signals
DV9CK = 0
DV9CK = 1
SLOW1/2, SLEEP1
mode
000
fcgck/222
fs/215
fs/215
001
fcgck/220
fs/213
fs/213
010
fcgck/215
fs/28
Reserved
011
fcgck/213
fs/26
Reserved
100
fcgck/2
12
5
Reserved
101
fcgck/211
fs/24
Reserved
110
fcgck/2
10
3
Reserved
111
fcgck/28
TBTCK
TBTCK
0
fs/2
fs/2
Reserved
Reserved
Note 1: fcgck : Gear clock [Hz], fs : Low-frequency clock [Hz]
Note 2: When the operation is changed to the STOP mode, TBTCR<TBTEN> is cleared to "0" and TBTCR<TBTCK> maintains
the value.
RA001
Page 127
12. Time Base Timer (TBT)
12.1 Time Base Timer
TMP89FM46
Note 3: TBTCR<TBTCK> should be set when TBTCR<TBTEN> is "0".
Note 4: When SYSCR1<DV9CK> is "1" in the NORMAL 1/2 or IDLE1/2 mode, the interrupt request is subject to some fluctuations
to synchronize fs and fcgck.
Note 5: Bits 7 to 4 of TBTCR are read as "0".
12.1.3 Functions
Select the source clock frequency for the time base timer by TBTCR<TBTCK>. TBTCR<TBTCK> should
be changed when TBTCR<TBTEN> is "0". Otherwise, the INTTBT interrupt request is generated at unexpected timing.
Setting TBTCR<TBTEN> to "1" causes interrupt request signals to occur at the falling edge of the source
clock. When TBTCR<TBTEN> is cleared to "0", no interrupt request signal will occur.
When the operation is changed to the STOP mode, TBTCR<TBTEN> is cleared to "0".
The source clock of the time base timer operates regardless of the TBTCR<TBTEN> value.
A time base timer interrupt is generated at the first falling edge of the source clock after a time base timer
interrupt request is enabled. Therefore, the period from when the time TBTCR<TBTEN> is set to "1" to the
time when the first interrupt request occurs is shorter than the frequency period set at TBTCR<TBTCK>.
Source clock
TBTCR<TBTEN>
INTTBT interrupt
request
Interrupt period
Time base timer enable
Figure 12-2 Time Base Timer Interrupt
When the operation is changed from NORMAL mode to SLOW mode or from SLOW mode to NORMAL
mode, The interrupt request will not occur at the expected timing due to synchronization of the gear clock
(fcgck) and the low-frequency clock (fs). It is recommened that the operation mode is changed when
TBTCR<TBTEN> is "0".
Table 12-1 Time Base Timer Interrupt Frequency (Example: when fcgck = 10.0 MHz and fs =
32.768 kHz)
Time base timer interrupt frequency [Hz]
TBTCK
NORMAL1/2, IDLE1/2 mode
NORMAL1/2, IDLE1/2 mode
DV9CK = 0
DV9CK = 1
000
2.38
1
1
001
9.54
4
4
010
305.18
128
Reserved
011
1220.70
512
Reserved
100
2441.41
1024
Reserved
101
4882.81
2048
Reserved
110
9765.63
4096
Reserved
111
39062.5
Reserved
Reserved
SLOW1/2, SLEEP1 mode
Example: Set the time base timer interrupt frequency to fcgck/215 [Hz] and enable interrupts.
RA001
Page 128
TMP89FM46
; IMF ← 0
DI
SET
(EIRL). 5
; Set the interrupt enable register
; IMF ← 1
EI
RA001
LD
(TBTCR), 0y00000010
; Set the interrupt frequency
LD
(TBTCR), 0y00001010
; Enable generation of interrupt request signals
Page 129
12. Time Base Timer (TBT)
12.1 Time Base Timer
RA001
TMP89FM46
Page 130
TMP89FM46
13. 16-bit Timer Counter (TCA)
The TMP89FM46 contains 2 channels of high-performance 16-bit timer counters (TCA).
This chapter describes the 16-bit timer counter A0. For the 16-bit timer counter A1, replace the SFR addresses and
pin names, as shown in Table 13-1 and Table 13-2.
Table 13-1 SFR Address Assignment
TAxDRAL
(Address)
TAxDRAH
(Address)
TAxDRBL
(Address)
TAxDRBH
(Address)
TAxMOD
(Address)
TAxCR
(Address)
TAxSR
(Address)
Low power
consumption register
Timer counter A0
TA0DRAL
(0x002D)
TA0DRAH
(0x002E)
TA0DRBL
(0x002F)
TA0DRBH
(0x0030)
TA0MOD
(0x0031)
TA0CR
(0x0032)
TA0SR
(0x0033)
POFFCR0
<TCA0EN>
Timer counter A1
TA1DRAL
(0x0FA8)
TA1DRAH
(0x0FA9)
TA1DRBL
(0x0FAA)
TA1DRBH
(0x0FAB)
TA1MOD
(0x0FAC)
TA1CR
(0x0FAD)
TA1SR
(0x0FAE)
POFFCR0
<TCA1EN>
Table 13-2 Pin Names
RA001
Timer input pin
PPG output pin
Timer counter A0
TCA0 pin
PPGA0 pin
Timer counter A1
TCA1 pin
PPGA1 pin
Page 131
fcgck/210 or fs/23
fcgck/26
fcgck/22
fcgck/2
External
trigger
input
selection
E
A
B
C
D
2
TA0CAP
TA0MOD
3
0
1
Selector
Count
clear
Pulse width
measurement
mode
External trigger
timer mode
PPG mode
Window
mode
Count up
Edge detection 1
Edge detection 2
S
Y
1
Timer start
control
Capture control
TA0DRBH
0
0
Selector
TA0DRBL
1
Double buffer (16 bits)
Edge detection 1
Auto capture
control
Decorder
Event counter
mode
S0 S1
Y
Edge detection 1
Edge detection 2
TA0CK
TA0TED
Noise
canceller
TA0M
Temporary buffer
TA0NC
Selector
TA0CR
TA0CAP
TCA0 pin input
TA0DBE
1
TA0S
0
1
0
1
Selector
Internal bus
Clear TA0S
0
1
Selector
Edge detection 2
Capture control
0
Selector
TA0DRAL
1
Overflow
TA0SR
Match
detection
TAMCAP
Comparator
PPG mode
EN
Timer
F/F
PPGA0 output
INTTA0
interrupt request
1
0
Rising
Falling
Falling
Rising
TA0TED Edge detection 1 Edge detection 2
TA0OVE
Pulse width
measurement mode
Selector
0
Edge detection 1
Edge detection 2
1
Reading and
writing of
TA0DRAL
Temporary buffer
Double buffer (16 bits)
TA0DRAH
Reading and
writing of
TA0DRAH
16-bit up counter
Match
detection
Selector
0
Comparator
TA0TFF
TA0NC
2
TA0TED
Figure 13-1 Timer Counter A0
TA0METT
Page 132
TA0MPPG
TA0DBE
TA0OVE
Internal bus
TA0CPFB
Reading and
writing of
TA0DRBL
TA0CPFA
RA001
TA0OVF
Reading and writing
of TA0DRBH
13.1 Configuration
13. 16-bit Timer Counter (TCA)
TMP89FM46
13.1 Configuration
TMP89FM46
13.2 Control
Timer Counter A0 is controlled by the low power consumption register (POFFCR0), the timer counter A0 mode
register (TA0MOD), the timer counter A0 control register (TA0CR) and two 16-bit timer A0 registers (TA0DRA and
TA0DRB).
Low power consumption register 0
POFFCR0
(0x0F74)
RA001
7
6
5
4
3
2
1
0
Bit Symbol
-
-
TC023EN
TC001EN
-
-
TCA1EN
TCA0EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
TC023EN
TC02,03 control
0
1
Disable
Enable
TC001EN
TC00,01 control
0
1
Disable
Enable
TCA1EN
TCA1 control
0
1
Disable
Enable
TCA0EN
TCA0 control
0
1
Disable
Enable
Page 133
13. 16-bit Timer Counter (TCA)
13.2 Control
TMP89FM46
Timer counter A0 mode register
TA0MOD
(0x0031)
7
6
5
4
Bit Symbol
TA0DBE
TA0TED
TA0MCAP
TA0METT
Read/Write
R/W
R/W
R/W
After reset
1
0
0
3
2
TA0CK
0
TA0M
R/W
0
1
R/W
0
TA0DBE
Double buffer control
0
1
Disable the double buffer
Enable the double buffer
TA0TED
External trigger input selection
0
1
Rising edge/H level
Falling edge/L level
TA0MCAP
Pulse width measurement mode
control
0
1
Double edge capture
Single edge capture
TA0METT
External trigger timer mode control
0
1
Trigger start
Trigger start & stop
0
0
0
NORMAL 1/2 or IDLE 1/2 mode
TA0CK
TA0M
Timer counter 1 source clock
selection
Timer counter 1 operation mode
selection
SLOW1/2 or SLEEP1
mode
SYSCR1<DV9CK>
="0"
SYSCR1<DV9CK>
="1"
00
fcgck/210
fs/23
fs/23
01
fcgck/26
fcgck/26
-
10
fcgck/22
fcgck/22
-
11
fcgck/2
fcgck/2
-
000
Timer mode
001
Timer mode
010
Event counter mode
011
PPG output mode (Software start)
100
External trigger timer mode
101
Window mode
110
Pulse width measurement mode
111
Reserved
Note 1: fcgck, Gear clock [Hz]; fs, Low-frequency clock [Hz]
Note 2: Set TA0MOD in the stopped state (TA0CR<TA0S>="0"). Writing to TA0MOD is invalid during the operation
(TA0CR<TA0S>="1").
RA001
Page 134
TMP89FM46
Timer counter A0 control register
TA0CR
(0x0032)
7
6
Bit Symbol
TA0OVE
TA0TFF
Read/Write
R/W
R/W
After reset
0
1
5
4
Overflow interrupt control
TA0TFF
Timer F/F control
TA0NC
Noise canceller sampling interval
setting
2
1
0
-
-
TA0CAP
TA0MPPG
TA0S
R
R
R/W
R/W
0
0
0
0
TA0NC
R/W
0
0
0
TA0OVE
3
1
0
1
Generate no INTTA0 interrupt request when the counter overflow
occurs.
Generate an INTTA0 interrupt request when the counter overflow
occurs.
Clear
Set
NORMAL 1/2 or IDLE 1/2 mode
SLOW1/2 or SLEEP1 mode
00
No noise canceller
No noise canceller
01
fcgck/2
-
10
fcgck/22
-
11
8
fcgck/2
TA0ACAP
Auto capture function
0
1
TA0MPPG
PPG output control
0
1
Continuous
One-shot
Timer counter A start control
0
1
Stop & counter clear
Start
TA0S
Disable the auto capture
Enable the auto capture
fs/2
Note 1: The auto capture can be used only in the timer, event counter, external trigger timer and window modes.
Note 2: Set TA0TFF, TA0OVE and TA0NC in the stopped state (TA0S="0"). Writing is invalid during the operation (TA0S="1").
Note 3: When the STOP mode is started, the start control (TA0S) is automatically cleared to "0" and the timer stops. Set TA0S
again to use the timer counter after the release of the STOP mode.
Note 4: When a read instruction is executed on TA0CR, bits 3 and 2 are read as "0".
Note 5: Do not set TA0NC to "01" or "10" when the SLOW 1/2 or SLEEP 1 mode is used. Setting TA0NC to "01" or "10" stops the
noise canceller and no signal is input to the timer.
RA001
Page 135
13. 16-bit Timer Counter (TCA)
13.2 Control
TMP89FM46
Timer counter A0 status register
TA0SR
(0x0033)
7
6
5
4
3
2
1
0
Bit Symbol
TA0OVF
-
-
-
-
-
TA0CPFA
TA0CPFB
Read/Write
R
R
R
R
R
R
R
R
After reset
0
0
0
0
0
0
0
0
TA0OVF
Overflow flag
TA0CPFA
Capture completion flag A
TA0CPFB
Capture completion flag B
0
1
No overflow has occurred.
At least an overflow has occurred.
0
1
No capture operation has been executed.
At least a pulse width capture has been executed in the double-edge
capture.
0
1
No capture operation has been executed.
At least a capture operation has been executed in the single-edge capture.
At least a pulse duty width capture has been executed in the doubleedge capture.
Note 1: TA0OVF, TA0CPFA and TA0CPFB are cleared to "0" automatically after TA0SR is read. Writing to TA0SR is invalid.
Note 2: When a read instruction is executed on TA0SR, bits 6 to 2 are read as "0".
Timer counter A0 register AH
TA0DRAH
(0x002E)
15
14
13
12
Bit Symbol
Read/Write
After reset
11
10
9
8
1
1
1
1
3
2
1
0
1
1
1
1
11
10
9
8
1
1
1
1
3
2
1
0
1
1
1
1
TA0DRAH
R/W
1
1
1
1
6
5
4
Timer counter A0 register AL
TA0DRAL
(0x002D)
7
Bit Symbol
TA0DRAL
Read/Write
After reset
R/W
1
1
1
1
14
13
12
Timer counter A0 register BH
TA0DRBH
(0x0030)
15
Bit Symbol
TA0DRBH
Read/Write
After reset
R/W
1
1
1
1
6
5
4
Timer counter A0 register BL
TA0DRBL
(0x002F)
7
Bit Symbol
TA0DRBL
Read/Write
After reset
R/W
1
1
1
1
Note 1: When a write instruction is executed on TA0DRAL (TA0DRBL), the set value does not become effective immediately, but is temporarily stored in the temporary buffer. Subsequently, when a write instruction is executed on the
higher-level register, TA0DRAH (TA0DRBH), the 16-bit set values are collectively stored in the double buffer or
TA0DRAL/H. When setting data to the timer counter A0 register, be sure to write the data into the lower level register and the higher level in this order.
Note 2: The timer counter A0 register is not writable in the pulse width measurement mode.
RA001
Page 136
TMP89FM46
13.3 Low Power Consumption Function
Timer counter A0 has the low power consumption register (POFFCR0) that saves power consumption when the
timer is not used.
Setting POFFCR0<TCA0EN> to "0" disables the basic clock supply to timer counter A0 to save power. Note that
this makes the timer unusable. Setting POFFCR0<TCA0EN> to "1" enables the basic clock supply to timer counter
A0 and allows the timer to operate.
After reset, POFFCR0<TCA0EN> is initialized to "0", and this makes the timer unusable. When using the timer
for the first time, be sure to set POFFCR0<TCA0EN> to "1" in the initial setting of the program (before the timer
control register is operated).
Do not change POFFCR0<TCA0EN> to "0" during the timer operation. Otherwise timer counter A0 may operate
unexpectedly.
RA001
Page 137
13. 16-bit Timer Counter (TCA)
13.4 Timer Function
TMP89FM46
13.4 Timer Function
Timer counter A0 has six types of operation modes; timer, external trigger timer, event counter, window, pulse
width measurement and programmable pulse generate (PPG) output modes.
13.4.1 Timer mode
In the timer mode, the up-counter counts up using the internal clock, and interrupts can be generated regularly at specified times.
13.4.1.1 Setting
Setting the operation mode selection TA0MOD<TA0M> to "000" or "001" activates the timer mode.
Select the source clock at TA0MOD<TA0CK>.
Setting TA0CR<TA0S> to "1" starts the timer operation. After the timer is started, writing to TA0MOD
and TA0CR<TA0OVE> becomes invalid. Be sure to complete the required mode settings before starting
the timer.
Table 13-3 Timer Mode Resolution and Maximum Time Setting
Source clock [Hz]
TA0MOD
<TA0CK>
Resolution
Maximum time setting
NORMAL 1/2 or IDLE 1/2 mode
SLOW1/2 or
SLEEP1 mode
fcgck=10MHz
fs=32.768KHz
fcgck=10MHz
fs=32.768KHz
fs/23
fs/23
102.4µs
244.1us
6.7s
16s
fcgck/26
fcgck/26
-
6.4µs
-
419.4ms
-
10
fcgck/22
fcgck/22
-
400ns
-
26.2ms
-
11
fcgck/2
fcgck/2
-
200ns
-
13.1ms
-
SYSCR1<DV9CK>
= "0"
SYSCR1<DV9CK>
= "1"
00
fcgck/210
01
13.4.1.2 Operation
Setting TA0CR<TA0S> to "1" allows the 16-bit up counter to increment based on the selected internal
source clock. When a match between the up-counter value and the value set to timer register A
(TA0DRA) is detected, an INTTA0 interrupt request is generated and the up counter is cleared to
"0000H". After being cleared, the up counter continues counting. Setting TA0CR<TA0S> to "0" during
the timer operation causes the up counter to stop counting and be cleared to "0000H".
13.4.1.3 Auto capture
The latest contents of the up counter can be taken into timer register B (TA0DRB) by setting
TA0CR<TA0ACAP> to "1" (auto capture function). When TA0CR<TA0ACAP> is "1", the current contents of the up counter can be read by reading TA0DRBL. TA0DRBH is loaded at the same time as
TA0DRBL is read. Therefore, when reading the captured value, be sure to read TA0DRBL and
TA0DRBH in this order. (The capture time is the timing when TA0DRBL is read.) The auto capture function can be used whether the timer is operating or stopped. When the timer is stopped, TA0DRBL is read
as "00H". TA0DRBH keeps the captured value after the timer stops, but it is cleared to "00H" when
TA0DRBL is read while the timer is stopped.
If the timer is started with TA0CR<TA0ACAP> written to "1", the auto capture is enabled immediately
after the timer is started.
Note 1: The value set to TA0CR<TA0ACAP> cannot be changed at the same time as TA0CR<TA0S> is
rewritten from "1" to "0". (This setting is invalid.)
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TMP89FM46
13.4.1.4 Register buffer configuration
(1)
Temporary buffer
The TMP89FM46 contains an 8-bit temporary buffer. When a write instruction is executed on
TA0DRAL, the data is first stored into this temporary buffer, whether the double buffer is enabled or
disabled. Subsequently, when a write instruction is executed on TA0DRAH, the set value is stored
into the double buffer or TA0DRAH. At the same time, the set value in the temporary buffer is stored
into the double buffer or TA0DRAL. (This structure is designed to enable the set values of the lowerlevel and higher-level registers simultaneously.) Therefore, when setting data to TA0DRA, be sure to
write the data into TA0DRAL and TA0DRAH in this order.
See Figure 13-1 for the temporary buffer configuration.
(2)
Double buffer
In the TMP89FM46, the double buffer can be used by setting TA0CR<TA0DBF>. Setting
TA0CR<TA0DBF> to "0" disables the double buffer. Setting TA0CR<TA0DBF> to "1" enables the
double buffer.
See Figure 13-1 for the double buffer configuration.
- When the double buffer is enabled
When a write instruction is executed on TA0DRAH during the timer operation, the set
value is first stored into the double buffer, and TA0DRAH/L are not updated immediately.
TA0DRAH/L compare the up counter value to the last set values. If the values are matched,
an INTTCA0 interrupt request is generated and the double buffer set value is stored in
TA0DRAH/L. Subsequently, the match detection is executed using a new set value.
When a read instruction is executed on TA0DRAH/L, the double buffer value (the last set
value) is read, rather than the TA0DRAH/L values (the current effective values).
When a write instruction is executed on TA0DRAH/L while the timer is stopped, the set
value is immediately stored into both the double buffer and TA0DRAH/L.
- When the double buffer is disabled
When a write instruction is executed on TA0DRAH during the timer operation, the set
value is immediately stored into TA0DRAH/L. Subsequently, the match detection is executed using a new set value.
If the values set to TA0DRAH/L are smaller than the up counter value, the match detection
is executed using a new set value after the up counter overflows. Therefore, the interrupt
request interval may be longer than the selected time. If that is a problem, enable the double
buffer.
When a write instruction is executed on TA0DRAH/L while the timer is stopped, the set
value is immediately stored into TA0DRAH/L.
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13. 16-bit Timer Counter (TCA)
13.4 Timer Function
TMP89FM46
Timer stop
Timer start
TA0CR<TA0S>
TA0MOD<TA0DBE>
Source clock
rs
mn
Counter
0
1
2
3
4
mn-1
0
1
2
3
rs-1
0
1
Counter clear
Write to TA0DRAL
Write n
Write to TA0DRAH
Temporary buffer
(8 bits)
Write r
n
s
n
s
Match detection
TA0DRAH
Match detection
m
INTTCA interrupt request
0
Write s
Write m
TA0DRAL
2
Counter clear
r
Reflected by writing to TA0DRAH
Reflected by writing to TA0DRAH
When the double buffer is disabled (TA0MOD<TA0DBE>=”0”)
Timer start
TA0CR<TA0S>
TA0MOD<TA0DBE>
Source clock
mn
mn
Counter
0
1
2
3
4
mn-1
0
1
2
3
mn-1
Write n
Write to TA0DRAH
Temporary buffer
(8 bits)
Double buffer
(16 bits)
TA0DRAL
INTTCA interrupt request
Write m
Write r
n
s
mn
rs
s
n
Match detection
Match detection
r
m
Reflected at the same time as data
is written into TA0DRAH while
the timer is stopped
Reflected by
an interrupt
When the double buffer is enabled (TA0MOD<TA0DBE>=”1”)
Figure 13-2 Timer Mode Timing Chart
RA001
rs-1
Write s
Match detection
TA0DRAH
1
Counter clear
Counter clear
Write to TA0DRAL
rs
0
Page 140
0
1
TMP89FM46
Timer stop
Timer start
TA0CR<TA0S>
TA0MOD<TA0ACAP>
Source clock
Counter
0000 0001 0002
00
TA0DRBL
01
02
18FD 18FE 18FF 1900 1901 1902 1903 1904 1905 1906 0000
FD
FE
FF
00
01
02
03
04
05
06
00
TA0DRBH is updated when TA0DRBL is read
TA0DRBH
00
18
00
Read TA0DRBL
Read TA0DRBH
Read Read
value value
00H 00H
Read
value
FEH
Read
value
18H
Read
value
18H
Figure 13-3 Timer Mode Timing Chart (Auto Capture)
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Read Read
value value
00H 00H
13. 16-bit Timer Counter (TCA)
13.4 Timer Function
TMP89FM46
13.4.2 External trigger timer mode
In the external trigger timer mode, the up counter starts counting when it is triggered by the input to the
TCA0 pin.
13.4.2.1 Setting
Setting the operation mode selection TA0MOD<TA0M> to "100" activates the external trigger timer
mode. Select the source clock at TA0MOD<TA0CK>.
Select the trigger edge at the trigger edge input selection TA0MOD<TA0TED>. Setting
TA0MOD<TA0TED> to "0" selects the rising edge, and setting it to "1" selects the falling edge.
Note that this mode uses the TA0 input pin, and the TCA0 pin must be set to the input mode beforehand
in port settings.
The operation is started by setting TA0CR<TA0S> to "1". After the timer is started, writing to
TA0MOD and TA0CR<TA0OVE> is disabled. Be sure to complete the required mode settings before
starting the timer.
13.4.2.2 Operation
After the timer is started, when the selected trigger edge is input to the TCA0 pin, the up counter increments according to the selected source clock. When a match between the up counter value and the value
set to timer register A (TA0DRA) is detected, an INTTA0 interrupt request is generated and the up counter
is cleared to "0000H". After being cleared, the up counter continues counting.
When TA0MOD<TA0METT> is "1" and the edge opposite to the selected trigger edge is detected, the
up counter stops counting and is cleared to "0000H". Subsequently, when the selected trigger edge is
detected, the up counter restarts counting. In this mode, an interrupt request can be generated by detecting
that the input pulse exceeds a certain pulse width. If TA0MOD<TA0METT> is "0", the detection of the
selected edge and the opposite edge is ignored during the period from the detection of the specified trigger
edge and the start of counting through until the match detection.
Setting TA0CR<TA0S> to "0" during the timer operation causes the up counter to stop counting and be
cleared to "0000H".
13.4.2.3 Auto capture
Refer to "13.4.1.3 Auto capture".
13.4.2.4 Register buffer configuration
Refer to "13.4.1.4 Register buffer configuration".
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TMP89FM46
Timer stop
Timer start
TA0CR<TA0S>
TA0MOD<TA0TED>
Counting
start
Edge is invalid
during counting
Edge is invalid
during counting
Counting
start
TA0 pin input
Source clock
mn
Counter
Write to TA0DRAL
Write to TA0DRAH
TA0DRAL
0
1
2
3
mn-1
rs
0
1
2
Counter
clear
Write n
3
INTTCA interrupt request
0
Write m
1
2
0
Counter
clear
Write s
Write r
s
n
Match detection
TA0DRAH
rs-1
Match detection
r
m
Reflected by writing to TA0DRAH
Reflected by writing to TA0DRAH
When the trigger is started (TA0MOD<TA0METT>=”0”)
Timer start
Timer stop
TA0CR<TA0S>
TA0MOD<TA0TED>
Counting
start
Counting
start
Counting Counting
stop
start
TA0 pin input
Source clock
mn
Counter
Write to TA0DRAL
Write to TA0DRAH
TA0DRAL
0
1
2
3
mn-1
rs
0
Counter
clear
Write n
1
2
0
Counter
clear
Write m
INTTCA interrupt request
n
Write s
0
1
Counter
clear
s
m
Match detection
r
Reflected by writing to TA0DRAH
When the trigger is started and stopped (TA0MOD<TA0METT>=”1”)
Figure 13-4 External Trigger Timer Timing Chart
RA001
rs-1
Write r
Match detection
TA0DRAH
1
Page 143
Reflected by writing
to TA0DRAH
0
13. 16-bit Timer Counter (TCA)
13.4 Timer Function
TMP89FM46
13.4.3 Event counter mode
In the event counter mode, the up counter counts up at the edge of the input to the TCA0 pin.
13.4.3.1 Setting
Setting the operation mode selection TA0MOD<TA0M> to "010" activates the event counter mode.
Set the trigger edge at the external trigger input selection TA0MOD<TA0TED>. Setting
TA0MOD<TA0TED> to "0" selects the rising edge, and setting it to "1" selects the falling edge for counting up.
Note that this mode uses the TA0 input pin, and the TCA0 pin must be set to the input mode beforehand
in port settings.
The operation is started by setting TA0CR<TA0S> to "1". After the timer is started, writing to
TA0MOD and TA0CR<TA0OVE> is disabled. Be sure to complete the required mode settings before
starting the timer.
13.4.3.2 Operation
After the event counter mode is started, when the selected trigger edge is input to the TCA0 pin, the up
counter increments.
When a match between the up counter value and the value set to timer register A (TA0DRA) is detected,
an INTTA0 interrupt request is generated and the up counter is cleared to "0000H". After being cleared,
the up counter continues counting and counts up at each edge of the input to the TCA0 pin. Setting
TA0CR<TA0S> to "0" during the operation causes the up counter to stop counting and be cleared to
"0000H".
The maximum frequency to be supplied is fcgck/2 [Hz] (in the NORMAL 1/2 or IDLE 1/2 mode) or fs/
2 [Hz] (in the SLOW 1/2 or SLEEP 1 mode), and a pulse width of two machine cycles or more is required
at both the "H" and "L" levels.
13.4.3.3 Auto capture
Refer to "13.4.1.3 Auto capture".
13.4.3.4 Register buffer configuration
Refer to "13.4.1.4 Register buffer configuration".
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TMP89FM46
Timer start
Timer stop
TA0CR<TA0S>
TA0 pin input
rs
mn
Counter
0
1
2
3
4
mn-1
0
1
2
3
rs-1
Write to TA0DRAL
Write to TA0DRAH
TA0DRAL
Write n
INTTCA interrupt request
1
2
0
Write s
Write m
Write r
s
n
Match detection
TA0DRAH
0
Counter clear
Counter clear
Match detection
r
m
Reflected by writing to TA0DRAH
Reflected by writing to TA0DRAH
When the rising edge is selected (TA0MOD<TA0TED>=”0”)
Figure 13-5 Event Count Mode Timing Chart
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13. 16-bit Timer Counter (TCA)
13.4 Timer Function
TMP89FM46
13.4.4 Window mode
In the window mode, the up counter counts up at the rising edge of the pulse that is logical anded product of
the input pulse to the TCA0 pin (window pulse) and the internal clock.
13.4.4.1 Setting
Setting the operation mode selection TA0MOD<TA0M> to "101" activates the window mode. Select
the source clock at TA0MOD<TA0CK>.
Select the window pulse level at the trigger edge input selection TA0MOD<TA0TED>. Setting
TA0MOD<TA0TED> to "0" enables counting up as long as the window pulse is at the "H" level. Setting
TA0MOD<TA0TED> to "1" enables counting up as long as the window pulse is at the "L" level.
Note that this mode uses the TA0 input pin, and the TCA0 pin must be set to the input mode beforehand
in port settings.
The operation is started by setting TA0CR<TA0S> to "1". After the timer is started, writing to
TA0MOD and TA0CR<TA0OVE> is disabled. Be sure to complete the required mode settings before
starting the timer.
13.4.4.2 Operation
After the operation is started, when the level selected at TA0MOD<TA0TED> is input to the TCA0 pin,
the up counter increments according to the source clock selected at TA0MOD<TA0CK>. When a match
between the up counter value and the value set to timer register A (TA0DRA) is detected, an INTTA0
interrupt request is generated and the up counter is cleared to "0000H". After being cleared, the up counter
restarts counting.
The maximum frequency to be supplied must be slow enough for the program to analyze the count
value. Define a frequency pulse that is sufficiently lower than the programmed internal source clock.
Setting TA0CR<TA0S> to "0" during the timer operation causes the up counter to stop counting and be
cleared to "0000H".
13.4.4.3 Auto capture
Refer to "13.4.1.3 Auto capture".
13.4.4.4 Register buffer configuration
Refer to "13.4.1.4 Register buffer configuration".
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TMP89FM46
Timer stop
Timer start
TA0CR<TA0S>
TA0MOD<TA0TED>
Count in the period of H level
Count in the period of H level
TA0 pin input
Source clock
mn
Counter
0
1
2
3
4
5
6
mn-1
0
1
2
Counter clear
Write to TA0DRAL
Write to TA0DRAH
Write n
Write m
TA0DRAL
n
TA0DRAH
m
Match detection
INTTCA interrupt request
Reflected by writing to TA0DRAH
During the H-level counting (TA0MOD<TA0TED>=”0”)
Figure 13-6 Window Mode Timing Chart
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3
4
5
6
0
13. 16-bit Timer Counter (TCA)
13.4 Timer Function
TMP89FM46
13.4.5 Pulse width measurement mode
In the pulse width measurement mode, the up counter starts counting at the rising/falling edge(s) of the input
to the TCA0 pin and measures the input pulse width based on the internal clock.
13.4.5.1 Setting
Setting the operation mode selection TA0MOD<TA0M> to "110" activates the pulse width measurement mode. Select the source clock at TA0MOD<TA0CK>.
Select the trigger edge at the trigger edge input selection TA0MOD<TA0TED>. Setting
TA0MOD<TA0TED> to "0" selects the rising edge, and setting it to "1" selects the falling edge as a trigger to start the capture.
The operation after capturing is determined by the pulse width measurement mode control
TA0MOD<TA0MCAP>. Setting TA0MOD<TA0MCAP> to "0" selects the double-edge capture. Setting
TA0MOD<TA0MCAP> to "1" selects the single-edge capture.
The operation to be executed in case of an overflow of the up counter can be selected at the overflow
interrupt control TA0CR<TA0OVE>. Setting TA0OVE to "1" makes an INTTA0 interrupt request occur
in case of an overflow. Setting TA0OVE to "0" makes no INTTA0 interrupt request occur in case of an
overflow.
Note that this mode uses the TA0 input pin, and the TCA0 pin must be set to the input mode beforehand
in port settings.
The operation is started by setting TA0CR<TA0S> to "1". After the timer is started, writing to
TA0MOD and TA0CR<TA0OVE> is disabled. Be sure to complete the required mode settings before
starting the timer.
13.4.5.2 Operation
After the timer is started, when the selected trigger edge (start edge) is input to the TCA0 pin, the up
counter increments according to the selected source clock. Subsequently, when the edge opposite to the
selected edge is detected, the up counter value is captured into TA0DRB, an INTTA0 interrupt request is
generated, and TA0SR<TA0CPFB> is set to "1". Depending on the TA0MOD<TA0MCAP> setting, the
operation differs as follows:
• Double-edge capture (When TA0MOD<TA0MCAP> is "0")
The up counter continues counting up after the edge opposite to the selected edge is detected.
Subsequently, when the selected trigger edge is input, the up counter value is captured into
TA0DRA, an INTTA0 interrupt request is generated, and TA0SR<TA0CPFA> is set to "1". At
this time, the up counter is cleared to "0000H".
• Single-edge capture (When TA0MOD<TA0MCAP> is "1")
The up counter stops counting up and is cleared to "0000H" when the edge opposite to the
selected edge is detected. Subsequently, when the start edge is input, the up counter restarts
increment.
When the up counter overflows during capturing, the overflow flag TA0SR<TA0OVF> is set to "1". At
this time, an INTTA0 interrupt request occurs if the overflow interrupt control TA0CR<TA0OVE> is set
to "1".
The capture completion flags (TA0SR<TA0CPFA, TA0CPFB>
(TA0SR<TA0OVF>) are cleared to "0" automatically when TA0SR is read.
RA001
Page 148
and
the
overflow
flag
TMP89FM46
The captured value must be read from TA0DRB (and also from TA0DRA for the double-edge capture)
before the next trigger edge is detected. If the captured value is not read, it becomes undefined. TA0DRA
and TA0DRB must be read by using a 16-bit access instruction.
Setting TA0CR<TA0S> to "0" during the timer operation causes the up counter to stop counting and be
cleared to "0000H".
Note 1: After the timer is started, if the edge opposite to the selected trigger edge is detected first, no capture
is executed and no INTTA0 interrupt request occurs. In this case, the capture starts when the selected
trigger edge is detected next.
Timer stop
Timer start
TA0CR<TA0S>
TA0MOD<TA0TED>
TA0 pin input
Count start
Source clock
mn
Counter
0
1
2
3
4
mn-1
0
1
2
3
Counter clear
TA0DRBH, L
0
Counter clear
mn
0
After the timer is started, if the falling edge
is detected first, no interrupt occurs.
INTTCA interrupt request
Single-edge capture (TA0MOD<TAMCAP>=”0”)
Timer stop
Timer start
TA0CR<TA0S>
TA0MOD<TA0TED>
TA0 pin input
Count start
Source clock
st
Counter
0
1
2
3
4
mn-1 mn mn+1
st-1
0
1
2
0
Counter clear Counter clear
TA0DRBH, L
0
TA0DRAH, L
0
INTTCA interrupt request
mn
st
After the timer is started, if the falling edge
is detected first, no interrupt occurs.
Double-edge capture (TA0MOD<TAMCAP>=”1”)
Figure 13-7 Pulse Width Measurement Mode Timing Chart
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13. 16-bit Timer Counter (TCA)
13.4 Timer Function
TMP89FM46
13.4.6 Programmable pulse generate (PPG) mode
In the PPG output mode, an arbitrary duty pulse is output by two timer registers.
13.4.6.1 Setting
Setting the operation mode selection TA0MOD<TA0M> to "011" activates the PPG output mode.
Select the source clock at TA0MOD<TA0CK>. Select continuous or one-shot PPG output at
TA0CR<TA0MPPG>.
Set the PPG output cycle at TA0DRA and set the time until the output is reversed first at TA0DRB. Be
sure to set register values so that TA0DRA is larger than TA0DRB.
Note that this mode uses the PPGA0 pin. the PPGA0 pin must be set to the output mode beforehand in
port settings.
Set the initial state of the PPGA0 pin at the timer flip-flop TA0CR<TA0TFF>. Setting
TA0CR<TA0TFF> to "1" selects the "H" level as the initial state of the PPGA0 pin. Setting
TA0CR<TA0TFF> to "0" selects the "L" level as the initial state of the PPGA0 pin.
The operation is started by setting TA0CR<TA0S> to "1". After the timer is started, writing to
TA0MOD and TA0CR<TA0OVE, TA0TFF> is disabled. Be sure to complete the required mode settings
before starting the timer.
13.4.6.2 Operation
after the timer is started, the up counter increments .
When a match between the up counter value and the value set to timer register B (TA0DRB) is detected,
the PPGA0 pin is changed to the "H" level if TA0CR<TA0TFF> is "0", or the PPGA0 pin is changed to the
"L" level if TA0CR<TA0TFF> is "1".
Subsequently, the up counter continues counting. When a match between the up counter value and the
value set to timer register A (TA0DRA) is detected, the PPGA0 pin is changed to the "L" level if
TA0CR<TA0TEFF> is "0", or the PPGA0 pin is changed to the "H" level if TA0CR<TA0TFF> is "1". At
this time, an INTTA0 interrupt request occurs. If the PPG output control TA0CR<TA0MPPG> is set to
"1" (one-shot), TA0CR<TA0S> is automatically cleared to "0" and the timer stops.
If TA0CR<TA0MPPG> is set to "0" (continuous), the up counter is cleared to "0000H" and continues
counting and PPG output. When TA0CR<TA0S> is set to "0" (including the auto stop by the one-shot
operation) during the PPG output, the PPGA0 pin returns to the level set in TA0CR<TA0TFF>.
TA0CR<TA0MPPG> can be changed during the operation. Changing TA0CR<TA0MPPG> from "1" to
"0" during the operation cancels the one-shot operation and enables the continuous operation. Changing
TA0CR<TA0MPPG> from "0" to "1" during the operation clears TA0CR<TA0S> to "0" and stops the
timer automatically after the current pulse output is completed.
Timer registers A and B can be set to the double buffer. Setting TA0CR<TA0DBF> to "1" enables the
double buffer. When the values set to TA0DRA and TA0DRB are changed during the PPG output with the
double buffer enabled, the writing to TA0DRA and TA0DRB will not immediately become effective but
will become effective when a match between TA0DRA and the up counter is detected. If the double buffer
is disabled, the writing to TA0DRA and TA0DRB will become effective immediately. If the written value
is smaller than the up counter value, the up counter overflows. After a cycle, the counter match process is
executed to reverse the output.
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TMP89FM46
13.4.6.3 Register buffer configuration
(1)
Temporary buffer
The TMP89FM46 contains an 8-bit temporary buffer. When a write instruction is executed on
TA0DRAL (TA0DRBL), the data is first stored into this temporary buffer, whether the double buffer
is enabled or disabled. Subsequently, when a write instruction is executed on TA0DRAH
(TA0DRBH), the set value is stored into the double buffer or TA0DRAH (TA0DRBH). At the same
time, the set value in the temporary buffer is stored into the double buffer or TA0DRAL
(TA0DRBL). (This structure is designed to enable the set values of the lower-level register and the
higher-level register simultaneously.) Therefore, when setting data to TA0DRA (TA0DRB), be sure
to write the data into TA0DRAL and TA0DRAH (TA0DRBL and TA0DRBH) in this order.
See Figure 13-1 for the temporary buffer configuration.
(2)
Double buffer
In the TMP89FM46, the double buffer can be used by setting TA0CR<TA0DBF>. Setting
TA0CR<TA0DBF> to "0" disables the double buffer. Setting TA0CR<TA0DBF> to "1" enables the
double buffer.
See Figure 13-1 for the double buffer configuration.
- When the double buffer is enabled
When a write instruction is executed on TA0DRAH (TA0DRBH) during the timer operation, the set value is first stored into the double buffer, and TA0DRAH/L are not updated
immediately. TA0DRAH/L (TA0DRBH/L) compare the last set values to the counter value.
If a match is detected, an INTTCA0 interrupt request is generated and the double buffer set
value is stored into TA0DRAH/L (TA0DRBH/L). Subsequently, the match detection is executed using a new set value.
When a read instruction is executed on TA0DRAH/L (TA0DRBH/L), the double buffer
value (the last set value) is read, not the TA0DRAH/L (TA0DRBH/L) values (the current
effective values).
When a write instruction is executed on TA0DRAH/L (TA0DRBH/L) while the timer is
stopped, the set value is immediately stored into both the double buffer and TA0DRAH/L
(TA0DRBH/L).
- When the double buffer is disabled
When a write instruction is executed on TA0DRAH (TA0DRBH) during the timer operation, the set value is immediately stored in TA0DRAH/L (TA0DRBH/L). Subsequently, the
match detection is executed using a new set value.
If the values set to TA0DRAH/L (TA0DRBH/L) are smaller than the up counter value, the
up counter overflows and the match detection is executed using a new set value. As a result,
the output pulse width may be longer than the set time. If that is a problem, enable the double
buffer.
When a write instruction is executed on TA0DRAH/L (TA0DRBH/L) while the timer is
stopped, the set value is immediately stored into TA0DRAH/L (TA0DRBH/L).
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13. 16-bit Timer Counter (TCA)
13.4 Timer Function
TMP89FM46
Timer start
Timer stop
TA0CR<TA0S>
TA0MOD<TA0TFF>
Source clock
n
Counter
Write to TA0DRAL, H
Write to TA0DRBL, H
0
1
2
m
Write n
n
TA0DRBL, H
m
s
0
1
2
r
r+1
Counter
clear
Write s
Write m
TA0DRAL, H
m+1
0
1
r
r+1
0
Counter
clear
Write r
s
Match detection
Match detection
Match detection
r Match detection
Match detection
PPG0 pin output
INTTCA interrupt request
Becomes the level set at TA0TFF
when the timer is stopped
Reflected by an
interrupt request
m
(Duty pulse)
r
(Duty pulse)
n (1 cycle)
s (1 cycle)
Continuous (TA0CR<TA0MPPG>=”0”)
Double buffer (TA0MOD<TA0DBE>=”1”)
Timer start
Timer stops
automatically
TA0CR<TA0S>
TA0MOD<TA0TFF>
Source clock
n
Counter
Write to TA0DRAL, H
Write to TA0DRBL, H
0
1
2
m
m+1
0
Counter
clear
Write n
Write m
TA0DRAL, H
n
TA0DRBL, H
m
Match detection
Match detection
PPG0 pin output
INTTCA interrupt request
Becomes the level set at TA0TFF
when the timer is stopped
Returns to the level
set at TA0TFF
m
(Duty pulse)
n (1 cycle)
One-shot (TA0CR<TA0MPPG>=”1”)
Figure 13-8 PPG Mode Timing Chart
RA001
Page 152
Returns to the level
set at TA0TFF
r
(Duty pulse)
TMP89FM46
13.5 Noise Canceller
The digital noise canceller can be used in the operation modes that use the TCA0 pin.
13.5.1 Setting
When the digital noise canceller is used, the input level is sampled at the sampling intervals set at
TA0CR<TA0NC>. When the same level is detected three times consecutively, the level of the input to the
timer is changed.
Setting TA0CR<TA0NC> to any values than "00" allows the noise canceller to start operation, regardless of
the TA0CR<TA0S> value.
When the noise canceller is used, allow the timer to start after a period of time that is equal to four times the
sampling interval after TA0CR<TA0NC> is set has elapsed. This stabilizes the input signal.
Set TA0CR<TA0NC> while the timer is stopped (TA0CR<TA0S> = "0"). When TA0CR<TA0S> is "1",
writing is ignored.
In the SLOW 1/2 or SLEEP 1 mode, setting TA0CR<TA0NC> to "11" selects fs/2 as the source clock for the
operation. Setting TA0CR<TA0NC> to "00" disables the noise canceller. Setting TA0CR<TA0NC> to "01" or
"10" disables the TCA0 pin input.
Table 13-4 Noise Cancel Time ( fcgck = 10 [MHz] )
RA001
TA0NC
Sampling interval
Time removed as noise
Time regarded as signal
00
None
-
-
01
200 ns (2/fcgck)
600 ns or less
800 ns or more
10
400 ns (4/fcgck)
1.2 µs or less
1.6 µs or more
11
25.6 µs (256/fcgck)
76.8 µs or less
102.4 µs or more
Page 153
13. 16-bit Timer Counter (TCA)
13.5 Noise Canceller
RA001
TMP89FM46
Page 154
TMP89FM46
14. 8-bit Timer Counter (TC0)
The TMP89FM46 contains 4 channels of high-performance 8-bit timer counters (TC0). Each timer can be used for
time measurement and pulse output with a prescribed width. Two 8-bit timer counters are cascadable to form a 16-bit
timer.
This chapter describes 2 channels of 8-bit timer counters 00 and 01. For 8-bit timer counters 02 and 03, replace the
SFR addresses and pin names as shown in Table 14-1 and Table 14-2.
Table 14-1 SFR Address Assignment
Timer counter 00
16-bit mode
T0xREG
(Address)
T0xPWM
(Address)
T0xMOD
(Address)
Lower
T00REG
(0x0026)
T00PWM
(0x0028)
T00MOD
(0x002A)
Timer counter 01
Higher
T01REG
(0x0027)
T01PWM
(0x0029)
T01MOD
(0x002B)
Timer counter 02
Lower
T02REG
(0x0F88)
T02PWM
(0x0F8A)
T02MOD
(0x0F8C)
T03REG
(0x0F89)
T03PWM
(0x0F8B)
T03MOD
(0x0F8D)
Timer counter 03
Higher
T0xxCR
(Address)
Low power
consumption
register
T001CR
(0x002C)
POFFCR0
<TC001EN>
T023CR
(0x0F8E)
POFFCR0
<TC023EN>
Table 14-2 Pin Names
RA002
Timer input pin
PWM output pin
PPG output pin
Timer counter 00
TC00 pin
PWM0 pin
PPG0 pin
Timer counter 01
TC01 pin
PWM1 pin
PPG1 pin
Timer counter 02
TC02 pin
PWM2 pin
PPG2 pin
Timer counter 03
TC03 pin
PWM3 pin
PPG3 pin
Page 155
fcgck/211 or fs/24
fcgck/210 or fs/23
fcgck/28
fcgck/26
fcgck/24
fcgck/22
fcgck/2
fc or fs/22
TC01 pin input
2
TCM0
fcgck/211 or fs/24
fcgck/210 or fs/23
fcgck/28
fcgck/26
fcgck/24
fcgck/22
fcgck/2
fc or fs/22
TC00 pin input
2
TFF0
I
A
B
C
D
E
F
G
H
I
A
B
C
D
E
F
G
H
DBE1
T01MOD
2
S0 S1
Y
Y
S0 S1
2
T00MOD
EIN0
EIN1
0
Selector
1
1
Count up
0
Internal bus
Clear
Selector
0
Selector
1
8-bit
PPG mode
0
1
0
S
Y
T001CR
1
Selector
Count up
T01REG
0
Double buffer
Reading and
writing of
T01REG
Timer/event
count modes
8-bit PWM mode
12-bit PWM mode
Counter
Comparator
Comparator
1
Overflow
Selector
T00PWM
1
Double buffer
8-bit up counter
Selector
T00REG
0
Double buffer
Internal bus
TC00RUN
TCK0
TCK1
Figure 14-1 8-bit Timer Counters 00 and 01
TCM1
DBE0
TFF1
Reading and
writing of
T00PWM
TCAS
Page 156
TC01RUN
RA002
OUTAND
Reading and writing
of T00REG
0
Selector
Clear
8-bit up counter
T01PWM
1
Double buffer
Selector
0
Overflow
Comparator
Comparator
1
Reading and
writing of
T01PWM
1
0
0
1
Y
8/16-bit
PPG mode
TCAS
Counter
Timer/event
count modes
S
S
Y
16-bit
PPG mode
8-bit PWM mode
12-bit PWM mode
TCAS
TCAS
DBE1
TFF1
TFF0
F/F
F/F
S
Y
INTT00
interrupt request
INTT01
interrupt request
OUTAND
1
0
PPG1
PWM1
pin output
PPG0
PWM0
pin output
14. 8-bit Timer Counter (TC0)
TMP89FM46
14.1 Configuration
TMP89FM46
14.2 Control
14.2.1 Timer counter 00
The timer counter 00 is controlled by the timer counter 00 mode register (T00MOD) and two 8-bit timer registers (T00REG and T00PWM).
Timer register 00
T00REG
(0x0026)
15
14
13
12
Bit Symbol
T00REG
Read/Write
R/W
After reset
11
10
9
8
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
1
1
1
1
Timer register 00
T00PWM
(0x0028)
Bit Symbol
T00PWM
Read/Write
R/W
After reset
1
1
1
1
Note 1: For the configuration of T00PWM in the 8-bit and 12-bit PWM modes, refer to "14.4.3 8-bit pulse width modulation (PWM)
output mode" and "14.4.7 12-bit pulse width modulation (PWM) output mode".
RA002
Page 157
14. 8-bit Timer Counter (TC0)
TMP89FM46
Timer counter 00 mode register
T00MOD
(0x002A)
7
6
5
4
3
2
1
0
Bit Symbol
TFF0
DBE0
TCK0
EIN0
TCM0
Read/Write
R/W
R/W
R/W
R/W
R/W
After reset
1
1
0
0
0
TFF0
Timer F/F0 control
0
1
Clear
Set
DBE0
Double buffer control
0
1
Disable the double buffer
Enable the double buffer
0
0
0
NORMAL1/2 or IDLE1/2 mode
TCK0
EIN0
TCM0
Operation clock selection
Selection for using external source
clock
SLOW1/2 or SLEEP1
mode
SYSCR1<DV9CK>
= "0"
SYSCR1<DV9CK>
= "1"
000
fcgck/211
fs/24
fs/24
001
fcgck/210
fs/23
fs/23
010
fcgck/28
fcgck/28
-
011
fcgck/26
fcgck/26
-
100
fcgck/24
fcgck/24
-
101
fcgck/2
2
fcgck/2
2
-
110
fcgck/2
fcgck/2
-
111
fcgck
fcgck
fs/22
0
1
Select the internal clock as the source clock.
Select an external clock as the source clock. (the falling edge of the
TC00 pin)
00
8-bit timer/event counter modes
01
8-bit timer/event counter modes
Operation mode selection
10
8-bit pulse width modulation output (PWM) mode
11
8-bit programmable pulse generate (PPG) mode
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Set T00MOD while the timer is stopped. Writing data into T00MOD is invalid during the timer operation.
Note 3: In the 8-bit timer/event modes, the TFF0 setting is invalid. In this mode, when the PWM0 and PPG0 pins are set as the
function output pins in the port setting, the pins always output the "H" level.
Note 4: When EIN0 is set to "1" and the external clock input is selected as the source clock, the TCK0 setting is ignored.
Note 5: When the T001CR<TCAS> bit is "1", timer 00 operates in the 16-bit mode. The T00MOD setting is invalid and timer 00
cannot be used independently in this mode. When the PWM0 and PPG0 pins are set to the function output pins in the port
setting, the pins always output the "H" level.
Note 6: When the 16-bit mode is selected at T001CR<TCAS>, the timer start is controlled at T001CR<T01RUN>. Timer 00 is not
started by writing data into T001CR<T00RUN>.
RA002
Page 158
TMP89FM46
14.2.2 Timer counter 01
Timer counter 01 is controlled by timer counter 01 mode register (T01MOD) and two 8-bit timer registers
(T01REG and T01PWM).
Timer register 01
T01REG
(0x0027)
15
14
13
12
Bit Symbol
T01REG
Read/Write
R/W
After reset
11
10
9
8
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
1
1
1
1
Timer register 01
T01PWM
(0x0029)
Bit Symbol
T01PWM
Read/Write
R/W
After reset
1
1
1
1
Note 1: For the configuration of T00PWM in the 8-bit and 12-bit PWM modes, refer to "14.4.3 8-bit pulse width modulation (PWM)
output mode" and "14.4.7 12-bit pulse width modulation (PWM) output mode".
RA002
Page 159
14. 8-bit Timer Counter (TC0)
TMP89FM46
Timer counter 01 mode register
T01MOD
(0x002B)
7
6
5
4
3
2
1
0
Bit Symbol
TFF1
DBE1
TCK1
EIN1
TCM1
Read/Write
R/W
R/W
R/W
R/W
R/W
After reset
1
1
0
0
0
TFF1
Timer F/F1 control
0
1
Clear
Set
DBE1
Double buffer control
0
1
Disable the double buffer
Enable the double buffer
0
0
0
NORMAL1/2 or IDLE1/2 mode
TCK1
EIN1
Operation clock selection
Selection for using external source
clock
SYSCR1<DV9CK>
= "1"
000
fcgck/211
fs/24
fs/24
001
fcgck/210
fs/23
fs/23
010
fcgck/28
fcgck/28
-
011
fcgck/26
fcgck/26
-
100
fcgck/24
fcgck/24
-
101
fcgck/2
2
fcgck/2
2
-
110
fcgck/2
fcgck/2
-
111
fcgck
fcgck
fs/22
0
1
Select the internal clock as the source clock.
Select an external clock as the source clock. (the falling edge of the
TC01 pin)
T001CR<TCAS>="0"
(8-bit mode)
00
TCM1
Operation mode selection
SLOW1/2 or SLEEP1
mode
SYSCR1<DV9CK>
= "0"
T001CR<TCAS>="1"
(16-bit mode)
8-bit timer/event counter modes
16-bit timer/event counter modes
8-bit timer/event counter modes
16-bit timer/event counter modes
10
8-bit pulse width modulation output (PWM) mode
12-bit pulse width modulation output (PWM) mode
11
8-bit programmable pulse generate (PPG) mode
16-bit programmable pulse generate (PPG) mode
01
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Set T01MOD while the timer is stopped. Writing data into T01MOD is invalid during the timer operation.
Note 3: In the 8-bit timer/event modes, the TFF1 setting is invalid. In this mode, when the PWM1 and PPG1 pins are set as the
function output pins in the port setting, the pins always output the "H" level.
Note 4: When EIN1 is set to "1" and the external clock input is selected as the source clock, the TCK1 setting is ignored.
RA002
Page 160
TMP89FM46
14.2.3 Common to timer counters 00 and 01
Timer counters 00 and 01 have the low power consumption register (POFFCR0) and timer 00 and 01 control
registers in common.
Low power consumption register 0
POFFCR0
(0x0F74)
RA002
7
6
5
4
3
2
1
0
Bit Symbol
-
-
TC023EN
TC001EN
-
-
TCA1EN
TCA0EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
TC023EN
TC02,03 control
0
1
Disable
Enable
TC001EN
TC00,01 control
0
1
Disable
Enable
TCA1EN
TCA1 control
0
1
Disable
Enable
TCA0EN
TCA0 control
0
1
Disable
Enable
Page 161
14. 8-bit Timer Counter (TC0)
TMP89FM46
Timer counter 01 control register
T001CR
(0x002C)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
-
OUTAND
TCAS
T01RUN
T00RUN
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
0
OUTAND
Timers 00 and 01 output control
1
Output the timer 00 output from the PWM0 and PPG0 pins and the timer
01 output from the PWM1 and PPG1 pins.
Output a pulse that is a logical ANDed product of the outputs of timers
00 and 01 from the PWM1 and PPG1 pins.
Timers 00 and 01 cascade control
0
1
Use timers 00 and 01 independently (8-bit mode).
Cascade timers 00 and 01 (16-bit mode).
T01RUN
Timer 01 control
Timers 00/01 control
(16-bit mode)
0
1
Stop and clear the counter
Start
T00RUN
Timer 00 control
0
1
Stop and clear the counter
Start
TCAS
Note 1: When STOP mode is started, T00RUN and T01RUN are cleared to "0" and the timers stop. Set T001CR again to use timers 00 and 01 after STOP mode is released.
Note 2: When a read instruction is executed on T001CR, bits 7 to 4 are read as "0".
Note 3: When OUTAND is "1", output is obtained from the PWM1 and PPG1 pins only. There is no timer output to the PWM0 and
PPG0 pins. If the PWM0 and PPG0 pins are set as the function output pins in the port setting, the pins always output "H".
Note 4: OUTAND and TCAS can be changed only when both TC01RUN and TC00RUN are "0". When either TC01RUN or
TC00RUN is "1" or both are "1", the register values remain unchanged by executing write instructions on OUTAND and
TCAS. OUTAND and TCAS can be changed at the same time as TC01RUN and TC00RUN are changed from "0" to "1".
RA002
Page 162
TMP89FM46
14.2.4 Operation modes and usable source clocks
The operations modes of the 8-bit timers and the usable source clocks are listed below.
Table 14-3 Operation Modes and Usable Source Clocks (NORMAL1/2 and IDLE1/2 modes)
TCK0
8-bit timer modes
001
010
011
100
101
110
111
fcgck/2
fcgck
TC0i
pin input
Ο
Ο
Ο
-
-
-
-
-
Ο
Ο
Ο
Ο
Ο
Ο
-
Ο
Ο
Ο
Ο
Ο
Ο
-
Ο
Ο
Ο
Ο
Ο
Ο
Ο
-
-
-
-
-
-
-
-
-
Ο
12-bit PWM
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
16-bit PPG
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Operation mode
16-bit timer modes
000
fcgck/2
or
11
fcgck/2
or
10
8
6
fcgck/2
fcgck/2
Ο
Ο
Ο
Ο
-
-
-
-
8-bit PWM
Ο
Ο
Ο
8-bit PPG
Ο
Ο
16-bit timer
Ο
16-bit event
counter
fs/24
fs/23
8-bit timer
Ο
8-bit event counter
fcgck/2
4
fcgck/2
2
Note 1: Ο: Usable, -: Unusable
Note 2: Set the source clock in the 16-bit modes on the TC01 side (TCK1).
Note 3: When the low-frequency clock, fs, is not oscillating, it must not be selected as the source clock. If fs is selected when it is
not oscillating, no source clock is supplied to the timer, and the timer remains stopped.
Note 4: i=0, 1 (i=0 only in the 16-bit modes)
Note 5: The operation modes of the 8-bit timers and the usable source clocks are listed below.
Table 14-4 Operation Modes and Usable Source Clocks (SLOW1/2 and SLEEP1 modes)
TCK0
16-bit timer modes
8-bit timer modes
Operation mode
000
001
4
3
010
011
100
101
110
111
-
-
-
-
-
fs/22
fs/2
8-bit timer
Ο
Ο
-
-
-
-
-
Ο
-
8-bit event counter
-
-
-
-
-
-
-
-
Ο
8-bit PWM
Ο
Ο
-
-
-
-
-
Ο
-
8-bit PPG
Ο
Ο
-
-
-
-
-
Ο
-
16-bit timer
Ο
Ο
-
-
-
-
-
Ο
-
16-bit event
counter
-
-
-
-
-
-
-
-
Ο
12-bit PWM
Ο
Ο
-
-
-
-
-
Ο
Ο
16-bit PPG
Ο
Ο
-
-
-
-
-
Ο
Ο
Note 1: Ο: Usable, -: Unusable
Note 2: Set the source clock in the 16-bit modes on the TC01 side (TCK1).
Note 3: i=0, 1 (i=0 only in the 16-bit modes)
RA002
TC0i
pin input
fs/2
Page 163
14. 8-bit Timer Counter (TC0)
TMP89FM46
14.3 Low Power Consumption Function
Timer counters 00 and 01 have the low power consumption registers (POFFCR0) that save power when the timers
are not used.
Setting POFFCR0<TC001EN> to "0" disables the basic clock supply to timer counters 00 and 01 to save power.
Note that this renders the timers unusable. Setting POFFCR0<TC001EN> to "1" enables the basic clock supply to
timer counters 00 and 01 and allows the timers to operate.
After reset, POFFCR0<TC001EN> are initialized to "0", and this makes the timers unusable. When using the timers for the first time, be sure to set POFFCR0<TC001EN> to "1" in the initial setting of the program (before the
timer control registers are operated).
Do not change POFFCR0<TC001EN> to "0" during the timer operation. Otherwise timer counters 00 and 01 may
operate unexpectedly.
RA002
Page 164
TMP89FM46
14.4 Functions
Timer counters TC00 and TC01 have 8-bit modes in which they are used independently and 16-bit modes in which
they are cascaded.
The 8-bit modes include four operation modes; the 8-bit timer mode, the 8-bit event counter mode, the 8-bit pulse
width modulation output (PWM) mode and the 8-bit programmable pulse generated output (PPG) mode.
The 16-bit modes include four operation modes; the 16-bit timer mode, the 16-bit event counter mode, the 12-bit
PWM mode and the 16-bit PPG mode.
14.4.1 8-bit timer mode
In the 8-bit timer mode, the up-counter counts up using the internal clock, and interrupts can be generated
regularly at specified times. The operation of TC00 is described below, and the same applies to the operation of
TC01. (Replace TC00- by TC01-).
14.4.1.1 Setting
TC00 is put into the 8-bit timer mode by setting T00MOD<TCM0> to "00" or "01", T001CR<TCAS>
to "0" and T00MOD<EIN0> to "0". Select the source clock at T00MOD<TCK0>. Set the count value to
be used for the match detection as an 8-bit value at the timer register T00REG.
Set T00MOD<DBE0> to "1" to use the double buffer.
Setting T001CR<T00RUN> to "1" starts the operation. After the timer is started, writing to T00MOD
becomes invalid. Be sure to complete the required mode settings before starting the timer.
14.4.1.2 Operation
Setting T001CR<T00RUN> to "1" allows the 8-bit up counter to increment based on the selected internal source clock. When a match between the up counter value and the T00REG set value is detected, an
INTT00 interrupt request is generated and the up counter is cleared to "0x00". After being cleared, the up
counter restarts counting. Setting T001CR<T00RUN> to "0" during the timer operation makes the up
counter stop counting and be cleared to "0x00".
14.4.1.3 Double buffer
The double buffer can be used for T00REG by setting T00MOD<DBE0>. The double buffer is disabled
by setting T00MOD<DBE0> to "0" or enabled by setting T00MOD<DBE0> to "1".
• When the double buffer is enabled
When a write instruction is executed on T00REG during the timer operation, the set value is
initially stored in the double buffer, and T00REG is not immediately updated. T00REG compares the previous set value with the up counter value. When the values match, an INTT00
interrupt request is generated and the double buffer set value is stored in T00REG. Subsequently, the match detection is executed using a new set value.
When a write instruction is executed on T00REG while the timer is stopped, the set value is
immediately stored in both the double buffer and T00REG.
• When the double buffer is disabled
When a write instruction is executed on T00REG during the timer operation, the set value is
immediately stored in T00REG. Subsequently, the match detection is executed using a new set
value.
RA002
Page 165
14. 8-bit Timer Counter (TC0)
TMP89FM46
If the value set to T00REG is smaller than the up counter value, the match detection is executed using a new set value after the up counter overflows. Therefore, the interrupt request
interval may be longer than the selected time. If the value set to T00REG is equal to the up
counter value, the match detection is executed immediately after data is written into T00REG.
Therefore, the interrupt request interval may not be an integral multiple of the source clock
(Figure 14-3). If these are problems, enable the double buffer.
When a write instruction is executed on T00REG while the timer is stopped, the set value is
immediately stored in T00REG.
When a read instruction is executed on T00REG, the last value written into T00REG is read out, regardless of the T00MOD<DBE0> setting.
Table 14-5 8-bit Timer Mode Resolution and Maximum Time Setting
Source clock [Hz]
T00MOD
<TCK0>
Resolution
Maximum time setting
NORMAL1/2 or IDLE1/2 mode
SLOW1/2 or
SLEEP1 mode
fcgck=10MHz
fs=32.768KHz
fcgck=10MHz
fs=32.768KHz
fs/24
fs/24
204.8µs
488.2µs
52.2ms
124.5ms
fcgck/210
fs/23
fs/23
102.4µs
244.1µs
26.1ms
62.3ms
010
fcgck/28
fcgck/28
-
25.6µs
-
6.5ms
-
011
fcgck/26
fcgck/26
-
6.4µs
-
1.6ms
-
100
fcgck/24
fcgck/24
-
1.6µs
-
408µs
-
101
fcgck/22
fcgck/22
-
400ns
-
102µs
-
110
fcgck/2
fcgck/2
-
200ns
-
51µs
-
111
fcgck
fcgck
fs/22
100ns
122.1µs
25.5µs
31.1ms
SYSCR1<DV9CK>
= "0"
SYSCR1<DV9CK>
= "1"
000
fcgck/211
001
(Example) Operate TC00 in the 8-bit timer mode with the operation clock of fcgck/22 [Hz] and generate interrupts at 64 µs intervals
(fcgck = 10 MHz)
LD
(POFFCR0),0x10
DI
SET
(EIRH).4
EI
RA002
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
LD
(T00MOD),0xE8
; Selects the 8-bit timer mode and fcgck/22
LD
(T00REG),0xA0
; Sets the timer register (64µs / (22/fcgck) = 0xA0)
SET
(T001CR).0
; Starts TC00
Page 166
TMP89FM46
Timer stop
Timer start
T001CR<T00RUN>
T00MOD<DBE0>
Source clock
n
m
Counter
0
1
2
3
4
m-1
0
1
2
3
n-1
0
1
Counter clear
Write to T00REG
Write m
Match detection
m
INTT00 interrupt request
0
Write n
Match detection
T00REG
2
Counter clear
n
Reflected by writing to T00REG
Reflected by writing to T00REG
When the double buffer is disabled (T00MOD<DBE0>=”0”)
Timer start
T001CR<T00RUN>
T00MOD<DBE0>
Source clock
m
m
Counter
0
1
2
3
4
m-1
0
1
2
3
m-1
Counter clear
Write to T00REG
Write m
n-1
1
0
1
Counter clear
Write n
Double buffer
m
T00REG
Match detection
m
Reflected at the same time
as data is written into T00REG
while the timer is stopped
INTT00 interrupt request
n
0
n
Match detection
n Match detection
Reflected by
an interrupt
When the double buffer is enabled (T00MOD<DBE0>=”1”)
Figure 14-2 Timer Mode Timing Chart
T00MOD<DBE0>
Source clock
Counter
n-5
n-4
n-3
n-2
0
1
2
Counter clear
Write to T00REG
T00REG
Write n-2
n
Match detection
n-2
INTT00 interrupt request
Figure 14-3 Operation When T00REG and the Up Counter Have the Same Value
RA002
Page 167
14. 8-bit Timer Counter (TC0)
TMP89FM46
14.4.2 8-bit event counter mode
In the 8-bit event counter mode, the up counter counts up at the falling edge of the input to the TC00 or TC01
pin. The operation of TC00 is described below, and the same applies to the operation of TC01.
14.4.2.1 Setting
TC00 is put into the 8-bit event counter mode by setting T00MOD<TCM0> to "00", T001CR<TCAS>
to "0" and T00MOD<EIN0> to "1". Set the count value to be used for the match detection as an 8-bit
value at the timer register T00REG.
Set T00MOD<DBE0> to "1" to use the double buffer.
Setting T001CR<T00RUN> to "1" starts the operation. After the timer is started, writing to T00MOD
becomes invalid. Be sure to complete the required mode settings before starting the timer.
14.4.2.2 Operation
Setting T001CR<T00RUN> to "1" allows the 8-bit up counter to increment at the falling edge of the
TC00 pin. When a match between the up-counter value and the T00REG set value is detected, an INTT00
interrupt request is generated and the up counter is cleared to "0x00". After being cleared, the up counter
restarts counting. Setting T001CR<T00RUN> to "0" during the timer operation makes the up counter stop
counting and be cleared to "0x00".
The maximum frequency to be supplied is fcgck/22 [Hz] (in NORMAL1/2 or IDLE1/2 mode) or fs/24
[Hz] (in SLOW1/2 or SLEEP1 mode), and a pulse width of two machine cycles or more is required at
both the "H" and "L" levels.
14.4.2.3 Double buffer
Refer to "14.4.1.3 Double buffer".
(Example) Operate TC00 in the 8-bit event counter mode and generate an interrupt each time 16 falling edges are detected at the
TC00 pin.
LD
(POFFCR0),0x10
DI
SET
(EIRH).4
EI
RA002
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
LD
(T00MOD),0xC4
LD
(T00REG),0x10
; Selects to the 8-bit event counter mode
; Sets the timer register
SET
(T001CR).0
; Starts TC00
Page 168
TMP89FM46
Timer start
Timer stop
T001CR<T00RUN>
TC00 pin input
n
m
Counter
0
1
2
3
4
m-1
0
1
2
3
n-1
0
Counter clear
Write to T00REG
Write m
INTT00 interrupt request
2
0
Counter clear
Write n
Match detection
T00REG
1
m
Match detection
n
Reflected by writing to T00REG
Reflected by writing to T00REG
When the double buffer is disabled (T00MOD<DBE0>=”0”)
Figure 14-4 Event Counter Mode Timing Chart
RA002
Page 169
14. 8-bit Timer Counter (TC0)
TMP89FM46
14.4.3 8-bit pulse width modulation (PWM) output mode
The pulse-width modulated pulses with a resolution of 7 bits are output in the 8-bit PWM mode. An additional pulse can be added to the 2 × n-th duty pulse. This enables PWM output with a resolution nearly equivalent to 8 bits. (n=1, 2, 3...)
The operation of TC00 is described below, and the same applies to the operation of TC01.
14.4.3.1 Setting
TC00 is put into the 8-bit PWM mode by setting T00MOD<TCM0> to "10" and T001CR<TCAS> to
"0". Set T00MOD<EIN0> to "0" and select the clock at T00MOD<TCK0>. Set the count value to be used
for the match detection and the additional pulse value at the PWM register T00PWM.
Set T00MOD<DBE0> to "1" to use the double buffer.
Setting T001CR<T00RUN> to "1" starts the operation. After the timer is started, writing to T00MOD
becomes invalid. Be sure to complete the required mode settings before starting the timer.
In the 8-bit PWM mode, the T00PWM register is configured as follows:
Timer register 00
T00PWM
(0x0028)
7
6
5
Read/Write
3
2
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
1
1
1
1
1
1
1
1
Bit Symbol
4
PWMDUTY
0
PWMAD
Timer register 01
T01PWM
(0x0029)
Bit Symbol
PWMDUTY
PWMAD
PWMDUTY is a 7-bit register used to set the duty pulse width value (the time before the first output
change) in a cycle (128 counts of the source clock).
PWMAD is a register used to set the additional pulse. When PWMAD is "1", an additional pulse that
corresponds to 1 count of the source clock is added to the 2 × n-th duty pulse (n=1, 2, 3...). In other words,
the 2 × n-th duty pulse has the output of PWMDUTY+1.
The additional pulse is not added when PWMAD is "0".
RA002
Page 170
TMP89FM46
Additional
pulse
Additional
pulse
Timer start
(Duty pulse
width)
T00PWM
Additional
pulse
(Duty pulse
width)
T00PWM
PWM0 pin output
(TFF0=“1”)
PWM0 pin output
(TFF0=“0”)
128 counts
(cycle width)
128 counts
(cycle width)
Cycle 1
Cycle 2
INTT00 interrupt
request
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Figure 14-5 PWM0 Pulse Output
Set the initial state of the PWM0 pin at T00MOD<TFF0>. Setting T00MOD<TFF0> to "0" selects the
"L" level as the initial state of the PWM0 pin. Setting T00MOD<TFF0> to "1" selects the "H" level as the
initial state of the PWM0 pin. If the PWM0 pin is set as the function output pin in the port setting while the
timer is stopped, the value of T00MOD<TFF0> is output to the PWM0 pin. Table 14-6 shows the list of
output levels of the PWM0 pin.
Table 14-6 List of Output Levels of PWM0 Pin
PWM0 pin output level
Before the start
of operation
(initial state)
T00PWM
<PWMDUTY>
matched
(after the additional pulse)
Overflow
Operation
stopped
(initial state)
0
L
H
L
L
1
H
L
H
H
TFF0
And by setting "1" to T001CR<OUTAND> bit, a logical product (AND) pulse of TC00 and TC01’s output can be output to PWM0 pin. By using this function, the remote-control waveform can be created eaily.
14.4.3.2 Operations
Setting T001CR<T00RUN> to "1" allows the up counter to increment based on the selected source
clock. When a match between the lower 7 bits of the up counter value and the value set to
T00PWM<PWMDUTY> is detected, the output of the PWM0 pin is reversed. When T00MOD<TFF0> is
"0", the PWM0 pin changes from the "L" to "H" level. When T00MOD<TFF0> is "1", the PWM0 pin
changes from the "H" to "L" level.
If T00PWM<PWMAD> is "1", an additional pulse that corresponds to 1 count of the source clock is
added at the 2 × n-th match detection (n=1, 2, 3...). In other words, the PWM0 pin output is reversed at the
timing of T00PWM<PWMDUTY>+1. When T00MOD<TFF0> is "0", the period of the "L" level
becomes longer than the value set to T00<PWMDUTY> by 1 source clock. When T00MOD<TFF0> is
"1", the period of the "H" level becomes longer than the value set to T00PWM<PWMDUTY> by 1 source
clock. This function allows two cycles of output pulses to be handled with a resolution nearly equivalent
to 8 bits.
No additional pulse is inserted when T00PWM<PWMAD> is "0".
RA002
Page 171
14. 8-bit Timer Counter (TC0)
TMP89FM46
Subsequently, the up counter continues counting up. When the up counter value reaches 128, an overflow occurs and the up counter is cleared to "0x00". At the same time, the output of the PWM0 pin is
reversed. When T00MOD<TFF0> is "0", the PWM0 pin changes from the "H" to "L" level. When
T00MOD<TFF0> is "1", the PWM0 pin changes from the "L" to "H" level. If the 2 × n-th overflow occurs
at this time, an INTT00 interrupt request is generated. (No interrupt request is generated at the 2 × n-th -1
overflow.) Subsequently, the up counter continues counting up.
When T001CR<T00RUN> is set to "0" during the timer operation, the up counter is stopped and
cleared to "0x00". The PWM0 pin returns to the level selected at T00MOD<TFF0>.
(Example) Operate TC00 in the 8-bit PWM mode with the operation clock of fcgck/2 and output a duty pulse nearly equivalent to 11.6
µs (fcgck = 10 MHz)
(Actually, output a total duty pulse of 23.2 µs in 2 cycles (102.4 µs))
SET
(P7FC).0
; Sets P7FC0 to "1"
SET
(P7CR).0
; Sets P7CR0 to "1"
LD
(POFFCR0),0x10
; Sets TC001EN to "1"
DI
; Sets the interrupt master enable flag to "disable"
SET
(EIRH).4
; Sets the INTTC00 interrupt enable register to "1"
EI
; Sets the interrupt master enable flag to "enable"
LD
(T00MOD),0xF2
; Selects the 8-bit PWM mode and fcgck/2
LD
(T00PWM),0x73
; Sets the timer register (duty pulse)
; (11.6µs × 2) / (2/fcgck) = 0x73
SET
(T001CR).0
; Starts TC00
Timer start
Timer stop
T001CR<T00RUN>
T00MOD<TFF0>
Source clock
Counter
0
1
Overflow
128
0 1
m m+1
Overflow
128
0 1
m m+1
Counter
clear
Write to T00PWM
Double buffer
Write m
r
r
r+1
Counter
clear
0
Counter
clear
Reflected by an
interrupt request
m
128
0 1
s
T00PWM
<PWMAD>
T00PWM
<PWMDUTY>
r+1
Counter
clear
Write s
Write r
m
r
Overflow
128
0 1
Match detection
Match detection
Reflected by an
interrupt request
Match detection
r
Match detection s
PWM0 pin output
Becomes the level selected at
TFF0 while the timer is stopped
INTT00 interrupt
request
m
(Duty pulse)
128 counts
(Cycle 1)
Additional pulse
No interrupt request
is generated
m
(Duty pulse)
128 counts
(Cycle 2)
Interrupt request
r
(Duty pulse)
No interrupt request
is generated
r+1
(Duty pulse)
128 counts
(Cycle 3)
When the double buffer is enabled (T00MOD<DBE0>=”1”)
Figure 14-6 8-bit PWM Mode Timing Chart
RA002
Page 172
128 counts
(Cycle 4)
Returns to the
level selected
at TFF0
TMP89FM46
14.4.3.3 Double buffer
The double buffer can be used for T00PWM by setting T00MOD<DBE0>. The double buffer is disabled by setting T00MOD<DBE0> to "0" or enabled by setting T00MOD<DBE0> to "1".
• When the double buffer is enabled
When a write instruction is executed on T00PWM during the timer operation, the set value is
first stored in the double buffer, and T00PWM is not updated immediately. T00PWM compares
the previous set value with the up counter value. When the 2 × n-th overflow occurs, an
INTT00 interrupt request is generated and the double buffer set value is stored in T00PWM.
Subsequently, the match detection is executed using a new set value.
When a read instruction is executed on T00PWM, the value in the double buffer (the last set
value) is read out, not the T00PWM value (the currently effective value).
When a write instruction is executed on T00PWM while the timer is stopped, the set value is
immediately stored in both the double buffer and T00PWM.
• When the double buffer is disabled
When a write instruction is executed on T00PWM during the timer operation, the set value is
immediately stored in T00PWM. Subsequently, the match detection is executed using a new set
value. If the value set to T00PWM is smaller than the up counter value, the PWM0 pin is not
reversed until the up counter overflows and a match detection is executed using a new set
value. If the value set to T00PWM is equal to the up counter value, the match detection is executed immediately after data is written into T00PWM. Therefore, the timing of changing the
PWM0 pin may not be an integral multiple of the source clock (Figure 14-7). Similarly, if
T00PWM is set during the additional pulse output, the timing of changing the PWM0 pin may
not be an integral multiple of the source clock. If these are problems, enable the double buffer.
When a write instruction is executed on T00PWM while the timer is stopped, the set value is
immediately stored in T00PWM.
T00MOD<DBE0>
Source clock
Counter
n-5
Write to T00PWM
T00PWM
<PWMDUTY>
n-4
n-3
n-2
n-1
n
Write n-2
n
Match detection
n-2
PWM0 pin output
Figure 14-7 Operation When T00PWM and the Up Counter Have the Same Value
RA002
Page 173
14. 8-bit Timer Counter (TC0)
TMP89FM46
Table 14-7 Resolutions and Cycles in the 8-bit PWM Mode
Source clock [Hz]
T00MOD
<TCK0>
RA002
7-bit cycle
(period × 2)
Resolution
NORMAL1/2 or IDLE1/2 mode
SLOW1/2 or
SLEEP1 mode
fcgck=10MHz
fs=32.768KHz
fcgck=10MHz
fs=32.768KHz
fs/24
fs/24
204.8µs
488.2µs
26.2ms
(52.4ms)
62.5ms
(125ms)
fcgck/210
fs/23
fs/23
102.4µs
244.1µs
13.1ms
(26.2ms)
31.3ms
(62.5ms)
010
fcgck/28
fcgck/28
-
25.6µs
-
3.3ms
(6.6ms)
-
011
fcgck/26
fcgck/26
-
6.4µs
-
819.2µs
(1638.4µs)
-
100
fcgck/24
fcgck/24
-
1.6µs
-
204.8µs
(409.6µs)
-
101
fcgck/22
fcgck/22
-
400ns
-
51.2µs
(102.4µs)
-
110
fcgck/2
fcgck/2
-
200ns
-
25.6µs
(51.2µs)
-
111
fcgck
fcgck
fs/22
100ns
122.1µs
12.8µs
(25.6µs)
15.6ms
(31.3ms)
SYSCR1<DV9CK>
= "0"
SYSCR1<DV9CK>
= "1"
000
fcgck/211
001
Page 174
TMP89FM46
14.4.4 8-bit programmable pulse generate (PPG) output mode
In the 8-bit PPG mode, the pulses with arbitrary duty and cycle are output by using the T00REG and
T00PWM registers.
By setting the T001CR<OUTAND> register, a pulse that is a logical ANDed product of the TC00 and TC01
outputs can be output to the TC01 pin. This function facilitates the generation of remote-controlled waveforms,
for example.
The operation of TC00 is described below, and the same applies to the operation of TC01.
14.4.4.1 Setting
TC00 is put into the 8-bit PPG mode by setting T00MOD<TCM0> to "10" and T001CR<TCAS> to
"0". Set T00MOD<EIN0> to "0" and select the clock at T00MOD<TCK0>. Set the duty pulse width at
T00PWM and the cycle width at T00REG.
Set T00MOD<DBE0> to "1" to use the double buffer.
Setting T001CR<T00RUN> to "1" starts the operation. After the timer is started, writing to T00MOD
becomes invalid. Be sure to complete the required mode settings before starting the timer.
Timer stop
Timer start
(Duty pulse)
T00PWM
(Duty pulse)
T00PWM
PPG0 pin output
(TFF0=“0”)
PPG0 pin output
(TFF0=“1”)
T00REG
(1 cycle)
T00REG
(1 cycle)
Figure 14-8 PPG0 Pulse Output
Set the initial state of the PPG0 pin at T00MOD<TFF0>. Setting T00MOD<TFF0> to "0" selects the
"L" level as the initial state of the PPG0 pin. Setting T00MOD<TFF0> to "1" selects the "H" level as the
initial state of the PPG0 pin. If the PPG0 pin is set as the function output pin in the port setting while the
timer is stopped, the value of T00MOD<TFF0> is output to the PPG0 pin. Table 14-8 shows the list of output levels of the PPG0 pin.
Table 14-8 List of Output Levels of PPG0 Pin
PPG0 pin output level
TFF0
Before the start
of operation
(initial state)
T00PWM
matched
T00REG
matched
Operation
stopped
(initial state)
0
L
H
L
L
1
H
L
H
H
Setting the T001CR<OUTAND> bit to "1" allows the PPG0 pin to output a pulse that is a logical
ANDed product of the TC00 and TC01 outputs.
RA002
Page 175
14. 8-bit Timer Counter (TC0)
TMP89FM46
14.4.4.2 Operation
Setting T001CR<T00RUN> to "1" allows the up counter to increment based on the selected source
clock. When a match between the internal up counter value and the value set to T00PWM is detected, the
output of the PPG0 pin is reversed. When T00MOD<TFF0> is "0", the PPG0 pin changes from the "L" to
"H" level. When T00MOD<TFF0> is "1", the PPG0 pin changes from the "H" to "L" level.
Subsequently, the up counter continues counting up. When a match between the up counter value and
T00REG is detected, the output of the PPG0 pin is reversed again. When T00MOD<TFF0> is "0", the
PPG0 pin changes from the "H" to "L" level. When T00MOD<TFF0> is "1", the PPG0 pin changes from
the "L" to "H" level. At this time, an INTT00 interrupt request is generated.
When T001CR<T00RUN> is set to "0" during the operation, the up counter is stopped and cleared to
"0x00". The PPG0 pin returns to the level selected at T00MOD<TFF0>.
14.4.4.3 Double buffer
The double buffer can be used for T00PWM and T00REG by setting T00MOD<DBE0>. The double
buffer is disabled by setting T00MOD<DBE0> to "0" or enabled by setting T00MOD<DBE0> to "1".
• When the double buffer is enabled
When a write instruction is executed on T00PWM (T00REG) during the timer operation, the
set value is first stored in the double buffer, and T00PWM (T00REG) is not updated immediately. T00PWM (T00REG) compares the previous set value with the up counter value. When
an INTT00 interrupt request is generated, the double buffer set value is stored in T00PWM
(T00REG). Subsequently, the match detection is executed using a new set value.
When a read instruction is executed on T00PWM (T00REG), the value in the double buffer
(the last set value) is read out, not the T00PWM (T00REG) value (the currently effective
value).
When a write instruction is executed on T00PWM (T00REG) while the timer is stopped, the
set value is immediately stored in both the double buffer and T00PWM (T00REG).
• When the double buffer is disabled
When a write instruction is executed on T00PWM (T00REG) during the timer operation, the
set value is immediately stored in T00PWM (T00REG). Subsequently, the match detection is
executed using a new set value. If the value set to T00PWM (T00REG) is smaller than the up
counter value, the PPG0 pin is not reversed until the up counter overflows and a match detection
is executed using a new set value. If the value set to T00PWM (T00REG) is equal to the up
counter value, the match detection is executed immediately after data is written into T00PWM
(T00REG). Therefore, the timing of changing the PPG0 pin may not be an integral multiple of
the source clock (Figure 14-10). If these are problems, enable the double buffer.
When a write instruction is executed on T00PWM (T00REG) while the timer is stopped, the
set value is immediately stored in T00PWM (T00REG).
(Example)
Operate TC00 in the 8-bit PPG mode with the operation clock of fcgck/2 and output the 8µs duty pulse in 32µs cycles (fcgck
= 10 MHz)
SET
(P7FC).0
; Sets P7FC0 to "1"
SET
(P7CR).0
; Sets P7CR0 to "1"
LD
(POFFCR0),0x10
DI
SET
(EIRH).4
EI
RA002
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
LD
(T00MOD),0xF3
; Selects the 8-bit PPG mode and fcgck/2
LD
(T00REG),0xA0
; Sets the timer register (cycle)
; 32µs / (2/fcgck) = 0xA0
Page 176
TMP89FM46
LD
(T00PWM),0x28
; Sets the timer register (duty pulse)
; 8µs / (2/fcgck) = 0x28
SET
(T001CR).0
; Starts TC00
Timer start
Timer stop
T001CR<T00RUN>
T00MOD<TFF0>
Source clock
s
p
Counter
0
1
m m+1
0 1
r
r+1
0 1
Counter
clear
Write to T00PWM
Write m
m
r
T00PWM
m
Match detection
Write to T00REG
Write p
r
w
r+1
0 1
Counter
clear
Write t
Write r
Double buffer
s
t
t+1
Counter
clear
0 1
0
Counter
clear
t
Match detection
r
Match detection s
Write s
Double buffer
p
s
T00REG
p
Match detection
Match detection
Write w
w
s
Match detection
Match detection
w
PPG0 pin output
INTT00 interrupt
request
Returns to the
level selected
at TFF0
Becomes the level selected at
TFF0 while the timer is stopped
m
(Duty pulse)
r
(Duty pulse)
p
(1 cycle)
r
(Duty pulse)
s
(1 cycle)
t
(Duty pulse)
s
(1 cycle)
w
(1 cycle)
When the double buffer is enabled (T00MOD<DBE0>=”1”)
Figure 14-9 8-bit PPG Mode Timing Chart
T00MOD<DBE0>
Source clock
Counter
n-5
Write to T00PWM
(T00REG)
T00PWM
(T00REG)
n-4
n-3
n-2
n-1
n
Write n-2
n
Match detection
n-2
PPG0 pin output
Figure 14-10 Operation When T00PWM (T00REG) and the Up Counter Have the Same
Value
RA002
Page 177
14. 8-bit Timer Counter (TC0)
TMP89FM46
14.4.5 16-bit timer mode
In the 16-bit timer mode, TC00 and TC01 are cascaded to form a 16-bit timer counter, which can measure a
longer period than an 8-bit timer.
14.4.5.1 Setting
Setting T001CR<TCAS> to "1" connects TC00 and TC01 and activates the 16-bit mode. All the settings of TC00 are ignored and those of TC01 are effective in the 16-bit mode.
The 16-bit timer mode is activated by setting T01MOD<TCM1> to "00" or "01" and T01MOD<EIN1>
to "0". Select the source clock at T01MOD<TCK1>.
Set the count value to be used for the match detection as a 16-bit value at the timer registers T00REG
and T01REG. Set the lower 8 bits of the 16-bit value at T00REG and the higher 8 bits at T01REG. (Hereinafter, the 16-bit value specified by the combined setting of T01REG and T00REG is indicated as
T01+00REG.) The timer register settings are reflected on the double buffer or T01+00REG when a write
instruction is executed on T01REG. Be sure to execute the write instructions on T00REG and T01REG in
this order. (When data is written to the high-order register, the set values of the low-order and high-order
registers become effective at the same time.)
Set T01MOD<DBE1> to "1" to use the double buffer.
Setting T001CR<T01RUN> to "1" starts the operation. After the timer is started, writing to T01MOD
becomes invalid. Be sure to complete the required mode settings before starting the timer. (Make settings
when T001CR<T00RUN> and <T01RUN> are "0".)
14.4.5.2 Operations
Setting T001CR<T01RUN> to "1" allows the 16-bit up counter to increment based on the selected
internal source clock. When a match between the up counter value and the T00+01REG set value is
detected, an INTT01 interrupt request is generated and the up counter is cleared to "0x0000". After being
cleared, the up counter restarts counting. Setting T001CR<T01RUN> to "0" during the timer operation
makes the up counter stop counting and be cleared to "0x0000".
14.4.5.3 Double buffer
The double buffer can be used for T01+00REG by setting T01MOD<DBE1>. The double buffer is disabled by setting T01MOD<DBE1> to "0" or enabled by setting T01MOD<DBE1> to "1".
• When the double buffer is enabled
When write instructions are executed on T00REG and T01REG in this order during the timer
operation, the set value is first stored in the double buffer, and T01+00REG is not updated
immediately. T01+00REG compares the previous set value with the up counter value. When
the values are matched, an INTT01 interrupt request is generated and the double buffer set
value is stored in T01+00REG. Subsequently, the match detection is executed using a new set
value.
When write instructions are executed on T00REG and T01REG in this order while the timer
is stopped, the set value is immediately stored in both the double buffer and T01+00REG.
• When the double buffer is disabled
When write instructions are executed on T00REG and T01REG in this order during the timer
operation, the set value is immediately stored in T01+00REG. Subsequently, the match detection is executed using a new set value.
RA002
Page 178
TMP89FM46
If the value set to T01+00REG is smaller than the up counter value, the match detection is
executed using a new set value after the up counter overflows. Therefore, the interrupt request
interval may be longer than the selected time. If the value set to T01+00REG is equal to the up
counter value, the match detection is executed immediately after data is written into
T01+00REG. Therefore, the interrupt request interval may not be an integral multiple of the
source clock. If these are problems, enable the double buffer.
When write instructions are executed on T00REG and T01REG in this order while the timer
is stopped, the set value is immediately stored in T01+00REG.
When a read instruction is executed on T01+00REG, the last value written into T01+00REG is read out,
regardless of the T00MOD<DBE1> setting.
(Example)
Operate TC00 and TC01 in the 16-bit timer mode with the operation clock of fcgck/2 [Hz] and generate interrupts at 96 µs
intervals (fcgck = 10 MHz)
LD
(POFFCR0),0x10
DI
SET
(EIRH).4
EI
RA002
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
LD
(T01MOD),0xF0
; Selects the 16-bit timer mode and fcgck/2
LD
(T00REG),0xE0
; Sets the timer register (96µs / (2/fcgck) = 0x1E0)
LD
(T01REG),0x01
; Sets the timer register
LD
(T001CR),0x06
; Starts TC00 and TC001 (16-bit mode)
Page 179
14. 8-bit Timer Counter (TC0)
TMP89FM46
Timer stop
Timer start
T001CR<T01RUN>
T01MOD<DBE1>
Source clock
Counter
0
1
2
3
4
km-1
km
0
sr
1
2
3
sr-1
0
1
Counter clear
Write to T00REG
Write to T01REG
Write m
Write k
Write s
Match detection
km
INTT01 interrupt
request
0
Write r
Match detection
T01+00REG
2
Counter clear
sr
Reflected by writing to T01REG
Reflected by writing to T01REG
When the double buffer is disabled (T01MOD<DBE1>=”0”)
Timer start
T001CR<T01RUN>
T01MOD<DBE1>
Source clock
km
km
Counter
0
1
2
3
4
km-1
0
1
2
3
km-1
sr
0
Counter clear
Counter clear
Write to T00REG
Write m
Write r
Write to T01REG
Write k
Double buffer
km
T01+00REG
Match detection
km
Reflected simultaneously by
writing to T01REG while the timer
is stopped
INTT01 interrupt
request
Write s
sr
Match detection
sr
Match detection
Reflected by
an interrupt
Reflected by writing to T01REG
When the double buffer is enabled (T01MOD<DBE1>=”1”)
Figure 14-11 16-bit Timer Counter Timing Chart
RA002
sr-1
1
Page 180
0
1
TMP89FM46
Table 14-9 16-bit Timer Mode Resolution and Maximum Time Setting
Source clock [Hz]
T01MOD
<TCK1>
RA002
Resolution
Maximum time setting
NORMAL1/2 or IDLE1/2 mode
SLOW1/2 or
SLEEP1 mode
fcgck=10MHz
fs=32.768KHz
fcgck=10MHz
fs=32.768KHz
fs/24
fs/24
204.8µs
488.2µs
13.4s
32s
fcgck/210
fs/23
fs/23
102.4µs
244.1µs
6.7s
16s
010
fcgck/28
fcgck/28
-
25.6µs
-
1.7s
-
011
fcgck/26
fcgck/26
-
6.4µs
-
419.4ms
-
100
fcgck/24
fcgck/24
-
1.6µs
-
104.9ms
-
101
fcgck/22
fcgck/22
-
400ns
-
26.2ms
-
110
fcgck/2
fcgck/2
-
200ns
-
13.1ms
-
111
fcgck
fcgck
fs/22
100ns
122.1µs
6.6ms
8s
SYSCR1<DV9CK>
= "0"
SYSCR1<DV9CK>
= "1"
000
fcgck/211
001
Page 181
14. 8-bit Timer Counter (TC0)
TMP89FM46
14.4.6 16-bit event counter mode
In the 16-bit event counter mode, the up counter counts up at the falling edge of the input to the TC00 pin.
TC00 and TC01 are cascaded to form a 16-bit timer counter, which can measure a longer period than an 8-bit
timer.
14.4.6.1 Setting
Setting T001CR<TCAS> to "1" connects TC00 and TC01 and activates the 16-bit timer mode. All the
settings of TC00 are ignored and those of TC01 are effective in the 16-bit timer mode.
The 16-bit timer mode is activated by setting T01MOD<TCM1> to "00" or "01" and T01MOD<EIN0>
to "1".
Set the count value to be used for the match detection as a 16-bit value at the timer registers T00REG
and T01REG. Set the lower 8 bits of the 16-bit value at T00REG and set the higher 8 bits at T01REG.
(Hereinafter, the 16-bit value specified by the combined setting of T01REG and T00REG is indicated as
T01+00REG.) The timer register settings are reflected on the double buffer or T01+00REG when a write
instruction is executed on T01REG. Be sure to execute the write instructions on T00REG and T01REG in
this order. (When data is written to the high-order register, the set values of the low-order and high-order
registers become effective at the same time.)
Set T01MOD<DBE1> to "1" to use the double buffer.
Setting T001CR<T01RUN> to "1" starts the operation. After the timer is started, writing to T01MOD
becomes invalid. Be sure to complete the required mode settings before starting the timer. (Make settings
when T001CR<T00RUN> and <T01RUN> are "0".)
14.4.6.2 Operations
Setting T001CR<T01RUN> to "1" allows the 16-bit up counter to increment at the falling edge of the
TC00 pin. When a match between the up counter value and the T00+01REG set value is detected, an
INTT01 interrupt request is generated and the up counter is cleared to "0x0000". After being cleared, the
up counter restarts counting. Setting T001CR<T01RUN> to "0" during the timer operation makes the up
counter stop counting and be cleared to "0x0000".
The maximum frequency to be supplied is fcgck/2 [Hz] (in NORMAL1/2 or IDLE1/2 mode) or fs/24
[Hz] (in SLOW1/2 or SLEEP1 mode), and a pulse width of two machine cycles or more is required at
both the "H" and "L" levels.
14.4.6.3 Double buffer
Refer to 14.4.5.3.
(Example)
Operate TC00 and TC01 in the 16-bit event counter mode and generate an interrupt each time the 384th falling edge is
detected at the TC00 pin
LD
(POFFCR0),0x10
DI
SET
(EIRH).4
EI
RA002
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
LD
(T00MOD),0xC4
; Selects the 16-bit event counter mode
LD
(T00REG),0x80
; Sets the timer register
LD
(T01REG),0x10
; Sets the timer register
LD
(T001CR),0x06
; Starts TC00 and TC001 (16-bit mode)
Page 182
TMP89FM46
Timer stop
Timer start
T001CR<T01RUN>
TC00 pin input
rs
km
Counter
Write to T00REG
Write to T01REG
0
1
2
3
4
km-1
0
1
2
Counter
clear
Write m
INTT00 interrupt
request
rs-1
0
Write k
1
Counter
clear
Write s
2
0
Counter
clear
Write r
Match detection
T01+00REG
3
Match detection
km
rs
Reflected by writing to T01REG
Reflected by writing to T01REG
When the double buffer is disabled (T01MOD<DBE1>=”0”)
Timer start
T001CR<T01RUN>
TC00 pin input
km
km
Counter
Write to T00REG
0
1
2
3
4
km-1
Write k
Double buffer
km
INTT00 interrupt
request
2
3
km-1
Write s
rs
0
1
Counter
clear
0
km
Match detection
rs
Reflected by writing to T01REG
Reflected by
an interrupt
Reflected by writing to T01REG
Figure 14-12 16-bit Event Counter Mode Timing Chart
Page 183
1
Counter
clear
rs
Match detection
When the double buffer is enabled (T01MOD<DBE1>=”1”)
RA002
rs-1
Write r
Match detection
T01+00REG
1
Counter
clear
Write m
Write to T01REG
0
14. 8-bit Timer Counter (TC0)
TMP89FM46
14.4.7 12-bit pulse width modulation (PWM) output mode
In the 12-bit PWM output mode, TC00 and TC01 are cascaded to output the pulse-width modulated pulses
with a resolution of 8 bits. An additional pulse of 4 bits can be inserted, which enables PWM output with a resolution nearly equivalent to 12 bits.
14.4.7.1 Setting
Setting T001CR<TCAS> to "1" connects TC00 and TC01 and activates the 16-bit timer mode. All the
settings of TC00 are ignored and those of TC01 are effective in the 16-bit timer mode.
The 12-bit PWM mode is selected by setting T01MOD<TCM1> to "10". To use the internal clock as the
source clock, set T01MOD<EIN1> to "0" and select the clock at T01MOD<TCK1>. To use an external
clock as the source clock, set T01MOD<EIN1> to "1".
Set T01MOD<DBE1> to "1" to use the double buffer.
Setting T001CR<T01RUN> to "1" starts the operation. After the timer is started, writing to T01MOD
becomes invalid. Be sure to complete the required mode settings before starting the timer. (Make settings
when T001CR<T00RUN> and <T01RUN> are "0".)
Set the count value to be used for the match detection and the additional pulse value as a 12-bit value at
the timer registers T00PWM and T01PWM. Set bits 11 to 8 of the 12-bit value at the lower 4 bits of
T01PWM and set bits 7 to 0 at T00PWM. Refer to the following table for the register configuration. Hereinafter, the 12-bit value specified by the combined setting of T00PWM and T01PWM is indicated as
T01+00PWM. The timer register settings are reflected on the double buffer or T01+00PWM when a write
instruction is executed on T01PWM. Be sure to execute the write instructions on T00PWM and T01PWM
in this order. (When data is written to the high-order register, the set values of the low-order and highorder registers become effective at the same time.)
Timer register 00
T00PWM
(0x0028)
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
After reset
1
1
1
7
6
5
Bit Symbol
3
2
1
0
PWMAD3
PWMAD2
PWMAD1
PWMAD0
R/W
R/W
R/W
R/W
1
1
1
1
1
4
3
2
1
0
R/W
R/W
R/W
R/W
1
1
1
1
PWMDUTYL
Timer register 01
T01PWM
(0x0029)
Bit Symbol
PWMDUTYH
Read/Write
After reset
1
1
1
1
Bits 7 to 4 of T01PWM are not used in the 12-bit PWM mode. However, data can be written to these
bits of T01PWM and the written values are read out as they are when the bits are read. Normally, set these
bits to "0".
PWMDUTYH and PWMDUTYL are 4-bit registers. They are combined to set an 8-bit value of duty
pulse width (time before the first change in the output) for one cycle (256 counts of the source clock).
Hereinafter, an 8-bit value specified by the combined setting of PWMDUTYH and PWMDUTYL is indicated as PWMDUTY.
PWMAD3 to 0 are the additional pulse setting register. Additional pulses can be inserted in specific
cycles of the duty pulse by setting each bit to "1". The additional pulses are inserted in the positions listed
in Table 14-10. PWMAD 3 to 0 can be combined to specify the number of times of inserting the additional
pulses in 16 cycles to any number from 1 to 16. Examples of inserting additional pulses are shown in Figure 14-13.
RA002
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TMP89FM46
Table 14-10 Cycles in Which Additional Pulses Are Inserted
Cycles in which additional pulses are inserted among
cycles 1 to 16
PWMAD0="1"
9
PWMAD1="1"
5, 13
PWMAD2="1"
3, 7, 11, 15
PWMAD3="1"
2, 4, 6, 8, 10, 12, 14, 16
Set the initial state of the PWM1 pin at T01MOD<TFF1>. Setting T01MOD<TFF1> to "0" selects the
"L" level as the initial state of the PWM1 pin. Setting T01MOD<TFF1> to "1" selects the "H" level as the
initial state of the PWM1 pin. If the PWM1 pin is set as the function output pin in the port setting while the
timer is stopped, the value of T01MOD<TFF1> is output to the PWM1 pin. Table 14-11 shows the list of
output levels of the PWM1 pin.
Table 14-11 List of Output Levels of PWM1 Pin
PWM1pin output level
Before the start
of operation
(initial state)
PWMDUTY
matched
(after the additional pulse)
Overflow
Operation
stopped
(initial state)
0
L
H
L
L
1
H
L
H
H
TFF1
RA002
Page 185
14. 8-bit Timer Counter (TC0)
TMP89FM46
Additional
pulse
Additional
pulse
Timer start
Timer stop
PWM1 pin output
(TFF1=“1”)
PWM1 pin output
(TFF1=“0”)
INTT00 interrupt
request
INTT01 interrupt
request
Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
When PWMAD1=“1”
Additional
pulse
Timer start
Additional
pulse
Additional
pulse
Additional
pulse
Additional
pulse
Timer stop
PWM1 pin output
(TFF1=“1”)
PWM1 pin output
(TFF1=“0”)
INTT00 interrupt
request
INTT01 interrupt
request
Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
When PWMAD0 = “1” and PWMAD2 = “1”
Figure 14-13 Examples of Inserting Additional Pulses
14.4.7.2 Operations
Setting T001CR<T01RUN> to "1" allows the up counter to increment based on the selected source
clock. When a match between the lower 8 bits of the up counter value and the value set to PWMDUTY is
detected, the output of the PWM1 pin is reversed. When T01MOD<TFF1> is "0", the PWM1 pin changes
from the "L" to "H" level. When T01MOD<TFF1> is "1", the PWM1 pin changes from the "H" to "L"
level.
If any of PWMAD3 to 0 is "1", an additional pulse that corresponds to 1 count of the source clock is
inserted in specific cycles of the duty pulse. In other words, the PWM1 pin output is reversed at the timing
of PWMDUTY+1. When T00MOD<TFF0> is "0", the period of the "L" level becomes longer than the
value set to PWMDUTY by 1 source clock. When T00MOD<TFF0> is "1", the period of the "H" level
becomes longer than the value set to PWMDUTY by 1 source clock. This function allows 16 cycles of
output pulses to be handled with a resolution nearly equivalent to 12 bits.
No additional pulse is inserted when PWMAD3 to 0 are all "0".
Subsequently, the up counter continues counting up. When the up counter value reaches 256, an overflow occurs and the up counter is cleared to "0x00". At the same time, the output of the PWM1 pin is
reversed. When T01MOD<TFF1> is "0", the PWM1 pin changes from the "H" to "L" level. When
T01MOD<TFF1> is "1", the PWM1 pin changes from the "L" to "H" level. At this time, an INTT00 inter-
RA002
Page 186
TMP89FM46
rupt request is generated (an INTT00 interrupt request is generated each time an overflow occurs.) An
INTT01 interrupt request is generated at the 16 × n-th overflow (n=1, 2, 3...). Subsequently, the up counter
continues counting up.
When T001CR<T01RUN> is set to "0" during the timer operation, the up counter is stopped and
cleared to "0x00". The PWM1 pin returns to the level selected at T01MOD<TFF1>.
When an external source clock is selected, input the clock at the TC00 pin. The maximum frequency to
be supplied is fcgck/2 [Hz] (in NORMAL1/2 or IDLE1/2 mode) or fs/24 [Hz] (in SLOW1/2 or SLEEP1
mode), and a pulse width of two machine cycles or more is required at both the "H" and "L" levels.
Timer start
(Duty pulse
width)
PWMDUTY
Additional
pulse
(1 source clock)
(Duty pulse
width)
PWMDUTY
PWM1 pin output
(TFF0=“1”)
PWM1 pin output
(TFF0=“0”)
256 counts
(cycle width)
256 counts
(cycle width)
Figure 14-14 PWM1 Pin Output
14.4.7.3 Double buffer
The double buffer can be used for T01+00PWM by setting T01MOD<DBE1>. The double buffer is disabled by setting T01MOD<DBE1> to "0" or enabled by setting T01MOD<DBE1> to "1".
• When the double buffer is enabled
When write instructions are executed on T00PWM and T01PWM in this order during the
timer operation, the set value is first stored in the double buffer, and T01+00PWM is not
updated immediately. T01+00PWM compares the previous set value with the up counter value.
When the 16 × n-th overflow occurs, an INTT01 interrupt request is generated and the double
buffer set value is stored in T01+00PWM. Subsequently, the match detection is executed using
a new set value.
When a read instruction is executed on T01+00PWM (T00REG), the value in the double
buffer (the last set value) is read out, not the T01+00PWM value (the currently effective value).
When write instructions are executed on T00PWM and T01PWM in this order while the
timer is stopped, the set value is immediately stored in both the double buffer and
T01+00PWM.
• When the double buffer is disabled
When write instructions are executed on T00PWM and T01PWM in this order during the
timer operation, the set value is immediately stored in T01+00PWM. Subsequently, the match
detection is executed using a new set value. If the value set to T01+00PWM is smaller than the
up counter value, the PWM1 pin is not reversed until the up counter overflows and a match
detection is executed using a new set value. If the value set to T01+00PWM is equal to the up
counter value, the match detection is executed immediately after data is written into
T01+00PWM. Therefore, the timing of changing the PWM1 pin may not be an integral multiple
of the source clock. Similarly, if T01+00PWM is set during the additional pulse output, the timing of changing the PWM1 pin may not be an integral multiple of the source clock. If these are
problems, enable the double buffer.
RA002
Page 187
14. 8-bit Timer Counter (TC0)
TMP89FM46
When write instructions are executed on T00PWM and T01PWM in this order while the
timer is stopped, the set value is immediately stored in T01+00PWM.
(Example)
Operate TC00 and TC01 in the 12-bit PWM mode with the operation clock of fcgck/2 and output a duty pulse nearly equivalent to 14.0625 µs in 51.2µs cycles (fcgck = 10 MHz)
(Actually, output a duty pulse of 225 µs in total in 16 cycles (819.2 µs))
SET
(P7FC).1
; Sets P7FC1 to "1"
SET
(P7CR).1
; Sets P7CR1 to "1"
LD
(POFFCR0),0x10
; Sets TC001EN to "1"
DI
; Sets the interrupt master enable flag to "disable"
SET
(EIRH).4
; Sets the INTTC00 interrupt enable register to "1"
EI
; Sets the interrupt master enable flag to "enable"
LD
(T01MOD),0xF2
; Selects the 16-bit PWM mode and fcgck/2
LD
(T00PWM),0x65
; Sets the timer register (duty pulse)
; (14.0625µs × 16) / (2/fcgck) = 0x465
LD
(T00PWM),0x04
; Sets the timer register (duty pulse)
LD
(T001CR),0x06
; Starts TC00 and TC01
Timer start
T001CR<T00RUN>
T00MOD<TFF0>
Source clock
Counter
0
Overflow
256
0 1
km km
+1
1
km km
+1
Counter
clear
Write to T00PWM
Write to T01PWM
Overflow
256
0 1
Overflow
256
0 1
km km
+1
Counter
clear
256
0 1
km km
+1
Counter
clear
Write s (0011)
Write m (0001)
Write k
rs
Counter
clear
Write r
Double buffer
km (0001)
PWMAD3 ~ 0
0001
PWMDUTY
km
rs (0011)
0011
Match detection
Match detection
Match detection rs
Match detection
PWM0 pin output
INTT00 interrupt request
Becomes the level selected at
TFF0 while the timer is stopped
Additional pulse
Interrupt request
Interrupt request
Interrupt request
Interrupt reques
INTT00 interrupt request
km
(Duty pulse)
256 counts
(Cycle 1)
km
(Duty pulse)
256 counts
(Cycle 2)
km+1
(Duty pulse)
km
(Duty pulse)
256 counts
(Cycle 9)
When the double buffer is enabled (T01MOD<DBE1>=”1”)
Figure 14-15 12-bit PWM Mode Timing Chart
RA002
Page 188
256 counts
(Cycle 16)
rs
(Duty pulse)
(Cycle 17)
TMP89FM46
Table 14-12 Resolutions and Cycles in the 12-bit PWM Mode
Source clock [Hz]
T01MOD
<TCK1>
RA002
8-bit cycle
(period × 16)
Resolution
NORMAL1/2 or IDLE1/2 mode
SLOW1/2 or
SLEEP1 mode
fcgck=10MHz
fs=32.768KHz
fcgck=10MHz
fs=32.768KHz
fs/24
fs/24
204.8µs
488.2µs
52.4ms
(838.9ms)
125ms
(2000ms)
fcgck/210
fs/23
fs/23
102.4µs
244.1µs
26.2ms
(419.4ms)
62.5ms
(1000ms)
010
fcgck/28
fcgck/28
-
25.6µs
-
6.6ms
(104.9ms)
-
011
fcgck/26
fcgck/26
-
6.4µs
-
1.6ms
(26.2ms)
-
100
fcgck/24
fcgck/24
-
1.6µs
-
409.6µs
(6.6ms)
-
101
fcgck/22
fcgck/22
-
400ns
-
102.4µs
(1.6ms)
-
110
fcgck/2
fcgck/2
-
200ns
-
51.2µs
(819.2µs)
-
111
fcgck
fcgck
fs/22
100ns
122.1µs
25.6µs
(409.6µs)
31.3ms
(500ms)
SYSCR1<DV9CK>
= "0"
SYSCR1<DV9CK>
= "1"
000
fcgck/211
001
Page 189
14. 8-bit Timer Counter (TC0)
TMP89FM46
14.4.8 16-bit programmable pulse generate (PPG) output mode
In the 16-bit PPG mode, TC00 and TC01 are cascaded to output the pulses that have a resolution of 16 bits
and arbitrary pulse width and duty. Two 16-bit registers, T01+00REG and T01+00PWM, are used to output the
pulses. This enables output of longer pulses than an 8-bit timer.
14.4.8.1 Setting
Setting T001CR<TCAS> to "1" connects TC00 and TC01 and activates the 16-bit mode. All the settings of TC00 are ignored and those of TC01 are effective in the 16-bit mode.
The 16-bit PPG mode is selected by setting T01MOD<TCM1> to "11". To use the internal clock as the
source clock, set T01MOD<EIN1> to "0" and select the clock at T01MOD<TCK1>. To use an external
clock as the source clock, set T01MOD<EIN0> to "1".
Set T01MOD<DBE1> to "1" to use the double buffer.
Set the count value that corresponds to a cycle as a 16-bit value at the timer registers T01REG and
T00REG. Set the count value that corresponds to a duty pulse as a 16-bit value at T01PWM and T00PWM
(hereinafter, the 16-bit value specified by the combined setting of T01REG and T00REG is indicated as
T01+00REG, and the 16-bit value specified by the combined setting of T01PWM and T00PWM is indicated as T01+00PWM). The timer register settings are reflected on the double buffer or T01+00PWM and
T01+00REG when a write instruction is executed on T01PWM. Be sure to execute the write instructions
on T00REG, T01REG and T00PWM before executing a write instruction on T01PWM. (When data is
written to T01PWM, the set values of the four timer registers become effective at the same time.)
Set the initial state of the PPG1 pin at T01MOD<TFF1>. Setting T01MOD<TFF1> to "0" selects the
"L" level as the initial state of the PPG1 pin. Setting T01MOD<TFF1> to "1" selects the "H" level as the
initial state of the PPG1 pin. If the PPG1 pin is set as the function output pin in the port setting while the
timer is stopped, the value of T01MOD<TFF1> is output to the PPG1 pin. Table 14-13 shows the list of
output levels of the PPG1 pin.
Table 14-13 List of Output Levels of PPG1 Pin
PPG1 pin output level
TFF1
Before the start
of operation
(initial state)
T01+00PWM
matched
T01+00REG
matched
Operation
stopped
(initial state)
0
L
H
L
L
1
H
L
H
H
14.4.8.2 Operations
Setting T001CR<T01RUN> to "1" allows the up counter to increment based on the selected source
clock. When a match between the up counter value and the value set to T01+00PWM is detected, the output of the PPG1 pin is reversed. When T01MOD<TFF1> is "0", the PPG1 pin changes from the "L" to "H"
level. When T01MOD<TFF1> is "1", the PPG1 pin changes from the "H" to "L" level. At this time, an
INTT00 interrupt request is generated.
The up counter continues counting up. When a match between the up counter value and the value set to
T01+00REG is detected, the output of the PPG1 pin is reversed again. When T01MOD<TFF1> is "0", the
PPG1 pin changes from the "H" to "L" level. When T01MOD<TFF1> is "1", the PPG1 pin changes from
the "L" to "H" level. At this time, an INTT01 interrupt request is generated and the up counter is cleared to
"0x0000".
When T001CR<T01RUN> is set to "0" during the timer operation, the up counter is stopped and
cleared to "0x0000". The PPG1 pin returns to the level selected at T01MOD<TFF1>.
RA002
Page 190
TMP89FM46
When an external source clock is selected, input the clock at the TC00 pin. The maximum frequency to
be supplied is fcgck/2 [Hz] (in NORMAL1/2 or IDLE1/2 mode) or fs/24 [Hz] (in SLOW1/2 or SLEEP1
mode), and a pulse width of two machine cycles or more is required at both the "H" and "L" levels.
14.4.8.3 Double buffer
The double buffer can be used for T01+00PWM and T01+00REG by setting T01MOD<DBE1>. The
double buffer is enabled by setting T01MOD<DBE1> to "0" or disabled by setting T01MOD<DBE1> to
"1".
• When the double buffer is enabled
When a write instruction is executed on T01PWM after write instructions are executed on
T00REG, T01REG and T00PWM during the timer operation, the set values are first stored in
the double buffer, and T01+00PWM and T01+00REG are not updated immediately.
T01+00PWM and T01+00REG compare the previous set values with the up counter value.
When a match between the up counter value and the T01+00REG set value is detected, an
INTT01 interrupt request is generated and the double buffer set values are stored in
T01+00PWM and T01+00REG. Subsequently, the match detection is executed using new set
values.
When a write instruction is executed on T01PWM after write instructions are executed on
T00REG, T01REG and T00PWM while the timer is stopped, the set values are immediately
stored in both the double buffer and T01+00PWM and T01+00REG.
• When the double buffer is disabled
When a write instruction is executed on T01PWM after write instructions are executed on
T00REG, T01REG and T00PWM during the timer operation, the set values are immediately
stored in T01+00PWM and T01+00REG. Subsequently, the match detection is executed using
new set values.
If the value set to T01+00PWM or T01+00REG is smaller than the up counter value, the
PPG1 pin is not reversed until the up counter overflows and a match detection is executed using
a new set value. If the value set to T01+00PWM or T01+00REG is equal to the up counter
value, the match detection is executed immediately after data is written into T01+00PWM and
T01+00REG. Therefore, the timing of changing the PPG1 pin may not be an integral multiple of
the source clock. If these are problems, enable the double buffer.
When a write instruction is executed on T01PWM after write instructions are executed on
T00REG, T01REG and T00PWM while the timer is stopped, the set values are immediately
stored in T01+00PWM and T01+00REG.
When read instructions are executed on T01+00PWM and T01+00REG, the last value written into
T01+00REG is read out, regardless of the T00MOD<DBE1> setting.
(Example)
Operate TC00 and TC01 in the 16-bit PPG mode with the operation clock of fcgck/2 and output the 68µs duty pulse in 96µs
cycles (fcgck = 10 MHz)
SET
(P7FC).1
; Sets P7FC0 to "1"
SET
(P7CR).1
; Sets P7CR0 to "1"
LD
(POFFCR0),0x10
DI
SET
(EIRH).4
EI
RA002
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
LD
(T01MOD),0xF3
; Selects the 8-bit PPG mode and fcgck/2
LD
(T00REG),0xE0
; Sets the timer register (cycle)
LD
(T01REG),0x01
; Sets the timer register (cycle)
; 96µs / (2/fcgck) = 0x01E0
LD
(T00PWM),0x54
; Sets the timer register (duty pulse)
LD
(T01PWM),0x01
; Sets the timer register (duty pulse)
; 68µs / (2/fcgck) = 0x0154
Page 191
14. 8-bit Timer Counter (TC0)
TMP89FM46
LD
(T001CR),0x06
; Starts TC00 and TC01
Timer start
Timer stop
T001CR<T01RUN>
T01MOD<TFF1>
Source clock
cd
ab
Counter
0
gh
gh +1
1
km km
+1
0 1
Counter
clear
Write to T00REG
Write to T01REG
Write b
Double buffer
ab
T01+00REG
ab
Write to T00PWM
Write to T01PWM
Write c
Write h
Double buffer
gh
T01+00PWM
gh
0
Counter
clear
ef
cd
Match detection
Match detection
Write m
Write g
Counter
clear
0 1
Write e
cd
Match detection
ef
qr
qr +1
0 1
Counter
clear
Write f
Write d
Write a
cd
km km
+1
0 1
ef
Match detection
Write r
Write k
Write q
km
qr
Match detection km
Match detection qr
Match detection
Match detection
PPG1 pin output
INTT00 interrupt
request
INTT00 interrupt
request
Returns to the
level selected
at TFF1
Becomes the level selected at
TFF1 while the timer is stopped
gh
(Duty pulse)
ab
(Cycle 1)
km
(Duty pulse)
cd
(Cycle 1)
km
(Duty pulse)
cd
(Cycle 1)
qr
(Duty pulse)
ef
(Cycle 1)
When the double buffer is enabled (T01MOD<DBE1>=”1”)
Figure 14-16 16-bit PPG Output Mode Timing Chart
RA002
Page 192
TMP89FM46
15. Real Time Clock (RTC)
The real time clock is a function that generates interrupt requests at certain intervals using the low-frequency
clock.
The number of interrupts is counted by the software to realize the clock function.
The real time clock can be used only in the operation modes where the low-frequency clock oscillates, except for
SLEEP0.
15.1 Configuration
RTCCR
RTCRUN
INTRTC
interrupt request
Selector
RTCSEL
15
14
13
12
11
2 /fs 2 /fs 2 /fs 2 /fs 2 /fs
fs
(32.768 kHz)
10
9
2 /fs 2 /fs
8
2 /fs
Binary counter
Figure 15-1 Real Time Clock
15.2 Control
The real time clock is controlled by following resisters.
Low power consumption register 2
POFFCR2
(0x0F76)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
RTCEN
-
-
-
-
SIO0EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
2
1
RTCEN
RTC control
0
1
Disable
Enable
SIO0EN
SIO0 control
0
1
Disable
Enable
Real time clock control register
RTCCR
(0x0FC8)
RA000
7
6
5
4
Bit Symbol
-
-
-
-
Read/Write
R
R
R
R
After reset
0
0
0
0
Page 193
3
RTCSEL
R/W
0
0
0
RTCRUN
R/W
0
0
15. Real Time Clock (RTC)
15.3 Function
TMP89FM46
000 : 215/fs (1.000 [s] @fs=32.768kHz)
001 : 214/fs (0.500 [s] @fs=32.768kHz)
010 : 213/fs (0.250 [s] @fs=32.768kHz)
RTCSEL
Selects the interrupt generation interval
011 : 212/fs (125.0 [ms] @fs=32.768kHz)
100 : 211/fs (62.50 [ms] @fs=32.768kHz)
101 : 210/fs (31.25 [ms] @fs=32.768kHz)
110 : 29/fs (15.62 [ms] @fs=32.768kHz)
111 : 28/fs (7.81 [ms] @fs=32.768kHz)
RTCRUN
Enables/disables the real time clock operation
0 : Disable
1 : Enable
Note 1: fs: Low-frequency clock [Hz]
Note 2: RTCCR<RTCSEL> can be rewritten only when RTCCR<RTCRUN> is "0". If data is written into RTCCR<RTCSEL> when RTCCR<RTCRUN> is "1", the existing data remains effective. RTCCR<RTCSEL> can be rewritten at
the same time as enabling the real time clock, but it cannot be rewritten at the same time as disabling the real time
clock.
Note 3: If the real time clock is enabled and when 1) SYSCR2<XTEN> is cleared to "0" to stop the low-frequency clock
oscillation circuit or 2) the operation is changed to the STOP mode or the SLEEP0 mode, the data in
RTCCR<RTCSEL> is maintained and RTCCR<RTCRUN> is cleared to "0".
15.3 Function
15.3.1 Low Power Consumption Function
Real time clock has the low power consumption registers (POFFCR2) that save power when the real time
clock is not being used.
Setting POFFCR2<RTCEN> to "0" disables the basic clock supply to real time clock to save power. Note
that this renders the real time clock unusable. Setting POFFCR2<RTCEN> to "1" enables the basic clock supply to real time clock and allows the real time clock to operate.
After reset, POFFCR2<RTCEN> are initialized to "0", and this renders the real time clock unusable. When
using the real time clock for the first time, be sure to set POFFCR2<RTCEN> to "1" in the initial setting of the
program (before the real time clock control registers are operated).
Do not change POFFCR2<RTCEN> to "0" during the real time clock operation. Otherwise real time clock
may operate unexpectedly.
15.3.2 Enabling/disabling the real time clock operation
Setting RTCCR<RTCRUN> to "1" enables the real time clock operation. Setting RTCCR<RTCRUN> to "0"
disables the real time clock operation.
RTCCR<RTCRUN> is cleared to "0" just after reset release.
15.3.3 Selecting the interrupt generation interval
The interrupt generation interval can be selected at RTCCR<RTCSEL>.
RTCCR<RTCSEL> can be rewritten only when RTCCR<RTCRUN> is "0". If data is written into
RTCCR<RTCSEL> when RTCCR<RTCRUN> is "1", the existing data remains effective.
RTCCR<RTCSEL> can be rewritten at the same time as enabling the real time clock operation, but it cannot
be rewritten at the same time as disabling the real time clock operation.
RA000
Page 194
TMP89FM46
15.4 Real Time Clock Operation
15.4.1 Enabling the real time clock operation
Set the interrupt generation interval to RTCCR<RTCSEL>, and at the same time, set RTCCR<RTCRUN> to
"1".
When RTCCR<RTCRUN> is set to "1", the binary counter for the real time clock starts counting of the lowfrequency clock.
When the interrupt generation interval selected at RTCCR<RTCSEL> is reached, a real time clock interrupt
request (INTRTC) is generated and the counter continues counting.
15.4.2 Disabling the real time clock operation
Clear RTCCR<RTCRUN> to "0".
When RTCCR<RTCRUN> is cleared to "0", the binary counter for the real time clock is cleared to "0" and
stops counting of the low-frequency clock.
RA000
Page 195
15. Real Time Clock (RTC)
15.4 Real Time Clock Operation
RA000
TMP89FM46
Page 196
TMP89FM46
16. Asynchronous Serial Interface (UART)
The TMP89FM46 contains 2 channels of asynchronous serial interfaces (UART).
This chapter describes asynchronous serial interface 0 (UART0). For UART1, replace the SFR addresses and pin
names as shown in Table 16-1 and Table 16-2.
Table 16-1 SFR Address Assignment
UARTxCR1
(address)
UARTxCR2
(address)
UARTxDR
(address)
UARTxSR
(address)
RDxBUF
(address)
TDxBUF
(address)
UART0
UART0CR1
(0x001A)
UART0CR2
(0x001B)
UART0DR
(0x001C)
UART0SR
(0x001D)
RD0BUF
(0x001E)
TD0BUF
(0x001E)
UART1
UART1CR1
(0x0F54)
UART1CR2
(0x0F55)
UART1DR
(0x0F56)
UART1SR
(0x0F57)
RD1BUF
(0x0F58)
TD1BUF
(0x0F58)
Table 16-2 Pin Names
RA001
Serial data
input pin
Serial data
output pin
UART0
RXD0 pin
TXD0 pin
UART1
RXD1 pin
TXD1 pin
Page 197
16. Asynchronous Serial Interface (UART)
16.1 Configuration
TMP89FM46
16.1 Configuration
UART0 control register 1
UART0CR1
UART0 transmit data buffer
UART0CR1
UART0 receive data buffer
RD0BUF
Receive control circuit
INTTXD0
interrupt request
2
Transmit control circuit
2
Shift register
Shift register
Parity bit
Stop bit
INTRXD0
interrupt request
TXD0
IrDA control
Baud rate
generator
S
Counter
Y
Transmit
RT clock
Transmission start
Counter
Y
Receive
RT clock
Selector
A
B
S
A
B
PPGA0 output
(TCA0 output)
RXD0
Noise rejection circuit
Y
A
B
C
fcgck/26
7
Frequency
fcgck/2
divider 8
fcgck/2
S
2 4
2
EN
UART0SR
8-bit counter
fcgck or fs
UART0 status
register
8-bit counter
EN
Start bit
detection
Comparator
Comparator
UART0CR2
UART0 control register 2
Match
detection
Match detection
UART0DR
UART0 baud rate register
Figure 16-1 Asynchronous Serial Interface (UART)
RA001
Page 198
TMP89FM46
16.2 Control
UART0 is controlled by the low power consumption registers (POFFCR1), UART0 control registers 1 and 2
(UART0CR1 and UART0CR2) and the UART0 baud rate register (UART0DR). The operating status can be monitored using the UART status register (UART0SR).
Low power consumption register 1
POFFCR1
(0x0F75)
7
5
4
3
2
1
0
Bit Symbol
-
-
-
SBI0EN
-
-
UART1EN
UART0EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
I2C0 control
0
1
Disable
Enable
UART1EN
UART1 control
0
1
Disable
Enable
UART0EN
UART0 control
0
1
Disable
Enable
SBI0EN
RA001
6
Page 199
16. Asynchronous Serial Interface (UART)
16.2 Control
TMP89FM46
UART0 control register 1
UART0CR1
(0x001A)
7
6
5
4
3
2
1
0
Bit Symbol
TXE
RXE
STOPBT
EVEN
PE
IRDASEL
BRG
-
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
After reset
0
0
0
0
0
0
0
0
TXE
Transmit operation
0:
1:
Disable
Enable
RXE
Receive operation
0:
1:
Disable
Enable
Transmit stop bit length
0:
1:
1 bit
2 bits
EVEN
Parity selection
0:
1:
Odd-numbered parity
Even-numbered parity
PE
Parity addition
0:
1:
No parity
Parity added
TXD pin output selection
0:
1:
UART output
IrDA output
STOPBT
IRDASEL
BRG
Transfer base clock selection
When SYSCR2<SYSCK> is "0"
When SYSCR2<SYSCK> is "1"
fcgck
fs
0:
1:
TCA0 output
Note 1: fcgck, Gear clock; fs, Low-frequency clock
Note 2: If the TXE or RXE bit is set to "0" during the transmission or receiving of data, the operation is not disabled until the data
transfer is completed. At this time, the data stored in the transmit data buffer is discarded.
Note 3: EVEN, PE and BRG settings are common to transmission and receiving.
Note 4: Set RXE and TXE to "0" before changing BRG.
Note 5: When BRG is set to the TCA0 output, the RT clock becomes asynchronous and the start bit of the transmitted/received
data may get shorter by a maximum of (UART0DR+1)/(Transfer base clock frequency)[s].
If the pin is not used for the TCA0 output, control the TCA0 output by using the port function control register.
Note 6: To prevent STOPBT, EVEN, PE, IRDASEL and BRG from being changed accidentally during the UART communication,
the register cannot be rewritten during the UART operation. For details, refer to "16.4 Protection to Prevent UART0CR1
and UART0CR2 Registers from Being Changed".
Note 7: When the STOP, IDLE0 or SLEEP0 mode is activated, TXE and RXE are cleared to "0" and the UART stops. Other bits
keep their values.
RA001
Page 200
TMP89FM46
UART0 control register 2
UART0CR2
(0x001B)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
RTSEL
RXDNC
STOPBR
Read/Write
R
R
R/W
R/W
R/W
After reset
0
0
RTSEL
0
Selects the number of RT clocks
RXDNC
Selects the RXD input noise rejection time
(Time of pulses to be removed as
noise)
STOPBR
Receive stop bit length
0
0
0
0
0
Odd-numbered bits
of transfer frame
Even-numbered bits
of transfer frame
000:
16 clocks
16 clocks
001:
16 clocks
17 clocks
010:
15 clocks
15 clocks
011:
15 clocks
16 clocks
100:
17 clocks
17 clocks
101:
Reserved
11*:
Reserved
00:
01:
10:
11:
0:
1:
No noise rejection
1 x (UART0DR+1)/(Transfer base clock frequency) [s]
2 x (UART0DR+1)/(Transfer base clock frequency) [s]
4 x (UART0DR+1)/(Transfer base clock frequency) [s]
1 bit
2 bits
Note 1: When a read instruction is executed on UART0CR2, bits 7 and 6 are read as "0".
Note 2: RTSEL can be set to two kinds of RT clocks for the even- and odd-numbered bits of the transfer frame. For details, refer to
"16.8.1 Transfer baud rate calculation method".
Note 3: For details of the RXDNC noise rejection time, refer to "16.10 Received Data Noise Rejection".
Note 4: When the STOP, IDLE0 or SLEEP0 mode is activated, the UART stops automatically but each bit value of UART0CR2
remains unchanged.
Note 5: When STOPBR is set to 2 bits, the first bit of the stop bits (during data receiving) is not checked for a framing error.
Note 6: To prevent RTSEL, RXDNC and STOPBR from being changed accidentally during the UART communication, the register
cannot be rewritten during the UART operation. For details, refer to "16.4 Protection to Prevent UART0CR1 and
UART0CR2 Registers from Being Changed".
UART0 baud rate register
UART0DR
(0x001C)
7
6
5
4
3
2
1
0
Bit Symbol
UART0DR7
UART0DR6
UART0DR5
UART0DR4
UART0DR3
UART0DR2
UART0DR1
UART0DR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
Note 1: Set UART0CR1<RXE> and UART0CR1<TXE> to "0" before changing UART0DR. For the set values, refer to "16.8 Transfer Baud Rate".
Note 2: When UART0CR1<BRG> is set to the TCA0 output, the value set to UART0DR has no meaning.
Note 3: When the STOP, IDLE0 or SLEEP0 mode is activated, the UART stops automatically but each bit value of UART0DR
remains unchanged.
UART0 status register
UART0SR
(0x001D)
RA001
7
6
5
4
3
2
1
0
Bit Symbol
PERR
FERR
OERR
-
RBSY
RBFL
TBSY
TBFL
Read/Write
R
R
R
R
R
R
R
R
After reset
0
0
0
0
0
0
0
0
Page 201
16. Asynchronous Serial Interface (UART)
16.2 Control
TMP89FM46
PERR
Parity error flag
0:
1:
No parity error
Parity error
FERR
Framing error flag
0:
1:
No framing error
Framing error
OERR
Overrun error flag
0:
1:
No overrrun error
Overrun error
RBSY
Receive busy flag
0:
1:
Before receiving or end of receiving
On receiving
RBFL
Receive buffer full flag
0:
1:
Receive buffer empty
Receive buffer full
TBSY
Transmit busy flag
0:
1:
Before transmission or end of transmission
On transmitting
TBFL
Transmit buffer full flag
0:
1:
Transmit buffer empty
Transmit buffer full (Transmit data writing is completed)
Note 1: TBFL is cleared to "0" automatically after an INTTXD0 interrupt request is generated, and is set to "1" when data is set to
TD0BUF.
Note 2: When a read instruction is executed on UART0SR, bit 4 is read as "0".
Note 3: When the STOP, IDLE0 or SLEEP0 mode is activated, each bit of UART0SR is cleared to "0" and the UART stops.
UART0 receive data buffer
RD0BUF
(0x001E)
7
6
5
4
3
2
1
0
Bit Symbol
RD0DR7
RD0DR6
RD0DR5
RD0DR4
RD0DR3
RD0DR2
RD0DR1
RD0DR0
Read/Write
R
R
R
R
R
R
R
R
After reset
0
0
0
0
0
0
0
0
Note 1: When the STOP, IDLE0 or SLEEP0 mode is activated, the RD0BUF values become undefined. If received data is
required, read it before activating the mode.
UART0 transmit data buffer
TD0BUF
(0x001E)
7
6
5
4
3
2
1
0
Bit Symbol
TD0DR7
TD0DR6
TD0DR5
TD0DR4
TD0DR3
TD0DR2
TD0DR1
TD0DR0
Read/Write
W
W
W
W
W
W
W
W
After reset
0
0
0
0
0
0
0
0
Note 1: When the STOP, IDLE0 or SLEEP0 mode is activated, the TD0BUF values become undefined.
RA001
Page 202
TMP89FM46
16.3 Low Power Consumption Function
UART0 has a low power consumption register (POFFCR1) that saves power consumption when the UART function is not used.
Setting POFFCR1<UART0EN> to "0" disables the basic clock supply to UART0 to save power. Note that this renders the UART unusable. Setting POFFCR1<UART0EN> to "1" enables the basic clock supply to UART0 and renders the UART usable.
After reset, POFFCR1<UART0EN> is initialized to "0", and this renders the UART unusable. When using the
UART for the first time, be sure to set POFFCR1<UART0EN> to "1" in the initial setting of the program (before the
UART control register is operated).
Do not change POFFCR1<UART0EN> to "0" during the UART operation, otherwise UART0 may operate unexpectedly.
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16. Asynchronous Serial Interface (UART)
16.4 Protection to Prevent UART0CR1 and UART0CR2 Registers from Being Changed
TMP89FM46
16.4 Protection to Prevent UART0CR1 and UART0CR2 Registers from Being
Changed
The TMP89FM46 has a function that protects the registers from being changed so that the UART communication
settings (for example, stop bit and parity) are not changed accidentally during the UART operation.
Specific bits of UART0CR1 and UART0CR2 can be changed only under the conditions shown in Table 16-3. If a
write instruction is executed on the register when it is protected from being changed, the bits remain unchanged and
keep their previous values.
Table 16-3 Changing of UART0CR1 and UART0CR2
Conditions that allow the bit to be changed
Bit to be changed
Function
UART0CR1<STOPBT>
Transmit stop bit length
UART0CR1<EVEN>
Parity selection
UART0CR1<PE>
Parity addition
UART0CR1<IRDASEL>
TXD pin output selection
UART0CR1<BRG>
Transfer base clock selection
UART0CR2<RTSEL>
Selection of number of RT
clocks
UART0CR2<RXDNC>
Selection of RXD pin input
noise rejection time
UART0CR2<STOPBR>
Receive stop bit length
UART0CR1
<TXE>
UART0SR
<TBSY>
Both of these bits are "0"
UART0CR1
<RXE>
UART0SR
<RBSY>
-
-
All of these bits are "0"
Both of these bits are "0"
-
-
All of these bits are "0"
RA001
-
Page 204
-
Both of these bits are "0"
TMP89FM46
16.5 Activation of STOP, IDLE0 or SLEEP0 Mode
16.5.1 Transition of register status
When the STOP, IDLE0 or SLEEP0 mode is activated, the UART stops automatically and each register
becomes the status as shown in Table 16-4. For the registers that do not hold their values, make settings again
as needed after the operation mode is recovered.
Table 16-4 Transition of Register Status
UART0CR1
7
6
5
4
3
2
1
0
TXE
RXE
STOPBT
EVEN
PE
IRDASEL
BRG
-
Cleared to
0
Cleared to
0
Hold the
value
Hold the
value
Hold the
value
Hold the
value
Hold the
value
-
-
-
-
-
Hold the
value
Hold the
value
Hold the
value
Hold the
value
Hold the
value
Hold the
value
PERR
FERR
OERR
-
RBSY
RBFL
TBSY
TBFL
Cleared to
0
Cleared to
0
Cleared to
0
-
Cleared to
0
Cleared to
0
Cleared to
0
Cleared to
0
UART0DR7
UART0DR6
UART0DR5
UART0DR4
UART0DR3
UART0DR2
UART0DR1
UART0DR0
Hold the
value
Hold the
value
Hold the
value
Hold the
value
Hold the
value
Hold the
value
Hold the
value
Hold the
value
RD0DR7
RD0DR6
RD0DR5
RD0DR4
RD0DR3
RD0DR2
RD0DR1
RD0DR0
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
TD0DR7
TD0DR6
TD0DR5
TD0DR4
TD0DR3
TD0DR2
TD0DR1
TD0DR0
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
RTSEL
UART0CR2
UART0SR
UART0DR
RD0BUF
TD0BUF
RXDNC
STOPBR
16.5.2 Transition of TXD pin status
When the IDLE0, SLEEP0 or STOP mode is activated, the TXD pin reverts to the status shown in Table 165, whether data is transmitted/received or the operation is stopped.
Table 16-5 TXD Pin Status When the STOP, IDLE0 or SLEEP0 Mode Is Activated
STOP mode
UART0CR1
<IRDASEL>
IDLE0 or SLEEP0 mode
"0"
H level
H level
"1"
L level
L level
SYSCR1<OUTEN>="1"
SYSCR1<OUTEN>="0"
Hi-Z
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16. Asynchronous Serial Interface (UART)
16.6 Transfer Data Format
TMP89FM46
16.6 Transfer Data Format
The UART transfers data composed of the following four elements. The data from the start bit to the stop bit is collectively defined as a "transfer frame". The start bit consists of 1 bit (L level) and the data consists of 8 bits. Parity
bits are determined by UART0CR1<PE> that selects the presence or absence of parity and UART0CR1<EVEN>
that selects even- or odd-numbered parity. The bit length of the stop bit can be selected at UART0CR1<STBT>.
Figure 16-2 shows the transfer data format.
• Start bit (1 bit)
• Data (8 bits)
• Parity bit (selectable from even-numbered, odd-numbered or no parity)
• Stop bit (selectable from 1 bit or 2 bits)
Transfer frame
PE
STBT
1
2
3
4
5
6
7
8
9
10
11
12
0
0
Start
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Stop 1
0
1
Start
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Stop 1 Stop 2
1
0
Start
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Parity Stop 1
1
1
Start
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Parity Stop 1 Stop 2
Figure 16-2 Transfer Data Format
16.7 Infrared Data Format Transfer Mode
The TXD0 pin can output data in the infrared data format (IrDA) by the setting of the IrDA output control register.
Setting UART0CR1<IRDASEL> to "1" allows the TXD0 pin to output data in the infrared data format.
Start bit
Stop bit
D0
UART output
D1
D2
D7
IrDA output
3/16
Bit width
Figure 16-3 Example of Infrared Data Format (Comparison between Normal Output and IrDA
Output)
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TMP89FM46
16.8 Transfer Baud Rate
The transfer baud rate of UART is set by UART0CR1<BRG>, UART0DR and UART0CR2<RTSEL>. Table 16-6
and Table 16-7 show the settings of UART0DR and UART0CR2<RTSEL> for general baud rates and operating frequencies.
For independent calculation of transfer baud rates, refer to "16.8.1 Transfer baud rate calculation method".
Table 16-6 Set Values of UART0DR and UART0CR2<RTSEL> for Transfer Baud Rates (fcgck=10 to 1 MHz,
UART0CR2<RXDNC>=0y00)
Basic
baud rate
[baud]
128000
115200
76800
62500
57600
38400
19200
9600
4800
2400
1200
RA001
Operating frequency
Register
10MHz
8MHz
7.3728
MHz
6.144
MHz
6MHz
5MHz
4.9152
MHz
4.19MHz
4MHz
2MHz
1MHz
UART0DR
0x04
0x03
-
0x02
0x02
-
-
0x01
0x01
0x00
-
RTSEL
0y011
0y011
-
0y000
0y011
-
-
0y001
0y011
0y011
-
Error
(+0.81%)
(+0.81%)
-
(0%)
(+0.81%)
-
-
(-0.80%)
(+0.81%)
(+0.81%)
-
UART0DR
0x04
0x03
0x03
-
0x02
-
-
-
0x01
0x00
-
RTSEL
0y100
0y100
0y000
-
0y100
-
-
-
0y100
0y100
-
Error
(+2.12%)
(+2.12%)
(0%)
-
(+2.12%)
-
-
-
(+2.12%)
(+2.12%)
-
UART0DR
0x07
0x06
0x05
0x04
0x04
0x03
0x03
-
0x02
-
-
RTSEL
0y001
0y010
0y000
0y000
0y011
0y001
0y000
-
0y100
-
-
Error
(-1.36%)
(-0.79%)
(0%)
(0%)
(+0.81%)
(-1.36%)
(0%)
-
(+2.12%)
-
-
UART0DR
0x09
0x07
0x06
0x05
0x05
0x04
0x04
0x03
0x03
0x01
0x00
RTSEL
0y000
0y000
0y100
0y001
0y000
0y000
0y011
0y100
0y000
0y000
0y000
Error
(0%)
(0%)
(-0.87%)
(-0.70%)
(0%)
(0%)
(+1.48%)
(-1.41%)
(0%)
(0%)
(0%)
UART0DR
0x0A
0x08
0x07
0x06
0x06
0x04
0x04
-
0x03
0x01
0x00
RTSEL
0y000
0y011
0y000
0y010
0y010
0y100
0y100
-
0y100
0y100
0y100
Error
(-1.36%)
(-0.44%)
(0%)
(+1.59%)
(-0.79%)
(+2.12%)
(+0.39%)
-
(+2.12%)
(+2.12%)
(+2.12%)
UART0DR
0x10
0x0C
0x0B
0x09
0x09
0x07
0x07
0x06
0x06
0x02
-
RTSEL
0y011
0y000
0y000
0y000
0y011
0y001
0y000
0y011
0y010
0y100
-
Error
(-1.17%)
(+0.16%)
(0%)
(0%)
(+0.81%)
(-1.36%)
(0%)
(+0.57%)
(-0.79%)
(+2.12%)
-
UART0DR
0x22
0x19
0x17
0x13
0x12
0x10
0x0F
0x0D
0x0C
0x06
0x02
RTSEL
0y010
0y000
0y000
0y000
0y001
0y011
0y000
0y011
0y000
0y010
0y100
Error
(-0.79%)
(+0.16%)
(0%)
(0%)
(-0.32%)
(-1.17%)
(0%)
(+0.57%)
(+0.16%)
(-0.79%)
(+2.12%)
UART0DR
0x40
0x30
0x2F
0x27
0x26
0x22
0x1F
0x1C
0x19
0x0C
0x06
RTSEL
0y000
0y100
0y000
0y000
0y000
0y010
0y000
0y010
0y000
0y000
0y010
Error
(+0.16%)
(+0.04%)
(0%)
(0%)
(+0.16%)
(-0.79%)
(0%)
(+0.34%)
(+0.16%)
(+0.16%)
(-0.79%)
UART0DR
0x8A
0x64
0x5F
0x4F
0x4D
0x40
0x3F
0x34
0x30
0x19
0x0C
RTSEL
0y010
0y001
0y000
0y000
0y000
0y000
0y000
0y001
0y100
0y000
0y000
Error
(-0.08%)
(+0.01%)
(0%)
(0%)
(+0.16%)
(+0.16%)
(0%)
(-0.18%)
(+0.04%)
(+0.16%)
(+0.16%)
UART0DR
0xF4
0xC9
0xBF
0x9F
0x92
0x8A
0x7F
0x6C
0x64
0x30
0x19
RTSEL
0y100
0y001
0y000
0y000
0y100
0y010
0y000
0y000
0y001
0y100
0y000
Error
(+0.04%)
(+0.01%)
(0%)
(0%)
(+0.04%)
(-0.08%)
(0%)
(+0.11%)
(+0.01%)
(+0.04%)
(+0.16%)
UART0DR
-
-
-
-
-
0xF4
0xFF
0xE8
0xC9
0x64
0x30
RTSEL
-
-
-
-
-
0y100
0y000
0y010
0y001
0y001
0y100
Error
-
-
-
-
-
(+0.04%)
(+0%)
(-0.10%)
(+0.01%)
(+0.01%)
(+0.04%)
Page 207
16. Asynchronous Serial Interface (UART)
16.8 Transfer Baud Rate
TMP89FM46
Table 16-7 Set Values of UART0DR and UART0CR2<RTSEL> for Transfer
Baud Rates (fs=32.768 kHz, UART0CR2<RXDNC>=0y00)
Basic baud
rate
[baud]
300
150
134
110
75
Operating frequency
Register
32.768 kHz
UART0DR
0x06
RTSEL
0y011
Error
(+0.67%)
UART0DR
0x0D
RTSEL
0y011
Error
(+0.67%)
UART0DR
0x0E
RTSEL
0y001
Error
(-1.20%)
UART0DR
0x11
RTSEL
0y001
Error
(+0.30%)
UART0DR
0x1C
RTSEL
0y010
Error
(+0.44%)
Note 1: The overall error from the basic baud rate must be within ±3%. Even if the overall error is within ±3%, the communication may fail due to factors such as frequency errors in external controllers (for example, a personal computer)
and oscillators and the load capacity of the communication pin.
16.8.1 Transfer baud rate calculation method
16.8.1.1 Bit width adjustment using UART0CR2<RTSEL>
The bit width of transmitted/received data can be finely adjusted by changing UART0CR2<RTSEL>.
The number of RT clocks per bit can be changed in a range of 15 to 17 clocks by changing
UART0CR2<RTSEL>. The RT clock is the transfer base clock, which is the pulses obtained by counting
the clock selected at UART0CR1<BRG> the number of times of (UART0DR set value) + 1. Especially,
when UART0CR2<RTSEL> is set to "0y001" or "0y011", two types of RT clocks alternate at each bit, so
that the pseudo baud rates of RT × 15.5 clocks and RT × 16.5 clocks can be generated. The number of RT
clocks per bit of transfer frame is shown in Figure 16-4.
For example, when fcgck is 4 [MHz], UART0CR2<RTSEL> is set to "0y000" and UART0DR is set to
"0x19", the baud rate calculated using the formula in Figure 16-4 is expressed as:
fcgck / (16 × (UART0DR + 1) = 9615 [baud]
These settings generate a baud rate close to 9600 [baud] (+0.16%).
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TMP89FM46
Transfer frame
PE
STBT
1
2
3
4
5
6
7
8
0
0
Start
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Stop 1
0
1
Start
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Stop 1 Stop 2
1
0
Start
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Parity Stop 1
1
1
Start
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Parity Stop 1 Stop 2
001
010
10
11
12
Number of RT clocks
RTSEL
000
9
16
16
15
16
17
15
16
16
15
16
17
15
16
16
15
16
17
15
16
16
17
16
15
15
Generated baud rate
16
16
15
16
17
15
16
16
15
16
17
15
16
16.5
15
011
15
16
15
16
15
16
15
16
15
16
15
16
15.5
100
17
17
17
17
17
17
17
17
17
17
17
17
17
fcgck
(UARTDR+1)
fcgck
(UARTDR+1)
fcgck
(UARTDR+1)
fcgck
(UARTDR+1)
fcgck
(UARTDR+1)
[baud]
[baud]
[baud]
[baud]
[baud]
*When BRG is set to fcgck
Figure 16-4 Fine Adjustment of Baud Rate Clock Using UART0CR2<RTSEL>
16.8.1.2 Calculation of set values of UART0CR2<RTSEL> and UART0DR
The set value of UART0DR for an operating frequency and baud rate can be calculated using the calculation formula shown in Figure 16-5. For example, to generate a basic baud rate of 38400 [baud] with
fcgck=4 [MHz], calculate the set value of UART0DR for each setting of UART0CR2<RTSEL> and compensate the calculated value to a positive number to obtain the generated baud rate as shown in Figure 166. Basically, select the set value of UART0CR2<RTSEL> that has the smallest baud rate error from
among the generated baud rates. In Figure 16-6, the setting of UART0CR2<RTSEL>="0y010" has the
smallest error among the calculated baud rates, and thus the generated baud rate is 38095 [baud] (−0.79%)
against the basic baud rate of 38400 [baud].
Note: The error from the basic baud rate should be accurate to within ±3%. Even if the error is within ±3%, the
communication may fail due to factors such as frequency errors of external controllers (for example, a
personal computer) and oscillators and the load capacity of the communication pin.
RTSEL
UARTDR set value
000
UARTDR =
001
UARTDR =
010
UARTDR =
011
UARTDR =
100
UARTDR =
fcgck [Hz]
16 A [baud]
fcgck [Hz]
16.5 A [baud]
fcgck [Hz]
15 A [baud]
fcgck [Hz]
15.5 A [baud]
fcgck [Hz]
17 A [baud]
1
1
1
1
1
Figure 16-5 UART0DR Calculation Method (When BRG Is Set to fcgck)
RA001
Page 209
16. Asynchronous Serial Interface (UART)
16.8 Transfer Baud Rate
TMP89FM46
RTSEL
UARTDR calculation
000
UARTDR =
001
UARTDR =
010
UARTDR =
011
UARTDR =
100
UARTDR =
4000000 [Hz]
16 38400 [baud]
4000000 [Hz]
16.5 38400 [baud]
4000000 [Hz]
15 38400 [baud]
4000000 [Hz]
15.5 38400 [baud]
4000000 [Hz]
17 38400 [baud]
Generated baud rate
1
≈6
1
≈5
1
≈6
1
≈6
1
≈5
4000000 [Hz]
16 (6 + 1)
4000000 [Hz]
16.5 (5 + 1)
4000000 [Hz]
15 (6 + 1)
4000000 [Hz]
15.5 (6 + 1)
4000000 [Hz]
17 (5 + 1)
35714 [baud] ( 6.99%)
40404 [baud] ( 5.22%)
38095 [baud] ( 0.79%)
36866 [baud] ( 3.99%)
39216 [baud] ( 2.12%)
Figure 16-6 Example of UART0DR Calculation
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TMP89FM46
16.9 Data Sampling Method
The UART receive control circuit starts RT clock counting when it detects a falling edge of the input pulses to the
RXD0 pin. 15 to 17 RT clocks are counted per bit and each clock is expressed as RTn (n=16 to 0). In a bit that has 17
RT clocks, RT16 to RT0 are counted. In a bit that has 16 RT clocks, RT15 to RT0 are counted. In a bit that has 15 RT
clocks, RT14 to RT0 are counted (Decrement). During counting of RT8 to RT6, the UART receive control circuit
samples the input pulses to the RXD0 pin to make a majority decision. The same level detected twice or more from
among three samplings is processed as the data for the bit.
The number of RT clocks can be changed in a range of 15 to 17 by setting UART0CR2<RTSEL>. However, sampling is always executed in RT8 to RT6, even if the number of RT clocks is changed (Figure 16-7).
RXD0 pin
Start Bit
Bit 0
RT15 14 13 12 11 10 9
8
7
6
5
4
3 2
1 0 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0 15 14 13
1 0 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
RT clock
Internal received
data
Start Bit
Bit 0
(a) UARTCR2<RTSEL> is “000B”
RXD0 pin
Start Bit
Bit 0
RT15 14 13 12 11 10 9
8
7
6
5
4
3 2
0 15 14
RT clock
Internal received
data
Start Bit
Bit 0
(b) UARTCR2<RTSEL> is “001B”
RXD0 pin
Start Bit
RT14 13 12 11 10 9
Bit 0
8
7
6
5
4
3
2 1
Bit 1
0 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0 14 13 12 11 10
RT clock
Internal received
data
Start Bit
Bit 0
Bit 1
(c) UARTCR2<RTSEL> is “010B”
RXD0 pin
Start Bit
RT14 13 12 11 10 9
Bit 1
Bit 0
8
7
6
5
4
3
2 1
0 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0 14 13 12 11
RT clock
Internal received
data
Start Bit
Bit 1
Bit 0
(d) UARTCR2<RTSEL> is “011B”
RXD0 pin
Start Bit
RT16 15 14 13 12 11 10 9
Bit 0
8
7
6
5
4
3
2
1
0 16 15 14 13 12 11 10 9
8
7
6
5
4
RT clock
Internal received
data
Start Bit
Bit 0
(e) UARTCR2<RTSEL> is “100B”
Figure 16-7 Data Sampling in Each Case of UARTCR2<RTSEL>
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3
2
1
0 16
16. Asynchronous Serial Interface (UART)
16.9 Data Sampling Method
TMP89FM46
If "1" is detected in sampling of the start bit, for example, due to the influence of noise, RT clock counting stops
and the data receiving is suspended. Subsequently, when a falling edge is detected in the input pulses to the RXD0
pin, RT clock counting restarts and the data receiving restarts with the start bit.
Counting is suspended until
the next falling edge is detected
RT15 14 13 12 11 10 9
8
7 6
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0 15 14 13 12 11 10 9
8
7
6
5
4
RT clock
Noise
RXD0 pin
Start Bit
Bit 0
Internal received
data
Start Bit
Bit 0
Bit 0
Shift register
A falling edge
is detected
Error because
the start bit is 1
A falling edge
is detected
Receiving continues
because the start bit is 0
Figure 16-8 Start Bit Sampling
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Page 212
The received data is taken
into the shift register
3
TMP89FM46
16.10Received Data Noise Rejection
When noise rejection is enabled at UART0CR2<RXDNC>, the time of pulses to be regarded as signals is as
shown in Table 16-8.
Table 16-8 Received Data Noise Rejection Time
RXDNC
Noise rejection time [s]
Time of pulses to be regarded as signals
00
No noise rejection
-
01
(UART0DR+1)/(Transfer base clock frequency)
2 × (UART0DR+1)/(Transfer base clock frequency)
10
2 × (UART0DR+1)/(Transfer base clock frequency)
4 × (UART0DR+1)/(Transfer base clock frequency)
11
4 × (UART0DR+1)/(Transfer base clock frequency)
8 × (UART0DR+1)/(Transfer base clock frequency)
Note 1: The transfer base clock frequency is the clock frequency selected at UARTCR1<BRG>.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0 15 14 13 12 11 10 9
8
7
6
5
4
RT clock
Noise
Start bit
RXD0 pin
Internal received
data
Noise is removed
Bit 0
Start bit
Bit 0
Bit 0
Shift register
A falling edge
is detected
Receiving continues
because the start bit is 0
When the noise rejection
circuit is used
Figure 16-9 Received Data Noise Rejection
RA001
Page 213
The received data is taken into
the shift register
3
16. Asynchronous Serial Interface (UART)
16.11 Transmit/Receive Operation
TMP89FM46
16.11Transmit/Receive Operation
16.11.1Data transmit operation
Set UART0CR1<TXE> to "1". Check UART0SR<TBFL> = "0", and then write data into TD0BUF (transmit
data buffer). Writing data into TD0BUF sets UART0SR<TBFL> to "1", transfers the data to the transmit shift
register, and outputs the data sequentially from the TXD0 pin. The data output includes a start bit, stop bits
whose number is specified in UART0CR1<STBT> and a parity bit if parity addition is specified. Select the
data transfer baud rate using UART0CR1<BRG>, UART0CR2<RTSEL> and UART0DR. When data transmission starts, the transmit buffer full flag UART0SR<TBFL> is cleared to "0" and an INTTXD0 interrupt
request is generated.
Note 1: After data is written into TD0BUF, if new data is written into TD0BUF before the previous data is transferred
to the shift register, the new data is written over the previous data and is transferred to the shift register.
Note 2: Under the conditions shown in Table 16-9, the TXD0 pin output is fixed at the L or H level according to the
setting of UART0CR1<IRDASEL>.
Table 16-9 TXD0 Pin Output
TXD0 pin output
Condition
IRDASEL="0"
IRDASEL="1"
H level
L level
When UART0CR1<TXE> is "0"
From when "1" is written to
UART0CR1<TXE> to when the transmitted data is written to TD0BUF
When the STOP, IDLE0 or SLEEP0
mode is active
16.11.2Data receive operation
Set UART0CR1<RXE> to "1". When data is received via the RXD0 pin, the received data is transferred to
RD0BUF (receive data buffer). At this time, the transmitted data includes a start bit, stop bit(s) and a parity bit
if parity addition is specified. When the stop bit(s) are received, data only is extracted and transferred to
RD0BUF (receive data buffer). Then the receive buffer full flag UART0SR<RBFL> is set and an INTRXD0
interrupt request is generated. Set the data transfer baud rate using UART0CR1<BRG>, UART0CR2<RTSEL>
and UART0DR.
If an overrun error occurs when data is received, the data is not transferred to RD0BUF (receive data buffer)
but discarded; data in the RD0BUF is not affected.
RA001
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TMP89FM46
16.12Status Flag
16.12.1Parity error
When the parity determined using the receive data bits differs from the received parity bit, the parity error
flag UART0SR<PERR> is set to "1". At this time, an INTRXD0 interrupt request is generated.
If UART0SR<PERR> is "1" when UART0SR is read, UART0SR<PERR> will be cleared to "0" when
RD0BUF is read subsequently. (The RD0BUF read value becomes undefined.)
If UART0SR<PERR> is set to "1" after UART0SR is read, UART0SR<PERR> will not be cleared to "0"
when RD0BUF is read subsequently. In this case, UART0SR<PERR> will be cleared to "0" when UART0SR
is read again and RD0BUF is read.
RXD0 pin input
Start Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7 Parity Stop
UART0SR<PERR>
PERR is cleared to “0”
when RD0BUF
is read after reading PERR=“1”.
INTRXD0 interrupt request
Reading of UART0SR
Reading of RD0BUF
RD0BUF
Indeterminate
Data reading
RXD0 pin input
Start Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7 Parity Stop
Not cleared
UART0SR<PERR>
PERR is cleared to “0”
when RD0BUF
is read after reading PERR=“1”.
INTRXD0 interrupt request
Reading of UART0SR
Reading of RD0BUF
RD0BUF
Indeterminate
Data reading
Figure 16-10 Occurrence of Parity Error
RA001
Page 215
Data reading
16. Asynchronous Serial Interface (UART)
16.12 Status Flag
TMP89FM46
16.12.2Framing Error
If the internal and external baud rates differ or "0" is sampled as the stop bit of received data due to the influence of noise on the RXD0 pin, the framing error flag UART0SR<FERR> is set to "1". At this time, an
INTRXD0 interrupt request is generated.
If UART0SR<FERR> is "1" when UART0SR is read, UART0SR<FERR> will be cleared to "0" when
RD0BUF is read subsequently.
If UART0SR<FERR> is set to "1" after UART0SR is read, UART0SR<FERR> will not be cleared to "0"
when RD0BUF is read subsequently. In this case, UART0SR<FERR> will be cleared to "0" when UART0SR
is read again and RD0BUF is read.
A falling edge is
detected
RXD0 pin input
Start Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7 Stop
FERR is generated if “0” is received
in the sampling of the stop bit.
Sampling
Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Stop
UART0SR<FERR>
FERR is cleared to “0”
when RD0BUF
is read after reading FERR=“1”.
INTRXD0 interrupt request
Reading of UART0SR
Reading of RD0BUF
RD0BUF
Indeterminate
Data reading
When the external baud rate is slower than the internally set baud rate
A falling edge is
detected
RXD0 pin input
Start Bit0
A falling edge is
detected
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7 Stop Start Bit0
Bit1
Bit2
Bit5
Bit6
Start
Bit3
Bit4
Bit5
Bit6
Bit7 Stop
Sampling
Start
UART0SR<FERR>
Bit0
Bit1
Bit2
Bit3
Bit4
Bit7
Stop
Bit0
Bit1
Bit3
Bit4
FERR is cleared to “0”
when RD0BUF
is read after reading FERR=“1”.
INTRXD0 interrupt request
Reading of UART0SR
Reading of RD0BUF
RD0BUF
Indeterminate
Data reading
When the external baud rate is faster than the internally set baud rate
Figure 16-11 Occurrence of Framing Error
RA001
Bit2
FERR is generated if “0” is received
in the sampling of the stop bit.
Page 216
Bit5
TMP89FM46
16.12.3Overrun error
If receiving of all data bits is completed before the previous received data is read from RD0BUF, the overrun
error flag UART0SR<OERR> is set to "1" and an INTRXD0 interrupt request is generated. The data received
at the occurrence of the overrun error is discarded and the previous received data is maintained. Subsequently,
if data is received while UART0SR<OERR> is still "1", no INTRXD0 interrupt request is generated, and the
received data is discarded. (Figure 16-12)
Note that parity or framing errors in the discarded received data cannot be detected. (These error flags are not
set.) That is to say, if these errors are detected together with an overrun error during the reading of UART0SR,
they have occurred in the previous received data (the data stored in RD0BUF). (Figure 16-13)
If UART0SR<OERR> is "1" when UART0SR is read, UART0SR<OERR> will be cleared to "0" when
RD0BUF is read subsequently. (Figure 16-14)
If UART0SR<OERR> is set to "1" after UART0SR is read, UART0SR<OERR> will not be cleared to "0"
when RD0BUF is read subsequently. In this case, UART0SR<OERR> will be cleared to "0" when UART0SR
is read again and RD0BUF is read. (Figure 16-14)
Data A
Start Bit0
RXD0 pin input
Bit1
Data B
Bit7 Stop Start Bit0
Bit1
Data C
Bit7 Stop Start Bit0
Bit1
Bit7 Stop
UART0SR<RBFL>
The flag is set.
UART0SR<OERR>
INTRXD0 interrupt request
An interrupt request
is generated.
RD0BUF
Data A
The contents of data B are discarded
and those of data A are maintained.
An interrupt request
is generated.
The contents of data C are discarded
and those of data A are maintained.
Figure 16-12 Generation of INTRXD0 Interrupt Request
RA001
Page 217
No interrupt
request is
generated.
16. Asynchronous Serial Interface (UART)
16.12 Status Flag
TMP89FM46
Data A
Start Bit0
RXD0 pin input
Data C
Data B
Parity Stop Start Bit0
Parity Stop
The parity is OK.
A parity error occurs.
UART0SR<FERR>
Start Bit0
Data D
Parity Stop Start Bit0
Parity Stop
The flag is not set even if
a framing error occurs.
The flag is set.
UART0SR<PERR>
UART0SR<RBFL>
UART0SR<OERR>
An interrupt request
is generated.
INTRXD0 interrupt request
RD0BUF
An interrupt request
is generated.
No interrupt request
is generated.
Data A
The contents of data B are discarded
and those of data A are maintained.
The contents of data C are discarded
and those of data A are maintained.
The contents of data D are
discarded and those of
data A are maintained.
When a parity error occurs in the first received data and a framing error occurs in the second data
Data A
RXD0 pin input
Start Bit0
Data B
Parity Stop Start Bit0
The parity is OK.
Data C
Parity Stop Start Bit0
A parity error occurs.
UART0SR<PERR>
Data D
Parity Stop Start Bit0
Parity Stop
The error flag is not set
together with an overrun error.
UART0SR<RBFL>
UART0SR<OERR>
INTRXD0 interrupt request
RD0BUF
An interrupt request
is generated.
An interrupt request
is generated.
No interrupt request
is generated.
Data A
The contents of data B are discarded
and those of data A are maintained.
The contents of data C are
discarded and those of
data A are maintained.
The contents of data D are
discarded and those of
data A are maintained.
When a parity error occurs in the second received data
Figure 16-13 Framing/Parity Error Flags When an Overrun Error Occurs
RA001
Page 218
TMP89FM46
Data B
Data A
RXD0 pin input
Start Bit0
Bit1
Bit7 Stop Start Bit0
Bit1
Bit7 Stop
UART0SR<RBFL>
UART0SR<OERR>
RBFL is cleared to “0” when
RD0BUF is read after reading
RBFL=“1”.
INTRXD0 interrupt request
OERR is cleared to “0” when
RD0BUF is read after reading
OERR=“1”.
Reading of UART0SR
Reading of RD0BUF
RD0BUF
Data A
The contents of data B are discarded
and those of data A are maintained.
Data A
RXD0 pin input
Start Bit0
Bit1
Reading of data A
Data B
Bit7 Stop Start Bit0
Bit1
Bit7 Stop
RBFL is cleared to “0” when
RD0BUF is read after reading
RBFL=“1”.
UART0SR<RBFL>
UART0SR<OERR>
OERR is cleared to “0” when
RD0BUF is read after reading
OERR=“1”.
INTRXD0 interrupt request
Reading of UART0SR
Reading of RD0BUF
RD0BUF
Data A
The contents of data B are discarded
and those of data A are maintained.
Reading
of data A
Reading
of data A
Figure 16-14 Clearance of Overrun Error Flag
RA001
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16. Asynchronous Serial Interface (UART)
16.12 Status Flag
TMP89FM46
16.12.4Receive Data Buffer Full
Loading the received data in RD0BUF sets UART0SR<RBFL> to "1".
If UART0SR<RBFL> is "1" when UART0SR is read, UART0SR<RBFL> will be cleared to "0" when
RD0BUF is read subsequently.
If UART0SR<RBFL> is set to "1" after UART0SR is read, UART0SR<RBFL> will not be cleared to "0"
when RD0BUF is read subsequently. In this case, UART0SR<RBFL> will be cleared to "0" when UART0SR
is read again and RD0BUF is read.
Data A
Start Bit1
RXD0 pin input
Bit0
Data B
Bit7 Stop Start Bit0
Bit1
Bit7 Stop
UART0SR<RBFL>
RBFL is cleared to “0” when
RD0BUF is read after
reading RBFL=“1”.
INTRXD0 interrupt request
Reading of UART0SR
Reading of RD0BUF
RD0BUF
Data A
Reading of data A
Data B
Reading of data B
Figure 16-15 Occurrence of Receive Data Buffer Full
RA001
Page 220
TMP89FM46
16.12.5 Transmit busy flag
If transmission is completed with no waiting data in TD0BUF (when UART0SR<TBFL>="0"),
UART0SR<TBSY> is cleared to "0". When transmission is restarted after data is written into TD0BUF,
UART0SR<TBSY> is set to "1". At this time, an INTTXD0 interrupt request is generated.
UART0CR1<TXE>
Data A
Start Bit0
TXD0 pin input
Bit1
Bit2
Bit3
Data B
Bit4
Bit5
Bit6
Bit7 Stop
Start Bit0
Bit1
Bit6
Bit7 Stop
UART0SR<TBFL>
UART0SR<TBSY>
INTTXD0 interrupt
request
Writing of TD0BUF
Writing of
data A
Writing of
data B
Figure 16-16 Transmit Busy Flag and Occurrence of Transmit Buffer Full
16.12.6Transmit Buffer Full
When TD0BUF has no data, or when data in TD0BUF is transferred to the transmit shift register and transmission is started, UART0SR<TBFL> is cleared to "0". At this time, an INTTXD0 interrupt request is generated.
Writing data into TD0BUF sets UART0SR<TBFL> to "1".
UART0CR1<TXE>
Data A
Start Bit0
TXD0 pin input
Bit1
Bit2
Bit3
Data B
Bit4
Bit5
Bit6
Bit7 Stop Start Bit0
Bit1
Bit2
Bit3
UART0SR<TBFL>
UART0SR<TBSY>
INTTXD0 interrupt
request
Writing of TD0BUF
Writing of
data A
Writing of
data B
Figure 16-17 Occurrence of Transmit Buffer Full
RA001
Page 221
Bit6
Bit7 Stop
16. Asynchronous Serial Interface (UART)
16.13 Receiving Process
TMP89FM46
16.13Receiving Process
Figure 16-18 shows an example of the receiving process. Details of flag judgments in the processing are shown in
Table 16-10 and Table 16-11.
If any framing error or parity error is detected, the received data has erroneous value(s). Execute the error handling, for example, by discarding the received data read from RD0BUF and receiving the data again.
If any overrun error is detected, the receiving of one or more pieces of data is unfinished. It is impossible to determine the number of pieces of data that could not be received. Execute the error handling, for example, by receiving
data again from the beginning of the transfer. Basically, an overrun error occurs when the internal software processing cannot follow the data transfer speed. It is recommended to slow the transfer baud rate or modify the software to
execute flow control.
Receiving process
INTRXD0 interrupt
subroutine
Read UART0SR
Read UART0SR
Read RD0BUF
Read RD0BUF
UART0SR<RBFL>
0
1
UART0SR<PERR>
1
Parity error
UART0SR<PERR>
0
UART0SR<FERR>
0
Data processing
(Received data is valid)
UART0SR<OERR>
1
Parity error
0
1
Framing error
UART0SR<FERR>
1
Framing error
0
Data processing
(Received data is valid)
Error handling
1
Overrun error
UART0SR<OERR>
0
Error handling
1
Overrun error
0
Error handling
Error handling
END
RETI
When no receive interrupt is used
When a receive interrupt is used
Figure 16-18 Example of Receiving Process
Note 1: If multiple interrupts are used in the INTRXD0 interrupt subroutine, the interrupt should be enabled after reading
UART0SR and RD0BUF.
RA001
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TMP89FM46
Table 16-10 Flag Judgments When No Receive Interrupt Is Used
RBFL
FERR/PERR
OERR
State
0
-
0
Data has not been received yet.
0
-
1
Some pieces of data could not be received during the previous data receiving process
(Receiving of next data is completed in the period from when
UART0SR is read to when RD0BUF is read in the previous
data receiving process.)
1
0
0
Receiving has been completed properly.
1
0
1
Receiving has been completed properly, but some pieces of
data could not be received.
1
1
0
Received data has erroneous value(s).
1
1
1
Received data has erroneous value(s) and some pieces of
data could not be received.
Table 16-11 Flag Judgments When a Receive Interrupt Is Used
RA001
FERR/PERR
OERR
State
0
0
Receiving has been completed properly.
0
1
Receiving has been completed properly, but some pieces of
data could not be received.
1
0
Received data has erroneous value(s).
1
1
Received data has erroneous value(s) and some pieces of
data could not be received.
Page 223
16. Asynchronous Serial Interface (UART)
16.14 AC Properties
TMP89FM46
16.14AC Properties
16.14.1IrDA properties
(VSS = 0 V, Topr = −40 to 85°C)
Item
TXD output pulse time
(RT clock × (3/16))
RA001
Condition
Min
Typ.
Max
Transfer baud rate = 2400 bps
–
78.13
–
Transfer baud rate = 9600 bps
–
19.53
–
Transfer baud rate = 19200 bps
–
9.77
–
Transfer baud rate = 38400 bps
–
4.88
–
Transfer baud rate = 57600 bps
–
3.26
–
Transfer baud rate = 115200 bps
–
1.63
–
Page 224
Unit
µs
TMP89FM46
17. Synchronous Serial Interface (SIO)
The TMP89FM46 contains 1 channel of high-speed 8-bit serial interfaces of the clock synchronization type.
Table 17-1 SFR Address Assignment
Serial interface 0
SIOxCR
(address)
SIOxSR
(address)
SIOxBUF
(address)
SIO0CR
(0x001F)
SIO0SR
(0x0020)
SIO0BUF
(0x0021)
Table 17-2 Pin Names
Serial interface 0
RA001
Serial clock
input/output pin
Serial data
input pin
Serial data
output pin
SCLK0 pin
SI0 pin
SO0 pin
Page 225
17. Synchronous Serial Interface (SIO)
17.1 Configuration
TMP89FM46
17.1 Configuration
Internal bus
INTSIO0
interrupt request
SIO0CR
SIO0SR
SIO0BUF
Shift register on transmitter
Shift clock
Internal clock
Control circuit
MSB/LSB selection
Port
(Note)
SO0 pin
Port
(Note)
SI0 pin
Shift register on receiver
SIO0BUF
Port
(Note)
SCLK0 pin
Internal bus
Figure 17-1 Serial Interface
Note: The serial interface input/output pins are also used as the I/O ports. The I/O port register settings are required to
use these pins for a serial interface. For details, refer to the chapter of I/O ports.
RA001
Page 226
TMP89FM46
17.2 Control
The synchronous serial interface SIO0 is controlled by the low power consumption registers (POFFCR2), the
serial interface data buffer register (SIO0BUF), the serial interface control register (SIO0CR) and the serial interface
status register (SIO0SR).
Low power consumption register 2
POFFCR2
(0x0F76)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
RTCEN
-
-
-
-
SIO0EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
3
2
1
0
RTCEN
RTC control
0
1
Disable
Enable
SIO0EN
SIO0 control
0
1
Disable
Enable
Serial interface buffer register
SIO0BUF
(0x0021)
7
6
5
4
Bit Symbol
SIO0BUF
Read/Write
R
After reset
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
1
1
1
1
Serial interface buffer register
SIO0BUF
(0x0021)
7
Bit Symbol
SIO0BUF
Read/Write
W
After reset
1
1
1
1
Note 1: SIO0BUF is the data buffer for both transmission and reception. The last received data is read each time SIO0BUF is
read. If SIO0BUF has never received data, it is read as "0". When data is written into it, the data is treated as the transmit
data.
RA001
Page 227
17. Synchronous Serial Interface (SIO)
17.2 Control
TMP89FM46
Serial interface control register
SIO0CR
(0x001F)
7
6
5
4
3
2
1
0
Bit Symbol
SIOEDG
SIOCKS
SIODIR
SIOS
SIOM
Read/Write
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
SIOEDG
SIOCKS
0
Transfer edge selection
Serial clock selection [Hz]
0
0
0
1
SIOS
NORMAL1/2 or IDLE1/2 mode
SLOW1/2 or SLEEP1 mode
000
fcgck/29
-
001
fcgck/26
-
010
fcgck/25
-
011
fcgck/24
-
100
fcgck/23
-
101
2
fcgck/2
-
110
fcgck/2
fs/23
External clock input
Transfer format (MSB/LSB) selection
0
1
LSB first (transfer from bit 0)
MSB first (transfer from bit 7)
Transfer operation start/stop
instruction
0
1
0: Operation stop (reserved stop)
1: Operation start
00
SIOM
Transfer mode selection and
operation
0
0: Receive data at a rising edge and transmit data at a falling edge
1: Transmit data at a rising edge and receive data at a falling edge
111
SIODIR
0
Operation stop (forced stop)
01
8-bit transmit mode
10
8-bit receive mode
11
8-bit transmit and receive mode
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: After the operation is started by writing "1" to SIOS, writing to SIOEDG, SIOCKS and SIODIR is invalid until
SIO0SR<SIOF> becomes "0". (SIOEDG, SIOCKS and SIODIR can be changed at the same time as changing SIOS from
"0" to "1".)
Note 3: After the operation is started by writing "1" to SIOS, no values other than"00" can be written to SIOM until SIOF becomes
"0" (if a value from "01" to "11" is written to SIOM, it is ignored). The transfer mode cannot be changed during the operation.
Note 4: SIOS remains at "0", if "1" is written to SIOS when SIOM is "00" (operation stop).
Note 5: When SIO is used in SLOW1/2 or SLEEP1 mode, be sure to set SIOCKS to "110". If SIOCKS is set to any other value,
SIO will not operate. When SIO is used in SLOW1/2 or SLEEP1 mode, execute communications with SIOCKS="110" in
advance or change SIOCKS after SIO is stopped.
Note 6: When STOP, IDLE0 or SLEEP0 mode is activated, SIOM is automatically cleared to "00" and SIO stops the operation. At
the same time, SIOS is cleared to "0". However, the values set for SIOEDG, SIOCKS and SIODIR are maintained.
RA001
Page 228
TMP89FM46
Serial interface status register
SIO0SR
(0x0020)
7
6
5
4
3
2
1
0
Bit Symbol
SIOF
SEF
OERR
REND
UERR
TBFL
-
-
Read/Write
R
R
R
R
R
R
R
R
After reset
0
0
0
0
0
0
0
0
SIOF
Serial transfer operation status
monitor
0
1
Transfer not in progress
Transfer in progress
SEF
Shift operation status monitor
0
1
Shift operation not in progress
Shift operation in progress
OERR
Receive overrun error flag
0
1
No overrun error has occurred
At least one overrun error has occurred
REND
Receive completion flag
0
1
No data has been received since the last receive data was read out
At least one data receive operation has been executed
UERR
Transmit underrun error flag
0
1
No transmit underrun error has occurred
At least one transmit underrun error has occurred
TBFL
Transmit buffer full flag
0
1
The transmit buffer is empty
The transmit buffer has the data that has not yet been transmitted
Note 1: The OERR and UERR flags are cleared by reading SIO0SR.
Note 2: The REND flag is cleared by reading SIO0BUF.
Note 3: Writing "00" to SIO0CR<SIOM> clears all the bits of SIO0SR to "0", whether the serial interface is operating or not. When
STOP, IDLE0 or SLEEP0 mode is activated, SIOM is automatically cleared to "00" and all the bits of SIO0SR are cleared
to "0".
Note 4: Bit 1 to 0 of SIO0SR are read "0".
RA001
Page 229
17. Synchronous Serial Interface (SIO)
17.3 Low Power Consumption Function
TMP89FM46
17.3 Low Power Consumption Function
Serial interface 0 has the low power consumption registers (POFFCR2) that save power when the serial interface is
not being used.
Setting POFFCR2<SIO0EN> to "0" disables the basic clock supply to serial interface 0 to save power. Note that
this renders the serial interface unusable. Setting POFFCR2<SIO0EN> to "1" enables the basic clock supply to serial
interface 0 and allows the serial interface to operate.
After reset, POFFCR2<SIO0EN> are initialized to "0", and this renders the serial interface unusable. When using
the serial interface for the first time, be sure to set POFFCR2<SIO0EN> to "1" in the initial setting of the program
(before the serial interface control registers are operated).
Do not change POFFCR2<SIO0EN> to "0" during the serial interface operation. Otherwise serial interface 0 may
operate unexpectedly.
RA001
Page 230
TMP89FM46
17.4 Functions
17.4.1 Transfer format
The transfer format can be set to either MSB or LSB first by using SIO0CR<SIODIR>. Setting
SIO0CR<SIODIR> to "0" selects LSB first as the transfer format. In this case, the serial data is transferred in
sequence from the least significant bit.
Setting SIO0CR<SIODIR> to "1" selects MSB first as the transfer format. In this case, the serial data is
transferred in sequence from the most significant bit.
17.4.2 Serial clock
The serial clock can be selected by using SIO0CR<SIOCKS>.
Setting SIO0CR<SIOCKS> to "000" to "110" selects the internal clock as the serial clock. In this case, the
serial clock is output from the SCLK0 pin. The serial data is transferred in synchronization with the edge of the
SCLK0 pin output.
Setting SIO0CR<SIOCKS> to "111" selects an external clock as the serial clock. In this case, an external
serial clock must be input to the SCLK0 pin. The serial data is transferred in synchronization with the edge of
the external clock.
The serial data transfer edge can be selected for both the external and internal clocks. For details, refer to
"17.4.3 Transfer edge selection".
Table 17-3 Transfer Baud Rate
Serial clock [Hz]
SIO0CR
<SIOCKS>
fcgck=4MHz
fcgck=8MHz
fcgck=10MHz
fs=32.768kHz
NORMAL1/2 or
IDLE1/2 mode
SLOW1/2 or
SLEEP1 mode
1-bit time
(µs)
Baud rate
(bps)
1-bit time
(µs)
Baud rate
(bps)
1-bit time
(µs)
Baud rate
(bps)
1-bit time
(µs)
Baud rate
(bps)
000
fcgck/29
-
128
7.813k
64
15.625k
51.2
19.531k
-
-
001
fcgck/26
-
16
62.5k
8
125k
6.4
156.25k
-
-
010
fcgck/25
-
8
125k
4
250k
3.2
312.5k
-
-
011
fcgck/24
-
4
250k
2
500k
1.6
625k
-
-
100
fcgck/23
-
2
500k
1
1M
0.8
1.25M
-
-
101
fcgck/22
-
1
1M
0.5
2M
0.4
2.5M
-
-
110
fcgck/2
fs/23
0.5
2M
0.25
4M
0.2
5M
244
4k
17.4.3 Transfer edge selection
The serial data transfer edge can be selected by using SIOCR<SIOEDG>.
Table 17-4 Transfer Edge Selection
SIO0CR<SIOEDG>
Data transmission
Data reception
0
Falling edge
Rising edge
1
Rising edge
Falling edge
When SIOCR<SIOEDG> is "0", the data is transmitted in synchronization with the falling edge of the clock
and the data is received in synchronization with the rising edge of the clock.
When SIOCR<SIOEDG> is "1", the data is transmitted in synchronization with the rising edge of the clock
and the data is received in synchronization with the falling edge of the clock.
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17. Synchronous Serial Interface (SIO)
17.4 Functions
TMP89FM46
SLCK0 pin
SO0 pin
T0
T1
T2
T3
T4
T5
T6
T7
SI0 pin
R0 R1 R2 R3 R4 R5 R6 R7
When SIOCR<SIOEDG>=“0”
SCLK0 pin
SO0 pin
T0
T1
T2
T3
T4
T5
T6
T7
SI0 pin
R0 R1 R2 R3 R4 R5 R6 R7
When SIOCR<SIOEDG>=“1”
Figure 17-2 Transfer Edge
Note:When an external clock input is used, 4/fcgck or longer is needed between the receive edge at the 8th bit and
the transfer edge at the first bit of the next transfer.
tBI
SCLK0 pin
SO0 pin
SI0 pin
RA001
A6
C6
A7
C7
B0
D0
B1
D1
B2
D2
Page 232
Trailing edge at the Leading edge at the
8th bit (receive edge) 1st bit (transmit edge)
Symbol
Name
Minimum time
tBI
Interval time between bytes
4/fcgck
TMP89FM46
17.5 Transfer Modes
17.5.1 8-bit transmit mode
The 8-bit transmit mode is selected by setting SIO0CR<SIOM> to "01".
17.5.1.1 Setting
Before starting the transmit operation, select the transfer edges at SIO0CR<SIOEDG>, a transfer format
at SIO0CR<SIODIR> and a serial clock at SIO0CR<SIOCKS>. To use the internal clock as the serial
clock, select an appropriate serial clock at SIO0CR<SIOCKS>. To use an external clock as the serial
clock, set SIO0CR<SIOCKS> to "111".
The 8-bit transmit mode is selected by setting SIO0CR<SIOM> to "01".
The transmit operation is started by writing the first byte of transmit data to SIO0BUF and then setting
SIO0CR<SIOS> to "1".
Writing data to SIO0CR<SIOEDG, SIOCKS and SIODIR> is invalid when the serial communication is
in progress, or when SIO0SR<SIOF> is "1". Make these settings while the serial communication is
stopped. While the serial communication is in progress (SIO0SR<SIOF>="1"), only writing "00" to
SIO0CR<SIOM> or writing "0" to SIO0CR<SIOS> is valid.
17.5.1.2 Starting the transmit operation
The transmit operation is started by writing data to SIO0BUF and then setting SIO0CR<SIOS> to "1".
The transmit data is transferred from SIO0BUF to the shift register, and then transmitted as the serial data
from the SO0 pin according to the settings of SIO0CR<SIOEDG, SIOCKS and SIODIR>. The serial data
becomes undefined if the transmit operation is started without writing any transmit data to SIO0BUF.
In the internal clock operation, the serial clock of the selected baud rate is output from the SCLK0 pin.
In the external clock operation, an external clock must be supplied to the SCLK0 pin.
By setting SIO0CR<SIOS> to "1", SIO0SR<SIOF and SEF> are automatically set to "1" and an
INTSIO0 interrupt request is generated.
SIO0SR<SEF> is cleared to "0" when the 8th bit of the serial data is output.
17.5.1.3 Transmit buffer and shift operation
If data is written to SIO0BUF when the serial communication is in progress and the shift register is
empty, the written data is transferred to the shift register immediately. At this time, SIO0SR<TBFL>
remains at "0".
If data is written to SIO0BUF when some data remains in the shift register, SIO0SR<TBFL> is set to
"1". If new data is written to SIO0BUF in this state, the contents of SIO0BUF are overwritten by the new
value. Make sure that SIO0SR<TBFL> is "0" before writing data to SIO0BUF.
17.5.1.4 Operation on completion of transmission
The operation on completion of the data transmission varies depending on the operating clock and the
state of SIO0SR<TBFL>.
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17. Synchronous Serial Interface (SIO)
17.5 Transfer Modes
TMP89FM46
(1)
When the internal clock is used and SIO0SR<TBFL> is "0"
When the data transmission is completed, the SCLK0 pin becomes the initial state and the SO0 pin
becomes the "H" level. SIO0SR<SEF> remains at "0". When the internal clock is used, the serial
clock and data output is stopped until the next transmit data is written into SIO0BUF (automatic
wait).
When the subsequent data is written into SIO0BUF, SIO0SR<SEF> is set to "1", the SCLK0 pin
outputs the serial clock, and the transmit operation is restarted. An INTSIO0 interrupt request is generated at the restart of the transmit operation.
(2)
When an external clock is used and SIO0SR<TBFL> is "0"
When the data transmission is completed, the SO pin keeps last output value. When an external
serial clock is input to the SCLK0 pin after completion of the data transmission, an undefined value
is transmitted and the transmit underrun error flag SIO0SR<UERR> is set to "1".
If a transmit underrun error occurs, data must not be written to SIO0BUF during the transmission
of an undefined value. (It is recommended to finish the transmit operation by setting
SIO0CR<SIOS> to "0" or force the transmit operation to stop by setting SIO0CR<SIOM> to "00".)
The transmit underrun error flag SIO0SR<UERR> is cleared by reading SIO0SR.
(3)
When an internal or external clock is used and SIO0SR<TBFL> is "1"
When the data transmission is completed, SIO0SR<TBFL> is cleared to "0". The data in
SIO0BUF is transferred to the shift register and the transmission of subsequent data is started. At this
time, SIO0SR<SEF> is set to "1" and an INTSIO0 interrupt request is generated.
17.5.1.5 Stopping the transmit operation
Set SIO0CR<SIOS> to "0" to stop the transmit operation. When SIO0SR<SEF> is "0", or when the
shift operation is not in progress, the transmit operation is stopped immediately and an INTSIO0 interrupt
request is generated. When SIO0SR<SEF> is "1", the transmit operation is stopped after all the data in the
shift register is transmitted (reserved stop). At this time, an INTSIO0 interrupt request is generated again.
When the transmit operation is completed, SIO0SR<SIOF, SEF and TBFL> are cleared to "0". Other
SIO0SR registers keep their values.
If the internal clock has been used, the SO0 pin automatically returns to the "H" level. If an external
clock has been used, the SO0 pin keeps the last output value. To return the SO0 pin to the "H" level, write
"00" to SIO0CR<SIOM> when the operation is stopped.
The transmit operation can be forced to stop by setting SIO0CR<SIOM> to "00" during the operation.
By setting SIO0CR<SIOM> to "00", SIO0CR<SIOS> and SIO0SR are cleared to "0" and the SIO stops
the operation, regardless of the SIO0SR<SEF> value. The SO0 pin becomes the "H" level. If the internal
clock is selected, the SCLK0 pin returns to the initial level.
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TMP89FM46
Start operation
Reserved stop
SIO0CR<SIOS>
01
SIO0CR<SIOM>
SIO0SR<SIOF>
Automatic wait
SIO0SR<SEF>
SIO0SR<TBFL>
Internal clock
Data A
Data B
Data C
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SO0 pin (output)
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SCLK0 pin (output)
SIO0BUF
An interrupt is generated
after transmission in
case of reserved stop
The level is held for the period
of the internal clock×(1/2)
INTSIO0 interrupt request
A
B
C
Write to SIO0BUF
Writing data A
Writing data B
Writing data C
Figure 17-3 8-bit Transmit Mode (Internal Clock and Reserved Stop)
Start operation
Forced stop
Start operation
Forced stop
Reserved stop
SIO0CR<SIOS>
01
SIO0CR<SIOM>
00
01
00
SIO0SR<SIOF>
SIO0SR<SEF>
SIO0SR<TBFL>
Internal clock
Data A
Data B
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2
SO0 pin (output)
Data C
Data is not held but
becomes the H level
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5
Clock output is stopped
SCLK0 pin (output)
Forced stop has priority
over reserved stop
INTSIO0 interrupt request
SIO0BUF
A
B
C
D
Write to SIO0BUF
Writing data A
Writing data B
Writing data C
Writing data D
Figure 17-4 8-bit Transmit Mode (Internal Clock and Forced Stop)
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17. Synchronous Serial Interface (SIO)
17.5 Transfer Modes
TMP89FM46
Start operation
Reserved stop
SIO0CR<SIOS>
01
SIO0CR<SIOM>
00
SIO0SR<SIOF>
SIO0SR<SEF>
Stopped while keeping
the current level in the operation
with an external clock
SIO0SR<TBFL>
Data A
Data B
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1
SO0 pin (output)
Data C
Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SCLK0 pin (input)
An interrupt is generated after
transmission in case of reserved stop
INTSIO0 interrupt request
SIO0BUF
A
B
C
Returned to the H level by setting
SIOCR1<SIOM> to “00”
Write to SIO0BUF
Writing data A
Writing data B
Writing data C
Figure 17-5 8-bit Transmit Mode (External Clock and Reserved Stop)
Start operation
Reserved stop
Start operation
Reserved stop
Forced stop
SIO0CR<SIOS>
01
SIO0CR<SIOM>
00
01
00
SIO0SR<SIOF>
SIO0SR<SEF>
SIO0SR<TBFL>
Data A
Data C
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2
SO0 pin (output)
Data C
Data is not held but
becomes the H level
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5
SCLK0 pin (input)
Forced stop has priority
over reserved stop
INTSIO0 interrupt request
SIO0BUF
A
B
C
D
If two pieces of data are written,
the latter data is effective
Write to SIO0BUF
Writing
data A
Writing
data B
Writing
data C
When the operation is restarted
after a forced stop, the last data
written to the buffer is transmitted.
Writing
data D
Figure 17-6 8-bit Transmit Mode (External Clock and Forced Stop)
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TMP89FM46
Start operation
Reserved stop
SIO0CR<SIOS>
01
SIO0CR<SIOM>
00
SIO0SR<SIOF>
SIO0SR<SEF>
Stopped while keeping the
current level in the operation
with an external clock
SIO0SR<TBFL>
SIO0SR<UERR>
Data A
Data A
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1
SO0 pin (output)
Data B
Bit2 Bit3 Bit4 Bit5 Bit6
Data B
Bit7
Data C
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6
Bit7
SCLK0 pin (input)
Transferred to the buffer
immediately after writing
INTSIO0 interrupt request
SIO0BUF
A
B
Transferred to the buffer
immediately after writing
C
Returned to the H level by
setting SIOCR1<SIOM> to “00”
Write to SIO0BUF
Writing
data A
Writing
data B
Writing
data C
Read SIO0SR
Reading
SIO0SR
Figure 17-7 8-bit Transmit Mode (External Clock and Occurrence of Transmit Underrun
Error)
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17. Synchronous Serial Interface (SIO)
17.5 Transfer Modes
TMP89FM46
17.5.2 8-bit Receive Mode
The 8-bit receive mode is selected by setting SIO0CR<SIOM> to "10".
17.5.2.1 Setting
As in the case of the transmit mode, before starting the receive operation, select the transfer edges at
SIO0CR<SIOEDG>, a transfer format at SIO0CR<SIODIR> and a serial clock at SIO0CR<SIOCKS>.
To use the internal clock as the serial clock, select an appropriate serial clock at SIO0CR<SIOCKS>. To
use an external clock as the serial clock, set SIO0CR<SIOCKS> to "111".
The 8-bit receive mode is selected by setting SIO0CR<SIOM> to "10".
Reception is started by setting SIO0CR<SIOS> to "1".
Writing data to SIO0CR<SIOEDG, SIOCKS and SIODIR> is invalid when the serial communication is
in progress, or when SIO0SR<SIOF> is "1". Make these settings while the serial communication is
stopped. While the serial communication is in progress (SIO0SR<SIOF>="1"), only writing "00" to
SIO0CR<SIOM> or writing "0" to SIO0CR<SIOS> is valid.
17.5.2.2 Starting the receive operation
Reception is started by setting SIO0CR<SIOS> to "1". External serial data is taken into the shift register
from the SI0 pin according to the settings of SIO0CR<SIOEDG, SIOCKS and SIODIR>.
In the internal clock operation, the serial clock of the selected baud rate is output from the SCLK0 pin.
In the external clock operation, an external clock must be supplied to the SCLK0 pin.
By setting SIO0CR<SIOS> to "1", SIO0SR<SIOF and SEF> are automatically set to "1".
17.5.2.3 Operation on completion of reception
When the data reception is completed, the data is transferred from the shift register to SIO0BUF and an
INTSIO0 interrupt request is generated. The receive completion flag SIO0SR<REND> is set to "1".
In the operation with the internal clock, the serial clock output is stopped until the receive data is read
from SIO0BUF (automatic wait). At this time, SIO0SR<SEF> is set to "0". By reading the receive data
from SIO0BUF, SIO0SR<SEF> is set to "1", the serial clock output is restarted and the receive operation
continues.
In the operation with an external clock, data can be continuously received without reading the received
data from SIO0BUF. In this case, data must be read from SIO0BUF before the subsequent data has been
fully received. If the subsequent data is received completely before reading data from SIO0BUF, the overrun error flag SIO0SR<OERR> is set to "1". When an overrun error has occurred, set SIO0CR<SIOM> to
"00" to abort the receive operation. The data received at the occurrence of an overrun error is discarded,
and SIO0BUF holds the data value received before the occurrence of the overrun error.
SIO0SR<REND> is cleared to "0" by reading data from SIO0BUF. SIO0SR<OERR> is cleared by
reading SIO0SR.
17.5.2.4 Stopping the receive operation
Set SIO0CR<SIOS> to "0" to stop the receive operation. When SIO0SR<SEF> is "0", or when the shift
operation is not in progress, the operation is stopped immediately. Unlike the transmit mode, no INTSIO0
interrupt request is generated in this state.
When SIO0SR<SEF> is "1", the operation is stopped after the 8-bit data has been completely received
(reserved stop). At this time, an INTSIO0 interrupt request is generated.
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TMP89FM46
After the operation has stopped completely, SIO0SR<SIOF and SEF> are cleared to "0". Other SIO0SR
registers keep their values.
The receive operation can be forced to stop by setting SIO0CR<SIOM> to "00" during the operation.
By setting SIO0CR<SIOM> to "00", SIO0CR<SIOS> and SIO0SR are cleared to "0" and the SIO stops
the operation, regardless of the SIO0SR<SEF> value. If the internal clock is selected, the SCLK0 pin
returns to the initial level.
Reserved
stop
SIO0CR<SIOS>
10
SIO0CR<SIOM>
SIO0SR<SIOF>
Automatic wait
SIO0SR<SEF>
SIO0SR<REND>
Internal clock
SI0 pin (input)
Data A
Data C
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SCLK0 pin (output)
INTSIO0 interrupt request
SIO0BUF
A
C
Read SIO0BUF
Reading data A
Reading data C
Figure 17-8 8-bit Receive Mode (Internal Clock and Reserved Stop)
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17. Synchronous Serial Interface (SIO)
17.5 Transfer Modes
TMP89FM46
Start operation
Forced stop
Start operation Reserved stop Forced stop
SIO0CR<SIOS>
10
SIO0CR<SIOM>
00
10
00
Automatic
wait
SIO0SR<SIOF>
SIO0SR<SEF>
SIO0SR<REND>
Internal clock
SI0 pin (input)
Data A
Data B
Data C
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Bit0 Bit1 Bit2
Bit0 Bit1 Bit2 Bit3
SCLK0 pin (output)
Returned to
the initial level
Returned to
the initial level
INTSIO0 interrupt request
SIO0BUF
A
Read SIO0BUF
Reading data A
Figure 17-9 8-bit Receive Mode (Internal Clock and Forced Stop)
Start operation
Reserved stop
SIO0CR<SIOS>
10
SIO0CR<SIOM>
SIO0SR<SIOF>
SIO0SR<SEF>
SIO0SR<REND>
Data A
SI0 pin (input)
Data B
Data C
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SCLK0 pin (input)
INTSIO0 interrupt request
SIO0BUF
A
B
C
Read SIO0BUF
Reading data A
Reading data B
Figure 17-10 8-bit Receive Mode (External Clock and Reserved Stop)
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TMP89FM46
Start operation
Forced stop
Start operation
SIO0CR<SIOS>
10
SIO0CR<SIOM>
00
10
SIO0SR<SIOF>
SIO0SR<SEF>
SIO0SR<REND>
Data A
Data B
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SI0 pin (input)
Data C
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SCLK0 pin (input)
Data B is discarded
INTSIO0 interrupt request
SIO0BUF
A
C
Read SIO0BUF
Reading data A
Reading data C
Figure 17-11 8-bit Receive Mode (External Clock and Forced Stop)
Start operation
Forced stop
SIO0CR<SIOS>
SIO0CR<SIOM>
10
00
SIO0SR<SIOF>
SIO0SR<SEF>
Subsequent data is received
completely before reading
data A
SIO0SR<REND>
SIO0SR<OERR>
Data A
SI0 pin (input)
Data B
Data C
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SCLK0 pin (input)
Data B is
discarded
INTSIO0 interrupt request
SIO0BUF
Data C is
discarded
A
Read SIO0BUF
Reading data A
Read SIO0SR
Reading SUI0SR
Figure 17-12 8-bit Receive Mode (External Clock and Occurrence of Overrun Error)
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17. Synchronous Serial Interface (SIO)
17.5 Transfer Modes
TMP89FM46
17.5.3 8-bit transmit/receive mode
The 8-bit transmit/receive mode is selected by setting SIO0CR<SIOM> to "11".
17.5.3.1 Setting
Before starting the transmit/receive operation, select the transfer edges at SIO0CR<SIOEDG>, a transfer format at SIO0CR<SIODIR> and a serial clock at SIO0CR<SIOCKS>. To use the internal clock as the
serial clock, select an appropriate serial clock at SIO0CR<SIOCKS>. To use an external clock as the
serial clock, set SIO0CR<SIOCKS> to "111".
The 8-bit transmit/receive mode is selected by setting SIO0CR<SIOM> to "11".
The transmit/receive operation is started by writing the first byte of transmit data to SIO0BUF and then
setting SIO0CR<SIOS> to "1".
Writing data to SIO0CR<SIOEDG, SIOCKS and SIODIR> is invalid when the serial communication is
in progress, or when SIO0SR<SIOF> is "1". Make these settings while the serial communication is
stopped. While the serial communication is in progress (SIO0SR<SIOF>="1"), only writing "00" to
SIO0CR<SIOM> or writing "0" to SIOCR<SIOS> is valid.
17.5.3.2 Starting the transmit/receive operation
The transmit/receive operation is started by writing data to SIO0BUF and then setting SIO0CR<SIOS>
to "1". The transmit data is transferred from SIO0BUF to the shift register, and the serial data is transmitted from the SO0 pin according to the settings of SIO0CR<SIOEDG, SIOCKS and SIODIR>. At the same
time, the serial data is received from the SI0 pin according to the settings of SIO0CR<SIOEDG, SIOCKS
and SIODIR>.
In the internal clock operation, the serial clock of the selected baud rate is output from the SCLK0 pin.
In the external clock operation, an external clock must be supplied to the SCLK0 pin.
The transmit data becomes undefined if the transmit/receive operation is started without writing any
transmit data to SIO0BUF.
By setting SIO0CR<SIOS> to "1", SIO0SR<SIOF and SEF> are automatically set to "1" and an
INTSIO0 interrupt request is generated.
SIO0SR<SEF> is cleared to "0" when the 8th bit of data is received.
17.5.3.3 Transmit buffer and shift operation
If any data is written to SIO0BUF when the serial communication is in progress and the shift register is
empty, the written data is transferred to the shift register immediately. At this time, SIO0SR<TBFL>
remains at "0".
If any data is written to SIO0BUF when some data remains in the shift register, SIO0SR<TBFL> is set
to "1". If new data is written to SIO0BUF in this state, the contents of SIO0BUF are overwritten by the
new value. Make sure that SIO0SR<TBFL> is "0" before writing data to SIO0BUF.
17.5.3.4 Operation on completion of transmission/reception
When the data transmission/reception is completed, SIO0SR<REND> is set to "1" and an INTSIO0
interrupt request is generated. The operation varies depending on the operating clock.
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TMP89FM46
(1)
When the internal clock is used
If SIO0SR<TBFL> is "1", it is cleared to "0" and the transmit/receive operation continues. If
SIO0SR<REND> is already "1", SIO0SR<OERR> is set to "1".
If SIO0SR<TBFL> is "0", the transmit/receive operation is aborted. The SCLK0 pin becomes the
initial state and the SO0 pin becomes the "H" level. SIO0SR<SEF> remains at "0". When the subsequent data is written to SIO0BUF, SIO0SR<SEF> is set to "1", the SCLK0 pin outputs the clock and
the transmit/receive operation is restarted. To confirm the receive data, read it from SIO0BUF before
writing data to SIO0BUF.
(2)
When an external clock is used
The transmit/receive operation continues. If the external serial clock is input without writing any
data to SIO0BUF, the last data value set to SIO0BUF is re-transmitted. At this time, the transmit
underrun error flag SIO0SR<UERR> is set to "1".
When the next 8-bit data is received completely before SIO0BUF is read, or in the state of
SIO0SR<REND>="1", SIO0SR<OERR> is set to "1".
17.5.3.5 Stopping the transmit/receive operation
Set SIO0CR<SIOS> to "0" to stop the transmit/receive operation. When SIO0SR<SEF> is "0", or when
the shift operation is not in progress, the operation is stopped immediately. Unlike the transmit mode, no
INTSIO0 interrupt request is generated in this state.
When SIO0SR<SEF> is "1", the operation is stopped after the 8-bit data is received completely. At this
time, an INTSIO0 interrupt request is generated.
After the operation has stopped completely, SIO0SR<SIOF, SEF and TBFL> are cleared to "0". Other
SIO0SR registers keep their values.
If the internal clock has been used, the SO0 pin automatically returns to the "H" level. If an external
clock has been used, the SO0 pin keeps the last output value. To return the SO0 pin to the "H" level, write
"00" to SIO0CR<SIOM> when the operation is stopped.
The transmit/receive operation can be forced to stop by setting SIO0CR<SIOM> to "00" during the
operation. By setting SIO0CR<SIOM> to "00", SIO0CR<SIOS> and SIO0SR are cleared to "0" and the
SIO stops the operation, regardless of the SIO0SR<SEF> value. The SO0 pin becomes the "H" level. If
the internal clock is selected, the SCLK0 pin returns to the initial level.
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17. Synchronous Serial Interface (SIO)
17.5 Transfer Modes
TMP89FM46
Start operation
Reserved stop
SIO0CR<SIOS>
SIO0SR<SIOF>
Wait
SIO0SR<SEF>
SIO0SR<TBFL>
SIO0SR<REND>
Internal clock
Data A
Data B
Data C
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SI0 pin (input)
Data D
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Data E
Data F
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SO0 pin (output)
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SCLK0 pin (output)
INTSIO0 interrupt request
SIO0BUF
(Read buffer)
A
B
Reading
data A
C
Reading
data B
Reading
data C
Read SIO0BUF
SIO0BUF
(Write buffer)
D
E
F
G
Write to SIO0BUF
Writing data D
Writing data E
Writing data F
Writing data G
Figure 17-13 8-bit Transmit/Receive Mode (Internal Clock and Reserved Stop)
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TMP89FM46
Start operation
Reserved stop
SIO0CR<SIOS>
11
SIO0CR<SIOM>
00
SIO0SR<SIOF>
SIO0SR<SEF>
SIO0SR<TBFL>
SIO0SR<REND>
Data A
Data B
Data C
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SI0 pin (input)
Data D
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Data E
Data F
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SO0 pin (output)
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SCLK0 pin (input)
INTSIO0 interrupt request
SIO0BUF
(Read buffer)
A
Reading
data A
B
C
Reading
data B
Reading
data C
Read SIO0BUF
SIO0BUF
(Write buffer)
D
E
F
G
Write to SIO0BUF
Writing data D
Writing data E
Writing data F
Writing data G
Figure 17-14 8-bit Transmit/Receive Mode (External Clock and Reserved Stop)
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17. Synchronous Serial Interface (SIO)
17.5 Transfer Modes
TMP89FM46
Start operation
Reserved stop
SIO0CR<SIOS>
SIO0SR<SIOF>
SIO0SR<SEF>
SIO0SR<TBFL>
SIO0SR<REND>
SIO0SR<OERR>
SIO0SR<UERR>
Data A
Data B
Data C
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SI0 pin (input)
Data D
Data D
Data F
Data G
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
SO0 pin (output)
SCLK0 pin (input)
INTSIO0 interrupt request
SIO0BUF
(Read buffer)
A
C
Reading
data A
Reading
data C
Read SIO0BUF
SIO0BUF
(Write buffer)
D
F
G
Write to SIO0BUF
Writing
data D
Writing
data F
Writing
data G
Read SIO0SR
Figure 17-15 8-bit Transmit/Receive Mode (External Clock, Occurrence of Transmit Underrun Error and Occurrence of Overrun Error)
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TMP89FM46
17.6 AC Characteristics
tSCY
tSCYL
tSCYH
VSCLKH
SCLK pin
VSCLKL
tSIS
tSIH
SI pin
tSOD
SO pin
Figure 17-16 AC Characteristics
(VSS = 0 V, VDD = 4.5 V - 5.5 V, Topr = -40 to 85°C)
Parameter
Symbol
Condition
tSCY
SCLK cycle time
SCLK "L" pulse width
tSCYL
SCLK "H" pulse width
tSCYH
Min
Typ.
Max
2 / fcgck
-
-
-
-
-
-
1 / fcgck
− 25
Internal clock operation
SO pin and SCLK pin load capacity=100 pF
1 / fcgck
− 15
SI input setup time
tSIS
60
-
-
SI input hold time
tSIH
35
-
-
SO output delay time
tSOD
−50
-
50
SCLK cycle time
tSCY
2 / fcgck
-
-
SCLK "L" pulse width
tSCYL
1 / fcgck
-
-
SCLK "H" pulse width
tSCYH
1 / fcgck
-
-
50
-
-
External clock operation
SO pin and SCLK pin load capacity=100 pF
SI input setup time
tSIS
SI input hold time
tSIH
50
-
-
SO output delay time
tSOD
0
-
60
SCLK low-level input voltage
tSCLKL
0
-
VDD × 0.30
SCLK high-level input voltage
tSCLKH
VDD × 0.70
-
VDD
SCLK0 pin
SI0 pin
A6
C6
A7
C7
B0
D0
B1
D1
B2
D2
Trailing edge at the Leading edge at the
8th bit (receive edge) 1st bit (transmit edge)
Symbol
Name
Minimum time
tBI
Interval time between bytes
4/fcgck
Figure 17-17 Interval time between bytes
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ns
V
tBI
SO0 pin
Unit
17. Synchronous Serial Interface (SIO)
17.6 AC Characteristics
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TMP89FM46
Page 248
TMP89FM46
18. Serial Bus Interface (SBI)
The TMP89FM46 contains 1 channels of serial bus interface (SBI).
The serial bus interface supports serial communication conforming to the I2C bus standards. It has clock synchronization and arbitration functions, and supports the multi-master in which multiple masters are connected on a bus. It
also supports the unique free data format.
18.1 Communication Format
18.1.1 I2C bus
The I2C bus is connected to devices via the SDA0 and SCL0 pins and can communicate with multiple
devices.
VDD
SDA
SDA
SDA
SCL
SCL
SCL
Device 1
Device 2
Device n
Figure 18-1 Device Connections
Communications are implemented between a master and slave.
The master transmits the start condition, the slave addresses, the direction bit and the stop condition to the
slave(s) connected to the bus, and transmits and receives data.
The slave detects these conditions transmitted from the master by the hardware, and transmits and receives
data.
The data format of the I2C bus that can communicate via the serial bus interface is shown in Figure 18-2.
The serial bus interface does not support the following functions among those specified by the I2C bus standards:
1. Start byte
2. 10-bit addressing
3. SDA and SCL pins falling edge slope control
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18. Serial Bus Interface (SBI)
18.1 Communication Format
TMP89FM46
(a) Addressing format
8 bits
S
Slave address
1
RA
/ C
WK
1 to 8 bits
1
1 to 8 bits
Data
A
C
K
Data
1
1
A
CP
K
1 or more
(b) Addressing format (with restart)
8 bits
S
Slave address
1
RA
/ C
WK
1
S
R/W
ACK
P
1 to 8 bits
1
A
CS
K
Data
8 bits
1
Slave address
1 or more
1 to 8 bits
RA
/ C
WK
Data
1
1 or more
: Start condition
: Direction bit
: Acknowledge bit
: Stop condition
Figure 18-2 Data Format of I2C Bus
18.1.2 Free data format
The free data format is for communication between a master and slave.
In the free data format, the slave address and the direction bit are processed as data.
(a) Free data format
S
8 bits
1
1 to 8 bits
1
1 to 8 bits
Data
A
C
K
Data
A
C
K
Data
1
S
R/W
ACK
P
1 or more
: Start condition
: Direction bit
: Acknowledge bit
: Stop condition
Figure 18-3 Free Data Format
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1
A
CP
K
1
A
CP
K
TMP89FM46
18.2 Configuration
INTSBI Interrupt request
Transfer
control
circuit
SBI0CR2
SBI0CR1
I2C0AR
SBI0DBR
LRB
AL/AAS/AS0
Data
control
circuit
MST/TRX/
BB
SA
Shift
register
ALS
NOACK
SCK
ACK
Clock
control circuit
BC
SWRST
MST/TRX/BB/PIN
Software
reset circuit
SBI0SR2
Figure 18-4 Serial Bus Interface 0 (SBI0)
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Noise
canceller
SCL
Input/output control
Noise
canceller
SDA
18. Serial Bus Interface (SBI)
18.3 Control
TMP89FM46
18.3 Control
The following registers are used to control the serial bus interface and monitor the operation status.
• Serial bus interface control register 1 (SBI0CR1)
• Serial bus interface control register 2 (SBI0CR2)
• Serial bus interface status register 2 (SBI0SR2)
• Serial bus interface data buffer register (SBI0DBR)
• I2C bus address register (I2C0AR)
In addition, the serial bus interface has low power consumption registers that save power when the serial bus interface is not being used.
Low power consumption register 1
POFFCR1
(0x0F75)
7
6
5
4
3
2
1
0
Bit Symbol
-
-
-
SBI0EN
-
-
UART1EN
UART0EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
I2C0 control
0
1
Disable
Enable
UART1EN
UART1 control
0
1
Disable
Enable
UART0EN
UART0 control
0
1
Disable
Enable
SBI0EN
Note 1: When SBI0EN is cleared to "0", the clock supply to the serial bus interface is stopped. At this time, the data written
to the serial bus interface control registers is invalid. When the serial bus interface is used, set SBI0EN to "1" and
then write the data to the serial bus interface control registers.
Serial bus interface control register 1
SBI0CR1
(0x0022)
7
5
4
3
2
1
Bit Symbol
BC
ACK
NOACK
SCK
Read/Write
R/W
R/W
R/W
R/W
0
0
After reset
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0
0
0
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0
0
0
0
TMP89FM46
ACK=0
Number of
clocks for data
transfer
Number of data
bits
Number of clocks
for data transfer
Number of data bits
000:
8
8
9
8
001:
1
1
2
1
010:
2
2
3
2
BC
BC
Number of data bits
011:
3
3
4
3
100:
4
4
5
4
101:
5
5
6
5
110:
6
6
7
6
111:
7
7
8
NOACK
Master mode
0:
Not generating the clocks for an
acknowledge signal. Generate an
interrupt request when the data
transfer is finished
(non-acknowledgement mode)
Generate an interrupt request when the
data transfer is finished
(non-acknowledgement mode)
1:
Generate the clocks for an
acknowledge signal and an interrupt request when the data transfer is finished
(acknowledgement mode)
Count the clocks for an acknowledge signal
and generate an interrupt request when the
data transfer is finished
(acknowledgement mode)
NOACK
Master mode
Slave mode
0:
Don’t Care
Enable the slave address match detection
and the GENERAL CALL detection
1:
Don’t Care
Disable the slave address match detection
and the GENERAL CALL detection
Enables/disables the
slave address match
detection and the GENERAL CALL detection
SCK
SCK
7
ACK
Generation and counting
of the clocks for an
acknowledge signal
ACK
ACK=1
HIGH and LOW periods
of the serial clock in the
master mode
Time before the release
of the SCL pin in the
slave mode
Slave mode
tHIGH(m/fcgck)
tLOW(n/fcgck)
m
n
fscl@fcgck=
8MHz
fscl@fcgck=
4MHz
000:
9
12
381KHz
Reserved (Note5)
001:
11
14
320KHz
Reserved (Note5)
010:
15
18
242KHz
Reserved (Note5)
011:
23
26
163KHz
82KHz
100:
39
42
99KHz
49KHz
101:
71
74
55KHz
28KHz
110:
135
138
29KHz
15KHz
111:
263
266
15KHz
8KHz
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock oscillation circuit clock
Note 2: Don't change the contents of the registers when the start condition is generated, the stop condition is generated or the
data transfer is in progress. Write data to the registers before the start condition is generated or during the period from
when an interrupt request is generated for stopping the data transfer until it is released.
Note 3: After a software reset is generated, all the bits of SBI0CR2 register except SBI0CR2<SBIM> and the SBI0CR1, I2C0AR
and SBI0SR2 registers are initialized.
Note 4: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and the
SBI0CR1, I2C0AR and SBI0DBR registers are initialized.
Note 5: When fcgck is 4MHz, SCK should be not set to 0y000, 0y001 or 0y010 because it is not possible to satisfy the bus specification of fast mode.
Serial bus interface control register 2
SBI0CR2
(0x0023)
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7
6
5
4
3
2
1
0
Bit Symbol
MST
TRX
BB
PIN
SBIM
-
SWRST
Read/Write
W
W
W
W
W
R
W
After reset
0
0
0
1
0
0
0
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18. Serial Bus Interface (SBI)
18.3 Control
TMP89FM46
0: Slave
MST
Master/slave selection
1: Master
0: Receiver
TRX
Transmitter/receiver selection
1: Transmitter
0: Generate the stop condition (when MST, TRX and PIN are "1")
BB
Start/stop generation
1: Generate the start condition (when MST, TRX and PIN are "1")
0: - (Cannot clear this bit by the software)
PIN
Cancel interrupt service request
1: Cancel interrupt service request
SBIM
SWRST
Serial bus interface operation
mode register
0: Port mode
Software reset start bit
The software reset starts by first writing "10" and next writing "01"
1: Serial bus interface mode
Note 1: When SBI0CR2<SBIM> is "0", no value can be written to SBI0CR2 except SBI0CR2<SBIM>. Before writing values to
SBI0CR2, write "1" to SBI0CR2<SBIM> to activate the serial bus interface mode.
Note 2: Don't change the contents of the registers, except SBI0CR2<SWRST>, when the start condition is generated, the stop
condition is generated or the data transfer is in progress. Write data to the registers before the start condition is generated
or during the period from when an interrupt request is generated for stopping the data transfer until it is released.
Note 3: Make sure that the port is in a high state before switching the port mode to the serial bus interface mode. Make sure that
the bus is free before switching the serial bus interface mode to the port mode.
Note 4: SBI0CR2 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit operation.
Note 5: After a software reset is generated, all the bits of SBI0CR2 register except SBI0CR2<SBIM> and the SBI0CR1, I2C0AR
and SBI0SR2 registers are initialized.
Note 6: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and the
SBI0CR1, I2C0AR and SBI0DBR registers are initialized.
Serial bus interface status register 2
SBI0SR2
(0x0023)
7
6
5
4
3
2
1
0
Bit Symbol
MST
TRX
BB
PIN
AL
AAS
AD0
LRB
Read/Write
R
R
R
R
R
R
R
R
After reset
0
0
0
1
0
0
0
*
MST
TRX
Master/slave selection status
monitor
0: Slave
Transmitter/receiver selection
status monitor
0: Receiver
1: Master
1: Transmitter
0: Bus free
BB
Bus status monitor
1: Bus busy
PIN
Interrupt service requests status monitor
0: Requesting interrupt service
1: Releasing interrupt service request
0: -
AL
Arbitration lost detection monitor
1: Arbitration lost detected
AAS
AD0
Slave address match detection
monitor
0: -
"GENERAL CALL" detection
monitor
0: -
1: Detect slave address match or "GENERAL CALL"
1: Detect "GENERAL CALL"
0: Last received bit is "0"
LRB
Last received bit monitor
1: Last received bit is "1"
Note 1: * : Unstable
Note 2: When SBI0CR2<SBIM> becomes "0", SBI0SR is initialized.
Note 3: After a software reset is generated, all the bits of the SBI0CR2 register except SBI0CR2<SBIM> and the SBI0CR1,
I2C0AR and SBI0SR2 registers are initialized.
Note 4: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and the
SBI0CR1, I2C0AR and SBI0DBR registers are initialized.
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TMP89FM46
I2C bus address register
I2C0AR
(0x0024)
7
6
5
4
Read/Write
R/W
R/W
R/W
After reset
0
0
0
Bit Symbol
SA
3
2
1
0
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
SA0
Slave address setting
ALS
Slave address in the slave mode
2
ALS
0: I C bus mode
Communication format selection
1: Free data format
Note 1: Don't set I2C0AR<SA> to "0x00". If it is set to "0x00", the slave address is deemed to be matched when the I2C bus standard start byte ("0x01") is received in the slave mode.
Note 2: Don't change the contents of the registers when the start condition is generated, the stop condition is generated or the
data transfer is in progress. Write data to the registers before the start condition is generated or during the period from
when an interrupt request is generated for stopping the data transfer until it is released.
Note 3: After a software reset is generated, all the bits of the SBI0CR2 register except SBI0CR2<SBIM> and the SBI0CR1,
I2C0AR and SBI0SR2 registers are initialized.
Note 4: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and the
SBI0CR1, I2C0AR and SBI0DBR registers are initialized.
Serial bus interface data buffer register
SBI0DBR
(0x0025)
7
6
5
4
Bit Symbol
SBI0DBR
Read/Write
R/W
After reset
0
0
0
0
3
2
1
0
0
0
0
0
Note 1: Write the transmit data beginning with the most significant bit (bit 7).
Note 2: SBI0DBR has individual writing and reading buffers, and written data cannot be read out. Therefore, SBI0DBR must not
be accessed by using a read-modify-write instruction, such as a bit operation.
Note 3: Don't change the contents of the registers when the start condition is generated, the stop condition is generated or the
data transfer is in progress. Write data to the registers before the start condition is generated or during the period from
when an interrupt request is generated for stopping the data transfer until it is released.
Note 4: To set SBI0CR2<PIN> to "1" by writing the dummy data to SBI0DBR, write 0x00. Writing any data other than 0x00 causes
an improper value in the subsequently received data.
Note 5: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and the
SBI0CR1, I2C0AR and SBI0DBR registers are initialized.
18.4 Functions
18.4.1 Low Power Consumption Function
The serial bus interface has a low power consumption register (POFFCR1) that saves power when the serial
bus interface is not being used.
Setting POFFCR1<SBI0EN> to "0" disables the basic clock supply to the serial bus interface to save power.
Note that this makes the serial bus interface unusable. Setting POFFCR1<SBI0EN> to "1" enables the basic
clock supply to the serial bus interface and makes external interrupts usable.
After reset, POFFCR1<SBI0EN> is initialized to "0", and this makes the serial bus interface unusable. When
using the serial bus interface for the first time, be sure to set POFFCR1<SBI0EN> to "1" in the initial setting of
the program (before the serial bus interface control registers are operated).
Do not change POFFCR1<SBI0EN> to "0" during the serial bus interface operation, otherwise serial bus
interface may operate unexpectedly.
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18. Serial Bus Interface (SBI)
18.4 Functions
TMP89FM46
18.4.2 Selecting the slave address match detection and the GENERAL CALL detection
SBI0CR1<NOACK> enables and disables the slave address match detection and the GENERAL CALL
detection in the slave mode.
Clearing SBI0CR1<NOACK> to "0" enables the slave address match detection and the GENERAL CALL
detection.
Setting SBI0CR1<NOACK> to "1" disables the subsequent slave address match and GENERAL CALL
detections. The slave addresses and "GENERAL CALL" sent from the master are ignored. No acknowledgement is returned and no interrupt request is generated.
In the master mode, SBI0CR1<NOACK> is ignored and has no influence on the operation.
Note:If SBI0CR1<NOACK> is cleared to "0" during data transfer in the slave mode, it remains at "1" and returns an
acknowledge signal of data transfer.
18.4.3 Selecting the number of clocks for data transfer and selecting the acknowledgement or non-acknowledgment mode
1-word data transfer consists of data and an acknowledge signal. When the data transfer is finished, an interrupt request is generated.
SBI0CR1<BC> is used to select the number of bits of data to be transmitted/received subsequently.
The acknowledgment mode is activated by setting SBI0CR1<ACK> to "1".
The master device generates the clocks for an acknowledge signal and outputs an acknowledge signal in the
receiver mode. The slave device counts the clocks for an acknowledge signal and outputs an acknowledge signal in the receiver mode.
The non-acknowledgment mode is activated by setting SBI0CR1<ACK> to "0".
The master device does not generate the clocks for an acknowledge signal. The slave device does not count
the clocks for an acknowledge signal.
18.4.3.1 Number of clocks for data transfer
The number of clocks for data transfer is set by using SBI0CR1<BC> and SBI0CR1<ACK>.
The acknowledgment mode is activated by setting SBI0CR1<ACK> to "1".
In the acknowledgment mode, the master device generates the clocks that correspond to the number of
data bits, generates the clocks for an acknowledge signal, and generates an interrupt request.
The slave device counts the clocks that correspond to the data bits, counts the clocks for an acknowledge signal, and generates an interrupt request.
The non-acknowledgment mode is activated by setting SBI0CR1<ACK> to "0".
In the non-acknowledgment mode, the master device generates the clocks that correspond to the number
of data bits, and generates an interrupt request.
The slave device counts the clocks that correspond to the data bits, and generates an interrupt request.
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TMP89FM46
1
SBI0CR1<BC>="110",
SBI0CR1<BC>="011",
SBI0CR1<ACK>="0"
SBI0CR1<ACK>="1"
2
3
4
5
6
1
2
3
4
Figure 18-5 Number of Clocks for Data Transfer and SBI0CR1<BC> and SBI0CR1<ACK>
The relationship between the number of clocks for data transfer and SBI0CR1<BC> and
SBI0CR1<ACK> is shown in Table 18-1.
Table 18-1 Relationship between the Number of Clocks for Data Transfer and SBI0CR1<BC>
and SBI0CR1<ACK>
ACK=0 (Non-acknowledgment mode)
BC
Number of clocks for data
transfer
000
ACK=1 (Acknowledgment mode)
Number of data bits
Number of clocks for data
transfer
Number of data bits
8
8
9
8
001
1
1
2
1
010
2
2
3
2
011
3
3
4
3
100
4
4
5
4
101
5
5
6
5
110
6
6
7
6
111
7
7
8
7
BC is cleared to "000" by the start condition.
Therefore, the slave address and the direction bit are always transferred in 8-bit units. In other cases, BC
keeps the set value.
Note: SBI0CR1<ACK> must be set before transmitting or receiving a slave address. When SBI0CR1<ACK>
is cleared, the slave address match detection and the direction bit detection are not executed properly.
18.4.3.2 Output of an acknowledge signal
In the acknowledgment mode, the SDA0 pin changes as follows during the period of the clocks for an
acknowledge signal.
• In the master mode
In the transmitter mode, the SDA0 pin is released to receive an acknowledge signal from the
receiver during the period of the clocks for an acknowledge signal. In the receiver mode, the
SDA0 pin is pulled down to the low level and an acknowledge signal is generated during the
period of the clocks for an acknowledge signal.
• In the slave mode
When a match between the received slave address and the slave address set to I2C0AR<SA>
is detected or when a GENERAL CALL is received, the SDA0 pin is pulled down to the low
level and an acknowledge signal is generated during the period of the clocks for an acknowledge signal.
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18. Serial Bus Interface (SBI)
18.4 Functions
TMP89FM46
During the data transfer after the slave address match is detected or a "GENERAL CALL" is
received in the transmitter mode, the SDA0 pin is released to receive an acknowledge signal
from the receiver during the period of the clocks for an acknowledge signal.
In the receiver mode, the SDA0 pin is pulled down to the low level and an acknowledge signal is generated. Table 18-2 shows the states of the SCL0 and SDA0 pins in the acknowledgment mode.
Note: In the non-acknowledgment mode, the clocks for an acknowledge signal are not generated or counted,
and thus no acknowledge signal is output.
Table 18-2 States of the SCL0 and SDA0 Pins in the Acknowledgment Mode
Mode
Pin
Condition
Transmitter
Receiver
SCL0
-
Add the clocks for an
acknowledge signal.
Add the clocks for an acknowledge signal
SDA0
-
Release the pin to receive an
acknowledge signal
Output the low level as an
acknowledge signal to the pin
SCL0
-
Count the clocks for an
acknowledge signal
Count the clocks for an
acknowledge signal
Master
Slave
When the slave address
match is detected or a
"GENERAL CALL" is
received
-
Output the low level as an
acknowledge signal to the pin
During transfer after the
slave address match is
detected or a "GENERAL CALL" is received
Release the pin to receive an
acknowledge signal
Output the low level as an
acknowledge signal to the pin
SDA0
18.4.4 Serial clock
18.4.4.1 Clock source
SBI0CR1<SCK> is used to set the HIGH and LOW periods of the serial clock to be output in the master
mode.
SCK
RA001
tHIGH(m/fcgck)
tLOW(n/fcgck)
m
n
000:
9
12
001:
11
14
010:
15
18
011:
23
26
100:
39
42
101:
71
74
110:
135
138
111:
263
266
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TMP89FM46
SCL output
tHIGH
tLOW
1/fscl
t HIGH = m / fcgck
tLOW = n / fcgck
fscl = 1/(t HIGH + tLOW )
Figure 18-6 SCL Output
Note: There are cases where the HIGH period differs from tHIGH selected at SBI0CR1<SCK> when the rising
edge of the SCL pin becomes blunt due to the load capacity of the bus.
In the master mode, the hold time when the start condition is generated is tHIGH [s] and the setup time
when the stop condition is generated is tHIGH [s].
When SBI0CR2<PIN> is set to "1" in the slave mode, the time that elapses before the release of the
SCL pin is tLOW [s].
In both the master and slave modes, the high level period must be 3/fcgck[s] or longer and the low level
period must be 5/fcgck[s] or longer for the externally input clock, regardless of the SBI0CR1<SCK> setting.
SCL input
tHIGH
tLOW
t HIGH >=
tLOW >=
Figure 18-7 SCL Input
18.4.4.2 Clock synchronization
In the I2C bus, due to the structure of the pin, in order to drive a bus with a wired AND, a master device
which pulls down a clock pulse to low will, in the first place, invalidate the clock pulse of another master
device which generates a high-level clock pulse. Therefore, the master outputting the high level must
detect this to correspond to it.
The serial bus interface circuit has a clock synchronization function. This function ensures normal
transfer even if there are two or more masters on the same bus.
The example explains clock synchronization procedures when two masters simultaneously exist on a
bus.
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18. Serial Bus Interface (SBI)
18.4 Functions
TMP89FM46
SCL pin (Master 1)
Count start
Wait
Count reset
Count reset
SCL pin (Master 2)
SCL (Bus)
a
b
c
Figure 18-8 Example of Clock Synchronization
As Master 1 pulls down the SCL pin to the low level at point "a", the SCL line of the bus becomes the
low level. After detecting this situation, Master 2 resets counting a clock pulse in the high level and sets
the SCL pin to the low level.
Master 1 finishes counting a clock pulse in the low level at point "b" and sets the SCL pin to the high
level. Since Master 2 holds the SCL line of the bus at the low level, Master 1 waits for counting a clock
pulse in the high level. After Master 2 sets a clock pulse to the high level at point "c" and detects the SCL
line of the bus at the high level, Master 1 starts counting a clock pulse in the high level. Then, the master,
which has finished the counting a clock pulse in the high level, pulls down the SCL pin to the low level.
The clock pulse on the bus is determined by the master device with the shortest high-level period and
the master device with the longest low-level period from among those master devices connected to the
bus.
18.4.5 Master/slave selection
To set a master device, SBI0CR2<MST> should be set to "1".
To set a slave device, SBI0CR2<MST> should be cleared to "0". When a stop condition on the bus or an
arbitration lost is detected, SBI0CR2<MST> is cleared to "0" by the hardware.
18.4.6 Transmitter/receiver selection
To set the device as a transmitter, SBI0CR2<TRX> should be set to "1". To set the device as a receiver,
SBI0CR2<TRX> should be cleared to "0".
For the I2C bus data transfer in the slave mode, SBI0CR2<TRX> is set to "1" by the hardware if the direction
bit (R/W) sent from the master device is "1", and is cleared to "0" if the bit is "0".
In the master mode, after an acknowledge signal is returned from the slave device, SBI0CR2<TRX> is
cleared to "0" by hardware if a transmitted direction bit is "1", and is set to "1" by hardware if it is "0". When
an acknowledge signal is not returned, the current condition is maintained.
When a stop condition on the bus or an arbitration lost is detected, SBI0CR2<TRX> is cleared to "0" by the
hardware. Table 18-3 shows SBI0CR2<TRX> changing conditions in each mode and SBI0CR2<TRX> value
after changing.
Note:When SBI0CR1<NOACK> is "1", the slave address match detection and the GENERAL CALL detection are
disabled, and thus SBI0CR2<TRX> remains unchanged.
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Table 18-3 SBI0CR1<TRX> Operation in Each Mode
Mode
Direction bit
Changing condition
"0"
TRX after changing
A received slave address is
the same as the value set to
I2C0AR<SA>
Slave mode
"1"
"0"
"1"
"0"
Master
mode
"1"
ACK signal is returned
"1"
"0"
When the serial bus interface circuit operates in the free data format, a slave address and a direction bit are
not recognized. They are handled as data just after generating the start condition. SBI0CR2<TRX> is not
changed by the hardware.
18.4.7 Start/stop condition generation
When SBI0SR2<BB> is "0", a slave address and a direction bit which are set to the SBI0DBR are output on
a bus after generating a start condition by writing "1" to SBI0CR2 <MST>, SBI0CR2<TRX>, SBI0CR2<BB>
and SBI0CR2<PIN>. It is necessary to set SBI0CR1<ACK> to "1" before generating the start condition.
SCL0 pin
1
SDA0 pin
A6
2
A5
Start condition
3
A4
4
A3
5
A2
6
A1
7
A0
Slave address and direction bit
8
9
R/W
Acknowledge signal
INTSBI0 Interrupt request
Figure 18-9 Generating the Start Condition and a Slave Address
When SBI0CR2<BB> is "1", the sequence of generating the stop condition on the bus is started by writing
"1" to SBI0CR2<MST>, SBI0CR2<TRX> and SBI0CR2<PIN> and writing "0" to SBI0CR2<BB>.
When a stop condition is generated. The SCL line on a bus is pulled down to the low level by another device,
a stop condition is generated after releasing the SCL line.
SCL0 pin
SDA0 pin
Stop condition
Figure 18-10 Stop Condition Generation
The bus condition can be indicated by reading the contents of SBI0SR2<BB>. SBI0SR2<BB> is set to "1"
when the start condition on the bus is detected (Bus Busy State) and is cleared to "0" when the stop condition is
detected (Bus Free State).
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18. Serial Bus Interface (SBI)
18.4 Functions
TMP89FM46
18.4.8 Interrupt service request and release
When a serial bus interface circuit is in the master mode and transferring a number of clocks set by
SBI0CR1<BC> and SBI0CR1<ACK> is complete, a serial bus interface interrupt request (INTSBI0) is generated.
In the slave mode, a serial bus interface interrupt request (INTSBI0) is generated when the above and following conditions are satisfied:
• At the end of the acknowledge signal when the received slave address matches to the value set by the
I2C0AR<SA> with SBI0CR1<NOACK> set at "0"
• At the end of the acknowledge signal when a "GENERAL CALL" is received with
SBI0CR1<NOACK> set at "0"
• At the end of transferring or receiving after matching of the slave address or receiving of "GENERAL
CALL"
When a serial bus interface interrupt request occurs, SBI0CR2<PIN> is cleared to "0". During the time that
SBI0CR2<PIN> is "0", the SCL0 pin is pulled down to the low level.
t LOW
SCL0 pin
1
2
3
7
8
9
SCL0 pin is pulled
to low when
SBI0CR2<PIN> is "0"
1
INTSBI0 interrupt request
SBI0CR2<PIN>
Set SBI0CR2<PIN> to "1" or
write data to SBI0DBR
Figure 18-11 SBI0CR2<PIN> and SCL0 Pin
Writing data to SBI0DBR sets SBI0CR2<PIN> to "1". The time from SBI0CR2<PIN> being set to "1" until
the SBI0 pin is released takes tLOW.
Although SBI0CR2<PIN> can be set to "1" by the software, SBI0CR2<PIN> can not be cleared to "0" by the
software.
18.4.9 Setting of serial bus interface mode
SBI0CR2<SBIM> is used to set serial bus interface mode.
Setting SBI0CR2<SBIM> to "1" selects the serial bus interface mode. Setting it to "0" selects the port mode.
Set SBI0CR2<SBIM> to "1" in order to set serial bus interface mode. Before setting of serial bus interface
mode, confirm serial bus interface pins in a high level, and then, write "1" to SBI0CR2<SBIM>.
And switch a port mode after confirming that a bus is free and set SBI0CR2<SBIM> to "0".
Note:When SBI0CR2<SBIM> is "0", no data can be written to SBI0CR2 except SBI0CR2<SBIM>. Before setting
values to SBI0CR2, write "1" to SBI0CR2<SBIM> to activate the serial bus interface mode.
18.4.10Software reset
The serial bus interface circuit has a software reset function that initializes the serial bus interface circuit. If
the serial bus interface circuit locks up, for example, due to noise, it can be initialized by using this function.
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A software reset is generated by writing "10" and then "01" to SBI0CR2<SWRST>.
After a software reset is generated, the serial bus interface circuit is initialized and all the bits of SBI0CR2
register, except SBI0CR2<SBIM> and the SBI0CR1, I2C0AR<SA> and SBI0SR2 registers, are initialized.
18.4.11Arbitration lost detection monitor
Since more than one master device can exist simultaneously on a bus, a bus arbitration procedure is implemented in order to guarantee the contents of transferred data.
Data on the SDA line is used for bus arbitration of the I2C bus.
The following shows an example of a bus arbitration procedure when two master devices exist simultaneously on a bus. Master 1 and Master 2 output the same data until point "a". After that, when Master 1 outputs
"1" and Master 2 outputs "0", since the SDA line of a bus is wired AND, the SDA line is pulled down to the
low level by Master 2. When the SCL line of a bus is pulled-up at point "b", the slave device reads data on the
SDA line, that is data in Master 2. Data transmitted from Master 1 becomes invalid. The state in Master 1 is
called "arbitration lost". A master device which loses arbitration releases the SDA pin and the SCL pin in order
not to effect data transmitted from other masters with arbitration. When more than one master sends the same
data at the first word, arbitration occurs continuously after the second word.
SCL (Bus)
SDA pin (Master 1)
The SDA pin becomes "1" after losing arbitration.
SDA pin (Master 2)
SDA (Bus)
a
b
Figure 18-12 Arbitration Lost
The serial bus interface circuit compares levels of a SDA line of a bus with its SDA pin at the rising edge of
the SCL line. If the levels are unmatched, arbitration is lost and SBI0SR2<AL> is set to "1".
When SBI0SR2<AL> is set to "1", SBI0CR2<MST> and SBI0CR2<TRX> are cleared to "0" and the mode
is switched to a slave receiver mode. Thus, the serial bus interface circuit stops output of clock pulses during
data transfer after the SBI0SR2<AL> is set to "1". After the data transfer is completed, SBICR2<PIN> is
cleared to "0" and the SCL pin is pulled down to the low level.
SBI0SR2<AL> is cleared to "0" by writing data to the SBI0DBR, reading data from the SBI0DBR or writing
data to the SBI0CR2.
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18. Serial Bus Interface (SBI)
18.4 Functions
TMP89FM46
1
SCL pin
Master A
2
3
4
5
6
7
8
9
1
D7A D6A D5A D4A D3A D2A D1A D0A
SDA pin
1
SCL pin
2
3
4
5
6
7
2
3
D7A’ D6A’ D5A’
8
9
Stop clock output
Master B
D7A D6A
SDA pin
Releasing SDA pin and SCL pin
to high level as losing arbitration.
SBI0SR2<AL>
SBI0CR2<MST>
SBI0CR2<PIN>
Access to SBI0DBR or
SBI0CR2
INTSBI0 Interrupt request
Figure 18-13 Example When Master B is a Serial Bus Interface Circuit
18.4.12Slave address match detection monitor
In the slave mode, SBI0SR2<AAS> is set to "1" when the received data is "GENERAL CALL" or the
received data matches the slave address setting by I2C0AR<SA> with SBI0CR1<NOACK> set at "0" and the
I2C bus mode is active (I2C0AR<ALS>="0").
Setting SBI0CR1<NOACK> to "1" disables the subsequent slave address match and GENERAL CALL
detections. SBI0SR2<AAS> remains at "0" even if a "GENERAL CALL" is received or the same slave
address as the I2C0AR<SA> set value is received.
When a serial bus interface circuit operates in the free data format (I2C0AR<ALS>= "1"), SBI0SR2<AAS>
is set to "1" after receiving the first 1-word of data. SBI0SR2<AAS> is cleared to "0" by writing data to the
SBI0DBR or reading data from the SBI0DBR.
SA6
SCL0 (Bus)
Start condition
SDA0 (Bus)
SA5
SA4
SA3
SA2
SA1
SA0
R/W
Slave address + Direction bit
Output of an acknowledge signal
SDA0 pin
Writing or reading SBI0DBR
INTSBI0 Interrupt request
Figure 18-14 Changes in the Slave Address Match Detection Monitor
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18.4.13GENERAL CALL detection monitor
SBI0SR2<AD0> is set to "1" when SBI0CR1<NOACK> is "0" and GENERAL CALL (all 8-bit received
data is "0" immediately after a start condition) in a slave mode.
Setting SBI0CR1<NOACK> to "1" disables the subsequent slave address match and GENERAL CALL
detections. SBI0SR2<AD0> remains at "0" even if a "GENERAL CALL" is received.
SBI0SR2<AD0> is cleared to "0" when a start or stop condition is detected on a bus.
SCL (Bus)
1
2
3
4
5
6
7
8
9
SDA (Bus)
GENERAL CALL
Start condition
Stop condition
SDA0 端子
Output of an acknowledge signal
SBI0SR2<AD0>
INTSBI0 Interrupt request
Figure 18-15 Changes in the GENERAL CALL Detection Monitor
18.4.14Last received bit monitor
The SDA line value stored at the rising edge of the SCL line is set to SBI0SR2<LRB>.
In the acknowledge mode, immediately after an interrupt request is generated, an acknowledge signal is read
by reading the contents of SBI0SR2<LRB>.
SCL
1
2
3
4
5
6
7
8
SDA
D7
D6
D5
D4
D3
D2
D1
D0
9
Acknowledgment
SBI0SR2<LRB>
D7
D6
D5
D4
D3
D2
D1
D
Acknowledgment
Figure 18-16 Changes in the Last Received Bit Monitor
18.4.15Slave address and address recognition mode specification
When the serial bus interface circuit is used in the I2C bus mode, clear I2C0AR<ALS> to "0", and set
I2C0AR<SA> to the slave address.
When the serial bus interface circuit is used with a free data format not to recognize the slave address, set
I2C0AR<ALS> to "1". With a free data format, the slave address and the direction bit are not recognized, and
they are processed as data from immediately after the start condition.
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18. Serial Bus Interface (SBI)
18.5 Data Transfer of I2C Bus
TMP89FM46
18.5 Data Transfer of I2C Bus
18.5.1 Device initialization
Set POFFCR1<SBI0EN> to "1".
After confirming that the serial bus interface pin is high level, set SBI0CR2<SBIM> to "1" to select the
serial bus interface mode.
Set SBI0CR1<ACK> to "1", SBI0CR1<NOACK> to "0" and SBI0CR1<BC> to "000" to count the number
of clocks for an acknowledge signal, to enable the slave address match detection and the GENERAL CALL
detection, and set the data length to 8 bits. Set THIGH and TLOW at SBI0CR1<SCK>.
Set a slave address at I2C0AR<SA> and set I2C0AR<ALS> to "0" to select the I2C bus mode.
Finally, set SBI0CR2<MST>, SBI0CR2<TRX> and SBI0CR2<BB> to "0", SBI0CR2<PIN> to "1" and
SBI0CR2<SWRST> to "00" for specifying the default setting to a slave receiver mode.
Note:The initialization of a serial bus interface circuit must be complete within the time from all devices which are
connected to a bus have initialized to and device does not generate a start condition. If not, the data can not
be received correctly because the other device starts transferring before an end of the initialization of a serial
bus interface circuit.
Example :Initialize a device
CHK_PORT:
CMP
(P2PRD), 0x0C
; Checks whether the serial bus interface pin is at the high level
JR
NZ, CHK_PORT
LD
(SBI0CR2), 0x18
; Selects the serial bus interface mode
LD
(SBI0CR1), 0x16
; Selects the acknowledgment mode and sets SBI0CR1<SCK> to
"110"
LD
(I2C0AR), 0xa0
; Sets the slave address to 1010000 and selects the I2C bus mode
LD
(SBI0CR2), 0x18
; Selects the slave receiver mode
18.5.2 Start condition and slave address generation
Confirm a bus free status (SBI0SR2<BB>="0").
Set SBI0CR1<ACK> to "1" and specify a slave address and a direction bit to be transmitted to the
SBI0DBR.
By writing "1" to SBI0CR2<MST>, SBI0CR2<TRX>, SBI0CR2<BB> and SBI0CR2<PIN>, the start condition is generated on a bus and then, the slave address and the direction bit which are set to the SBI0DBR are
output. The time from generating the START condition until the falling SBI0 pin takes tHIGH.
An interrupt request occurs at the 9th falling edge of a SCL clock cycle, and SBI0CR2<PIN> is cleared to
"0". The SCL0 pin is pulled down to the low level while SBI0CR2<PIN> is "0". When an interrupt request
occurs, SBI0CR2<TRX> changes by the hardware according to the direction bit only when an acknowledge
signal is returned from the slave device.
Note 1: Do not write a slave address to the SBI0DBR while data is transferred. If data is written to the SBI0DBR,
data to be output may be destroyed.
Note 2: The bus free state must be confirmed by software within 98.0 µs (the shortest transmitting time according to
the standard mode I2C bus standard) or 23.7µs (the shortest transmitting time according to the fast mode
I2C bus standard) after setting of the slave address to be output. Only when the bus free state is confirmed,
set "1" to SBI0CR2<MST>, SBI0CR2<TRX>, SBI0CR2<BB> and SBI0CR2<PIN> to generate the start
conditions. If the writing of slave address and setting of SBI0CR2<MST>, SBI0CR2<TRX>, SBI0CR2<BB>
and SBI0CR2<PIN> doesn't finish within 98.0µs or 23.7µs, the other masters may start the transferring and
the slave address data written in SBI0DBR may be broken.
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Example :Generate the start condition
CHK_BB:
SCL0 pin
TEST
(SBI0SR2).BB
; Confirms that the bus is free
JR
F, CHK_BB
LD
(SBI0DBR), 0xcb
; The transmission slave address 0x65 and the direction bit "1"
LD
(SBI0CR2), 0xf8
; Write "1" to SBI0CR2<MST>, <TRX>, <BB> and <PIN> to "1"
1
2
3
4
5
6
7
8
9
SDA0 pin
Start condition
Slave address + Direction bit
Acknowledgem
ent signal from
a slave
SBI0CR1<PIN>
Interrupt request
signal
SBI0CR2<TRX>
SBI0CR2 <TRX> is cleared to "0" when
the direction bit is "1"and an
acknowledge signal is returned.
Figure 18-17 Generating the Start Condition and the Slave Address
18.5.3 1-word data transfer
Check SBI0SR2<MST> by the interrupt process after a 1-word data transfer is completed, and determine
whether the mode is a master or slave.
18.5.3.1 When SBI0SR2<MST> is "1" (Master mode)
Check SBI0SR2<TRX> and determine whether the mode is a transmitter or receiver.
(1)
When SBI0SR2<TRX> is "1" (Transmitter mode)
Check SBI0SR2<LRB>. When SBI0SR2<LRB> is "1", a receiver does not request data. Implement the process to generate a stop condition (described later) and terminate data transfer.
When SBI0SR2<LRB> is "0", the receiver requests subsequent data. When the data to be transmitted subsequently is other than 8 bits, set SBI0CR1<BC> again, set SBI0CR1<ACK> to "1", and
write the transmitted data to SBI0DBR.
After writing the data, SBI0CR2<PIN> becomes "1", a serial clock pulse is generated for transferring the subsequent 1-word data from the SCL0 pin, and then the 1-word data is transmitted from the
SDA0 pin.
After the data is transmitted, an interrupt request occurs. SBI0CR2<PIN> become "0" and the
SCL0 pin is set to the low level. If the data to be transferred is more than one word in length, repeat
the procedure from the SBI0SR2<LRB> checking above.
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18. Serial Bus Interface (SBI)
18.5 Data Transfer of I2C Bus
TMP89FM46
SCL0 pin
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
9
Write to SBI0DBR
SDA0 pin
Acknowledge signal
from the receiver
SBI0CR2<PIN>
INTSBI0 Interrupt request
Figure 18-18 Example when SBI0CR1<BC>="000" and SBI0CR1<ACK>="1"
(2)
When SBI0SR2<TRX> is "0" (Receiver mode)
When the data to be transmitted subsequently is other than 8 bits, set SBI0CR1<BC> again. Set
SBI0CR1< ACK> to "1" and read the received data from the SBI0DBR (Reading data is undefined
immediately after a slave address is sent).
After the data is read, SBI0CR2<PIN> becomes "1" by writing the dummy data (0x00) to the
SBI0DBR. The serial bus interface circuit outputs a serial clock pulse to the SCL0 pin to transfer the
subsequent 1-word data and sets the SDA0 pin to "0" at the acknowledge signal timing.
An interrupt request occurs and SBI0CR2<PIN> becomes "0". Then a serial bus interface circuit
outputs a clock pulse for 1-word data transfer and the acknowledge signal by writing data to the
SBI0DBR or setting SBI0CR2<PIN> to "1" after reading the received data.
Read SBI0DBR
Write to SBI0DBR
SCL0 pin
9
SDA0 pin
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
9
New D7
Acknowledge signal
to the transmitter
SBI0CR2<PIN>
INTSBI0 Interrupt
request
Figure 18-19 Example when SBI0CR1<BC>="000" and SBI0CR1<ACK>="1"
To make the transmitter terminate transmission, execute following procedure before receiving a
last data.
1. Read the received data.
2. Clear SBI0CR1<ACK> to "0" and set SBI0CR1<BC> to "000".
3. To set SBI0CR2<PIN> to "1", write a dummy data (0x00) to SBI0DBR.
Transfer 1-word data in which no clock is generated for an acknowledge signal by setting
SBI0CR2<PIN> to "1". Next, execute following procedure.
1. Read the received data.
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2. Clear SBI0CR1<ACK> to "0" and set SBI0CR1<BC> to "001".
3. To set SBI0CR2<PIN> to "1", write a dummy data (0x00) to SBI0DBR.
Transfer 1-bit data by setting SBI0CR1<PIN> to "1".
In this case, since the master device is a receiver, the SDA line on a bus keeps the high level. The
transmitter receives the high-level signal as a negative acknowledge signal. The receiver indicates to
the transmitter that data transfer is complete.
After 1-bit data is received and an interrupt request has occurred, generate the stop condition to terminate data transfer.
SCL0 pin
9
SDA0 pin
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
Negative
acknowledge signal
to the transmitter
SBI0CR<PIN>
INTSBI0 Interrupt
request
After reading the received data, clear
SBI0CR1<ACK> to "0" and writing the
dummy data (0x00)
After reading the reveived
data, set SBI0CR1<BC> to
"001" and write dummy data
(0x00)
Figure 18-20 Termination of Data Transfer in the Master Receiver Mode
18.5.3.2 When SBI0SR2<MST> is "0" (Slave mode)
In the slave mode, a serial bus interface circuit operates either in the normal slave mode or in the slave
mode after losing arbitration.
In the slave mode, the conditions of generating the serial bus interface interrupt request (INTSBI0) are
follows:
• At the end of the acknowledge signal when the received slave address matches the value set by the
I2C0AR<SA> with SBI0CR1<NOACK> set at "0"
• At the end of the acknowledge signal when a "GENERAL CALL" is received with
SBI0CR1<NOACK> set at "0"
• At the end of transferring or receiving after matching of slave address or receiving of "GENERAL
CALL"
The serial bus interface circuit changes to the slave mode if arbitration is lost in the master mode. And
an interrupt request occurs when the word data transfer terminates after losing arbitration. The generation
of the interrupt request and the behavior of SBI0CR2<PIN> after losing arbitration are shown in Table 184.
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18. Serial Bus Interface (SBI)
18.5 Data Transfer of I2C Bus
TMP89FM46
Table 18-4 The Behavior of an interrupt request and SBI0CR2<PIN> After Losing Arbitration
When the Arbitration Lost Occurs during Transmission of Slave Address as a Master
When the Arbitration Lost Occurs during Transmission of Data as Master Transmitter
interrupt request
An interrupt request is generated at the termination of word-data transfer.
SBI0CR2<PIN>
SBI0CR2<PIN> is cleared to "0".
When an interrupt request occurs, SBI0CR2<PIN> is reset to "0", and the SCL0 pin is set to the low
level. Either writing data to the SBI0DBR or setting SBI0CR2<PIN> to "1" releases the SCL0 pin after
taking tLOW.
Check SBI0SR2<AL>, SBI0SR2<TRX>, SBI0SR2<AAS> and SBI0SR2<AD0> and implement processes according to conditions listed in Table 18-5.
Table 18-5 Operation in the Slave Mode
SBI0SR2
<TRX>
SBI0SR2
<AL>
1
SBI0SR2
<AAS>
1
1
SBI0SR2
<AD0>
0
0
1
Conditions
The serial bus interface circuit loses
arbitration when transmitting a slave
address, and receives a slave address
of which the value of the direction bit
sent from another master is "1".
In the slave receiver mode, the serial
bus interface circuit receives a slave
address of which the value of the direction bit sent from the master is "1".
1
0
In the slave transmitter mode, the serial
bus interface circuit finishes the transmission of 1-word data
1/0
The serial bus interface circuit loses
arbitration when transmitting a slave
address, and receives a slave address
of which the value of the direction bit
sent from another master is "0" or
receives a "GENERAL CALL".
Write the dummy data (0x00) to the
SBI0DBR to set SBI0CR2<PIN> to "1", or
write "1" to SBI0CR2<PIN>.
0
The serial bus interface circuit loses
arbitration when transmitting a slave
address or data, and terminates transferring the word data.
The serial bus interface circuit is changed
to the slave mode. Write the dummy data
(0x00) to the SBI0DBR to clear
SBI0SR2<AL> to "0" and set
SBI0CR2<PIN> to "1".
1/0
In the slave receiver mode, the serial
bus interface circuit receives a slave
address of which the value of the direction bit sent from the master is "0" or
receives "GENERAL CALL".
Write the dummy data (0x00) to the
SBI0DBR to set SBI0CR2<PIN> to "1", or
write "1" to SBI0CR2<PIN>.
1/0
In the slave receiver mode, the serial
bus interface circuit terminates the
receipt of 1-word data.
Set the number of bits in 1-word to
SBI0CR1<BC>, read the received data
from the SBI0DBR and write the dummy
data (0x00).
1
0
0
1
0
0
Set the number of bits in 1 word to
SBI0CR1<BC> and write the transmitted
data to the SBI0DBR.
Check SBI0SR2<LRB>. If it is set to "1",
set SBI0CR2<PIN> to "1" since the
receiver does not request subsequent
data. Then, clear SBI0CR2<TRX> to "0"
to release the bus. If SBI0SR2<LRB> is
set to "0", set the number of bits in 1 word
to SBI0CR1<BC> and write the transmitted data to SBI0DBR since the receiver
requests subsequent data.
0
0
Process
Note: In the slave mode, if the slave address set in I2C0AR<SA> is "0x00", a START Byte "0x01" in I2C bus standard is received,
the device detects slave address match and SBI0CR2<TRX> is set to "1". Do not set I2C0AR<SA> to "0x00".
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TMP89FM46
18.5.4 Stop condition generation
When SBI0CR2<BB> is "1", a sequence of generating a stop condition is started by setting "1" to
SBI0CR2<MST>, SBI0CR2<TRX> and SBI0CR2<PIN> and clearing SBI0CR2<BB> to "0". Do not modify
the contents of SBI0CR2<MST>, SBI0CR2<TRX>, SBI0CR2<BB> and SBI0CR2<PIN> until a stop condition is generated on a bus.
When a SCL line on a bus is pulled down by other devices, a serial bus interface circuit generates a stop condition after a SCL line is released.
The time from the releasing SCL line until the generating the STOP condition takes tHIGH.
Example :Generate the stop condition
CHK_BB:
LD
(SBI0CR2), 0xD8
; Sets SBI0CR2<MST>, <TRX> and <PIN> to "1" and SBI0CR2<BB> to
"0"
TEST
(SBI0SR2).BB
;Waits until the bus is set free
JR
T, CHK_BB
SBI0CR2<MST>="1"
SBI0CR2<TRX>="1"
SBI0CR2<BB>="0"
SBI0CR2<PIN>="1"
If the SCL of the bus is pulled
down by other devices, the stop
condition is generated after it is
released
Stop condition
SCL0 pin
SCL (Bus)
SDA0 pin
SBI0CR2<PIN>
SBI0SR2<BB>
Figure 18-21 Stop Condition Generation
18.5.5 Restart
Restart is used to change the direction of data transfer between a master device and a slave device during
transferring data. The following explains how to restart the serial bus interface circuit.
Clear SBI0CR2<MST>, SBI0CR2<TRX> and SBI0CR2<BB> to "0" and set SBI0CR2 <PIN> to "1". The
SDA0 pin retains the high level and the SCL0 pin is released.
Since this is not a stop condition, the bus is assumed to be in a busy state from other devices.
Check SBI0SR2<BB> until it becomes "0" to check that the SCL0 pin of the serial bus interface circuit is
released.
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18. Serial Bus Interface (SBI)
18.5 Data Transfer of I2C Bus
TMP89FM46
Check SBI0SR2<LRB> until it becomes "1" to check that the SCL line on the bus is not pulled down to the
low level by other devices.
After confirming that the bus stays in a free state, generate a start condition in the procedure "18.5.2 Start
condition and slave address generation".
In order to meet the setup time at a restart, take at least 4.7µs of waiting time by the software in the standard
mode I2C bus standard or at least 0.6µs of waiting time in the fast mode I2C bus standard from the time of
restarting to confirm that a bus is free until the time to generate a start condition.
Note:When the master is in the receiver mode, it is necessary to stop the data transmission from the slave device
before the STOP condition is generated. To stop the transmission, the master device make the slave device
receiving a negative acknowledge. Therefore, SBI0SR2<LRB> is "1" before generating the Restart and it can
not be confirmed that SCL line is not pulled down by other devices. Please confirm the SCL line state by reading the port.
Example :Generate a restart
CHK_BB:
CHK_LRB:
LD
(SBI0CR2), 0x18
; Sets SBI0CR2<MST>, <TRX> and <BB> to "0" and SBI0CR2<PIN> to
"1"
TEST
(SBI0SR2).BB
; Waits until SBI0SR2<BB> becomes "0"
JR
T, CHK_BB
TEST
(SBI0SR2).LRB
JR
F, CHK_LRB
; Waits until SBI0SR2<LRB> becomes "1"
.
.
; Wait time process by the software
.
LD
(SBI0CR2), 0xf8
; Sets SBI0CR2<MST>, <TRX>, <BB> and <PIN> to "1"
SBI0CR2<MST>="1"
SBI0CR2<TRX>="1"
SBI0CR2<BB>="1"
SBI0CR2<PIN>="1"
SBI0CR2<MST>="0"
SBI0CR2<TRX>="0"
SBI0CR2<BB>="0"
SBI0CR2<PIN>="1"
4.7 µs min. in the normal mode or
0.6 µs min. in the fast mode
SCL (Bus)
SCL0 pin
SDA0 pin
SBI0SR2<LRB>
SBI0SR2<BB>
SBI0CR2<PIN>
Figure 18-22 Timing Diagram When Restarting
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Start condition
TMP89FM46
18.6 AC Specifications
The AC specifications are as listed below.
The operating mode (fast or standard) mode should be selected suitable for frequency of fcgck. For these operating
mode, refer to the following table.
Table 18-6 AC Specifications (Circuit Output Timing)
Standard mode
Parameter
Fast mode
Symbol
Unit
MIN.
MAX.
MIN.
MAX.
fSCL
0
fcgck / (m+n)
0
fcgck / (m+n)
kHz
Hold time (re)start condition. This
period is followed by generation of the
first clock pulse.
tHD;STA
m / fcgck
-
m / fcgck
-
µs
Low-level period of SCL clock (output)
tLOW
n / fcgck
-
n / fcgck
-
µs
High-level period of SCL clock (output)
tHIGH
m / fcgck
-
m / fcgck
-
µs
Low-level period of SCL clock (input)
tLOW
5 / fcgck
-
5 / fcgck
-
µs
High-level period of SCL clock (input)
tHIGH
3 / fcgck
-
3 / fcgck
-
µs
Restart condition setup time
tSU;STA
Depends on
the software
-
Depends on
the software
-
µs
Data hold time
tHD;DAT
0
5 / fcgck
0
5 / fcgck
µs
Data setup time
tSU;DAT
250
-
100
-
ns
Rising time of SDA and SCL signals
tr
-
1000
-
300
ns
Falling time of SDA and SCL signals
tf
-
300
-
300
ns
tSU;STO
m / fcgck
-
m / fcgck
-
µs
Bus free time between the stop condition and the start condition
tBUF
Depends on
the software
-
Depends on
the software
-
µs
Time before rising of SCL after
SBICR2<PIN> is changed from "0" to
"1"
tSU;SCL
n / fcgck
-
n / fcgck
-
µs
SCL clock frequency
Stop condition setup time
Note: For m and n, refer to"18.4.4.1 Clock source".
tf
t SU;DAT
t LOW
tr
t HD;STA
tf
t HD;STA
t HD;DAT
t SU;STA
t HIGH
Figure 18-23 Definition of Timing (No. 1)
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tf
t BUF
t SU;STO
18. Serial Bus Interface (SBI)
18.6 AC Specifications
TMP89FM46
SCL
SBICR2<PIN>
t SU;SCL
Figure 18-24 Definition of Timing (No. 2)
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TMP89FM46
19. Key-on Wakeup (KWU)
The key-on wakeup is a function for releasing the STOP mode at the STOP pin or at pins KWI7 through KWI0.
19.1 Configuration
SYSCR1<RELM>
S
Stop mode
Y 0
release signal
1
(to be released
Selector
if set to “1”)
Rising edge
detection
Port
STOP
Port
KWI0
Port
KWI1
Port
KWI2
Port
KWI3
Port
KWI4
Port
KWI5
Port
KWI6
Port
KWI7
KWUCR0
(0x0FC4) 7 6 5 4 3 2 1 0
KWUCR1
(0x0FC5) 7 6 5 4 3 2 1 0
Figure 19-1 Key-on Wakeup Circuit
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19. Key-on Wakeup (KWU)
19.1 Configuration
TMP89FM46
19.2 Control
Key-on wakeup control registers (KWUCR0 and KWUCR1) can be configured to designate the key-on wakeup
pins (KWI7 through KWI0) as STOP mode release pins and to specify the STOP mode release levels of each of these
designated pins.
Key-on wakeup control register 0
KWUCR0
(0x0FC4)
7
6
5
4
3
2
1
0
Bit Symbol
KW3LE
KW3EN
KW2LE
KW2EN
KW1LE
KW1EN
KW0LE
KW0EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
KW3LE
STOP mode release level of KWI3
pin
0:
1:
Low level
High level
KW3EN
Input enable/disable control of
KWI3 pin
0:
1:
Disable
Enable
KW2LE
STOP mode release level of KWI2
pin
0:
1:
Low level
High level
KW2EN
Input enable/disable control of
KWI2 pin
0:
1:
Disable
Enable
KW1LE
STOP mode release level of KWI1
0:
1:
Low level
High level
KW1EN
Input enable/disable control of
KWI1 pin
0:
1:
Disable
Enable
KW0LE
STOP mode release level of KWI0
pin
0:
1:
Low level
High level
KW0EN
Input enable/disable control of
KWI0 pin
0:
1:
Disable
Enable
Key-on wakeup control register 1
KWUCR1
(0x0FC5)
RA000
7
6
5
4
3
2
1
0
Bit Symbol
KW7LE
KW7EN
KW6LE
KW6EN
KW5LE
KW5EN
KW4LE
KW4EN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
KW7LE
STOP mode release level of KWI7
pin
0:
1:
Low level
High level
KW7EN
Input enable/disable control of
KWI7 pin
0:
1:
Disable
Enable
KW6LE
STOP mode release level of KWI6
pin
0:
1:
Low level
High level
KW6EN
Input enable/disable control of
KWI6 pin
0:
1:
Disable
Enable
KW5LE
STOP mode release level of KWI5
pin
0:
1:
Low level
High level
KW5EN
Input enable/disable control of
KWI5 pin
0:
1:
Disable
Enable
KW4LE
STOP mode release level of KWI4
pin
0:
1:
Low level
High level
KW4EN
Input enable/disable control of
KWI4 pin
0:
1:
Disable
Enable
Page 276
TMP89FM46
19.3 Functions
By using the key-on wakeup function, the STOP mode can be released at a STOP pin or at KWIm pin (m: 0
through 7). After resetting, the STOP pin is the only STOP mode release pin. To designate the KWIm pin as a STOP
mode release pin, therefore, it is necessary to configure the key-on wakeup control register (KWUCRn) (n: 0 or 1).
Because the STOP pin lacks a function for disabling inputs, it can be designated as a pin for receiving a STOP mode
release signal, irrespective of whether the key-on wakeup function is used or not.
• Setting KWUCRn and P4PU registers
To designate a key-on wakeup pin (KWIm) as a STOP mode release pin, set KWUCRn<KWmEN> to
"1". After KWIm pin is set to "1" at KWUCRn<KWmEN>, a specific STOP mode release level can be
specified for this pin at KWUCRn<KWmLE>. If KWUCRn<KWmLE> is set to "0", STOP mode is
released when an input is at a low level. If it is set to "1", STOP mode is released when an input is at a
high level. For example, if you want to release STOP mode by inputting a high-level signal into a KWI0
pin, set KWUCR0<KW0EN> to "1", " and KWUCR0<KW0LE> to "1".
Each KWIm pin can be connected to internal pull-up resistors. Before connecting to internal pull-up
resistors, the corresponding bits in the pull-up control register (P4PU) at port P4 must be set to "1".
• Starting STOP mode
To start the STOP mode, set SYSCR1<RELM> to "1" (level release mode), and SYSCR1<STOP> to
"1".
To use the key-on wakeup function, do not set SYSCR1<RELM> to "0" (edge release mode). If the
key-on wakeup function is used in edge release mode, STOP mode cannot be released, although a rising
edge is input into the STOP pin. This is because the KWIm pin enabling inputs to be received is at a
release level after the STOP mode starts.
• Releasing STOP mode
To release STOP mode, input a high-level signal into the STOP pin or input a specific release level into
the KWIm pin for which receipt of inputs is enabled. If you want to release STOP mode at the KWIm pin,
rather than the STOP pin, continue inputting a low-level signal into the STOP pin throughout the period
from when the STOP mode is started to when it is released.
If the STOP pin or KWIm pin is already at a release level when the STOP mode starts, the following
instruction will be executed without starting the STOP mode (with no warm-up performed).
Note 1: If an analog voltage is applied to KWIm pin for which receipt of inputs is enabled by the key-on wakeup control
register (KWUCRn) setting, a penetration current will flow. Therefore, in this case, the analog voltage should be
not applied to this pin.
Table 19-1 STOP Mode Release Level (edge)
Release level (edge)
Pin name
SYSCR1<RELM>="1"
(level release mode)
KWUCRn<KWmLE>="0"
KWIm
RA000
KWUCRn<KWmLE>="1"
"H" level
STOP
SYSCR1<RELM>="0"
(edge release mode)
"L" level
Rising edge
"H" level
Page 277
Don't use
19. Key-on Wakeup (KWU)
19.1 Configuration
TMP89FM46
Example :A case in which STOP mode is started with the release level of the STOP pin set to a high level and the release
level of KWI0 set to a low level (connected to an internal pull-up resistor of the KWI0 pin)
DI
RA000
; IMF←0
SET
(P4PU).0
; KWI0 (P40) connected to a pull-up resistor
LD
(KWUCR0), 00000001B
; the KWI0 pin is set to enable inputs, and its release level is set
to a low level.
LD
(SYSCR1), 10100000B
; Starting in level release mode
Page 278
TMP89FM46
20. 10-bit AD Converter (ADC)
The TMP89FM46 has a 10-bit successive approximation type AD converter.
20.1 Configuration
The circuit configuration of the 10-bit AD converter is shown in Figure 20-1.
It consists of control registers ADCCR1 and ADCCR2, converted value registers ADCDRL and ADCDRH, a DA
converter, a sample-hold circuit, a comparator, a successive comparison circuit, etc.
DA converter
VAREF
VSS
R/2
R
R/2
AVDD
Sample-hold
circuit
Input selector
AIN0
A
Reference
voltage
Y
10
Analog
comparator
n
S EN
Shift clock
10
INTADC
Control circuit
AINEN
ADRS
4
SAIN
Successive
approximation circuit
2
AMD
ADCCR1
EOCF
ADBF
AIN7
3
ACK
ADCCR2
AD converter control registers 1 and 2
8
ADCDRL
2
ADCDRH
AD converted value registers 1 and 2
Figure 20-1 10-bit AD Converter
Note 1: Before using the AD converter, set an appropriate value to the I/O port register which is also used as an analog
input port. For details, see the section on "I/O ports".
Note 2: The DA converter current (IREF) is automatically cut off at times other than during AD conversion.
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20. 10-bit AD Converter (ADC)
20.2 Control
TMP89FM46
20.2 Control
The AD converter consists of the following four registers:
1. AD converter control register 1 (ADCCR1)
This register selects an analog channel in which to perform AD conversion, selects an AD conversion
operation mode, and controls the start of the AD converter.
2. AD converter control register 2 (ADCCR2)
This register selects the AD conversion time, and monitors the operating status of the AD converter.
3. AD converted value registers (ADCDRH and ADCDRL)
These registers store the digital values generated by the AD converter.
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TMP89FM46
AD converter control register 1
ADCCR1
(0x0034)
7
6
5
4
3
2
Bit Symbol
ADRS
AMD
AINEN
SAIN
Read/Write
R/W
R/W
R/W
R/W
After reset
0
0
0
0
AD conversion start
0:
1:
AMD
AD operating mode
00:
01:
10:
11:
AINEN
Analog input control
0:
1:
ADRS
SAIN
Analog input channel select
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
1011:
1100:
1101:
1110:
1111:
0
0
1
0
0
0
AD conversion start
AD operation disable, forcibly stop AD operation
Single mode
Reserved
Repeat mode
Analog input disable
Analog input enable
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note 1: Do not perform the following operations on the ADCCR1 register while AD conversion is being executed
(ADCCR2<ADBF>="1").
- Changing SAIN
- Setting AINEN to "0"
- Changing AMD (except a forced stop by setting AMD to "00")
- Setting ADRS to "1"
Note 2: If you want to disable all analog input channels, set AINEN to "0".
Note 3: Although analog input pins are also used as input/output ports, it is recommended for the purpose of maintaining the accuracy of AD conversion that you do not execute input/output instructions during AD conversion. Additionally, do not input
widely varying signals into the ports adjacent to analog input pins.
Note 4: When STOP, IDLE0 or SLOW mode is started, ADRS, AMD and AINEN are initialized to "0". If you use the AD converter
after returning to NORMAL mode, you must reconfigure ADRS, AMD and AINEN.
Note 5: After the start of AD conversion, ADRS is automatically cleared to "0" ("0" is read).
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20. 10-bit AD Converter (ADC)
20.2 Control
TMP89FM46
AD converter control register 2
ADCCR2
(0x0035)
7
6
5
4
3
2
1
Bit Symbol
EOCF
ADBF
-
-
"0"
ACK
Read/Write
R
R
R
R
W
R/W
After reset
0
0
0
0
0
0
0
EOCF
AD conversion end flag
0:
1:
Before conversion or during conversion
Conversion end
ADBF
AD conversion BUSY flag
0:
1:
AD conversion being halted
AD conversion being executed
ACK
000:
001:
010:
011:
100:
101:
110:
111:
AD conversion time select (examples of AD conversion time are
shown in the table below)
0
0
39/fcgck
78/fcgck
156/fcgck
312/fcgck
624/fcgck
1248/fcgck
Reserved
Reserved
Note 1: Make sure that you make the ACK setting when AD conversion is in a halt condition (ADCCR2<ADBF>="0").
Note 2: Make sure that you write "0" to bit 3 of ADCCR2.
Note 3: If STOP, IDLE0 or SLOW mode is started, EOCF and ADBF are initialized to "0".
Note 4: If the AD converted value register (ADCDRH) is read, EOCF is cleared to "0". It is also cleared to "0" if AD conversion is
started (ADCCR1<ADRS>="1") without reading ADCDRH after completing AD conversion in single mode.
Note 5: If an instruction to read ADCCR2 is executed, 0 is read from bits 3 through 5.
Table 20-1 ACK Settings and Conversion Times Relative to Frequencies
Frequency (fcgck)
Conversion
time
10MHz
8MHz
4MHz
2MHz
5MHz
2.5MHz
1MHz
0.5MHz
0.25
MHz
000
39/fcgck
-
-
-
19.5 µs
-
15.6 µs
39.0 µs
78.0 µs
156.0 µs
001
78/fcgck
-
-
19.5 µs
39.0 µs
15.6 µs
31.2 µs
78.0 µs
156.0 µs
-
010
156/fcgck
15.6 µs
19.5 µs
39.0 µs
78.0 µs
31.2 µs
62.4 µs
156.0 µs
-
-
011
312/fcgck
31.2 µs
39.0 µs
78.0 µs
156.0 µs
62.4 µs
124.8 µs
-
-
-
100
624/fcgck
62.4 µs
78.0 µs
156.0 µs
-
124.8 µs
-
-
-
-
101
1248/fcgck
124.8 µs
156.0 µs
-
-
-
-
-
-
-
ACK setting
11*
Reserved
Note 1: Spaces indicated by "-" in the above table mean that it is prohibited to establish conversion times in these spaces.
fcgck: High Frequency oscillation clock [Hz]
Note 2: Above conversion times do not include the time shown below.
- Time from when ADCCR1<ADRS> is set to 1 to when AD conversion is started
- Time from when AD conversion is finished to when a converted value is stored in ADCDRL and ADCDRH.
If ACK = 00*, the longest conversion time is 10/fcgck (s). If ACK = 01*, it is 32/fcgck (s). If ACK = 10*, it is 128/fcgck(s).
Note 3: The conversion time must be longer than the following time by analog reference voltage (VAREF).
RA001
- VAREF = 4.5 to 5.5 V
15.6 µs or longer
- VAREF = 2.7 to 5.5 V
31.2 µs or longer
- VAREF = 2.2 to 5.5 V
124.8 µs or longer
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TMP89FM46
AD converted value register (lower side)
ADCDRL
(0x0036)
7
6
5
4
3
2
1
0
Bit Symbol
AD07
AD06
AD05
AD04
AD03
AD02
AD01
AD00
Read/Write
R
R
R
R
R
R
R
R
After reset
0
0
0
0
0
0
0
0
5
4
3
2
1
0
AD converted value register (upper side)
ADCDRH
(0x0037)
7
6
Bit Symbol
-
-
-
-
-
-
AD09
AD08
Read/Write
R
R
R
R
R
R
R
R
After reset
0
0
0
0
0
0
0
0
Note 1: A read of ADCDRL or ADCDRH must be read after the INTADC interrupt is generated or after ADCCR2<EOCF> becomes
"1".
Note 2: In single mode, do not read ADCDRL or ADCDRH during AD conversion (ADCCR2<ADBF>="1"). (If AD conversion is finished in the interim between a read of ADCDRL and a read of ADCDRH, the INTADC interrupt request is canceled, and
the conversion result is lost.)
Note 3: If STOP, IDLE0 or SLOW mode is started, ADCDRL and ADCDRH are initialized to "0".
Note 4: If ADCCR1<AMD> is set to "00", ADCDRL and ADCDRH are initialized to "0".
Note 5: If an instruction to read ADCDRH is executed, "0" is read from bits 7 through 2.
Note 6: If AD conversion is finished in repeat mode in the interim between a read of ADCDRL and a read of ADCDRH, the previous converted value is retained without overwriting the AD converted value register. In this case, the INTADC interrupt
request is canceled, and the conversion result is lost.
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20. 10-bit AD Converter (ADC)
20.3 Functions
TMP89FM46
20.3 Functions
The 10-bit AD converter operates in either single mode in which AD conversion is performed only once or repeat
mode in which AD conversion is performed repeatedly.
20.3.1 Single mode
In single mode, the voltage at a designated analog input pin is AD converted only once.
Setting ADCCR1<ADRS> to "1" after setting ADCCR1<AMD> to "01" allows AD conversion to start.
ADCCR1<ADRS> is automatically cleared after the start of AD conversion. As AD conversion starts,
ADCCR2<ADBF> is set to "1". It is cleared to "0" if AD conversion is finished or if AD conversion is forced
to stop.
After AD conversion is finished, the conversion result is stored in the AD converted value registers
(ADCDRL and ADCDRH), ADCCR2<EOCF> is set to "1", and the AD conversion finished interrupt
(INTADC) is generated. The AD converted value registers (ADCDRL and ADCDRH) should be usually read
according to the INTADC interrupt processing routine. If the upper side (ADCDRH) of the AD converted
value register is read, ADCCR2<EOCF> is cleared to "0".
Note:Do not perform the following operations on the ADCCR1 register when AD conversion is being executed
(ADCCR2<ADBF>="1"). If the following operations are performed, there is the possibility that AD conversion
may not be executed properly.
• Changing the ADCCR1<SAIN> setting
• Setting ADCCR1<AINEN> to "0"
• Changing the ADCCR1<AMD> setting (except a forced stop by setting AMD to "00")
• Setting ADCCR1<ADRS> to "1"
AD conversion start
AD conversion start
ADCCR1<ADRS>
ADCCR2<ADBF>
Status of ADCDRL
and ADCDRH
Indeterminate
Result of the first conversion
Result of the second conversion
Clearing EOCF based on
the conversion result
ADCCR2<EOCF>
INTADC interrupt
request
Read of ADCDRH
Read of conversion result
Read of conversion result
Read of ADCDRL
Read of conversion result
Read of conversion result
Figure 20-2 Single Mode
20.3.2 Repeat mode
In repeat mode, the voltage at an analog input pin designated at ADCCR1<SAIN> is AD converted repeatedly.
Setting ADCCR1<ADRS> to "1" after setting ADCCR1<AMD> to "11" allows AD conversion to start.
After the start of AD conversion, ADCCR1<ADRS> is automatically cleared. After the first AD conversion is
finished, the conversion result is stored in the AD converted value registers (ADCDRL and ADCDRH),
ADCCR2<EOCF> is set to "1", and the AD conversion finished interrupt (INTADC) is generated. After this
interrupt is generated, the second (next) AD conversion starts immediately.
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TMP89FM46
The AD converted value registers (ADCDRL and ADDRH) should be read before the next AD conversion is
finished. If the next AD conversion is finished in the interim between a read of ADCDRL and a read of
ADCDRH, the previous converted value is retained without overwriting the AD converted value registers
(ADCDRL and ADCDRH). In this case, the INTADC interrupt request is not generated, and the conversion
result is lost. (See Figure 20-3.)
To stop AD conversion, write "00" (AD operation disable) to ADCCR1<AMD>. As "00" is written to
ADCCR1<AMD>, AD conversion stops immediately. In this case, the converted value is not stored in the AD
converted value register. As AD conversion starts, ADCCR2<ADBF> is set to "1". It is cleared to "0" if "00" is
written to AMD.
ADCCR1<AMD>
“11”
“00”
AD conversion start
ADCCR1<ADRS>
Result of the
2nd conversion
Conversion
operation
Status of ADCDRL
and ADCDRH
Indeterminate
Result of the 3rd
conversion
Result of the 1st conversion
Result of the 4th
conversion
Result of the 3rd
conversion
AD conversion is
suspended.
The conversion result
is not stored.
Result of the 4th
conversion
ADCCR2<EOCF>
A read of the
conversion result
will clear EOCF.
INTADC interrupt
Read of ADCDRH
Read of
conversion
result
Read of ADCDRL
The INTADC interrupt request is
not generated in the interim
between a read of ADCDRL
and a read of ADCDRH.
Read of
conversion
result
Read of
conversion
result
Read of
conversion
result
Read of
conversion
result
Read of
conversion
result
Figure 20-3 Repeat Mode
20.3.3 AD operation disable and forced stop of AD operation
If you want to force the AD converter to stop when AD conversion is ongoing in single mode or if you want
to stop the AD converter when AD conversion is ongoing in repeat mode, set ADCCR1<AMD> to "00".
If ADCCR1<AMD> is set to "00", registers ADCCR2<EOCF>, ADCCR2<ADBF>, ADCDRL, and
ADCDRH are initialized to "0".
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20. 10-bit AD Converter (ADC)
20.4 Register Setting
TMP89FM46
20.4 Register Setting
1. Set the AD converter control register 1 (ADCCR1) as described below:
• From the AD input channel select (SAIN), select the channel in which AD conversion is to be performed.
• Set the analog input control (AINEN) to "Analog input enable".
• At AMD, specify the AD operating mode (single or repeat mode).
2. Set the AD converter control register 2 (ADCCR2) as described below:
• At the AD conversion time (ACK), specify the AD conversion time. For information on how to specify
the conversion time, refer to the AD converter control register 2 and Table 20-1.
3. After the above two steps are completed, set "1" on the AD conversion start (ADRS) of the AD converter
control register 1 (ADCCR1), and AD conversion starts immediately if single mode is selected.
4. As AD conversion is finished, the AD conversion end flag (EOCF) of the AD converter control register 2
(ADCCR2) is set to "1", the AD conversion result is stored in the AD converted value registers (ADCDRH
and ADCDRL), and the INTADC interrupt request is generated.
5. After the conversion result is read from the AD converted value register (ADCDRH), EOCF is cleared to
"0". EOCF will also be cleared to "0" if AD conversion is performed once again before reading the AD converted value register (ADCDRH). In this case, the previous conversion result is retained until AD conversion is finished.
Example: After selecting the conversion time 15.6 µs at 10 MHz and the analog input channel AIN3 pin, perform AD conversion once. After checking EOCF, store the conversion result in the HL register. The operation mode is single
mode.
: (Port setting)
SLOOP :
; Before setting AD converter registers, make an appropriate port register setting.(For further details, refer to the section that describes I/O
ports.)
LD
(ADCCR1), 0y00110011
; Select AIN3.
LD
(ADCCR2), 0y00000011
; Select conversion time (156/fcgck) and operation mode.
SET
(ADCCR1). 7
; ADRS = 1 (AD conversion start)
TEST
(ADCCR2). 7
; EOCF = 1 ?
JRS
T, SLOOP
LD
HL, (ADCDRL)
; Read result data
20.5 Starting STOP/IDLE0/SLOW Modes
If STOP/IDLE0/SLOW mode is started, registers ADCCR1<ADRS, AMD, AINEN>, ADCCR2<EOCF, ADBF>,
ADCDRL and ADCDRH are initialized to "0". If any of these modes is started during AD conversion, AD conversion is suspended, and the AD converter stops (registers are likewise initialized). When restored from STOP/ IDLE0/
SLOW mode, AD conversion is not automatically restarted. Therefore, registers must be reconfigured as necessary.
If STOP/IDLE0/SLOW mode is started during AD conversion, analog reference voltage is automatically disconnected and, therefore, there is no possibility of current flowing into the analog reference voltage.
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20.6 Analog Input Voltage and AD Conversion Result
Analog input voltages correspond to AD-converted, 10-bit digital values, as shown in Figure 20-4.
AD-converted value
3FFH
3FEH
3FDH
03H
02H
01H
VAREF − VSS
0
1
2
3
1021 1022 1023 1024
1024
Analog input voltage
Figure 20-4 Relationships between Analog Input Voltages and AD-converted Values
(typical values)
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20. 10-bit AD Converter (ADC)
20.7 Precautions about the AD Converter
TMP89FM46
20.7 Precautions about the AD Converter
20.7.1 Analog input pin voltage range
Analog input pins (AIN0 through AIN7) should be used at voltages from VAREF to VSS. If any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain,
and converted values on other pins will also be affected.
20.7.2 Analog input pins used as input/output ports
Analog input pins (AIN0 to AIN7) are also used as input/output ports. In using one of analog input pins
(ports) to execute AD conversion, input/output instructions at all other pins (ports) must not be executed. If
they are executed, there is the possibility that the accuracy of AD conversion may deteriorate. This also applies
to pins other than analog input pins; if one pin receives inputs or generates outputs, noise may occur and its
adjacent pins may be affected by that noise.
20.7.3 Noise countermeasure
The internal equivalent circuit of the analog input pins is shown in Figure 20-5. The higher the output impedance of the analog input source, the more susceptible it becomes to noise. Therefore, make sure the output
impedance of the signal source in your design is 5 kΩ or less. It is recommended that a capacitor be attached
externally.
rnal resistance:
Analog comparator
5 kΩ (max)
AINi
Permissible signal
rnal capacitance:
source impedance:
Internal resistance:
Analog comparator
kΩ (typ)
5#!Undefined!#
kΩ (typ)
Internal capacitance:
C = 22 pF (typ.)
DA converter
DA converter
Note) i = 7 to 0
Figure 20-5 Analog Input Equivalent Circuit and Example of Input Pin Processing
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TMP89FM46
21. Flash Memory
The TMP89FM46 has flash memory of 32768 bytes. A write and erase to be performed on flash memory can be
controlled in the following three modes:
- MCU mode
In MCU mode, the flash memory is accessed by the CPU control, and the flash memory can be executed
the erasing and writing without affecting the operations of a running application. Therefore, this mode is
used for software debugging and firmware change after shipment of the TMP89FM46.
- Serial PROM mode
In serial PROM mode, the flash memory is accessed by the CPU control. Use of the serial interface
(UART and SIO) enables the flash memory to be controlled by the small number of pins. The
TMP89FM46 used in serial PROM mode supports on-board programming, which enables users to program flash memory after the microcontroller is mounted on a user board.
- Parallel PROM mode
The parallel PROM mode allows the flash memory to be accessed as a stand-alone flash memory by the
program writer provided by a third party. High-speed access to the flash memory is available by controlling address and data signals directly. To receive a support service for the program writer, please ask a
Toshiba sales representative.
In MCU and serial PROM modes, flash memory control registers (FLSCR1 and FLSCR2) are used to control the
flash memory. This chapter describes how to access the flash memory using the MCU and serial PROM modes.
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21. Flash Memory
TMP89FM46
21.1 Flash Memory Control
The flash memory is controlled by the flash memory control register 1 (FLSCR1), flash memory control register 2
(FLSCR2), and flash memory standby control register (FLSSTB).
Flash memory control register 1
FLSCR1
(0x0FD0)
7
6
5
4
3
2
1
0
Bit Symbol
FLSMD
BAREA
FAREA
-
-
Read/Write
R/W
R/W
R/W
R/W
R/W
0
0
After reset
0
1
FLSMD
Flash memory command
sequence and toggle control
BAREA
BOOTROM mapping control
0
0
010:
101:
Others:
0
0
Disable command sequence and toggle execution
Enable command sequence and toggle execution
Reserved
MCU mode
FAREA
0:
1:
Serial PROM mode
Hide BOOTROM
Show BOOTROM
Show BOOTROM
00:
Assign the data area 0x8000 through 0xFFFF
to the data area 0x8000 through 0xFFFF (standard mapping).
01:
Reserved
10:
Assign the code area 0x8000 through 0xFFFF
to the data area 0x8000 through 0xFFFF.
11:
Reserved
Flash memory area select control
Note 1:
It is prohibited to make a setting in "Reserved".
Note 2:
The flash memory control register 1 has a double-buffer structure comprised of the register FLSCR1 and a shift register.
Writing "0xD5" to the register FLSCR2 allows a register setting to be reflected and take effect in the shift register. This
means that a register setting value does not take effect until "0xD5" is written to the register FLSCR2. The value of the shift
register can be checked by reading the register FLSCRM.
Note 3:
FLSMD must be set to either "0y010" or "0y101".
Flash memory control register 2
FLSCR2
(0x0FD1)
7
6
5
4
Bit Symbol
Read/Write
After reset
CR1EN
3
2
1
0
*
*
*
*
CR1EN
W
*
FLSCR1 register
enable/disable control
*
*
0xD5
Others
*
Enable a change in the FLSCR1 setting
Reserved
Note 1: If "0xD5" is set on FLSCR2<CR1EN> with FLSCR1<FLSMD> set to "101", the flash memory goes into an active state,
and MCU consumes the same amount of current as it does during a read.
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Flash memory control register 1 monitor
FLSCRM
(0x0FD1)
7
6
Read/Write
R
R
After reset
0
0
Bit Symbol
5
4
FLSMDM
BAREAM
FAREAM
ROMSELM
R
R
R
R
0
0
2
0
0
FLSMDM
Monitoring of FLSCR1<FLSMD>
status
BAREAM
Monitoring of FLSCR1<BAREA> status
Value of currently enabled FLSCR1<BAREA>
Monitoring of FLSCR1<FAREA> status
Value of currently enabled FLSCR1<FAREA>
Monitoring of FLSCR1<ROMSEL> status
Value of currently enabled FLSCR1<ROMSEL>
FAREAM
ROMSELM
0
1
3
1
0
0
FLSCR1<FLSMD>="101" setting disabled
FLSCR1<FLSMD>="101" setting enabled
Note 1: FLSCRM is the register that checks the value of the shift register of the flash memory control register 1.
Note 2: FLSMDM turns into "1" only if FLSMD="101" becomes effective.
Note 3: If an instruction to read FLSCRM is executed, "0" is read from bits 7 and 6.
Note 4: In serial PROM mode, "1" is always read from BAREAM.
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0
21. Flash Memory
TMP89FM46
Flash memory standby control register
FLSSTB
(0x0FD2)
7
6
5
4
3
2
1
Read/Write
R
R
R
R
R
R
R
W
After reset
0
0
0
0
0
0
0
0
Bit Symbol
FSTB
0
FSTB
0
1
Flash memory standby control
Disable flash memory standby
Enable flash memory standby
Note 1: A value can be written to FSTB only by using a program that resides in RAM. A value written using a program residing in
the flash memory will be invalidated.
Note 2: If FSTB is set to "1", do not execute instructions to fetch or read data from or write data to the flash memory. If they are
executed, a flash standby reset will occur.
Note 3: If an instruction to read FLSSTB is executed, "0" is read from bits 7 through 0.
Port input control register (this register works only in serial PROM mode)
SPCR
(0x0FD3)
7
6
5
4
3
2
Bit Symbol
1
0
PIN1
PIN0
Read/Write
R
R
R
R
R
R
R/W
R/W
After reset
1
0
0
0
0
0
0
0
In serial PROM mode
PIN1
PIN0
Port input control (SCLK0 pin) in
serial PROM mode
Port input control (except RXD0,
TXD0 and SCLK0) in serial PROM
mode
0
1
Port input disabled
Port input enabled
0
1
Port input disabled
Port input enabled
In MCU mode
Input enabled for all ports
Nonfunctional whatever settings
are made
"0" is read
Note 1: A read or write can be performed on the SPCR register only in serial PROM mode. If a write is performed on this register
in MCU mode, the port input control does not function. If a read is performed on the SPCR register in MCU mode, "0" is
read from bits 7 through 0.
Note 2: All I/O ports are controlled by PIN0, except the ports RXD0, TXD0 and SCLK0 which are used in serial PROM mode. By
using PIN1, the SCLK0 pin can be configured separately from other pins.
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21.2 Functions
21.2.1 Flash memory command sequence execution and toggle control (FLSCR1
<FLSMD>)
To prevent inadvertent writes to the flash memory due to program error or microcontroller malfunction, the
execution of the flash memory command sequence and the toggle operation can be disabled (the flash memory
can be write protected) by making an appropriate control register setting (write protect). To enable the execution of the command sequence and the toggle operation, set FLSCR1<FLSMD> to "0y101", and then set
"0xD5" on FLSCR2<CR1EN>. To disable the execution of the command sequence, set FLSCR1<FLSMD> to
"0y010", and then set "0xD5" on FLSCR2<CR1EN>. If the command sequence or the toggle operation is executed with the execution of the command sequence and the toggle operation set to "disable", the executed command sequence or toggle operation takes no effect.
After a reset, FLSCR1<FLSMD> is initialized to "0y010" to disable the execution of the command
sequence. FLSCR1<FLSMD> should normally be set to "0y010" except when a write or erase is to be performed on the flash memory.
Note 1: If "0xD5" is set on FLSCR2<CR1EN> with FLSCR1<FLSMD> set to "101", the flash memory goes into an
active state, and MCU consumes the same amount of current as it does during a read.
Note 2: If FLSCR1<FLSMD> is set to "disable", subsequent commands (write instructions) generated are rejected
but a command sequence being executed is not initialized.
If you want to set FLSCR1<FLSMD> to "disable", you must finish all command sequences and verify that
the flash memory is ready to be read.
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21. Flash Memory
TMP89FM46
21.2.2 Flash memory area switching (FLSCR1<FAREA>)
To perform an erase or write on the flash memory, a memory transfer instruction (command sequence) must
be executed. If a memory transfer instruction is used to read or write data, a read or write can be performed
only on the data area. To perform an erase or write on the code area, therefore, part of the code area must be
temporarily switched to the data area. This switching between data and code areas is performed by making the
appropriate FLSCR1<FAREA> setting.
By setting "0xD5" on FLSCR2<CR1EN> after setting FLSCR1<FAREA> to "10", 0x8000 through 0xFFFF
(AREA C1) in the code area is mapped to 0x8000 through 0xFFFF (AREA D1) in the data area.
To restore the flash memory to the initial state of mapping, set FLSCR1<FAREA> to "00", and then set
"0xD5" on FLSCR2<CR1EN>.
All flash memory areas can be accessed by performing the appropriate steps described above and then executing the memory transfer instruction on 0x8000 through 0xFFFF (AREA D1) in the data area.
0x8000 through 0xFFFF (AREA D1) in the data area and 0x8000 through 0xFFFF (AREA C1) in the code
area are mirror areas; these two areas refer to the same physical address in memory. Therefore, an erase or write
must be performed on one of these two mirror areas. For example, If a write is performed on 0x8000 in the data
area with FLSCR1<FAREA> set to "10" after performing a write on 0x8000 in the data area with
FLSCR1<FAREA> set to "00", data is overwritten. To write data to the flash memory that already has data written to it, existing data must first be erased from the flash memory by performing a sector erase or chip erase, and
then data must be written.
Additionally, access to areas to which memory is not assigned should be avoided by executing an instruction
or specifying such an area by using jump or call instructions.
0x0000
SFR
RAM
0x0000
0x0FFF
0x7FFF
0x8000
0x7FFF
0x8000
32768
bytes
Flash
32768
bytes
AREA D1
Flash
0xFFFF
AREA C1
0xFFFF
Data area
Code area
If FLSCR<FAREA> = “00”
0x0000
0x0000
SFR
RAM
0x0FFF
0x7FFF
0x8000
0x7FFF
0x8000
32768
bytes
Flash
AREA C1
32768
bytes
Flash
0xFFFF
AREA C1
0xFFFF
Data area
Code area
If FLSCR<FAREA> = “10”
Figure 21-1 Area Switching Using the FLSCR1<FAREA> Setting
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TMP89FM46
21.2.3 RAM area switching (SYSCR3<RAREA>)
If "0xD4" is set on SYSCR4 after SYSCR3<RAREA> is set to "1" in MCU mode, RAM is mapped to the
code area. To restore the RAM area to the initial state of mapping, set SYSCR3<RAREA> to "0", and then set
"0xD4" on SYSCR4.
In serial PROM mode, RAM is mapped to the code area, irrespective of the SYSCR3<RAREA> setting.
21.2.4 BOOTROM area switching (FLSCR1<BAREA>)
If "0xD5" is set on FLSCR2<CR1EN> after FLSCR1<BAREA> is set to "1" in MCU mode, 0x1000 through
0x17FF in the code and data areas is masked by flash memory, and 2K-byte (first half of 4KB) BOOTROM is
mapped. If you do not want to map BOOTROM, set "0xD5" on FLSCR2<CR1EN> after setting
FLSCR1<BAREA> to "0".
A set of codes for programming flash memory in serial PROM mode are built into BOOTROM, and a support program (API) for performing an erase or write on flash memory in a simple manner is also built into one
part in the BOOTROM area. Therefore, by calling a subroutine in the support program after BOOTROM is
mapped, it is possible to erase, write and read flash memory easily.
In serial PROM mode, BOOTROM is mapped to 0x1000 through 0x17FF in the data area and 0x1000
through 0x1FFF in the code area, irrespective of the FLSCR1<BAREA> setting. BAREA is always "1", and
the set BAREA value remains unchanged, even if data is written. "1" is always read from BAREA.
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21. Flash Memory
TMP89FM46
0x0000
0x003F
0x0040
0x0000
0x0000
SFR
0x003F
0x0040
RAM
0xXXXX
0xXXXX
0x1000
0x1000
0xFFFF
0xFFFF
RAM
0x0000
0x0000
0xFFFF
Data area
Code area
If SYSSR4<RAREAS>=“1”
FLSCR1<BAREA>=“0”
0x0000
SFR
0x003F
0x0040
RAM
0xXXXX
0x0000
SFR
0x003F
0x0040
RAM
0xXXXX
0x1000
0x1000
BOOTROM
0x17FF
0x1800
0xFFFF
0x1000
BOOTROM
0x17FF
0x1800
0xFFFF
BOOTROM
0x17FF
0x1800
0xFFFF
Code area
Data area
RAM
0xXXXX
0x1000
BOOTROM
0x17FF
0x1800
RAM
0xXXXX
0xXXXX+1
If SYSSR4<RAREAS>=“0”
FLSCR1<BAREA>=“0”
0x003F
0x0040
0x003F
0x0040
0xFFFF
Code area
Data area
0x0000
SFR
0xFFFF
Data area
If SYSSR4<RAREAS>=“0”
FLSCR1<BAREA>=“1”
Code area
If SYSSR4<RAREAS>=“1”
FLSCR1<BAREA>=“1”
0x0000
0x0000
0x003F
0x0040
SFR
RAM
0x003F
0x0040
RAM
0xXXXX
0xXXXX
0x1000
0x1000
BOOTROM
BOOTROM
0x17FF
0x1800
0x17FF
0x1800
0xFFFF
0xFFFF
Data area
Note : XXXXH is end of RAM address.
Code area
In serial PROM mode
Figure 21-2 Show/Hide Switching for BOOTROM and RAM
21.2.5 Flash memory standby control (FLSSTB<FSTB>)
FLSSTB<FSTB> is the register provided to maintain the compatibility with the previous product version. It
must normally be set to "0". In using FLSSTB<FSTB> built into the TMP89FM46, the following point should
be noted: FLSSTB<FSTB> can be configured only by using a program allocated to RAM. If it is configured by
using a program allocated to the flash memory, the configured value will be invalidated and does not take effect.
To access the flash memory again after setting FLSSTB<FSTB> to "1", set FLSSTB<FSTB> to "0" by using
a program allocated to RAM. If the flash memory is accessed with FLSSTB<FSTB> set to "1," a flash standby
reset will occur.
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TMP89FM46
If an interrupt occurs when the interrupt vector is assigned to the flash memory area (SYSCR3<RVCTR> =
"0" is effective), FSTB is automatically initialized to "0", and then the interrupt vector of the flash memory
area is read. If an interrupt occurs when the interrupt vector is assigned to the RAM area (SYSCR3<RVCTR>
= "1" is effective), FSTB is not cleared to "0", and then the interrupt vector of the RAM area is read. In this
case, the RAM area should be designated as a referential address of interrupt vector. If the flash memory area is
designated as a referential address of interrupt vector, a flash standby reset occurs after an interrupt is generated.
21.2.6 Port input control register (SPCR<PIN0, PIN1>)
In serial PROM mode, the input levels of all ports, except the ports RXD0 and TXD0 used in serial PROM
mode, are physically fixed after a reset is released. This is designed to prevent a penetration current from flowing through unused ports (port inputs and functional peripheral inputs, which are also used as ports, are disabled). To access the flash memory using the RAM loader mode and a method other than the UART, therefore,
port inputs must be set to "enable". To enable the SCLK0 port input, set SPCR<PIN0> to "1". To enable port
inputs other than RXD0, TXD0 and SCLK0 port inputs, set SPCR<PIN1> to "1".
In MCU mode, the SPCR register does not function.
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21. Flash Memory
TMP89FM46
21.3 Command Sequence
In MCU and serial PROM modes, the command sequence consists of six commands (JEDEC compatible), as
shown in Table 21-1.
Table 21-1 Command Sequence
Command sequence
1st Bus Write
Cycle
2nd Bus Write
Cycle
3rd Bus Write
Cycle
4th Bus Write
Cycle
5th Bus Write
Cycle
6th Bus Write
Cycle
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
1
Byte Program
0x#555
0xAA
0x#AAA
0x55
0x#555
0xA0
BA
(Note 1)
Data
(Note 1)
-
-
-
-
2
Sector Erase
(partial erase in units of
4KB)
0x#555
0xAA
0x#AAA
0x55
0x#555
0x80
0x#555
0xAA
0x#AAA
0x55
SA
(Note 2)
0x30
3
Chip Erase
(all erase)
0x#555
0xAA
0x#AAA
0x55
0x#555
0x80
0x#555
0xAA
0x#AAA
0x55
0x#555
0x10
4
Product ID Entry
0x#555
0xAA
0x#AAA
0x55
0x#555
0x90
-
-
-
-
-
-
5
Product ID Exit
0xXX
0xF0
-
-
-
-
-
-
-
-
-
-
6
Security Program
0x#555
0xAA
0x#AAA
0x55
0x#555
0xA5
0xFF7F
0x00
-
-
-
-
Note 1: Specify the address and data to be written (Refer to Table 21-2 about BA).
Note 2: The area to be erased is specified with the upper 4 bits of the address (Refer to Table 21-3 about SA).
Note 3: Do not start the STOP, IDLE0, IDLE1, IDLE2, SLEEP1 or SLEEP0 mode while a command sequence is being executed or
a task specified in a command sequence is being executed (write, erase or ID entry).
Note 4: # ; 0x8 through 0xF should be specified as the upper 4bits of the address. Usually, it is recommended that 0xF is specified.
Note 5: XXX ; Don’t care
21.3.1 Byte program
This command writes the flash memory in units of one byte. The address and data to be written are specified
in the 4th bus write cycle. The range of addresses that can be specified is shown in Table 21-2. For example, to
write data to 0x8000 in the data area, set FLSCR1<FAREA> to "0y00", set "0xD5" on FLSCR2<CR1EN>, and
then specify 0x8000 as an address in the 4th bus write cycle. The time needed to write each byte is 40 µs maximum. The next command sequence cannot be executed if an ongoing write operation is not completed. To
check the completion of the write operation, perform read operations twice on the same address in the flash
memory, and perform polling until the same data is read from the flash memory. During the write operation, bit
6 is reversed each time a read is performed.
Note 1: To rewrite data to addresses in the flash memory where data (including 0xFF) is already written, make sure
that you erase the existing data by performing a sector erase or chip erase before writing data.
Note 2: The data and code areas become mirror areas. As you access these areas, you are brought to the same
physical address in memory. When performing a Byte Program, make sure that you write data to either of
these two areas, not both.
Note 3: Do not perform a Byte Program on areas other than those shown in Table 21-2.
Table 21-2 Range of Addresses Specifiable (BA)
Write Area
RA003
FLSCR1
<FAREA>
Address specified by instruction
(Address of 4th bus write cycle)
AREA D1
(Data area)
0x8000 through 0xFFFF
00
0x8000 through 0xFFFF
AREA C1
(Code area)
0x8000 through 0xFFFF
10
0x8000 through 0xFFFF
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TMP89FM46
21.3.2 Sector erase (4-kbyte partial erase)
This command erases the flash memory in units of 4 kbytes. The flash memory area to be erased is specified
by the upper 4 bits of the 6th bus write cycle address. The range of addresses that can be specified is shown in
Table 21-3. For example, to erase 4 kbytes from 0x8000 through 0x8FFF in the code area, set FLSCR1<FAREA> to "0y10", set "0xD5" on FLSCR2<CR1EN>, and then specify either 0x8000 or 0x8FFF as the 6th bus
write cycle. The sector erase command is effective only in MCU and serial PROM modes, and it cannot be used
in parallel PROM mode.
The time needed to erase 4 kbytes is 30 ms maximum. The next command sequence cannot be executed if an
ongoing erase operation is not completed. To check the completion of the erase operation, perform read operations twice on the same address in the flash memory, and perform polling until the same data is read from the
flash memory. During the erase operation, bit 6 is reversed each time a read is performed.
Data in the erased area is 0xFF.
Note 1: The data and code areas become mirror areas. As you access these areas, you are brought to the same
physical address in memory. When performing a sector erase, make sure that you erase data from either of
these two areas, not both.
Note 2: Do not perform a sector erase on areas other than those shown in Table 21-3.
Table 21-3 Range of Addresses Specifiable
FLSCR1
<FAREA>
Erase Area
AREA D1
(Data area)
AREA C1
(Code area)
Address specified by instruction
(Address of 6th bus write cycle)
0x8000 through 0x8FFF
0x8000 through 0x8FFF
0x9000 through 0x9FFF
0x9000 through 0x9FFF
0xA000 through 0xAFFF
0xA000 through 0xAFFF
0xB000 through 0xBFFF
0xB000 through 0xBFFF
00
0xC000 through 0xCFFF
0xC000 through 0xCFFF
0xD000 through 0xDFFF
0xD000 through 0xDFFF
0xE000 through 0xEFFF
0xE000 through 0xEFFF
0xF000 through 0xFFFF
0xF000 through 0xFFFF
0x8000 through 0x8FFF
0x8000 through 0x8FFF
0x9000 through 0x9FFF
0x9000 through 0x9FFF
0xA000 through 0xAFFF
0xA000 through 0xAFFF
0xB000 through 0xBFFF
0xB000 through 0xBFFF
10
0xC000 through 0xCFFF
0xC000 through 0xCFFF
0xD000 through 0xDFFF
0xD000 through 0xDFFF
0xE000 through 0xEFFF
0xE000 through 0xEFFF
0xF000 through 0xFFFF
0xF000 through 0xFFFF
21.3.3 Chip erase (all erase)
This command erases the entire flash memory.
The time needed to erase it is 30 ms maximum. The next command sequence cannot be executed if an ongoing erase operation is not completed. To check the completion of the erase operation, perform read operations
twice on the same address in the flash memory, and perform polling until the same data is read from the flash
memory. During the erase operation, bit 6 is reversed each time a read is performed.
Data in the erased area is 0xFF.
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21. Flash Memory
21.4 Toggle Bit (D6)
TMP89FM46
21.3.4 Product ID entry
This command activates the product ID mode. If an instruction to read the flash memory is executed in Product ID mode, the vendor ID, flash ID and security status can be read from the flash memory.
Table 21-4 Values to Be Read in Product ID Mode
Address
Meaning
Read value
0xF000
Vendor ID
0x98
0xF001
Flash ID
0x4D
0xFF7F
Security status
0xFF:
Security program disabled
Other than 0xFF: Security program enabled
21.3.5 Product ID exit
This command is used to exit the Product ID mode.
21.3.6 Security program
If the security program is enabled, the flash memory is write and read protected in parallel PROM mode, and
the flash memory overwrite command and the RAM loader command cannot be executed in serial PROM
mode.
To disable the security program, the chip erase must be performed. To check whether the security program is
enabled or disabled, read 0xFF7F in product ID mode. Refer to Table 21-4 for further details. The time needed
to enable or disable the security program is 40 µs maximum. The next command sequence cannot be executed
until the security program setting is completed. To check the completion of the security program setting, perform read operations twice on the same address in the flash memory, and perform polling until the same data is
read. When the security program setting is being made, bit 6 is reversed each time a read is performed.
21.4 Toggle Bit (D6)
After the flash memory write, the chip erase, and the security program command sequence are executed, the value
of the 6th bit (D6) in data read by a read operation is reversed each time a read is performed. This bit reversal can be
used as a software mechanism for checking the completion of each operation. Normally, perform read operations
twice on the same address in the flash memory, and perform polling until the same data is read from the flash memory.
After the flash memory write, the chip erase, and the security program command sequence are executed, the toggle
bit read by the first read operation is always "1".
Note 1: If FLSCR1<FLSMD> is set to "disable", the toggle bit is not reversed.
Note 2: Do not read the toggle bit by using a 16-bit transfer instruction. If the toggle bit is read using a 16-bit transfer
instruction, the toggle bit does not function properly.
Note 3: Because the instruction cycle is longer than the write time in SLOW mode, the value is not reversed, even if the
toggle bit is read right after the Byte Program is performed.
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21.5 Access to the Flash Memory Area
A read or a program fetch cannot be performed on the whole of the flash memory area if data is being written to
the flash memory, if data in flash memory is being erased or if a security setting is being made in the flash memory.
When performing these operation on the flash memory area, the flash memory cannot be directly accessed by using
a program in the flash memory; the flash memory must be accessed using a program in the BOOTROM area or the
RAM area.
Data can be written to and read from the flash memory area in units of one byte. Data in the flash memory can be
erased in units of 4 kbytes, and all data in the flash memory can be erased at one stroke. A read can be performed
using one memory transfer instruction. A write or erase, however, must be performed using more than one memory
transfer instruction because the command sequence method is used. For information on the command sequence,
refer to Table 21-1.
Note 1: To allow a program to resume control on the flash memory area that is rewritten, it is recommended that you let
the program jump (return) after verifying that the program has been written properly.
Note 2: Do not reset the MCU (including a reset generated due to internal factors) when data is being written to the flash
memory, data is being erased from the flash memory or the security command is being executed. If a reset
occurs, there is the possibility that data in the flash memory may be rewritten to an unexpected value.
21.5.1 Flash memory control in serial PROM mode
The serial PROM mode is used to access the flash memory by using a control program provided in the
BOOTROM area. Since almost all operations relating to access to the flash memory can be controlled simply
using data supplied through the serial interface (UART or SIO), it is not necessary to operate the control register for the user. For details of the serial PROM mode, see "Serial PROM Mode".
To access the flash memory in serial PROM mode by using a user-specific program or peripheral functions
other than UART and SIO, it is necessary to execute a control program in the RAM area by using the RAM
loader command of the serial PROM mode. How to execute this control program is described in "21.5.1.1 How
to transfer and write a control program to the RAM area in RAM loader mode of the serial PROM mode".
21.5.1.1 How to transfer and write a control program to the RAM area in RAM loader mode of
the serial PROM mode
How to execute a control program in the RAM area in serial PROM mode is described below. A control
program to be executed in the RAM area must be generated in the Intel-Hex format and be transferred
using the RAM loader of the serial PROM mode.
Steps 1 and 2 shown below are controlled by a program in the BOOTROM, and other steps are controlled by a program transferred to the RAM area. The following procedure is linked with a program
example to be explained later.
1. Transfer the write control program to the RAM area in RAM loader mode.
2. Jump to the RAM area.
3. Set a nonmaskable interrupt vector in the RAM area.
4. Set FLSCR1<FLSMD> to "0y101", and specify the area to be erased by making the appropriate
FLSCR1<FAREA> setting. (Make the appropriate FLSCR1<ROMSEL> setting as required.)
Then set "0xD5" on FLSCR2<CR1EN>.
5. Execute the erase command sequence.
6. Read the same flash memory address twice consecutively.
(Repeat step 6 until the read values become the same.)
7. Specify the area (area erased in step 5 above) to which data is written by making the appropriate
FLSCR1<FAREA> setting. (Make the appropriate FLSCR1<ROMSEL> setting as required.)
Then set "0xD5" on FLSCR2<CR1EN>.
8. Execute the write command sequence.
9. Read the same flash memory address twice consecutively.
(Repeat step 9 until the read values become the same.)
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21. Flash Memory
21.4 Toggle Bit (D6)
TMP89FM46
10. Set FLSCR1<FLSMD> to "0y010", and then set "0xD5" on FLSCR2<CR1EN> (to disable the
execution of the command sequence).
Note 1: If the RAM loader is used in serial PROM mode, the BOOTROM disables (DI) a maskable interrupt,
and the interrupt vector area is designated as a RAM area (SYSCR3<RVCTR>="1"). Considering that
a nonmaskable interrupt may be generated unexpectedly, it is recommended that vector addresses
corresponding these interrupts (INTUNDEF, INTSWI: 0x01F8 to 0x01F9, WDT: 0x01FC to 0x01FD)
be established and that an interrupt service routine be defined inside the RAM area.
Note 2: If a certain interrupt is used in the RAM loader program, a vector address corresponding to that interrupt and the interrupt service routine must be established inside the RAM area. In this case, it is recommended that a nonmaskable interrupt be handled as explained in Note 1.
Note 3: Do not set SYSCR3<RVCTR> to "0" by using the RAM loader program. If an interrupt occurs with
SYSCR3<RVCTR> set to "0", the BOOTROM area is referenced as a vector address and, therefore,
the program will not function properly.
Example: A case in which a program is transferred to RAM, the sector erase is performed on 0xE000 through 0xEFFF
in the code area, and then data of 0x3F is written to 0xE500.
main section code abs = 0x0100
; #### Set a nonmaskable interrupt vector inside the RAM area #### (step 3)
LD
HL,0x01FC
LDW
(HL),sINTSWI
LD
HL,0x01F8
LDW
(HL),sINTWDT
; Set INTUNDEF and INTSWI interrupt vectors
; Set INTWDT interrupt vector
; #### Sector erase and write process ####
LD
HL,0xF555
; Variable for command sequence
LD
DE,0xFAAA
; Variable for command sequence
; Sector erase process (step 5)
LD
C,0x00
; Set upper address
LD
IX,0xE000
; Set middle and lower addresses
CALL
sSectorErase
; Perform a sector erase (0xE000)
; Write process (step 8)
LD
C,0x00
; Set upper address
LD
IX,0xE500
; Set middle and lower addresses
LD
B,0x3F
; Data to be written
CALL
sByteProgram
; Write process (0xE500)
; #### Execute the next main program ####
:
:
J
XXXXX
; Execute the main program
; #### Program to be executed in RAM ####
sSectorErase:
CALL
sAddConv
; Address conversion process
LD
(HL),E
; 1st Bus Write Cycle (note 1)
LD
(DE),L
; 2nd Bus Write Cycle (note 1)
LD
(HL),0x80
; 3rd Bus Write Cycle (note 1)
LD
(HL),E
; 4th Bus Write Cycle (note 1)
LD
(DE),L
; 5th Bus Write Cycle (note 1)
LD
(IX),0x30
; 6th Bus Write Cycle (note 1)
J
sRAMopEnd
; Sector erase process
; Write process
sByteProgram:
CALL
sAddConv
; Convert address
LD
(HL),E
; 1st Bus Write Cycle (note 1)
LD
(DE),L
; 2nd Bus Write Cycle (note 1)
LD
(HL),0xA0
; 3rd Bus Write Cycle (note 1)
LD
(IX),B
; 4th Bus Write Cycle (note 1)
; End process
sRAMopEnd
NOP
; (note 2)
NOP
; (note 2)
NOP
sLOOP1:
; (note 2)
LD
A,(IX)
CMP
A,(IX)
; (step 6,9)
J
NZ,sLOOP1
; Loop until the read values become the same
LD
(FLSCR1),0x40
; Disable the execution of command sequence (step 10)
LD
(FLSCR2),0xD5
RET
; Reflect the FLSCR1 setting
; Return to flash memory
; Convert address (steps 4 and 7)
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TMP89FM46
sAddConv:
sAddConvEnd:
LD
WA,IX
SWAP
C
AND
C,0x10
SWAP
W
AND
W,0x08
OR
C,W
XOR
C,0x08
SHRC
C
OR
C,0xA0
LD
(FLSCR1),C
; Enable the execution of command sequence. Make the
FAREA setting.
LD
(FLSCR2),0xD5
; Reflect the FLSCR1 setting
LD
WA,IX
TEST
C.3
J
Z,sAddConvEnd
OR
W,0x80
LD
IX,WA
RET
; Interrupt subroutine
sINTWDT:
:
:
; Error processing
:
; Error processing
RETN
sINTSWI:
:
RETN
Note 1: In using a write instruction in the xxx bus write cycle, make sure that you use a write instruction of
more than three machine cycles or arrange write instructions in such a way that they are generated at
intervals of three or more machine cycles. If a 16-bit transfer instruction is used or if write instructions
are executed at intervals of two machine cycles, the flash memory command sequence will not be
transmitted properly, and a malfunction may occur.
Note 2: If a read of the flash memory (toggle operation) is to be performed after a write instruction is generated in the xth bus write cycle, instructions must be arranged in such a way that they are generated at
intervals of three or more machine cycles; machine cycles are counted from when the last xth bus
write cycle is generated to when each instruction is generated. Three NOP instructions are normally
used. If the interval between instructions is short, the toggle bit does not operation correctly.
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21. Flash Memory
21.4 Toggle Bit (D6)
TMP89FM46
21.5.2 Flash memory control in MCU mode
In MCU mode, a write can be performed on the flash memory by executing a control program in RAM or
using a support program (API) provided inside BOOTROM.
21.5.2.1 How to write to the flash memory by transferring a control program to the RAM area
This section describes how to execute a control program in RAM in MCU mode. A control program to
be executed in RAM must be acquired and stored in the flash memory or it must be imported from an outside source through a communication pin. (The following procedure assumes that a program copy is provided inside the flash memory.)
Steps 1 through 5 and 11 shown below concern the control by a program in the flash memory, and other
steps concern the control by a program transferred to RAM. The following procedure is linked with a program example to be described later.
1. Set the interrupt master enable flag to "disable (DI)" (IMF ← "0").
2. Transfer the write control program to RAM.
3. Establish the nonmaskable interrupt vector in the RAM area.
4. After setting both SYSCR3<RAREA> and SYSCR3<RVCTR> to "1", set "0xD4" on FLSCR4.
Then allocate RAM to the code area, and switch the vector area to the RAM area.
5. Invoke the erase processing program in the RAM area by generating a CALL instruction.
6. Set FLSCR1<FLSMD> to "0y101", and specify the area to be erased by making the appropriate
FLSCR1<FAREA> setting. (Make the appropriate FLSCR1<ROMSEL> setting, as necessary.)
Then set "0xD5" on FLSCR2<CR1EN>.
7. Execute the erase command sequence.
8. Perform a read on the same address in the flash memory twice consecutively. (Repeat this step
until the read values become the same.)
9. After setting FLSCR1<FLSMD> to "0y010" and FLSCR1<FAREA> to "0y00", set "0xD5" on
FLSCR2<CR1EN>. (This disables the execution of the command sequence and returns FAREA
to the initial state of mapping.)
10. Generate the RET instruction to return to the flash memory.
11. Invoke the write program in the RAM area by generating a CALL instruction.
12. Set FLSCR1<FLSMD> to "0y101", and make the appropriate FLSCR1<FAREA> setting to
specify the area (area erased by performing step 7 above) on which a write is to be performed.
(Make the appropriate FLSCR1<ROMSEL> setting, as necessary.) Then set "0xD5" on
FLSCR2<CR1EN>.
13. Execute the write command sequence.
14. Perform a read on the same address in the flash memory twice consecutively.
(Repeat this step until the read values become the same.)
15. After setting FLSCR1<FLSMD> to "0y010" and FLSCR1<FAREA> to "0y00", set "0xD5" on
FLSCR2<CR1EN>. (This disables the execution of the command sequence and returns FAREA
to the initial state of mapping.)
16. Generate the RET instruction to return to the flash memory.
Note 1: Before writing data to the flash memory from the RAM area in MCU mode, the vector area must be
switched to the RAM area by using SYSCR3<RVCTR>, data must be written to the vector addresses
(INTUNDEF, INTSWI: 0x01F8 to 0x01F9, INTWDT: 0x01FC to 0x01FD) that correspond to nonmaskable interrupts, and the interrupt subroutine (RAM area) must be defined. This allows you to trap
the errors that may occur due to an unexpected nonmaskable interrupt during a write. If
SYSCR3<RVCTR> is set in the flash memory area and if an unexpected interrupt occurs during a
write, a malfunction may occur because the vector area in the flash memory cannot be read properly.
Note 2: Before using a certain interrupt in MCU mode, the vector address corresponding to that interrupt and
the interrupt service routine must be established inside the RAM area. In this case, the nonmaskable
interrupt setting must be made, as explained in Note 1.
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TMP89FM46
Note 3: Before jumping from the flash memory to the RAM area, RAM must be allocated to the code area by
making the appropriate SYSCR3<RAREA> setting (setting made in step 4 in the procedure described
on the previous page).
Example: Case in which a program is transferred to RAM, a sector erase is performed on 0xE000 through 0xEFFF in
the code area, and then 0x3F data is written to 0xE500.
cRAMStartAdd
equ 0x0200
; RAM start address
main section code abs = 0x1000
DI
; Disable interrupts (step 1)
; #### Transfer the program to RAM #### (step 2)
sRAMLOOP:
LD
HL,cRAMStartAdd
LD
IX,sRAMprogStart
LD
A,(IX)
; Transfer the program from sRAMprogStart to
LD
(HL),A
; sRAMprogEnd to cRAMStartAdd.
INC
HL
INC
IX
CMP
IX,sRAMprogEnd
J
NZ,sRAMLOOP
; #### Set a nonmaskable interrupt vector inside the RAM area #### (step 3)
LD
HL,0x01FC
LDW
(HL),sINTSWI - sRAMprogStart + cRAMStartAdd
; Set INTUNDEF and INTSWI interrupt vectors
LD
HL,0x01F8
LDW
(HL),sINTWDT - sRAMprogStart + cRAMStartAdd
; Set INTWDT interrupt vector
; #### Allocate RAM to the code area. Switch the vector area to RAM #### (step 4)
LD
(SYSCR3),0x06
; Set RAREA and RVCTR to "1"
LD
(SYSCR4),0xD4
; Enable Code
; #### Sector erase and write process ####
LD
HL,0xF555
; Variable for command sequence
LD
DE,0xFAAA
; Variable for command sequence
; Sector erase process (step 5)
LD
C,0x00
; Set upper addresses
LD
IX,0xE000
; Set middle and lower addresses
CALL
sRAMStartAdd
; Perform a sector erase (0xE000)
; Write process (step 11)
LD
C,0x00
; Set upper addresses
LD
IX,0xE500
; Set middle and lower addresses
LD
B,0x3F
; Data to be written
CALL
sByteProgram - sRAMprogStart + cRAMStartAdd
; Write process (0xE500)
; #### Execute the next main program ####
:
:
J
XXXXX
; Execute the main program
; #### Program to be executed in RAM ####
sRAMprogStart:
sSectorErase:
CALL
sAddConv - sRAMprogStart + cRAMStartAdd
; Address conversion process
; Sector erase process (step 7)
LD
(HL),E
LD
(DE),L
; 1st Bus Write Cycle (note 1)
; 2nd Bus Write Cycle (note 1)
LD
(HL),0x80
; 3rd Bus Write Cycle (note 1)
LD
(HL),E
; 4th Bus Write Cycle (note 1)
LD
(DE),L
; 5th Bus Write Cycle (note 1)
LD
(IX),0x30
; 6th Bus Write Cycle (note 1)
J
sRAMopEnd
; Write process (step 13)
sByteProgram
CALL
sAddConv - sRAMprogStart + cRAMStartAdd
LD
(HL),E
LD
(DE),L
; 2nd Bus Write Cycle (note 1)
LD
(HL),0xA0
; 3rd Bus Write Cycle (Note 1)
LD
(IX),B
; 4th Bus Write Cycle (note 1)
; Address conversion process
; 1st Bus Write Cycle (note 1)
; End process
sRAMopEnd:
RA003
NOP
; (note 2)
NOP
; (note 2)
NOP
; (note 2)
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21. Flash Memory
21.4 Toggle Bit (D6)
TMP89FM46
sLOOP1:
LD
A,(IX)
CMP
A,(IX)
J
NZ,sLOOP1
; Loop until the read values become the same
LD
(FLSCR1),0x40
; Disable the execution of command sequence (steps 9 and
15)
LD
(FLSCR2),0xD5
RET
; (steps 8,14)
; Reflect the FLSCR1 setting
; Return to flash memory
; Address conversion process (steps 6 and 12)
sAddConv:
sAddConvEnd:
LD
WA,IX
SWAP
C
AND
C,0x10
SWAP
W
AND
W,0x08
OR
C,W
XOR
C,0x08
SHRC
C
OR
C,0xA0
LD
(FLSCR1),C
; Enable the execution of command sequence. Make the
FAREA setting.
LD
(FLSCR2),0xD5
; Reflect the FLSCR1 setting
LD
WA,IX
TEST
C.3
J
Z,sAddConvEnd
OR
W,0x80
LD
IX,WA
RET
; Interrupt subroutine
sINTWDT:
:
:
; Error processing
:
; Error processing
RETN
sINTSWI:
:
RETN
sRAMprogEnd:
NOP
Note 1: In using a write instruction in the xxx bus write cycle, make sure that you use a write instruction of
more than three machine cycles or arrange write instructions in such a way that they are generated at
intervals of three or more machine cycles. If a 16-bit transfer instruction is used or if write instructions
are executed at intervals of two machine cycles, the flash memory command sequence will not be
transmitted properly, and a malfunction may occur.
Note 2: If a read of the flash memory (toggle operation) is to be performed after a write instruction is generated in the xth bus write cycle, instructions must be arranged in such a way that they are generated at
intervals of three or more machine cycles; machine cycles are counted from when the last xth bus
write cycle is generated to when each instruction is generated. Three NOP instructions are normally
used. If the interval between instructions is short, the toggle bit does not operation correctly.
Example: Case in which data is read from 0xF000 in the code area and stored at 0x98 in RAM
RA003
LD
(FLSCR1),0xA8
LD
(FLSCR2),0xD5
; Select AREA C1
; Reflect the FLSCR1 setting
LD
A,(0xF000)
; Read data from 0xF000
LD
(0x98),A
; Store data at 0x98
LD
(FLSCR1),0x40
; Select AREA D0
LD
(FLSCR2),0xD5
; Reflect the FLSCR1 setting
Page 306
TMP89FM46
21.5.2.2 How to write to the flash memory by using a support program (API) of BOOTROM
This section describes how to perform an erase and a write on the flash memory by using a support program (API) of BOOTROM in MCU mode.
Example: Case in which a sector erase is performed on 0xE000 through 0xEFFF in the data area, and then data at
0x0100 through 0x01FF is written to 0xE000 through 0xE0FF in the data area.
.BTWrite
equ 0x1010
; Write data to the flash memory
.BTEraseSec
equ 0x1012
; Sector Erase
.BTEraseChip equ 0x1014
; Chip Erase
.BTGetRP
equ 0x1016
; Check the status of the security program
.BTSetRP
equ 0x1018
; Configure the security program
main section code abs = 0xF000
; Initial setting
LD
(FLSCR1),0x50
; Set BAREA to "1" (note)
LD
(FLSCR2),0xD5
; Reflect the FLSCR1 setting
LD
A,0x0E
; Specify the area to be erased (0xE000 through 0xEFFF)
LD
C,0xD5
; Enable Code
CALL
(.BTEraseSec)
; Execute sector erase
; Sector erase process (API)
; Write process
LD
HL,0xE000
; Flash start address (address where data is written)
LD
IY,0x0100
; RAM start address
LD
C,0x00
; Address where data is written (bit 16)
LD
WA,HL
; Address where data is written (bits 15 to 0)
LD
E,(IY)
; Data to be written
LD
(SP-),0xD5
; Enable Code
CALL
(.BTWrite)
; Write data to the flash memory (1 byte)
INC
IY
; Increment flash address
INC
HL
; Increment RAM address
CMP
L,0x00
; Finish 256-byte write?
J
NZ,sLOOP1
; Return to sLOOP1 if the number of bytes is less than 256
LD
(FLSCR1),0x40
; Set BAREA to "0"
LD
(FLSCR2),0xD5
sLOOP1:
; End process
Example: Whether the security program is enabled or disabled is checked. If it is disabled, it is enabled.
.BTWrite
equ 0x1010
; Write data to the flash memory
.BTEraseSec
equ 0x1012
; Sector Erase
.BTEraseChip equ 0x1014
; Chip Erase
.BTGetRP
equ 0x1016
; Check the status of the security program
.BTSetRP
equ 0x1018
; Enable the security program
main section code abs = 0xF000
; Initial setting
LD
(FLSCR1),0x50
; Set BAREA to "1"
LD
(FLSCR2),0xD5
; Reflect the FLSCR1 setting
; Check the status of the security program
LD
A,0xD5
LD
C,0x00
; Enable Code
; Set 0x00 (note 1)
CALL
(.BTGetRP)
; Check the status of the security program
CMP
A,0xFF
J
NZ,sSKIP
; Go to sSKIP if the security program is enabled
; Security program enable process (API)
sSKIP
RA003
LD
A,0xD5
LD
C,0x00
; Enable Code
; Set 0x00 (note 1)
CALL
(.BTSetRP)
; Enable the security program
LD
(FLSCR1),0x40
; Set BAREA to "0"
Page 307
21. Flash Memory
21.4 Toggle Bit (D6)
TMP89FM46
LD
(FLSCR2),0xD5
:
:
Note 1: Make sure that you set the C register to "0x00".
RA003
Page 308
TMP89FM46
22. Serial PROM Mode
22.1 Outline
The TMP89FM46 has a 4K-byte BOOTROM (Mask ROM) for programming to flash memory. BOOTROM is
available in serial PROM mode. The serial PROM mode is controlled by RXD0/SI0 pins, TXD0/SO0 pins, MODE
pin, and RESET pin. In serial PROM mode, communication is performed via the UART or SIO.
Table 22-1 Operating Range in Serial PROM Mode
Parameter
Power supply voltage
High frequency
Min
Max
Unit
4.5
5.5
V
1
10
MHz
22.2 Security
In serial PROM mode, two security functions are provided to prevent illegal memory access attempts by a third
party: password and security program functions. For more security-related information, refer to "22.12 Security".
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22. Serial PROM Mode
22.3 Serial PROM Mode Setting
TMP89FM46
22.3 Serial PROM Mode Setting
22.3.1 Serial PROM mode control pins
To execute on-board programming, activate the serial PROM mode. Table 22-2 shows the pin setting used to
activate the serial PROM mode.
Table 22-2 Serial PROM Mode Setting
Pin
Setting
RXD0 / SI0 / P21 pin
H level
TXD0 / SO0 / P20 pin
H level
MODE, RESET pin
Note: Before you activate the serial PROM mode, you must set the RXD0/SI0/P21 and TXD0/SO0/P20 pins to high (H) level by
using a pull-up resistor.
Table 22-3 Pin Functions in Serial PROM Mode
Pin name
(in serial PROM mode)
Input/output
TXD0 / SO0
Output
RXD0 / SI0
Function
Pin name (in MCU mode)
Serial PROM mode control/serial data output
TXD0 / SO0 / P20
Input
Serial PROM mode control/serial data input
RXD0 / SI0 / P21
RESET
Input
Serial PROM mode control
RESET
MODE
Input
Serial PROM mode control
SCLK0
Input
Serial clock input (if SIO is used)
These ports are in the high-impedance state in the
serial PROM mode. If the UART is used, the port input
is physically fixed to a specified input level in order to
prevent a penetration current. To enable the port input,
the SPCR<PIN1> must be set to "1" by operating the
RAM loader control program.
VDD
Power
supply
4.5 V to 5.5 V
AVDD
Power
supply
Connect to VDD.
VSS
Power
supply
0V
AVSS
Power
supply
Connect to VSS.
VAREF
Power
supply
Leave open or apply reference voltage.
Input/output port other than
RXD0 and TXD0
XIN
Input/output
MODE
(See note 1)
SCLK0
These ports are in the high-impedance state in the serial PROM mode. The port input is physically
fixed to a specified input level in order to prevent a penetration current (the port input is disabled). To
enable the port input, the SPCR<PIN0> must be set to "1" by operating the RAM loader control program.
Input
Connect a resonator to make these pins self-oscillate.
XOUT
Output
Note 1: If other parts are mounted on a user board, they may interfere with data being communicated through these communication pins during on-board programming. It is recommended that these parts be somehow isolated to prevent the pins from
being affected.
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Page 310
TMP89FM46
TMP89FM46
VDD (4.5 V to 5.5 V)
VDD
XIN
Pull-up resistors
SCLK0
RXD0 (P21)
XOUT
VSS
TXD0 (P20)
External control
RESET
MODE
GND
Figure 22-1 Serial PROM Mode Pin Setting
Note 1: In the case of access using the UART, the control of the SCLK0 pin is unnecessary.
Note 2: For information on other pin settings, refer to "Table 22-3 Pin Functions in Serial PROM Mode".
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22. Serial PROM Mode
22.4 Example Connection for On-board Writing
TMP89FM46
22.4 Example Connection for On-board Writing
Figure 22-2 shows example connections to perform on-board writing.
VDD (4.5 V to 5.5 V)
VDD
Pull-up resistors
RXD0 (P21)
Level
converter
TXD0 (P20)
PC control
(Note 2)
Other
parts
TMP89FM46
RESET
control
(Note 1)
RC power-on
reset circuit
RESET
MODE
Serial PROM mode
MCU mode
XIN
XOUT
VSS
GND
Target board
External control board
If UART is used
VDD (4.5 V to 5.5 V)
VDD
Pull-up resistors
SI0 (P21)
Microcomputer,
etc.
SO0 (P20)
SCLK0 (P22)
(Note 2)
Other
parts
TMP89FM46
RESET
control
(Note 1)
RC power-on
reset circuit
RESET
MODE
Serial PROM mode
MCU mode
XIN
XOUT
VSS
GND
Target board
External control board
If SIO is used
Figure 22-2 Example Connections for On-board Writing
Note 1: If other parts on a target board interfere with the UART communication in serial PROM mode, disconnect these
pins by using a jumper or switch.
Note 2: If the reset control circuit on a target board interferes with the startup of serial PROM mode, disconnect the circuit
by using a jumper, etc.
Note 3: For information on other pin settings, refer to "Table 22-3 Pin Functions in Serial PROM Mode".
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TMP89FM46
22.5 Activating the Serial PROM Mode
Activate the serial PROM mode by performing the following procedure. For information on the detailed timing,
refer to "22.14.1 Reset timing".
1. Supply power to the VDD pin.
2. Set the RESET and MODE pins to low.
3. Set the RXD0/SI0/P21 and TXD0/SO0/P20 pins to high.
4. Wait until the power supply and clock oscillation stabilize.
5. Set the RESET and MODE pins from low to high.
6. Input the matching data 0x86 or 0x30 to the RXD0/SI0/P21 pins after the setup period has elapsed.
RA002
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22. Serial PROM Mode
22.6 Interface Specifications
TMP89FM46
22.6 Interface Specifications
The serial PROM mode supports two communication methods: UART and SIO. The communication method is
selected based on the first serial data value received after a reset.
To execute an on-board program, the communication format of the external controller (personal computer, microcontroller, etc.) must be set as described below.
22.6.1 SIO communication
- Transfer rate: 250 kbps (Max.)
- Data length: 8 bits
- Slave (external clock)
- Hardware flow control (SO0 pin)
If the TMP89FM46 receives serial data "0x30" after a reset, it starts the SIO communication.
In the SIO communication, the TMP89FM46 functions as a slave device. Therefore, the external controller
must supply the TMP89FM46 with a serial clock (SCLK0 pin) for synchronization.
If the TMP89FM46 is not outputting serial data, it controls the hardware flow by using the SO0 pin. If internal data processing is not completed yet, though data has been received, the SO0 pin outputs the L level. If
internal data processing has progressed to a near-completion state or if it has been completed, the SO0 pin outputs the H level. The external controller must check the status of the SO0 pin before it starts to supply a serial
clock.
For information on the communication timings of each operation command, refer to " 1.11 AC Characteristics (SIO) ".
22.6.2 UART communication
- Baud rate: 9600 to 128000 bps (automatic detection)
- Data length: 8 bits (LSB first)
- Parity bit: None
- STOP bit: 1 bit
If the TMP89FM46 receives serial data "0x86" after a reset, it starts the UART communication. It also measures the pulse width of the received data (0x86), and automatically establishes the reference baud rate. In all
subsequent data communication transactions, this reference baud rate is used. For information on the communication timings of each operation command, refer to "22.14 AC Characteristics (UART)".
Usable baud rates differ depending on the operating frequency and are shown in Table 22-4. However, there
is the possibility of data communication not working properly, even if a baud rate shown in Table 22-4 is used,
because data communication is affected by frequency errors of a resonator of the external controller (personal
computer, etc.), the load capacity of a communication pin, and various other factors.
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Page 314
TMP89FM46
Table 22-4 Usable Baud Rates as a General Guideline
9600 bps
19200 bps
38400 bps
57600bps
115200 bps
128000 bps
10 MHz
Ο
Ο
Ο
Ο
Ο
Ο
8 MHz
Ο
Ο
Ο
Ο
Ο
Ο
7.3728 MHz
Ο
Ο
Ο
Ο
Ο
-
6.144 MHz
Ο
Ο
Ο
-
-
Ο
6 MHz
Ο
Ο
Ο
Ο
Ο
Ο
5 MHz
Ο
Ο
Ο
-
-
-
4.9152 MHz
Ο
Ο
Ο
Ο
-
-
4.19 MHz
Ο
Ο
Ο
-
-
Ο
4 MHz
Ο
Ο
Ο
Ο
Ο
Ο
2 MHz
Ο
Ο
Ο
Ο
-
-
1 MHz
Ο
Ο
-
Ο
-
-
Note 1: "Ο" means a usable baud rate. "-" means an unusable baud rate.
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Page 315
22. Serial PROM Mode
22.7 Memory Mapping
TMP89FM46
22.7 Memory Mapping
Figure 22-3 shows memory maps in serial PROM and MCU modes.
In serial PROM mode, the BOOTROM (mask ROM) is mapped to the 0x1000 through 0x17FF in the data area
and 0x1000 through 0x1FFF in the code area respectively.
To write data to or erase data from flash memory by using the RAM loader command (hereafter called the 0x60
command) and an original program, data write or erase operations must be performed while switching between areas
by using the flash memory control registers (FLSCR1 and 2). For information on how to specify addresses, refer to
Flash Memory.
When the command to write data to flash memory (hereafter called the 0x30 command) or the command to erase
data from flash memory (hereafter called the 0xF0 command) is executed, BOOTROM automatically converts
addresses. Therefore, as the address of flash memory, specify an address equivalent to that specified in MCU mode
(if FLSCR1<BAREA>="0"), namely, 0x8000 through 0xFFFF.
0x0000
0x003F
0x0040
SFR
0x0000
0x0000
0x003F
0x0040
RAM
0x1000
0x17FF
0x8000
0x8000
FLASH
BOOTROM
(2048 bytes
0x1000
0x17FF
BOOTROM
(2048 bytes
0x8000
FLASH
FLASH
0xFFFF
0xFFFF
0xFFFF
Data area
RAM
0x8000
FLASH
0xFFFF
0x0000
SFR
Code area
Data area
If FLSCR1<BAREA>=”0”
(MCU mode)
Code area
If FLSCR1<BAREA>=”1”
(MCU mode)
0x0000
0x003F
0x0040
0x1000
0x17FF
0x0000
SFR
RAM
BOOTROM
(2048 bytes
0x1000
BOOTROM
(4096 bytes
0x1FFF
0x8000
0x8000
FLASH
0xFFFF
FLASH
0xFFFF
Data area
Code area
If serial PROM mode
Figure 22-3 Memory Mapping
22.8 Operation Commands
In serial PROM mode, the commands shown in Table 22-5 are used. After a reset is released, the TMP89FM46
goes into a standby state and awaits the arrival of matching data 1 (0x86 or 0x30).
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Page 316
TMP89FM46
Table 22-5 Operation Command in Serial PROM Mode
Command data
Operation command
Description
0x86 or 0x30
Setup
(matching data 1, 2)
After a reset is released, the serial PROM mode always starts operation with this
command.
If matching data 1 is 0x86, communication starts in the UART format. If matching
data 1 is 0x30, communication starts in the SIO format.
0xF0
Flash memory erase
Data in the flash memory area (address 0x8000 through 0xFFFF) can be erased.
0x30
Flash memory write
Data can be written to the flash memory area (address 0x8000 through 0xFFFF).
0x40
Flash memory read
Data can be read from the flash memory area (address 0x8000 through 0xFFFF).
0x60
RAM loader
Data can be written to a specified RAM area (address 0x0060 through 0x083F).
0x90
Flash memory SUM output
0xFF check data and 2-byte checksums of the entire flash memory area (address
0x8000 through 0xFFFF) are output in descending order (from upper to lower
bytes).
0xC0
Product ID code output
Product ID codes are output.
0xC3
Flash memory status output
The security program status and other status codes are output.
0xD0
Mask ROM emulation setting
Flash products of 124K or 96Kbytes can be provisioned to emulate a smallcapacity mask ROM product.
0xFA
Flash memory security setting
The security program setting is enabled.
Each command is outlined below. For detailed information on how each command works, refer to 22.8.1 and subsequent sections.
1. Flash memory erase command
Either Chip Erase (total erase of flash memory) or Sector Erase (erase of flash memory in 4K-byte
units) can be used to erase the data in flash memory. Data in the erased area is 0xFF. If the security program is enabled or if the option code EPFC_OP is 0xFF, the flash erase command of Sector Erase cannot
be executed.
To disable the security program setting, execute the flash erase command of Chip Erase. Before erasing
the data in flash memory, the TMP89FM46 performs password authentication except where a product is a
blank product or EPFC_OP is 0xFF. If a password is not authenticated, the flash memory erase command
is not executed.
2. Flash memory write command
Data can be written in single-byte units to a specified address in flash memory. Provision the external
controller so that it transmits data to write as binary data in the Intel Hex format. If errors do not occur
until the end record is reached, the TMP89FM46 calculates checksums in the entire flash memory area
(0x8000 through 0xFFFF), and returns the calculation results. If the security program is enabled, the flash
memory write command cannot be executed. In this case, execute Chip Erase beforehand by using the
flash memory erase command. Before executing the flash memory write command, the TMP89FM46 performs password authentication except where a product is a blank product. If a password is not authenticated, the flash memory write command is not executed.
3. Flash memory read command
Data can be read from a specified address in flash memory in single-byte units. Provision the external
controller so that it transmits the address in memory where a read starts, as well as the number of bytes.
After outputting the number of data equal to the number of bytes, the TMP89FM46 calculates the checksums of the output data, and returns the calculation results. If the security program is enabled, the flash
memory read command cannot be executed. In this case, execute Chip Erase beforehand by using the
flash memory erase command. Before executing the flash memory read command, the TMP89FM46 performs password authentication except where a product is blank. If a password is not authenticated, the
flash memory read command is not executed.
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Page 317
22. Serial PROM Mode
22.8 Operation Commands
TMP89FM46
4. RAM loader command
The RAM loader transfers the Intel Hex format data sent by the external controller to the built-in RAM.
If it completes the data transfer normally, it calculates the checksums, transmits the calculation results,
jumps to the RAM address specified by the first data record, and starts to execute the user program. If the
security program is enabled, the RAM loader command is not executed. In this case, execute Chip Erase
beforehand by using the flash memory erase command. Before executing the RAM loader command, the
TMP89FM46 performs password authentication except where a product is blank. If a password is not
authenticated, the RAM loader command is not executed.
5. Flash memory SUM output command
Checksums in the entire flash memory area (0x8000 through 0xFFFF) are calculated, and the calculation results are returned.
6. Product ID code output code
This is a code output used to identify a product. The output code consists of information on the ROM
area and on the RAM area respectively. The external controller reads this code to identify the product to
which data is to be written.
7. Flash memory status output code
The status of 0xFFE0 through 0xFFFF and that of the security program are output. The external controller reads this code to identify the status of flash memory.
8. Mask ROM emulation setting command
This command is nonfunctional in the TMP89FM46. It becomes functional if used for a product with
flash memory of more than 96Kbytes.
9. Flash memory security setting command
This command is used to prohibit the reading or writing of data in flash memory in parallel mode. In
serial PROM mode, the flash memory write command and RAM loader command are prohibited. To disable the flash memory security program, execute Chip Erase by using the flash memory erase command.
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TMP89FM46
22.8.1 Flash memory erase command (0xF0)
Table 22-6 shows the flash memory erase commands.
Table 22-6 Flash Memory Erase Commands
Transfer data from the external controller to
TMP89FM46
Transfer byte
BOOT
ROM
Transfer data from TMP89FM46 to the
external controller
Baud rate
1st byte
2nd byte
Matching data 1 (0x86 or 0x30)
-
Automatic adjustment
Baud rate after adjustment
- (Automatic baud rate adjustment)
OK: Echo back data (0x86 or 0x30)
Error: No data transmitted
3rd byte
4th byte
Matching data 2 (0x79 or 0xCF)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0x79 or 0xCF)
Error: No data transmitted
5th byte
6th byte
Operation command data (0xF0)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0xF0)
Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1)
7th byte
8th byte
Password count storage address bit 23 to 16
9th byte
10th byte
Password count storage address bit 15 to 08
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
11th byte
12th byte
Password count storage address bit 07 to 00
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
13th byte
14th byte
Password comparison start address bit 23 to 16
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
15th byte
16th byte
Password comparison start address bit 15 to 08
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
17th byte
18th byte
Password comparison start address bit 07 to 00
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
19th byte
:
m-th byte
Password string
Baud rate after adjustment
-
-
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
n-th - 2 byte
Erase area specification
Baud rate after adjustment
-
n-th - 1 byte
-
Baud rate after adjustment
OK: Checksum (upper byte) (note 3)
Error: No data transmitted
n-th byte
-
Baud rate after adjustment
OK: Checksum (lower byte) (note 3)
Error: No data transmitted
n-th + 1 byte
(Wait for the next operation command data)
Baud rate after adjustment
-
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
Note 1: "0x** × 3" means that the device goes into an idle state after transmitting 3 bytes of 0x**.
Note 2: For information on the erase area specification, refer to "22.8.1.1 Specifying the erase area". For information on checksums, refer to "22.10 Checksum (SUM)". For information on passwords, refer to "22.12.1 Passwords".
Note 3: Do not transmit a password string if 0xFFFA of a flash memory is 0xFF, or blank product. (However, the password count
storage address and the password comparison start address must be transmitted.)
Note 4: If a value less than 0x20 is transmitted at the n-th - 2 byte (execution of Sector Erase) and if 0xFFFA of flash memory is
0xFF, the TMP89FM46 goes into an idle state.
Note 5: When a password error occurs, the TMP89FM46 stops communication and goes into an idle state. Therefore, when a
password error occurs, initialize the TMP89FM46 by using the RESET pin, and restart the serial PROM mode.
Note 6: If a communication error occurs during the transfer of a password address or a password string, the TMP89FM46 stops
communication and goes into an idle state. Therefore, when a password error occurs, initialize the TMP89FM46 by using
the RESET pin, and restart the serial PROM mode.
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Page 319
22. Serial PROM Mode
22.8 Operation Commands
TMP89FM46
22.8.1.1 Specifying the erase area
The flash memory erase command is used to specify an area in flash memory to be erased at n-th-2 byte;
specifically, ERASEC is used to specify the address of an area to be erased.
If data of less than 0x20 is specified, Sector Erase (erasing flash memory in 4K-byte units) is executed..
Executing Sector Erase with 0xFFFA memory set to "0xFF" or with the security program enabled will
cause the device to go into an infinite loop state.
If data of more than 0x20 is specified, Chip Erase (total erasure of flash memory) is executed, and the
security program in flash memory is disabled. Therefore, to disable the security program in flash memory,
execute Chip Erase, not Sector Erase.
Erase area specification data (data at n-th-2 bytes)
7
6
5
4
3
2
1
0
ERASEC
ERASEC
RA002
Erase area start address
0x00
Reserved
0x01
Reserved
0x02
Reserved
0x03
Reserved
0x04
Reserved
0x05
Reserved
0x06
Reserved
0x07
Reserved
0x08
0x8000 - 0x8FFF
0x09
0x9000 - 0x9FFF
0x0A
0xA000 - 0xAFFF
0x0B
0xB000 - 0xBFFF
0x0C
0xC000 - 0xCFFF
0x0D
0xD000 - 0xDFFF
0x0E
0xE000 - 0xEFFF
0x0F
0xF000 - 0xFFFF
0x10
Reserved
0x11
Reserved
0x12
Reserved
0x13
Reserved
0x14
Reserved
0x15
Reserved
0x16
Reserved
0x17
Reserved
0x18
Reserved
0x19
Reserved
0x1A
Reserved
0x1B
Reserved
0x1C
Reserved
0x1D
Reserved
0x1E
Reserved
0x1F
Reserved
0x20 or more
Chip Erase (erasure of the entire area)
Page 320
TMP89FM46
Note 1: If Sector Erase is performed on an area where flash memory does not exist, the TMP89FM46 stops
communication, and goes into an idle state.
Note 2: If Reserved data is transmitted, the TMP89FM46 stops communication, and goes into an idle state.
RA002
Page 321
22. Serial PROM Mode
22.8 Operation Commands
TMP89FM46
22.8.2 Flash memory write command (operation command: 0x30)
Table 22-7 shows the transfer formats of flash memory write commands.
Table 22-7 Transfer Formats of Flash Memory Write Commands
Transfer data from the external controller to
TMP89FM46
Transfer byte
BOOT
ROM
Transfer data from TMP89FM46 to the
external controller
Baud rate
1st byte
2nd byte
Matching data 1 (0x86 or 0x30)
-
Automatic adjustment
Baud rate after adjustment
- (Automatic baud rate adjustment)
OK: Echo back data (0x86 or 0x30)
Error: No data transmitted
3rd byte
4th byte
Matching data 2 (0x79 or 0xCF)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0x79 or 0xCF)
Error: No data transmitted
5th byte
6th byte
Operation command data (0x30)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0x30)
Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1)
7th byte
8th byte
Password count storage address 23 to 16
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
9th byte
10th byte
Password count storage address 15 to 08
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
11th byte
12th byte
Password count storage address 07 to 00
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
13th byte
14th byte
Password comparison start address 23 to 16
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
15th byte
16th byte
Password comparison start address 15 to 08
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
17th byte
18th byte
Password comparison start address 07 to 00
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
19th byte
:
m-th byte
Password string (note)
Baud rate after adjustment
-
-
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
m-th+1 byte
:
n-th-3 byte
Intel Hex format (binary)
Baud rate after adjustment
-
n-th-2 byte
-
Baud rate after adjustment
OK: 0x55
Overwrite detect: 0xAA
n-th-1 byte
-
Baud rate after adjustment
OK: Checksum (high) (note 3)
Error: No data transmitted
n-th byte
-
Baud rate after adjustment
OK: Checksum (low) (note 3)
Error: No data transmitted
n-th+1 byte
(Wait for the next operation command data)
Baud rate after adjustment
-
-
Note 1: "0x** × 3" means that the device goes into an idle state after transmitting 3 bytes of 0x**. For further information, refer to
Table 22-18.
Note 2: For information on the Intel Hex format, refer to "22.11 Intel Hex Format (Binary)". For information on checksums, refer to
"22.10 Checksum (SUM)". For information on passwords, refer to "22.12.1 Passwords".
Note 3: If the area 0xFFE0 through 0xFFFF is all 0xFF, password authentication is not performed and, therefore, the password
string need not be transmitted. The password count storage address and password comparison start address, however,
must be specified, even for a blank product. If the password count storage address and/or password comparison start
address is/are incorrect, a password error occurs, the TMP89FM46 stops communication, and it goes into an idle state.
RA002
Page 322
TMP89FM46
Therefore, if a password error occurs, initialize the TMP89FM46 by using the RESET pin, and restart the serial PROM
mode.
Note 4: If the security program is enabled in flash memory or if a password error occurs, the TMP89FM46 stops communication,
and goes into an idle state. Therefore, if a password error occurs, initialize the TMP89FM46 by using the RESET pin, and
restart the serial PROM mode.
Note 5: If a communication error occurs during the transfer of a password address or a password string, the TMP89FM46 stops
communication and goes into an idle state. Therefore, when a password error occurs, initialize the TMP89FM46 by using
the RESET pin, and restart the serial PROM mode.
Note 6: If all data in flash memory are the same data, make sure that you never write data to the address 0xFFE0 through
0xFFFF. If data is written to this address, a password error occurs, and the subsequent operations cannot be performed.
Note 7: The n-th-2 byte is a flag for detecting an overwrite. If memory contents at an address where data is to be written are other
than 0xFF, the n-th-2 byte is 0xAA (data is not written to this address, and the data write routine is skipped). The checksum at the n-th-1 byte or n-th byte is calculated based on data in which data in memory areas where data was not written
are included. Therefore, if an overwrite is detected, the checksum of transmitted data does not match that at the n-th-1
byte or n-th byte.
RA002
Page 323
22. Serial PROM Mode
22.8 Operation Commands
TMP89FM46
22.8.3 Flash memory read command (operation command: 0x40)
Table 22-8 shows the transfer formats of the flash memory read command.
Table 22-8 Transfer Formats of the Flash Memory Read Command
Transfer data from the external controller to
TMP89FM46
Transfer byte
BOOT
ROM
RA002
Transfer data from TMP89FM46 to the
external controller
Baud rate
1st byte
2nd byte
Matching data 1 (0x86 or 0x30)
-
Automatic adjustment
Baud rate after adjustment
- (Automatic baud rate adjustment)
OK: Echo back data (0x86 or 0x30)
Error: No data transmitted
3rd byte
4th byte
Matching data 2 (0x79 or 0xCF)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0x79 or 0xCF)
Error: No data transmitted
5th byte
6th byte
Operation command data (0x40)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0x40)
Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1)
7th byte
8th byte
Password count storage address 23 to 16
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
9th byte
10th byte
Password count storage address 15 to 08
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
11th byte
12th byte
Password count storage address 07 to 00
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
13th byte
14th byte
Password comparison start address 23 to 16
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
15th byte
16th byte
Password comparison start address 15 to 08
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
17th byte
18th byte
Password comparison start address 07 to 00
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
19th byte
:
m-th byte
Password string
Baud rate after adjustment
-
-
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
m-th + 1 byte
m-th + 2 byte
Read start address 23 to 16
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
m-th + 3 byte
m-th + 4 byte
Read start address 15 to 08
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
m-th + 5 byte
m-th + 6 byte
Read start address 07 to 00
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
m-th + 7 byte
m-th + 8 byte
Number of bytes to read 23 to 16
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
m-th + 9 byte
m-th + 10 byte
Number of bytes to read 15 to 08
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
m-th + 11 byte
m-th + 12 byte
Number of bytes to read 07 to 00
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
Page 324
TMP89FM46
Table 22-9 Transfer Formats of the Flash Memory Read Command
Transfer data from the external controller to
TMP89FM46
Transfer byte
m-th + 13 byte
:
n-th - 2 byte
BOOT
ROM
Transfer data from TMP89FM46 to the
external controller
Baud rate
Baud rate after adjustment
Memory data
Baud rate after adjustment
Memory data
n-th - 1 byte
-
Baud rate after adjustment
OK: Checksum (high)
Error: No data transmitted
n-th byte
-
Baud rate after adjustment
OK: Checksum (low)
Error: No data transmitted
n-th + 1 byte
(Wait for the next operation command data)
Baud rate after adjustment
-
Note 1: "0x** × 3" means that the device goes into an idle state after transmitting 3 bytes of 0x**. For further information, refer to
Table 22-18.
Note 2: For information on checksums, refer to "22.10 Checksum (SUM)". For information on passwords, refer to "22.12.1 Passwords".
Note 3: If the area 0xFFE0 through 0xFFFF is all 0xFF, password authentication is not performed and, therefore, the password
string need not be transmitted. The password count storage address and password comparison start address, however,
must be specified, even for a blank product. If the password count storage address and/or password comparison start
address are/is incorrect, a password error occurs; the TMP89FM46 stops communication and goes into an idle state.
Therefore, if a password error occurs, initialize the TMP89FM46 by using the RESET pin, and restart the serial PROM
mode.
Note 4: If the security program is enabled in flash memory or if a password error occurs, the TMP89FM46 stops communication,
and goes into an idle state. Therefore, if a password error occurs, initialize the TMP89FM46 by using the RESET pin, and
restart the serial PROM mode.
Note 5: If a communication error occurs during the transfer of a password address or a password string, the TMP89FM46 stops
communication and goes into an idle state. Therefore, when a password error occurs, initialize the TMP89FM46 by using
the RESET pin, and restart the serial PROM mode.
Note 6: If the number of bytes received at the m-th + 7 byte, m-th + 9 byte or m-th + 11 byte is more than 0x000000 or the size of
internal memory, the TMP89FM46 stops communication and goes into an idle state.
RA002
Page 325
22. Serial PROM Mode
22.8 Operation Commands
TMP89FM46
22.8.4 RAM loader command (operation command: 0x60)
Table 22-10 shows the transfer formats of the RAM loader command.
Table 22-10 Transfer Formats of the RAM Loader Command
Transfer data from the external controller to
TMP89FM46
Transfer byte
BOOT
ROM
RAM
Transfer data from TMP89FM46 to the
external controller
Baud rate
1st byte
2nd byte
Matching data 1 (0x86 or 0x30)
-
Automatic adjustment
Baud rate after adjustment
- (Automatic baud rate adjustment)
OK: Echo back data (0x86 or 0x30)
Error: No data transmitted
3rd byte
4th byte
Matching data 2 (0x79 or 0xCF)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0x79 or 0xCF)
Error: No data transmitted
5th byte
6th byte
Operation command data (0x60)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0x60)
Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1)
7th byte
8th byte
Password count storage address 23 to 16
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
9th byte
10th byte
Password count storage address 15 to 08
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
11th byte
12th byte
Password count storage address 07 to 00
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
13th byte
14th byte
Password comparison start address 23 to 16
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
15th byte
16th byte
Password comparison start address 15 to 08
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
17th byte
18th byte
Password comparison start address 07 to 00
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
19th byte
:
m-th byte
Password string
Baud rate after adjustment
-
-
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
m-th + XX byte
:
n-th - 2 byte
Intel Hex format (binary)
Baud rate after adjustment
-
Baud rate after adjustment
-
n-th - 1 byte
-
Baud rate after adjustment
OK: Checksum (high) (note 3)
Error: No data transmitted
n-th byte
-
Baud rate after adjustment
OK: Checksum (low) (note 3)
Error: No data transmitted
-
The program jumps to the start address of RAM in which the first transferred data is written, and executes itself.
Note 1: "0x** × 3" means that the device goes into an idle state after transmitting 3 bytes of 0x**. For further information, refer to
Table 22-18.
Note 2: For information on the Intel Hex format, refer to "22.11 Intel Hex Format (Binary)". For information on checksums, refer to
"22.10 Checksum (SUM)". For information on passwords, refer to "22.12.1 Passwords".
Note 3: If the area 0xFFE0 through 0xFFFF is all 0xFF, password authentication is not performed and, therefore, the password
string need not be transmitted. The password count storage address and password comparison start address, however,
must be specified, even for a blank product. If the password count storage address and/or password comparison start
address are/is incorrect, a password error occurs; the TMP89FM46 stops communication and goes into an idle state.
Therefore, if a password error occurs, initialize the TMP89FM46 by using the RESET pin, and restart the serial PROM
mode.
RA002
Page 326
TMP89FM46
Note 4: After sending a password string, do not send the end record only. If the TMP89FM46 receives the end record after receiving a password string, it may malfunction.
Note 5: If the security program is enabled in flash memory or if a password error occurs, the TMP89FM46 stops communication,
and goes into an idle state. Therefore, if a password error occurs, initialize the TMP89FM46 by using the RESET pin, and
restart the serial PROM mode.
Note 6: If a communication error occurs during the transfer of a password address or a password string, the TMP89FM46 stops
communication and goes into an idle state. Therefore, when a password error occurs, initialize the TMP89FM46 by using
the RESET pin, and restart the serial PROM mode.
RA002
Page 327
22. Serial PROM Mode
22.8 Operation Commands
TMP89FM46
22.8.5 Flash memory SUM output command (operation command: 0x90)
Table 22-11 shows the transfer formats of the flash memory SUM output command.
Table 22-11 Transfer Formats of the Flash Memory SUM Output Command
Transfer data from the external controller to
TMP89FM46
Transfer byte
BOOT
ROM
Transfer data from TMP89FM46 to the
external controller
Baud rate
1st byte
2nd byte
Matching data 1 (0x86 or 0x30)
-
Automatic adjustment
Baud rate after adjustment
- (Automatic baud rate adjustment)
OK: Echo back data (0x86 or 0x30)
Error: No data transmitted
3rd byte
4th byte
Matching data 2 (0x79 or 0xCF)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0x79 or 0xCF)
Error: No data transmitted
5th byte
6th byte
Operation command data (0x90)
-
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted (0x90)
Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1)
7th byte
-
Baud rate after adjustment
0x55 : 0xAA: All data are 0xFF.
8th byte
-
Baud rate after adjustment
OK: Checksum (high) (note 2)
Error: No data transmitted
9th byte
-
Baud rate after adjustment
OK: Checksum (low) (note 2)
Error: No data transmitted
10th byte
(Wait for the next operation command data)
Baud rate after adjustment
-
Note 1: "0x** × 3" means that the device goes into an idle state after transmitting 3 bytes of 0x**. For further information, refer to
Table 22-18.
Note 2: For information on checksums, refer to "22.10 Checksum (SUM)".
Note 3: If data to be included in the checksum are all 0xFF, the 7th byte becomes 0xAA. If any one piece of data to be included in
the checksum is other than 0xFF, the 7th byte becomes 0x55.
RA002
Page 328
TMP89FM46
22.8.6 Product ID code output command (operation command: 0xC0)
Table 22-12 shows the transfer formats of the product ID code output command.
Table 22-12 Transfer Formats of the Product ID Code Output Command
Transfer byte
Transfer data from the external controller to
TMP89FM46
Baud rate
1st byte
2nd byte
Matching data 1 (0x86 or 0x30)
-
Automatic adjustment
Baud rate after adjustment
-(Automatic baud rate adjustment)
OK: Echo back data (0x86 or 0x30)
Error: No data transmitted
3rd byte
4th byte
Matching data 2 (0x79 or 0xCF)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0x79 or 0xCF)
Error: No data transmitted
5th byte
6th byte
Operation command data (0xC0)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0xC0)
Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1)
7th byte
Baud rate after adjustment
0x3A
Start mark
8th byte
Baud rate after adjustment
0x13
Number of transfer data (from 9th to
27th bytes)
9th byte
Baud rate after adjustment
0x03
Length of address (3 bytes)
10th byte
Baud rate after adjustment
0xFD
Reserved
11th byte
Baud rate after adjustment
0x00
Reserved
12th byte
Baud rate after adjustment
0x00
Reserved
13th byte
Baud rate after adjustment
0x00
Reserved
0x80
ROM size code
14th byte (note 2)
BOOT
ROM
Transfer data from TMP89FM46 to the external
controller
15th byte
Baud rate after adjustment
0x01
ROM block count
(1 block)
16th byte (note 3)
Baud rate after adjustment
0x00
First address of ROM (upper byte)
17th byte (note 3)
Baud rate after adjustment
0x80
First address of ROM (middle byte)
0x00
First address of ROM (lower byte)
Baud rate after adjustment
18th byte (note 3)
19th byte (note 3)
Baud rate after adjustment
0x00
End address of ROM (upper byte)
20th byte (note 3)
Baud rate after adjustment
0xFF
End address of ROM (middle byte)
21st byte (note 3)
Baud rate after adjustment
0xFF
End address of ROM (lower byte)
22nd byte (note 4)
Baud rate after adjustment
0x00
First address of RAM (upper byte)
23rd byte (note 4)
Baud rate after adjustment
0x00
First address of RAM (middle byte)
24th byte (note 4)
Baud rate after adjustment
0x60
First address of RAM (lower byte)
25th byte (note 4)
Baud rate after adjustment
0x00
End address of RAM (upper byte)
26th byte (note 4)
Baud rate after adjustment
0x08
End address of RAM (middle byte)
27th byte (note 4)
Baud rate after adjustment
0x3F
End address of RAM (lower byte)
28th byte
Baud rate after adjustment
0xYY
YYH : Checksum of transfer data
(complement of 2 of the sum total from
9th through 27th bytes)
29th byte
(Wait for the next operation command data)
Baud rate after adjustment
-
Note 1: "0x** × 3" means that the device goes into an idle state after transmitting 3 bytes of 0x**. For further information, refer to
Table 22-18.
Note 2: The ROM size code at the 14th byte is shown in Table 22-13.
Note 3: 16th through 21st bytes show the range of addresses in flash memory where data can be written.
RA002
Page 329
22. Serial PROM Mode
22.8 Operation Commands
TMP89FM46
Note 4: 22nd through 27th bytes show the flash memory area and RAM area that can be used by the RAM loader. Because the
range of addresses shown here does not include the work area used by BOOTROM, it is smaller than the size of a RAM
built into an actual product.
Table 22-13 ROM Size Code (14th Byte)
7
6
5
4
ROMSIZE
ROMSIZE
RA002
Data on the flash memory size
3
2
1
0
"0"
"0"
"0"
00010 : 4Kbytes
00100 : 8Kbytes
01000 : 16Kbytes
10000 : 32Kbytes
11000 : 48Kbytes
11110 : 60Kbytes
10001 : 96Kbytes
11111 : 124Kbytes
Page 330
TMP89FM46 specified value
(1000 0000)
Read
only
TMP89FM46
22.8.7 Flash memory status output command (0xC3)
Table 22-14 shows the flash memory status output commands.
Table 22-14 Flash Memory Status Output Commands
Transfer byte
BOOT
ROM
Transfer data from the external controller to
TMP89FM46
Baud rate
Transfer data from TMP89FM46 to the external controller
1st byte
2nd byte
Matching data 1 (0x86 or 0x30)
-
Automatic adjustment
Baud rate after adjustment
-(Automatic baud rate adjustment)
OK: Echo back data (0x86 or 0x30)
Error: No data transmitted
3rd byte
4th byte
Matching data 2 (0x79 or 0xCF)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0x79 or 0xCF)
Error: No data transmitted
5th byte
6th byte
Operation command data (0xC3)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0xC3)
Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1)
7th byte
Baud rate after adjustment
0x3A
Start mark
8th byte
Baud rate after adjustment
0x04
Byte count
(from 9th through 12th bytes)
9th byte
Baud rate after adjustment
0x00 to 0x7F
Status code 1
10th byte
Baud rate after adjustment
0x00
Reserved
11th byte
Baud rate after adjustment
0x00
Reserved
12th byte
Baud rate after adjustment
0x00
Reserved
13th byte
Baud rate after adjustment
Checksum
(complement of 2 of the sum total from 9th
through 12th bytes)
Baud rate after adjustment
-
14th byte
(Wait for the next operation command data)
Note 1: "xxH × 3" means that the device goes into an idle state after transmitting 3 bytes of xxH.
Note 2: For detailed information on the status code 1, refer to "22.8.7.1 Flash memory status code".
RA002
Page 331
22. Serial PROM Mode
22.8 Operation Commands
TMP89FM46
22.8.7.1 Flash memory status code
The flash memory status code is 7-byte data. It shows the status of the flash memory security program
and that of the address from 0xFFE0 to 0xFFFF.
Table 22-15 Flash Memory Status Code
Data
Description
In the case of TMP89FM46
1st
Start mark
0x3A
2nd
Number of transfer data (4 bytes from 3rd through
6th bytes)
0x04
3rd
Status code
0x00 through 0x1F
(see information below)
4th
Reserved
0x00
5th
Reserved
0x00
6th
Reserved
0x00
7th
Checksum of transfer data
(complement of 2 of the sum total of 3rd through
6th bytes)
If 3rd data is 0x00: 0x00
If 3rd data is 0x01: 0xFF
If 3rd data is 0x02: 0xFE
If 3rd data is 0x03: 0xFD
:
Status code 1
7
6
5
4
3
2
1
0
EPFC
DAFC
RPENA
BLANK
Initial value (**** ****)
EPFC
Password string judgment when the
flash memory erase command is
executed
(status of 0xFFFA)
0:
1:
To skip the judgment of a password string (to judge PNSA and
PCSA only)
To judge a password string, PNSA, and PCSA
DAFC
Security program check of the onchip debugging function (OCD)
(status of 0xFFFB)
0:
1:
To skip the security program check at the start of OCD
To perform the security program check at the start of OCD
RPENA
Status of the flash memory security
program
0:
1:
Status in which the security program is disabled
Status in which the security program is enabled
BLANK
Status of 0xFFE0 through 0xFFFF
0:
1:
If data in the area 0xFFE0 through 0xFFFF are all 0xFF
If data in the area 0xFFE0 through 0xFFFF are other than 0xFF
Restrictions are placed on the execution of some operation commands, depending on the contents of the
status code 1. Detailed information on this is shown in the table below. If the security program is enabled,
three commands cannot be executed: the flash memory write command, RAM loader mode command,
and Sector Erase command. To execute these commands, Chip Erase must be performed on flash memory
before they are executed.
RA002
Page 332
TMP89FM46
RPENA
BLANK
EPFC
DAFC
Flash memory erase
command
Flash memory overwrite
command, flash memory
read command, and
RAM loader command
Flash memory SUM output command, product
ID output command, and
status output command
Chip erase
Sector
erase
Flash memory security
setting command
0
0
0
0
Ο
Ο
Ο
×
×
1
0
0
0
×
Ο
Ο
×
×
0
*
Pass
Ο
Ο
×
Pass
0
1
1
*
Pass
Ο
0
*
×
Ο
Ο
×
Pass
1
*
×
Ο
Pass
×
Pass
1
Pass
Pass
1
Note: Ο : A command can be executed.
Pass: A password is required to execute a command.
×: A command cannot be executed.
(After a command is echoed back, the TMP89FM46 stops communication, and goes into an idle state.)
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22. Serial PROM Mode
22.8 Operation Commands
TMP89FM46
22.8.8 Mask ROM emulation setting command (0xD0)
Table 22-16 shows the mask ROM emulation setting command.
This command is nonfunctional in the TMP89FM46. It becomes functional if used for a product with flash
memory of more than 96Kbytes.
Table 22-16 Command to Change the Mask ROM Emulation Setting
Number of
transfer bytes
BOOT
ROM
Transfer data from the external controller to
TMP89FM46
Transfer data from TMP89FM46 to the
external controller
Baud rate
1st byte
2nd byte
Matching data 1 (0x86 or 0x30)
-
Automatic adjustment
Baud rate after adjustment
-(Automatic baud rate adjustment)
OK: Echo back data (0x86 or 0x30)
Error: No data transmitted
3rd byte
4th byte
Matching data 2 (0x79 or 0xCF)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0x79 or 0xCF)
Error: No data transmitted
5th byte
6th byte
Operation command data (0xD0)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0xD0)
Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1)
7th byte
8th byte
Set value
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0xD1)
Error: No data transmitted
9th byte
(Wait for the next operation command data)
Baud rate after adjustment
-
Note 1: "xxH × 3" means that the device goes into an idle state after transmitting 3 bytes of xxH.
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TMP89FM46
22.8.9 Flash memory security setting command (0xFA)
Table 22-17 shows the flash memory security setting command.
Table 22-17 Flash Memory Security Setting Command
Transfer data from the external controller to
TMP89FM46
Transfer byte
BOOT
ROM
Transfer data from TMP89FM46 to the
external controller
Baud rate
1st byte
2nd byte
Matching data 1 (0x86 or 0x30)
-
Automatic adjustment
Baud rate after adjustment
- (Automatic baud rate adjustment)
OK: Echo back data (0x86 or 0x30)
Error: No data transmitted
3rd byte
4th byte
Matching data 2 (0x79 or 0xCF)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0x79 or 0xCF)
Error: No data transmitted
5th byte
6th byte
Operation command data (0xFA)
-
Baud rate after adjustment
Baud rate after adjustment
OK: Echo back data (0xFA)
Error: 0xA1 × 3, 0xA3 × 3, 0x63 × 3 (note 1)
7th byte
8th byte
Password count storage address 23 to 16
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
9th byte
10th byte
Password count storage address 15 to 08
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
11th byte
12th byte
Password count storage address 07 to 00
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
13th byte
14th byte
Password comparison start address 23 to 16
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
15th byte
16th byte
Password comparison start address 15 to 08
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
17th byte
18th byte
Password comparison start address 07 to 00
Baud rate after adjustment
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
19th byte
:
m-th byte
Password string
Baud rate after adjustment
-
-
Baud rate after adjustment
OK: No data transmitted
Error: No data transmitted
n-th byte
-
Baud rate after adjustment
OK: 0xFB (note 3)
Error: No data transmitted
n-th + 1 byte
(Wait for the next command data)
Baud rate after adjustment
-
Note 1: "xxH × 3" means that the device goes into an idle state after transmitting 3 bytes of xxH.
Note 2: For information on passwords, refer to "22.12.1 Passwords".
Note 3: If the flash memory security setting command is executed for a blank product or if a password error occurs for a non-blank
product, the TMP89FM46 stops communication and goes into an idle state. Therefore, if a password error occurs, initialize
the TMP89FM46 by using the RESET pin, and restart the serial PROM mode.
Note 4: If a communication error occurs during the transfer of a password address or password string, the TMP89FM46 stops
communication and goes into an idle state. Therefore, if a password error occurs, initialize the TMP89FM46 by using the
RESET pin, and restart the serial PROM mode.
Note 5: If the flash memory security is not enabled, it becomes possible to read ROM data freely in parallel PROM mode. Make
sure that you enable the flash memory security in mass production.
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22. Serial PROM Mode
22.9 Error Code
TMP89FM46
22.9 Error Code
Table 22-18 shows the error codes that the TMP89FM46 transmits when it detects errors.
Table 22-18 Error Codes
Data transmitted
Meaning of error data
0x63, 0x63, 0x63
Operation command error
0xA1, 0xA1, 0xA1
Framing error in the received data
0xA3, 0xA3, 0xA3
Overrun error in the received data
Note: If a password error occurs, the TMP89FM46 does not transmit an error code.
RA002
Page 336
TMP89FM46
22.10Checksum (SUM)
For the following operation commands, a checksum is returned to verify the appropriateness of the result of command execution:
- Flash memory erase command (0xF0)
- Flash memory write command (0x30)
- Flash memory SUM output command (0x30)
- Flash memory read command (0x40)
- RAM loader command (0x60)
- Product ID code output command (0xC0)
- Flash memory status output command (0xC3)
22.10.1Calculation method
The checksum (SUM) is calculated with the sum of all bytes, and the obtained result is returned as a word.
The data is read in single-byte units, and the calculated result is returned as a word.
Example:
0xA1
0xB2
0xC3
0xD4
If the data to be calculated consists of four bytes as shown
on the left, the checksum of the data is as follows:
0xA1 + 0xB2 + 0xC3 + 0xD4 = 0x02EA
SUM (HIGH)= 0x02
SUM (LOW)= 0xEA
In the case of the product ID code output command and flash memory status output command, however, a
different calculation method is used. For more information, refer to Table 22-19.
22.10.2Calculation data
Table 22-19 shows the data for which a checksum is calculated for each command.
Table 22-19 Data for which a Checksum Is Calculated
Operation command
Flash memory erase command
Calculation data
Description
All data in the erased area of flash memory (whole or part of flash memory)
When the sector erase is executed, only the erased area is
used to calculate the checksum. In the case of the chip erase,
an entire area of the flash memory is used.
Data in the entire area of flash memory
Even if a part of the flash memory is written, the checksum of
the entire flash memory area (0x8000 to 0xFFFF) is calculated. The data length, address, record type and checksum in
Intel Hex format are not included in the checksum.
Flash memory write command
Flash memory SUM output command
Flash memory read command
Data in the read area of flash memory
RAM loader command
RAM data written in the first received
RAM address through the last received
RAM address
The length of data, address, record type and checksum in Intel
Hex format are not included in the checksum.
Product ID code output command
9th through 18th bytes of transferred data
For details, refer to "22.8.6 Product ID code output command
(operation command: 0xC0)".
Flash memory status output command
9th through 12th bytes of transferred data
For details, refer to Table "Table 22-14 Flash Memory Status
Output Commands".
RA002
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22. Serial PROM Mode
22.11 Intel Hex Format (Binary)
TMP89FM46
22.11Intel Hex Format (Binary)
For the following two commands, the Intel Hex format is used in part of the transfer format:
- Flash memory write command (0x30)
- RAM loader command (0x60)
For information on the definition of the Intel Hex format, refer to Table 22-20.
Data is in binary form. The start mark ":" must be transmitted as binary data of 0x3A.
1. After receiving the checksum of each data record, the TMP89FM46 goes into a wait state and awaits the
arrival of the start mark (0x3A ":") of the next data record. Although the external controller transmits data
other than 0x3A between records, the TMP89FM46 ignores such data when it is in this wait state.
2. The external controller must be provisioned so that after it transmits the checksum of end record, it goes
into a wait state and does not transmit any data until the arrival of 3-byte data (overwrite detection, upper
and lower bytes of the checksum). (3-byte data is used if the flash memory write command is used. If the
RAM loader command is used, the external controller awaits the arrival of 2-byte data, or upper and lower
bytes of the checksum.)
3. If a receiving error or Intel Hex format error occurs, the TMP89FM46 goes into an idle state without returning an error code to the external controller. The Intel Hex format error occurs in the following cases:
- If the record type is other than 00h, 01h, or 02h
- If a checksum error of the Intel Hex format occurs
- If the data length of an extended record (record type = 0x02) is not 0x02
- If the TMP89FM46 receives the data record after receiving an extended record (record type = 0x02)
whose segment address is more than 0x2000
- I the data length of the end record (record type = 0x01) is not 0x00
- If the offset address of an extended record (record type = 0x02) is not 0x0000
Table 22-20 Definition of the Intel Hex Format
(1)
(2)
(3)
(4)
(5)
(6)
Start
mark
Data length
(1 byte)
Offset address
(2 bytes)
Record type
(1 byte)
Data
Checksum
(1 byte)
Number of data
in a data field
Starting byte storage address
* Specified using
big-endian
Data record
3A
(record type = 00)
Data
(1 to 255 bytes)
(2) Data length
(3) Offset address
(4) Record type
(5) Data
Complement of 2 of the
sum total of the above
01
None
(2) Data length
(3) Offset address
(4) Record type
Complement of 2 of the
sum total of the above
02
Segment address
(2 bytes)
* Specified using
big-endian
(2) Data length
(3) Offset address
(4) Record type
(5) Segment address
Complement of 2 of the
sum total of the above
00
End record
3A
00
00 00
(record type = 01)
Extended record
3A
02
00 00
(record type = 02)
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TMP89FM46
22.12Security
In serial PROM mode, two security functions are provided to prohibit illegal memory access attempts by a third
party: password and security program functions.
22.12.1Passwords
A password is one of the security functions, and can be used when the TMP89FM46 operates in serial
PROM mode or when the on-chip debugging function (hereafter called OCD) is used. Specifically, a password
can be established by using data (part of user memory) in flash memory. If a password is established, a password authentication process must be performed to execute the flash memory read command, flash memory
write command, and other operation commands. In the case of the OCD, the password authentication process is
required prior to the start of the OCD system.
In parallel PROM mode, there are no access-related restrictions using a password. To establish the accessrelated restrictions that work in both serial and parallel PROM modes, the security program must be set to an
appropriate setting.
22.12.1.1How a password can be specified
With the TMP89FM46, any piece of data in flash memory (8 or more consecutive bytes) can be specified as a password. A password thus specified is authenticated by comparing a password string transmitted by the external controller with the memory data string of MCU where the password is specified. The
area where a password can be specified is 0x8000 through 0xFEFF in flash memory.
22.12.1.2Password structure
A password consists of three components: PNSA, PCSA, and a password string. Figure 22-4 shows the
password structure (example of a transmitted password).
• PNSA (password count storage address)
A 3-byte address is specified in the area 0x8000 through 0xFEFF. The memory data of a
specified address is the number of bytes of a password string. If the memory data is less than
0x07 or if an address is outside the specified address range, a password error occurs.
The memory data specified here is defined as N.
• PCSA (password comparison start address)
A 3-byte address is specified in the area 0x8000 through 0xFEFF-N. An address thus specified is the starting address to be used to compare with a password string. If an address is outside
the specified address range, a password error occurs.
• Password string
Data of 8 bytes to 255 bytes (=N) must be specified as a password string. Memory data and a
password string are compared by a specified number "N" of bytes; a comparison starts at an
address specified by PCSA. If there is a mismatch as a result of this comparison or if data of 3
or more consecutive bytes is specified, a password error occurs, and the TMP89FM46 goes into
an idle state. In this idle state, external devices cannot communicate with the TMP89FM46. To
resume communication, the TMP89FM46 must be restarted in serial PROM mode by using the
reset pin.
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22. Serial PROM Mode
22.12 Security
TMP89FM46
MCU
RXD/SI pin
0x00 0xF0 0x12 0x00 0xF1 0x07 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
PNSA
Password string
PCSA
Flash memory
0xF012
Example:
PNSA=0xF012
PCSA=0xF107
0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 and
0x08 are assumed.
0x08
0xF107
0x01
0xF108
0x02
0xF109
0x03
0xF10A
0x04
0xF10B
0x05
0xF10C
0x06
0xF10D
0x07
0xF10E
0x08
0x08 is the number
of passwords.
Compare
8 bytes
Figure 22-4 Password Structure (Example of a Password Transmitted)
RA002
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TMP89FM46
22.12.1.3Password setting, cancellation and authentication
• Password setting
Because a password is created by using part of a user program, a special password setting
routine is unnecessary. A password can be set by simply writing a program to flash memory.
• Password cancellation
To cancel a password, Chip Erase (all erase) must be performed on flash memory. A password is canceled when flash memory is all initialized to 0xFF.
• Password authentication
If there is data other than 0xFF in any one byte of data written to the address 0xFFE0 through
0xFFFF of the TMP89FM46, a product is considered a non-blank product, and password
authentication is required to execute an operation command. In this password authentication
process, PNSA, PCSA and a password string are used. An operation command is executed only
if a password has been successfully authenticated. If a password is unsuccessfully authenticated, the TMP89FM46 goes into an idle state.
If all data written to the address 0xFFE0 through 0xFFFF are 0xFF, a product is considered
blank, and no password authentication is performed. To execute some special operation commands, however, PNSA and PCSA are still required (a password string is not required) even if
a product is blank. In this case, the addresses defined in Table 22-21 must be selected as PNSA
and PCSA.
Whether a product is blank or non-blank can be confirmed by executing the status output
command.
The operation commands that require PNSA and PCSA (password string) for them to be executed are as follows:
- Flash memory erase command (0xF0)
- Flash memory write command (0x30)
- Flash memory read command (0x40)
- RAM loader command (0x60)
- Flash memory security setting command (0xFA)
22.12.1.4Password values and setting range
A password must be set in accordance with the conditions shown in Table 22-21. If a password created
without meeting these conditions is used, a password error occurs. In this case, the TMP89FM46 does not
transmit data and goes into an idle state.
Table 22-21 Password Values and Setting Range
RA002
Password
Blank product (note 1)
Non-blank product
PNSA
(password count storage address)
0x8000 ≤ PNSA ≤ 0xFEFF
0x8000 ≤ PNSA ≤ 0xFEFF
PCSA
(password comparison start
address)
0x8000 ≤ PCSA ≤ 0xFEFF
0x8000 ≤ PCSA ≤ 0xFF00 - N
N
(password count)
*
8≤N
Password string
Not required (notes 4 and 5)
Required (note 3)
Page 341
22. Serial PROM Mode
22.12 Security
TMP89FM46
Note 1: *: Don’t care.
Note 2: When addresses from 0xFFE0 through 0xFFFF are filled with "0xFF", the product is recognized as a blank product.
Note 3: The data including the same consecutive data (three or more bytes) cannot be used as a password. (A password error
occurs during password authentication. The TMP89FM46 does not transmit any data and goes into an idle state.)
Note 4: In flash memory writing mode or RAM loader mode, the blank product receives the Intel Hex format data immediately after
receiving PCSA; it does not receive password strings. In this case, the subsequent processing is performed correctly
because the TMP89FM46 keeps ignoring incoming data until the start mark (0x3A ":") in the Intel Hex format is detected,
even if the external controller transmits the dummy password string. However, if the dummy password string contains
"0x3A", it is detected as the start mark erroneously, and the microcontroller enters the halt mode. If this causes a problem,
do not transmit the dummy password strings.
Note 5: In executing the flash memory erase command, do not transmit a password string to a blank product.
RA002
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TMP89FM46
22.12.2Security program
The security program can be used in parallel and serial PROM modes and for OCD. It has a special memory
for protection, and a special command is required to make this protection setting. If the security program is
enabled, the reading or writing of flash memory in parallel PROM mode is prohibited. In serial PROM mode,
the read and write of flash memory and other operation commands cannot be used. In performing OCD, two
options about system startup are provided: prohibiting the system startup by using an option code and starting
the system by password authentication.
22.12.2.1How the security program functions
With the TMP89FM46, you can control the read of flash memory by writing protection-related information to a specially-designed memory. Because protection-related information is written to this speciallydesigned memory, no user memory resource are required.
22.12.2.2Enabling or disabling the security program
• Enabling the security program
To enable the security program, execute the flash memory security setting command.
• Disabling the security program
To disable the security program, execute Chip Erase of the flash memory erase command.
RA002
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22. Serial PROM Mode
22.12 Security
TMP89FM46
22.12.3Option codes
If a specified option code is placed at a specified address inside the interrupt vector area, whether password
string authentication is performed or not when executing the flash memory erase command and whether the
security program is checked or not when starting OCD can be designated.
- Erase password free code EPFC_OP (0xFFFA)
If changes are frequently made to a program during software development, there are cases in which
a password may get lost. In this case, you can cancel the password string authentication of the flash
memory erase command (0xF0) by setting the erase password free code (EPFC_OP). EPFC_OP is
assigned to 0xFFFA in the vector area. Allocate 0xFF to this EPFC_OP to cancel the password string
of the flash memory erase command (0xF0).
It is recommended that the password string authentication of the flash memory erase command
(0xF0) be enabled during mass production by allocating data other than 0xFF to EPFC_OP.
Only Chip Erase can cancel the password string authentication by using the flash memory erase
command. If Sector Erase is executed with EPFC_OP set to 0xFF, the TMP89FM46 goes into an idle
state. Commands other than the flash memory erase command cannot cancel the password string
authentication.
- OCD security program free code DAFC_OP (0xFFFB)
With the TMP89FM46, you can enable the security program to prevent illegal access attempts by a
third party. If the security program is enabled, restrictions are imposed on operation commands
related to memory access, and the startup of OCD.
The security program should be usually enabled at the time of shipment. If there is the possibility
that the OCD may be used by keeping the contents of memory intact, it is possible to directly start the
OCD by setting the OCD security program free code (DAFC_OP) and thereby skipping the security
program check (the password string authentication, however, is still required).
DAFC_OP is assigned to 0xFFFB in the vector area. To skip the security program check at the
startup of the OCD, assign 0xFF to DAFC_OP. In this case, the security program check is not performed, and the OCD can be started by performing only the password string authentication.
If DAFC_OP is not 0xFF, whether the OCD can be used or not is determined by the status of the
security program. If the OCD is started with the security program enabled, the TMP89FM46 stops
communication and goes into an idle state. To use the OCD when the TMP89FM46 is in this idle
state, Chip Erase must be executed for flash memory by using the flash memory erase command
(0xF0). If the security program is disabled, the OCD can be started by performing only the password
string authentication.
Table 22-22 Option Codes
RA002
Symbol
Function
Address
EPFC_OP
Password string authentication when the flash
memory erase command is executed
0xFFFA
0xFF : The password string authentication is
skipped (only PNSA and PCSA are authenticated).
Other than 0xFF: The password string, PNSA, and
PCSA are authenticated.
DAFC_OP
Security program check when the OCD is
started
0xFFFB
0xFF: The security program check is skipped.
Other than 0xFF: The security program check is performed.
Page 344
Set value
TMP89FM46
Example :Case in which the password authentication and OCD security program authentication are disabled
Vector Section romdata abs = 0xFFFA
DB
DB
RA002
0xFF
0xFF
; Cancel the password string during the erase operation (EPFC_OP)
; Permit access when the OCD is started (DAFC_OP)
Page 345
22. Serial PROM Mode
22.12 Security
TMP89FM46
22.12.4Recommended settings
Table 22-23 shows the option codes and recommended security program settings.
Table 22-23 Option Codes and Recommended Security Program Settings
Device status
At the time of debugging during software
development
Serial PROM mode
Parallel PROM mode
OCD
EPFC_OP
(0xFFFA)
DAFC_OP
(0xFFFB)
Security
Program
Memory
read
Erase
Memory
read
Erase
0xFF
0xFF
Disable
Password
string
required
Possible
Possible
Possible
Can be
used
0xFF
Possible
0xFF
Other than
0xFF
Cannot be
used
Enable
In quantity production
Impossible
0xFF
Other than
0xFF
Can be
used
Impossible
Possible
Password
string
required
Other than
0xFF
Can be
used
Cannot be
used
Note 1: In parallel PROM mode, Chip Erase can be performed irrespective of the option code setting.
Note 2: If the security program is not enabled in parallel PROM mode, ROM data can be read with no restrictions. Make sure that
in parallel PROM mode, you always enable the security program to protect ROM data.
RA002
Page 346
RA002
Figure 22-5 Flowchart
Page 347
(detect all 0xFF)
Transmit data
(checksum of the entire area)
Transmit data
(checksum of the entire area)
Non-blank
product
Execute a write
OK
Password check
Blank product
Blank check
Disabled
Security Program
check
Transmit data
(0x60)
Receive data =0x60
(RAM loader
command)
≠ 0xCF
Jump to the user
program in RAM
0x55 : 0xAA: All data are 0xFF.
Transmit data
0x55 : There is no error.
0xAA: There is an error.
(Double writes
are detected)
Transmit data
Calculate checksum
Closed loop
NG
Enabled
Transmit data
(0x90)
Receive data =0x90
(flash memory SUM
output command)
Transmit S1O data
(0xCF)
(detect double writes)
Execute a write
OK
Password check
Non-blank
product
Blank check
Disabled
Security Program
check
Transmit data
(0x30)
Receive data =0x30
(flash memory
write command)
Receive data
Transmit UART data
(0x79)
= 0xCF
Receive data
Receive data
= 0x79
Receive data
Receive data
Blank product
≠ 0x79
Transmit S1O data
(0x30)
Transmit UART data
(0x86)
= 0x30
Receive data
S1O mode
≠ 0x86
UART mode
= 0x86
Received data
Receive data
Setup
Start
(product ID code)
Transmit data
Closed loop
NG
Enabled
Transmit data
(0xC0)
Receive data =0xC0
(product ID code
output command)
Transmit data
(0xFB)
Transmit data
(0xC3)
(status)
Transmit data
DAFC-OP and
EPFC-OP check
Blank check
Security Program
check
Closed loop
NG
= FFH
= 0xFF
Change
FLSCR1<ROMSEL>
Receive data
Transmit data
(0xD0)
(mask ROM emulation
setting command)
Receive data =D0H
Transmit data
(0xD1)
Closed loop
(erase in 4KB units)
Security Program
check
Enabled
Disabled
Sector erase
≠ 0xFF
EPFC-OP
Closed loop
< 0x20
(checksum of the erased area)
Transmit data
Disable
Security Program
(erase the entire area)
Chip erase
≥ 0x20
Received data
Receive data
Execute an erase
OK
NG
Non-blank
product
Password check
Blank product
Blank check
≠ 0xFF
Perform
password check
EPFC-OP
Transmit data
(0xF0)
Receive data =0xF0
(flash memory
erase command)
Not perform
password check
Receive data =0xC3
(status output
command)
Blank product
Enable Security Program
OK
Password check
Non-blank
product
Blank check
Transmit data
(0xFA)
Receive data =0xFA
(Security Program
enable command)
(checksum)
Transmit data
(Read data)
Transmit data
Receive data
OK
Enabled
Closed loop
NG
Non-blank
product
Password check
Blank product
Blank check
Disabled
Security Program
check
Transmit data
(0x40)
Receive data =40H
(flash memory
read command)
TMP89FM46
22.13Flowchart
22. Serial PROM Mode
22.14 AC Characteristics (UART)
TMP89FM46
22.14AC Characteristics (UART)
Table 22-24 UART Timing-1
Parameter
Symbol
Minimum required time
Clock frequency
(fcgck)
At fcgck = 1 MHz
At fcgck = 10 MHz
Time from when MCU receives 0x86 to when it echoes back
CMeb1
Approx. 660
660 µs
66 µs
Time from when MCU receives 0x79 to when it echoes back
CMeb2
Approx. 540
540 µs
54 µs
Time from when MCU receives an operation command to when it
echoes back
CMeb3
Approx. 300
300 µs
30 µs
Time required to calculate the checksum (flash memory)
CMfsm
Approx. 1493340
(32KB)
1.5 s
149 ms
Time required to calculate the checksum (RAM)
CMrsm
Approx. 160
160 µs
16 µs
Time when MCU receives Intel Hex data to when it transmits overwrite detection data
CMwr
Approx. 200
200 µs
20 µs
Time from when MCU receives data (number of read bytes) to
when it transmits memory data
CMrd
Approx. 430
430 µs
43 µs
CMem2
Approx. 420
420 µs
42 µs
CMrp
Approx. 1080
1.08 ms
108 µs
Symbol
Clock frequency
(fcgck)
Time from when MCU receives data (mask ROM emulation setting
data) to when it echoes back
Time required to enable the security program
Table 22-25 UART Timing-2
Parameter
Minimum required time
At fcgck = 1 MHz
At fcgck = 10 MHz
Time required to keep MODE and RESET pins at L after power-on
RSsup
-
10 ms
Time from when MODE and RESET pins are set to H to the acceptance of RXD
RXsup
-
20 ms
Time from when MCU echoes back 0x86 to the acceptance of
RXD
CMtr1
Approx. 140
140 µs
14 µs
Time from when MCU echoes back 0x79 to the acceptance of
RXD
CMtr2
Approx. 90
90 µs
9 µs
Time from when MCU echoes back an operation command to the
acceptance of RXD
CMtr3
Approx. 270
270 µs
27 µs
Time from when the execution of a current command is completed
to the acceptance of the next operation command
CMnx
Approx. 1100
1.1 ms
110 µs
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TMP89FM46
22.14.1Reset timing
VDD
MODE
RSsup
RESET
(0x86)
RXD
RXsup
(0x79)
(0x86)
(0x79)
TXD
CMtr2
CMtr1
CMeb1
CMeb2
CMtr3
CMeb3
Operation command
Figure 22-6 Reset Timing
22.14.2Flash memory erase command (0xF0)
PNSA
PCSA
Password string
Area to be erased
[23:16] [15:8] [7:0] [23:16] [15:8] [7:0]
RXD
(0xF0)
TXD
CMtr3
Next command
RXD
[15:8] [7:0]
TXD
Checksum
CMfsm
Figure 22-7 Flash Memory Erase Command
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CMnx
22. Serial PROM Mode
22.14 AC Characteristics (UART)
TMP89FM46
22.14.3Flash memory write command (0x30)
PNSA
PCSA
Password string
[23:16] [15:8] [7:0] [23:16] [15:8] [7:0]
IntelHex
(0x3A)
RXD
(0x30)
TXD
CMtr3
IntelHex(End Record)
(0x00) (0x00) (0x01) (0xFF)
Next command
RXD
(0x55) or (0xAA)
[15:8] [7:0]
TXD
Overwrite
CMwr detection
Checksum
CMfsm
CMnx
Figure 22-8 Flash Memory Write Command
22.14.4Flash memory read command (0x40)
PNSA
PCSA
Password string
[23:16] [15:8] [7:0] [23:16] [15:8] [7:0]
Read start address
[23:16] [15:8] [7:0]
RXD
(0x40)
TXD
CMtr3
Number of read bytes
Next command
[23:16] [15:8] [7:0]
RXD
[15:8] [7:0]
TXD
CMrd
Memory data
Checksum
Figure 22-9 Flash Memory Read Command
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CMnx
TMP89FM46
22.14.5RAM loader command (0x60)
PNSA
PCSA
Password string
[23:16] [15:8] [7:0] [23:16] [15:8] [7:0]
IntelHex
(0x3A)
RXD
(0x60)
TXD
CMtr3
IntelHex(End Record)
(0x00) (0x00) (0x01) (0xFF)
Next command
RXD
[15:8] [7:0]
TXD
Checksum
CMrsm
CMnx
Figure 22-10 RAM Loader Command
22.14.6Flash memory SUM output command (0x90)
Next command
RXD
(0x55) or
(0xAA) [15:8] [7:0]
(0x90)
TXD
FF
check
CMfsm
Checksum
CMnx
Figure 22-11 Flash Memory SUM Output Command
22.14.7Product ID code output command (0xC0)
Next command
RXD
(0xC0)
TXD
Product ID code
Figure 22-12 Product ID Code Output Command
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CMnx
22. Serial PROM Mode
22.14 AC Characteristics (UART)
TMP89FM46
22.14.8Flash memory status output command (0xC3)
Next command
RXD
(0xC3)
TXD
Status code
CMnx
Figure 22-13 Flash Memory Status Output Command
22.14.9Mask ROM emulation setting command (0xD0)
Figure 22-14 Mask ROM Emulation Setting Command
22.14.10Flash memory security setting command (0xFA)
PNSA
PCSA
Password string
[23:16] [15:8] [7:0] [23:16] [15:8] [7:0]
RXD
(0xFA)
TXD
CMtr3
Next command
RXD
0xFB
TXD
Echo
back CMnx
CMrp
Figure 22-15 Flash Memory Security Setting Command
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TMP89FM46
23. On-chip Debug Function (OCD)
The TMP89FM46 has an on-chip debug function. Using a combination of this function and the TOSHIBA on-chip
debug emulator RTE870/C1, the user is able to perform software debugging in the on-board environment. This emulator can be operated from a debugger installed on a PC so that the emulation and debugging functions of an application program can be used to modify a program or for other purposes.
This chapter describes the control pins needed to use the on-chip debug function and how a target system is connected to the on-chip debug function. For more detailed information on how to use the on-chip debug emulator
RTE870/C1, refer to the emulator operating manual.
23.1 Features
The on-chip debug function of the TMP89FM46 has the following features:
• Debugging can be performed in much the same way as when a microcontroller packaged with the MCU is
used.
• The debugging function can be realized using two communication control pins.
• Useful on-chip debug functions include the following:
- 8 breaks function are provided (one of which can also be used as an event function).
- A trace function that allows the newest two branch instructions to be stored in real time is provided.
- Functions to display active memory and to overwrite active memory are provided.
• Built-in flash memory can be erased and written.
23.2 Control Pins
The on-chip debug function uses two pins for communication and four pins for power supply, reset and mode control. The pins used for the on-chip debug function are shown in Table 23-1.
Ports P20 and P21 are used as communication control pins of the on-chip debug function. If the on-chip debug
emulator RTE870/C1 is used, therefore, the port functions and the functions of UART0 and SIO0, which are also
used as ports, cannot be debugged.
Table 23-1 Pins Used for the On-chip Debug Function
Pin name
(during on-chip debugging)
Input/output
Pin name
(in MCU mode)
Function
OCDCK
Input
Communication control pin (clock control)
OCDIO
I/O
Communication control pin (data control)
P20 / TXD0 / SO0
P21 / RXD0 / SI0
(Note 1)
RESET
Input
Reset control pin
RESET
MODE
Input
Mode control pin
MODE
VDD
Power
supply
4.5 V to 5.5 V (note 1)
VSS
Power
supply
0V
Input and output ports other than
P20 and P21
XIN
I/O
Can be used for an application in a target system
Input
To be connected to an oscillator to put these pins in a state of self-oscillation
XOUT
Output
Note 1: To use all on-chip debug functions, the power supply voltage must be within the range 4.5 V to 5.5 V. If it is within the range
2.7 V to 4.5 V, functional limitations occur with some of the debug functions. For more detailed information, refer to the
emulator operating manual.
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23. On-chip Debug Function (OCD)
23.3 How to Connect the On-chip Debug Emulator to a Target
System
TMP89FM46
23.3 How to Connect the On-chip Debug Emulator to a Target System
To use the on-chip debug function, the specific pins on a target system must be connected to an external debugging
system.
The on-chip debug emulator RTE870/C1 can be connected to a target system via an interface control cable.
TOSHIBA provides a connector for this interface control cable as an accessory tool. Mounting this connector on a
target system will make it easier to use the on-chip debug function.
The connection between the on-chip debug emulator RTE870/C1 and a target system is shown in Figure 23-1.
Level Shifter
(provided power supply by target system)
Control Circuit
(provided power supply by bus power)
VDD (Note 3)
VDD
OCDCK (P20)
OCDIO (P21)
(Note 2)
Other
parts
TMP89FM46
RESET
control
(Note 1)
RESET
Interface
control cable
USB connection
During on-chip debugging
MODE
MCU mode
XIN
(Note 3)
XOUT
VSS
Target system
Connectors
On-chip debug
emulator
RTE870/C1
PC (host system)
Figure 23-1 How the On-chip Debug Emulator RTE870/C1 Is Connected to a Target System
Note 1: Ports P20 and P21 are used as communication control pins of the on-chip debug function. If the on-chip debug
emulator RTE870/C1 is used, therefore, the port functions and the functions of UART0 and SIO0, which are also
used as ports, cannot be debugged. If the emulator is disconnected to be used as a single MCU, the functions of
ports P20 and P21 can be used. To use the on-chip debug function, however, P20 and P21 should be disconnected using a jumper, switch, etc. if there is the possibility of other parts affecting the communication control.
Note 2: If the reset control circuit on an application board affects the control of the on-chip debug function, it must be disconnected using a jumper, switch, etc.
Note 3: The power supply voltage VDD must be provided by a target system. The VDD pin is connected to the emulator
so that the level of voltage appropriate for driving communication pins can be obtained by using the power supply
of a target system. The connection of the VDD pin is for receiving the power supply voltage, not for supplying it
from the emulator side to a target system.
23.4 Security
The TMP89FM46 provides two security functions to prevent the on-chip debug function from being used through
illegal memory access attempted by a third person: a password function and a Security Program function. If a password is set on the TMP89FM46, it is necessary to authenticate the password for using the on-chip debug function.
By setting both a password and the Security Program on the TMP89FM46, it is possible to prohibit the use of all onchip debug functions. Furthermore, by using the option code, the on-chip debug function only can be used even if the
Security Program is enabled. However, to use the on-chip debug function in this setting, a password authentication
process is required.
For information on how to set a password and to enable the read protection and option code, refer to "Serial PROM
Mode".
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TMP89FM46
24. Input/Output Circuit
24.1 Control Pins
The input/output circuitries of the TMP89FM46 control pins are shown below.
Control pin
I/O
Circuitry
XIN
XOUT
Input
Output
Refer to the P0 ports in the chapter of Input/Output Ports.
XTIN
XTOUT
Input
Output
Refer to the P0 ports in the chapter of Input/Output Ports.
RESET
Input
Refer to the P1 ports in the chapter of Input/Output Ports.
Remarks
R
MODE
RA000
R = 100 Ω (typ.)
Input
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24. Input/Output Circuit
24.1 Control Pins
RA000
TMP89FM46
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TMP89FM46
25. Electrical Characteristics
25.1 Absolute Maximum Ratings
The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant.
Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down
or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when
designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
(VSS = 0 V)
Parameter
Supply voltage
Input voltage
Output voltage
Symbol
Pins
VDD
Ratings
Unit
−0.3 to 6.0
V
VIN1
P0, P1, P2 (excluding P23 and P24), P4, P7,
P8, P9, PB (tri-state port)
−0.3 to VDD + 0.3
VIN2
P23, P24 (sink open drain port)
−0.3 to VDD + 0.3
VIN3
AIN0 to AIN7 (analog input voltage)
−0.3 to AVDD + 0.3
−0.3 to VDD + 0.3
VOUT1
IOUT1
P0, P1, P2 (excluding P23 and P24), P4, P7,
P8, P9, PB (tri-state port)
−1.8
IOUT2
P0, P1, P2, P4, P9 (pull-up resistor)
−0.4
IOUT3
P0, P1, P2, P4, P74 to P77, P8, P9 (tri-state
port)
3.2
IOUT4
P70 to P73, PB (large current port)
30
ΣIOUT1
P0, P1, P2 (excluding P23 and P24), P4, P7,
P8, P9, PB (tri-state port)
−30
ΣIOUT2
P0, P1, P2, P4, P9 (pull-up resistor)
−4
ΣIOUT3
P0, P1, P2, P4, P74 to P77, P8, P9 (tri-state
port)
60
ΣIOUT4
P70 to P73, PB (large current port)
120
V
V
Output current (per pin)
mA
Output current (total)
Power dissipation (Topr = 85°C)
PD
250
Soldering temperature (time)
Tsld
260 (10 s)
Storage temperature
Tstg
−55 to 125
Operating temperature
Topr
−40 to 85
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mW
°C
25. Electrical Characteristics
25.2 Operating Conditions
TMP89FM46
25.2 Operating Conditions
The operating conditions for a device are operating conditions under which it can be guaranteed that the device
will operate as specified. If the device is used under operating conditions other than the operating conditions (supply
voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus, when designing
products which include this device, ensure that the operating conditions for the device are always adhered to.
25.2.1 MCU mode (Flash Programming or erasing)
(VSS = 0 V, Topr = −10 to 40°C)
Pins
Condition
VDD
NORMAL1, 2 modes
VIH1
MODE pin
VIH2
Hysteresis input
VIL1
MODE pin
VIL2
Hysteresis input
fc
XIN, XOUT
fcgck
5.5
5.5
4.5
4.5
10
[V]
0.250
[V]
[MHz]
Gear clock(fcgck) frequency range
5.5
VDD
V
0
VDD × 0.25
1.0
10.0
0.25
10.0
MHz
[MHz]
High-frequency clock(fc) frequency range
Figure 25-1 Clock gear (fcgck) and High-frequency clock (fc)
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Unit
VDD × 0.30
VDD ≥ 4.5 V
Clock frequency
4.5
VDD × 0.75
VDD ≥ 4.5 V
Input low level
Max
VDD × 0.70
VDD ≥ 4.5 V
Input high level
Min
10
Supply voltage
Symbol
1
Parameter
TMP89FM46
25.2.2 MCU mode (Except Flash Programming or erasing)
(VSS = 0 V, Topr = −40 to 85°C)
Parameter
Symbol
Pins
Condition
Min
fc = 10.0 MHz
5.5
V
2.2
fcgck = 10.0 MHz
NORMAL1, 2 modes
IDLE0, 1, 2 modes
4.3
fcgck = 4.2 MHz
VDD
Unit
2.7
fc = 8.0 MHz
Supply voltage
Max
2.7
fcgck = 2.0 MHz
fs = 32.768 kHz
SLOW1, 2 modes
SLEEP0, 1 modes
2.2
STOP mode
Input high level
VIH1
MODE pin
VIH2
Hysteresis input
VIL1
MODE pin
VIL2
Hysteresis input
0
VDD = 2.2 to 5.5 V
1.0
8.0
1.0
10.0
2.0
VDD = 2.7 to 5.5 V
fcgck
0.25
VDD = 4.3 to 5.5 V
VDD = 2.2 to 5.5 V
2.2
[MHz]
Gear clock(fcgck) frequency range
10
2.2
8
8.4
2.7
1
2.7
10
4.3
4.2
4.3
2
[V]
5.5
0.250
[V]
5.5
30.0
4
4.2
XTIN, XTOUT
MHz
4.2
10.0
2
fs
VDD × 0.25
VDD = 2.7 to 5.5 V
VDD = 2.2 to 5.5 V
Clock frequency
V
VDD × 0.10
VDD < 4.5 V
XIN, XOUT
VDD
VDD × 0.30
VDD ≥ 4.5 V
VIL3
fc
VDD × 0.75
VDD × 0.90
VDD < 4.5 V
VIH3
Input low level
VDD × 0.70
VDD ≥ 4.5 V
34.0
kHz
[MHz]
High-frequency clock(fc) frequency range
fc, fc/2 or fc/4 can be used as gear clock (fcgck).
Only fc/2 or fc/4 can be used as gear clock (fcgck).
Only fc/4 can be used as gear clock (fcgck).
Figure 25-2 Clock gear (fcgck) and High-frequency clock (fc)
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25. Electrical Characteristics
25.2 Operating Conditions
TMP89FM46
25.2.3 Serial PROM mode
(VSS = 0 V, Topr = −10 to 40°C)
Pins
Condition
VDD
NORMAL1, 2 modes
VIH1
MODE pin
VIH2
Hysteresis input
VIL1
MODE pin
VIL2
Hysteresis input
fc
XIN, XOUT
fcgck
5.5
5.5
4.5
4.5
10
[V]
0.250
[V]
[MHz]
Gear clock(fcgck) frequency range
5.5
VDD
V
0
VDD × 0.25
1.0
10.0
0.25
10.0
MHz
[MHz]
High-frequency clock(fc) frequency range
Figure 25-3 Clock gear (fcgck) and High-frequency clock (fc)
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Unit
VDD × 0.30
VDD ≥ 4.5 V
Clock frequency
4.5
VDD × 0.75
VDD ≥ 4.5 V
Input low voltage
Max
VDD × 0.70
VDD ≥ 4.5 V
Input high voltage
Min
10
Supply voltage
Symbol
1
Parameter
TMP89FM46
25.3 DC Characteristics
(VSS = 0 V, Topr = −40 to 85°C)
Parameter
Hysteresis voltage
Input current
Symbol
Pins
VHS
Hysteresis input
IIN1
MODE
IIN2
P0, P1, P2, P4, P5, P7, P8, P9,
PB
IIN3
RESET, STOP
RIN2
RESET pull-up
Input resistance
Condition
Min
Typ.
Max
Unit
−
0.9
−
V
−
−
±2
µA
100
220
500
30
50
100
VDD = 5.5 V
VIN = VMODE = 5.5 V/0 V
VDD = 5.5 V, VIN = VMODE = 0 V
kΩ
RIN3
P0, P1, P2 (excluding P23 and
P24), P4, P9 pull-up
ILO1
P23, P24 (skin open drain port)
VDD = 5.5 V, VOUT = 5.5 V
−
−
2
ILO2
P0, P1, P2 (excluding P23 and
P24), P4, P5, P7, P8, P9, PB (tristate port)
VDD = 5.5 V, VOUT = 5.5 V/0 V
−
−
±2
Output high voltage
VOH
Except P23, P24, XOUT, XTOUT
VDD = 4.5 V, IOH = −0.7 mA
4.1
−
−
Output low voltage
VOL
Except XOUT, XTOUT
VDD = 4.5 V, IOL = 1.6 mA
−
−
0.4
Output low current
IOL
P70 to P73, PB (Large current
port)
VDD = 4.5 V, VOL = 1.0 V
−
20
−
Output leakage current
Note 1: Typical values show those at Topr = 25°C and VDD = 5.0 V.
Note 2: Input current IIN3 : The current through pull-up resistor is not included.
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µA
V
mA
25. Electrical Characteristics
25.3 DC Characteristics
TMP89FM46
(VSS = 0 V, Topr = −40 to 85°C)
Parameter
Symbol
Pins
Condition
VDD = 5.5 V
Supply current in
NORMAL 1, 2 modes
(Note 7)
VIN = 5.3 V/0.2 V
VMODE=5.3V/0.1V
fcgck = 10.0 MHz
fs = 32.768 kHz
Supply current in
IDLE0, 1, 2 modes
Min
Typ.
Max
When a program
operates on flash
memory
−
14.5
20.0
When a program
operates on RAM
−
9.5
12.5
−
5.5
7.5
Unit
mA
VDD = 5.5 V
Supply current in
NORMAL 1, 2 modes
(Note 7)
Supply current in
IDLE0, 1, 2 modes
VIN = 5.3 V/0.2 V
VMODE=5.3V/0.1V
IDD
fcgck = 8.0 MHz
fs = 32.768 kHz
When a program
operates on flash
memory
−
13
−
When a program
operates on RAM
−
8
−
−
4.5
−
When a program
operates on flash
memory
−
20
39
When a program
operates on RAM
−
11
30
−
10
24
−
9
22
−
10
25
−
10
−
−
2
−
−
26
−
(Note 8)
Supply current in
SLOW1 mode
(Notes 5 and 7)
VDD = 3.0 V
VIN = 2.8 V/0.2 V
VMODE=2.8V/0.1V
Supply current in
SLEEP1 mode
fs = 32.768 kHz
Supply current in
SLEEP0 mode
µA
VDD = 5.5 V
Supply current in
STOP mode
VIN = 5.3 V/0.2 V
VMODE=5.3V/0.1V
VDD = 5.5 V
VIN = 5.3 V/0.2 V
Peak current of intermittent operation
(Notes 7 and 9)
VMODE=5.3V/0.1V
IDDRP-P
VDD = 3.0V
VIN = 2.8 V/0.2 V
When a program
operates on flash
memory or when
data is being read
from flash memory
mA
VMODE=2.8V/0.1V
Current for writing to
flash memory, erasing
and security program
(Notes 4, 8 and 9)
VDD = 5.5 V
IDDEW
VIN = 5.3 V/0.2 V
VMODE=5.3V/0.1V
Note 1: Typical values shown are Topr = 25°C and VDD = 5.0 V, unless otherwise specified.
Note 2: IDD does not include IREF. It is the electrical current in the state in which the peripheral circuitry has been operated.
Note 3: VIN : The input voltage on the pin except MODE pin, VMODE : The input voltage on the MODE pin
Note 4: When performing a write or erase on the flash memory or activating a security program in the flash memory, make sure
that the operating temperature Topr is within the range −10°C to 40°C. If the temperature is outside this range, the resultant performance cannot be guaranteed.
Note 5: In SLOW1 mode, the difference between the peak current and the average current becomes large.
Note 6: Each supply current in SLOW2 mode is equivalent to that in IDLE0, IDLE1 and IDLE2 modes.
Note 7: When a program operates in the flash memory or when data is being read from the flash memory, the flash memory operates intermittently, and a peak current flows, as shown in Figure 25-4. In this case, the supply current IDD (in NORMAL1,
NORMAL2 and SLOW1 modes) is defined as the sum of the average peak current and MCU current.
Note 8: If a write or erase is performed on the flash memory or a security program is enabled in the flash memory, an instantaneous peak current flows, as shown in Figure 25-5.
Note 9: The circuit of a power supply must be designed such as to enable the supply of a peak current. This peak current causes
the supply voltage in the device to fluctuate. Connect a bypass capacitor of about 0.1 µF near the power supply of the
device to stabilize its operation.
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TMP89FM46
1 machine cycle
n
Program counter (PC)
n+1
n+2
n+3
Momentary flash current
I DDP-P
[mA]
Maximum current
Typical current
Sum of average
momentary flash
current and
MCU current
MCU current
Figure 25-4 Intermittent Operation of Flash Memory
1 machine cycle
Program counter (PC)
Internal data bus
Internal write signal
Last write cycle of each of the Byte Program,
Security Program, Chip Erase and Sector Erase
TBD, TSCE
I DDEW
[mA]
Figure 25-5 Current When an Erase or Write is Being Performed on the Flash Memory
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25. Electrical Characteristics
25.4 AD Conversion Characteristics
TMP89FM46
25.4 AD Conversion Characteristics
(VSS = 0.0 V, 4.5 V ≤ VDD ≤ 5.5 V, Topr = −40 to 85°C)
Parameter
Symbol
Analog reference voltage
VAREF
Power supply voltage of analog control
circuit
AVDD
Analog reference voltage range (Note
4)
∆VAREF
Condition
Min
Typ.
Max
AVDD − 1.0
−
AVDD
Unit
VDD
V
Analog input voltage range
Power supply current of analog reference voltage
VAIN
IREF
VDD = AVDD =VAREF = 5.5 V
VSS = AVSS = 0.0 V
Non-linearity error
VDD = AVDD = 5.0 V
Zero point error
VSS = AVSS = 0.0V
Full scale error
VAREF = 5.0V
Total error
3.5
−
−
VSS
−
VAREF
−
0.6
1.0
−
−
±2
−
−
±2
−
−
±2
−
−
±2
mA
LSB
(VSS = 0.0 V, 2.7 V ≤ VDD < 4.5 V, Topr = −40 to 85°C)
Parameter
Symbol
Analog reference voltage
VAREF
Condition
Min
Typ.
Max
AVDD − 1.0
−
AVDD
Power supply voltage of analog control
circuit
AVDD
Analog reference voltage range (Note
4)
∆VAREF
2.5
−
−
Analog input voltage range
VAIN
VSS
−
VAREF
Power supply current of analog reference voltage
IREF
−
0.5
0.8
−
−
±2
−
−
±2
−
−
±2
−
−
±2
Unit
VDD
V
VDD = AVDD = VAREF = 4.5 V
VSS = AVSS = 0.0 V
Non-linearity error
VDD = AVDD = 2.7 V
Zero point error
VSS = AVSS = 0.0V
VAREF = 2.7V
Full scale error
Total error
mA
LSB
(VSS = 0.0 V, 2.2 V ≤ VDD < 2.7 V, Topr = −40 to 85°C)
Parameter
Symbol
Condition
Min
Typ.
Max
Analog reference voltage
VAREF
AVDD − 0.9
−
AVDD
Power supply voltage of analog control
circuit
AVDD
Analog reference voltage range (Note
4)
∆VAREF
2.2
−
−
Analog input voltage range
VAIN
VSS
−
VAREF
Power supply current of analog reference voltage
IREF
−
0.3
0.5
−
−
±4
−
−
±4
−
−
±4
−
−
±4
Unit
VDD
V
VDD = AVDD = VAREF = 2.7 V
VSS = AVSS = 0.0 V
Non-linearity error
Zero point error
Full scale error
VDD = AVDD = 2.2 V
VSS = AVSS = 0.0V
VAREF = 2.2 V
Total error
mA
LSB
Note 1: The total error includes all errors except a quantization error, and is defined as the maximum deviation from the ideal conversion line.
Note 2: Conversion times differ with variation in the power supply voltage.
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TMP89FM46
Note 3: The voltage to be input to the AIN input pin must be within the range VAREF to VSS. If a voltage outside this range is input,
converted values will become indeterminate, and converted values of other channels will be affected.
Note 4: Analog reference voltage range: ∆VAREF = VAREF − VSS
Note 5: If the AD converter is not used, fix the AVDD and VAREF pins to the VDD level.
25.5 Power-on Reset Circuit Characteristics
Power supply voltage (VDD)
Operating voltage
VPROFF
VPRON
tPPW
t VDD
tPROFF
tPRON
Power-on reset signal
Warm-up counter start
Warm-up counter clock
tPWUP
CPU and peripheral circuit
reset signal
Figure 25-6 Power-on Reset Operation Timing
Note: Care must be taken in system designing since the power-on reset circuit may not fulfill its functions due to the fluctuations in the power supply voltage (VDD).
(VSS=0 V, Topr = −40 to 85°C)
Symbol
Parameter
Min.
Typ.
Max.
VPROFF
Power-on reset releasing voltageNote
1.85
2.02
2.19
VPRON
Power-on reset detecting
voltageNote
1.75
1.85
1.95
tPROFF
Power-on reset releasing response time
−
0.01
0.1
tPRON
Power-on reset detecting response time
−
0.01
0.1
tPRW
Power-on reset minimum pulse width
1.0
−
−
Unit
V
tPWUP
tVDD
ms
Warming-up time after a reset is cleared
−
102 x 2 /fc
−
s
Power supply rise time
−
−
5
ms
9
Note 1: Because the power-on reset releasing voltage and the power-on reset detecting voltage change relative to one another,
the detected voltage will never become inverted.
Note 2: A clock output by an oscillating circuit is used as the input clock for a warming-up counter. Because the oscillation frequency does not stabilize until an oscillating circuit stabilizes, some errors may be included in the warming-up time.
Note 3: Boost the power supply voltage such that tVDD becomes smaller that tPWUP.
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25. Electrical Characteristics
25.6 Voltage Detecting Circuit Characteristics
TMP89FM46
25.6 Voltage Detecting Circuit Characteristics
Power supply voltage (VDD)
Operating voltage
Level of detected voltage
tVLTPW
tVLTOFF
tVLTON
Signal to request the voltage
detection interrupt
Voltage detection reset signal
Figure 25-7 Operation Timing of the Voltage Detecting Circuit
Note: Care must be taken in system designing since the power-on reset circuit may not fulfill its functions due to the fluctuations in the power supply voltage (VDD).
(VSS = 0 V, Topr = −40 to 85°C)
Symbol
RA002
Parameter
Min.
Typ.
Max.
tVLTOFF
Voltage detection releasing response time
−
0.01
0.1
tVLTON
Voltage detecting detection response time
−
0.01
0.1
tVLTPW
Voltage detecting minimum pulse width
1.0
−
−
Page 366
Unit
ms
TMP89FM46
25.7 AC Characteristics
25.7.1 MCU mode (Flash programming or erasing)
(VSS = 0 V, VDD = 4.5 V to 5.5 V, Topr = −10 to 40°C)
Parameter
Symbol
Condition
Min
Typ.
Max
0.100
−
4
117.6
−
133.3
For external clock operation (XIN input).
fc = 10.0 MHz
−
50.0
−
ns
For external clock operation (XTIN input)
fs = 32.768 kHz
−
15.26
−
µs
NORMAL1, 2 modes
Machine cycle time
tcy
IDLE0, 1, 2 modes
Unit
µs
SLOW1, 2 modes
SLEEP0, 1 modes
High-level clock pulse width
tWCH
Low-level clock pulse width
tWCL
High-level clock pulse width
tWSH
Low-level clock pulse width
tWSL
25.7.2 MCU mode (Except Flash Programming or erasing)
(VSS = 0 V, VDD = 4.3 V to 5.5 V, Topr = −40 to 85°C)
Parameter
Symbol
Condition
Min
Typ.
Max
0.100
−
4
117.6
−
133.3
For external clock operation (XIN input).
fc = 10.0 MHz
−
50.0
−
ns
For external clock operation (XTIN input)
fs = 32.768 kHz
−
15.26
−
µs
NORMAL1, 2 modes
Machine cycle time
tcy
IDLE0, 1, 2 modes
Unit
µs
SLOW1, 2 modes
SLEEP0, 1 modes
High-level clock pulse width
tWCH
Low-level clock pulse width
tWCL
High-level clock pulse width
tWSH
Low-level clock pulse width
tWSL
(VSS = 0 V, VDD = 2.7 V to 4.3 V, Topr = −40 to 85°C)
Parameter
Symbol
Condition
Min
Typ.
Max
0.238
−
4
NORMAL1, 2 modes
Machine cycle time
tcy
IDLE0, 1, 2 modes
Unit
µs
SLOW1, 2 modes
117.6
−
133.3
For external clock operation (XIN input).
fc = 10.0 MHz
−
50.0
−
ns
For external clock operation (XTIN input)
fs = 32.768 kHz
−
15.26
−
µs
SLEEP0, 1 modes
High-level clock pulse width
tWCH
Low-level clock pulse width
tWCL
High-level clock pulse width
tWSH
Low-level clock pulse width
tWSL
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25. Electrical Characteristics
25.8 Flash Characteristics
TMP89FM46
(VSS = 0 V, VDD = 2.2 V to 2.7 V, Topr = −40 to 85°C)
Parameter
Symbol
Condition
Min
Typ.
Max
0.500
−
4
117.6
−
133.3
For external clock operation (XIN input).
fc = 8.0 MHz
−
62.5
−
ns
For external clock operation (XTIN input)
fs = 32.768 kHz
−
15.26
−
µs
NORMAL1, 2 modes
Machine cycle time
tcy
IDLE0, 1, 2 modes
Unit
µs
SLOW1, 2 modes
SLEEP0, 1 modes
High-level clock pulse width
tWCH
Low-level clock pulse width
tWCL
High-level clock pulse width
tWSH
Low-level clock pulse width
tWSL
25.7.3 Serial PROM mode
(VSS = 0 V, VDD = 4.5 V to 5.5 V, Topr = −10 to 40°C)
Parameter
Symbol
Condition
Min
Typ.
Max
0.100
−
4
117.6
−
133.3
For external clock operation (XIN input).
fc = 10.0 MHz
−
50.0
−
ns
For external clock operation (XTIN input)
fs = 32.768 kHz
−
15.26
−
µs
NORMAL1, 2 modes
Machine cycle time
tcy
IDLE0, 1, 2 modes
Unit
µs
SLOW1, 2 modes
SLEEP0, 1 modes
High-level clock pulse width
tWCH
Low-level clock pulse width
tWCL
High-level clock pulse width
tWSH
Low-level clock pulse width
tWSL
25.8 Flash Characteristics
25.8.1 Write characteristics
(VSS = 0 V, Topr = −10 to 40°C)
Condition
Min
Typ.
Max
Number of guaranteed writes to
flash memory
Parameter
Symbol
−
−
100
Times
Flash memory write time
−
−
40
µs
Chip erase
−
−
30
Sector erase
−
−
30
Flash memory erase time
RA002
Page 368
ms
TMP89FM46
25.9 Recommended Oscillating Condition- 1
XIN
C1
XOUT
XTIN
C2
C1
(1) High-frequency oscillation
XTOUT
C2
(2) Low-frequency oscillation
Note 1: To ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. Because these factors are
greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be
mounted.
Note 2: The product numbers and specifications of the resonators supplied by Murata Manufacturing Co., Ltd. are subject to
change.
For up to date information, please refer to the following
http://www.murata.com
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25. Electrical Characteristics
25.10 Handling Precaution
TMP89FM46
25.10Handling Precaution
- The solderability test conditions for lead-free products (indicated by the suffix G in product name) are shown
below.
1. When using the Sn-37Pb solder bath
Solder bath temperature = 230°C
Dipping time = 5 seconds
Number of times = once
R-type flux used
2. When using the Sn-3.0Ag-0.5Cu solder bath
Solder bath temperature = 245°C
Dipping time = 5 seconds
Number of times = once
R-type flux used
Note: The pass criteron of the above test is as follows: Solderability rate until forming ≥ 95%
- When using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we
recommend electrically shielding the package in order to maintain normal operating condition.
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TMP89FM46
25.11Revision History
Rev
RA002
RA002
Description
"25.5 Power-on Reset Circuit Characteristics" Revised table (IPWUP Unit) from "ms" to "s".
Page 371
25. Electrical Characteristics
25.11 Revision History
RA002
TMP89FM46
Page 372
TMP89FM46
26. Package Dimensions
LQFP48-P-0707-0.50D Rev 01
Unit: mm
RA000
Page 373
26. Package Dimensions
TMP89FM46
RA000
Page 374
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