MOTOROLA MC74HCT74AD Dual d flip-flop with set and reset with lsttl compatible input Datasheet

 SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
14
1
The MC74HCT74A is identical in pinout to the LS74. This device may be
used as a level converter for interfacing TTL or NMOS outputs to High Speed
CMOS inputs.
This device consists of two D flip–flops with individual Set, Reset, and
Clock inputs. Information at a D–input is transferred to the corresponding Q
output on the next positive going edge of the clock input. Both Q and Q
outputs are available from each flip–flop. The Set and Reset inputs are
asynchronous.
1
ORDERING INFORMATION
MC54HCTXXAJ
MC74HCTXXAN
MC74HCTXXAD
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 136 FETs or 34 Equivalent Gates
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
5
1
14
VCC
DATA 1
2
13
RESET 2
CLOCK 1
3
12
DATA 2
SET 1
4
11
CLOCK 2
Q1
5
10
SET 2
Q1
6
9
Q2
3
6
GND
7
8
Q2
Q1
Q1
4
FUNCTION TABLE
13
Inputs
9
12
Q2
L
H
L
H
H
H
H
H
8
11
Outputs
Set Reset Clock Data
Q2
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SET 2
10
PIN 14 = VCC
PIN 7 = GND
Design Criteria
Value
Units
Internal Gate Count*
34
ea.
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
µW
.0075
pJ
Speed Power Product
10/95
1
H
L
L
H
H
H
H
H
X
X
X
L
H
X
X
X
H
L
X
X
X
Q
Q
H
L
L
H
H*
H*
H
L
L
H
No Change
No Change
No Change
* Both outputs will remain high as long as
Set and Reset are low, but the output
states are unpredictable if Set and Reset
go high simultaneously.
* Equivalent to a two–input NAND gate.
 Motorola, Inc. 1995
RESET 1
1
2
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
LOGIC DIAGRAM
RESET 1
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
REV 6
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MC74HCT74A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: –10mW/_C from 65_ to 125_C
SOIC Package: –7mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
Vin = VIH or VIL
|Iout|
4.0 mA
4.5
3.98
3.84
3.7
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout|
4.0 mA
4.5
0.26
0.33
0.4
VOH
VOL
Maximum Low–Level Output
Voltage
V
Maximum Input Leakage Current
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
µA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
5.5
2.0
20
80
µA
∆ICC
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 µA
Iin
5.5
≥ – 55_C
25_C to 125_C
2.9
2.4
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HCT74A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
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Guaranteed Limit
– 55 to
25_C
85_C
125_C
Unit
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
24
30
36
ns
tPLH,
tPHL
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
24
30
36
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
15
19
22
ns
Maximum Input Capacitance
10
10
10
pF
Symbol
fmax
Cin
Parameter
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
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CPD
Power Dissipation Capacitance (Per Enabled Output)*
pF
130
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to
25_C
Symbol
Parameter
Fig.
Min
Max
85_C
Min
Max
125_C
Min
Max
Units
tsu
Minimum Setup Time, Data to Clock
3
15
19
22
ns
th
Minimum Hold Time, Clock to Data
3
3
3
3
ns
Minimum Recovery Time, Set or Reset Inactive to Clock
2
6
8
9
ns
tw
Minimum Pulse Width, Clock
1
15
19
22
ns
tw
Minimum Pulse Width, Set or Reset
2
15
19
22
ns
tr, tf
Maximum Input Rise and Fall Times
1
trec
High–Speed CMOS Logic Data
DL129 — Rev 6
3
500
500
500
ns
MOTOROLA
MC74HCT74A
SWITCHING WAVEFORMS
tw
tr
3V
tf
2.7 V
1.3 V
0.3 V
CLOCK
SET OR
RESET
3V
1.3 V
GND
tPHL
GND
Q OR Q
tw
1.3 V
1/fmax
tPLH
Q OR Q
tPLH
tPHL
1.3 V
Q OR Q
trec
90%
1.3 V
10%
3V
1.3 V
CLOCK
tTLH
tTHL
GND
Figure 1.
Figure 2.
VALID
TEST POINT
3V
DATA
1.3 V
OUTPUT
GND
tsu
DEVICE
UNDER
TEST
th
3V
1.3 V
CL*
GND
CLOCK
* Includes all probe and jig capacitance
Figure 3.
Figure 4.
EXPANDED LOGIC DIAGRAM
SET
4, 10
2, 12
5, 9
Q
DATA
3, 11
CLOCK
6, 8
Q
1, 13
RESET
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HCT74A
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
14
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
8
B
1
7
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
J
N
H
G
D
SEATING
PLANE
K
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
–A–
14
1
P 7 PL
0.25 (0.010)
7
G
D
0.25 (0.010)
M
T
F
J
M
K
14 PL
B
S
M
R X 45°
C
SEATING
PLANE
B
M
A
S
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
8
–B–
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.75
8.55
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.228 0.244
0.010 0.019
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INTERNET: http://Design–NET.com
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
High–Speed CMOS Logic Data
DL129 — Rev 6
◊
CODELINE
5
*MC74HCT74A/D*
MC74HCT74A/D
MOTOROLA
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