FPD750 Datasheet v3.0 0.5W POWER PHEMT FEATURES: • • • • • LAYOUT: 27.5 dBm Linear Output Power at 12 GHz 11.5 dB Power Gain at 12 GHz 14.5 dB Max Stable Gain at 12 GHz 38 dBm Output IP3 50% Power-Added Efficiency GENERAL DESCRIPTION: The FPD750 is an AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (PHEMT), featuring a 0.25 µm by 750 µm Schottky barrier gate, defined by highresolution stepper-based photolithography. The double recessed gate structure minimizes parasitics to optimize performance. The epitaxial structure and processing have been optimized for reliable high-power applications. The FPD750 also features Si3N4 passivation and is available in the low cost plastic SOT89 SOT343 and DFN packages. TYPICAL APPLICATIONS: • • • • Narrowband and broadband highperformance amplifiers SATCOM uplink transmitters PCS/Cellular low-voltage high-efficiency output amplifiers Medium-haul digital radio transmitters ELECTRICAL SPECIFICATIONS1: PARAMETER SYMBOL CONDITIONS MIN TYP Power at 1dB Gain Compression P1dB VDS = 8 V; IDS = 50% IDSS 26.5 27.5 dBm Maximum Stable Gain (S21/S12) MSG VDS = 8 V; IDS = 50% IDSS 13.5 14.5 dB Power Gain at P1dB G1dB VDS = 8 V; IDS = 50% IDSS 10.5 11.5 dB Power-Added Efficiency PAE VDS = 8 V; IDS = 50% IDSS; POUT = P1dB 45 % VDS = 8V; IDS = 50% IDSS 38 Matched for optimal power; Tuned for best IP3 40 Output Third-Order Intercept Point MAX UNITS IP3 (from 15 to 5 dB below P1dB) 185 230 dBm Saturated Drain-Source Current IDSS VDS = 1.3 V; VGS = 0 V 280 mA Maximum Drain-Source Current IMAX VDS = 1.3 V; VGS ≅ +1 V 370 mA Transconductance GM VDS = 1.3 V; VGS = 0 V 200 mS Gate-Source Leakage Current IGSO VGS = -5 V 10 µA Pinch-Off Voltage |VP| VDS = 1.3 V; IDS = 0.75 mA 1.0 V Gate-Source Breakdown Voltage |VBDGS| IGS = 0.75 mA 12.0 14.0 V Gate-Drain Breakdown Voltage |VBDGD| IGD = 0.75 mA 14.5 16.0 V Thermal Resistivity (see Notes) θJC VDS > 6V 65 °C/W Note: 1TAmbient = 22°C; RF specifications measured at f = 12 GHz using CW signal 1 Tel: +44 (0) 1325 301111 Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: [email protected] Website: www.filtronic.com FPD750 Datasheet v3.0 1 ABSOLUTE MAXIMUM RATING : PARAMETER SYMBOL TEST CONDITIONS ABSOLUTE MAXIMUM 6 Drain-Source Voltage VDS -3V < VGS < -0.5V 10V Gate-Source Voltage VGS 0V < VDS < +8V -3V Drain-Source Current IDS For VDS < 2V IDss Gate Current IG Forward or reverse current 7.5mA RF Input Power PIN Under any acceptable bias state 22dBm Channel Operating Temperature TCH Under any acceptable bias state 175°C Storage Temperature TSTG Non-Operating Storage -65°C to 150°C PTOT See De-Rating Note below 2.3W 2 or more Max. Limits 80% Total Power Dissipation 4 Simultaneous Combination of Limits Notes: 1 TAmbient = 22°C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause permanent damage to the device 2 Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power 3 Total Power Dissipation to be de-rated as follows above 22°C: PTOT= 2.3 - (0.015W/°C) x THS where THS= heatsink or ambient temperature above 22°C Example: For a 85°C carrier temperature: PTOT = 2.3 - (0.015 x (85 – 22)) = 1.4W 4 Users should avoid exceeding 80% of 2 or more Limits simultaneously 5 Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib. 6 Operating at absolute maximum VD continuously is not recommended. If operation at 10V is considered then IDS must be reduced in order to keep the part within it's thermal power dissipation limits. Therefore VGS is restricted to < -0.5V. PAD LAYOUT: A B PAD DESCRIPTION PIN COORDINATES (µm) A Gate Pad 130, 170 B Drain Pad 380, 170 C Source Pad Note: Co-ordinates are referenced from the bottom left hand corner of the die to the centre of bond pad opening C DIE SIZE (µm) DIE THICKNESS (µm) MIN. BOND PAD OPENING (µm x µm ) 470 x 340 75 70 x 80 2 Tel: +44 (0) 1325 301111 Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: [email protected] Website: www.filtronic.com FPD750 Datasheet v3.0 PREFERRED ASSEMBLY INSTRUCTIONS: GaAs devices are fragile and should be handled with great care. Specially designed collets should be used where possible. PART NUMBER DESCRIPTION FPD750 Die The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage temperature should be 280-290°C; maximum time at temperature is one minute. The recommended wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm) gold wire. Stage temperature should be 250-260°C. HANDLING PRECAUTIONS: To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 0 (0-250 V) as defined in JEDEC Standard No. 22-A114. Further information on ESD control measures can be found in MIL-STD-1686 and MILHDBK-263. APPLICATION NOTES & DESIGN DATA: Application Notes and design data including Sparameters, noise parameters and device model are available on request. DISCLAIMERS: This product is not designed for use in any space based or life sustaining/supporting equipment. ORDERING INFORMATION: 3 Tel: +44 (0) 1325 301111 Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: [email protected] Website: www.filtronic.com