TI CD74HC7266E High speed cmos logic quad 2-input exclusive nor gate Datasheet

[ /Title
(CD74H
C7266)
/Subject
(High
Speed
CMOS
Logic
Quad 2Input
EXCLUSIVE
CD74HC7266
Data sheet acquired from Harris Semiconductor
SCHS219
High Speed CMOS Logic
Quad 2-Input EXCLUSIVE NOR Gate
August 1997
Features
Description
• Four Independent EXCLUSIVE NOR Gates
The Harris CD74HC7266 contains four independent
Exclusive NOR gates in one package. They provide the
system designer with a means for implementation of the
EXCLUSIVE NOR function.
• Buffered Inputs and Outputs
• Logical Comparators
• Parity Generators and Checkers
This device is functionally the same as the TTL226. They
differ in that the HC7266 has active high and low outputs
whereas the 226 has open collector outputs.
• Adders/Subtracters
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
• Wide Operating Temperature Range . . . -55oC to 125oC
TEMP. RANGE (oC)
PKG.
NO.
• Balanced Propagation Delay and Transition Times
PART NUMBER
• Significant Power Reduction Compared to LSTTL
Logic ICs
CD74HC7266E
-55 to 125
14 Ld PDIP
E14.3
CD74HC7266M
-55 to 125
14 Ld SOIC
M14.15
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
PACKAGE
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
Pinout
CD74HC7266
(PDIP, SOIC)
TOP VIEW
1A 1
14 VCC
1B 2
13 4B
1Y 3
12 4A
2Y 4
11 4Y
2A 5
10 3Y
2B 6
9 3B
GND 7
8 3A
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number
1780.1
CD74HC7266
Functional Diagram
1A
1B
2A
2B
3A
3B
4A
4B
1
2
3
5
6
4
8
10
1Y
2Y
3Y
9
12
11
13
4Y
GND = 7
VCC = 14
TRUTH TABLE
INPUTS
OUTPUT
nA
nB
nY
L
L
H
L
H
L
H
L
L
H
H
H
NOTE: H = High Voltage Level, L = Low Voltage Level
Logic Symbol
nA
nY
nB
2
CD74HC7266
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
VIH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
VIL
VOH
-
VIH or VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
VOL
VIH or VIL
-
3
CD74HC7266
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
2
-
20
-
40
µA
Input Leakage
Current
Quiescent Device
Current (Note)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
NOTE:
4. For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
Switching Specifications
Input tr, tf = 6ns
25oC
PARAMETER
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
-40oC TO 85oC -55oC TO 125oC
VCC (V)
TYP
MAX
MAX
MAX
UNITS
2
-
115
145
150
ns
4.5
-
23
29
35
ns
6
-
30
25
30
ns
HC TYPES
Propagation Delay
Propagation Delay Time, Any
Input
tPLH, tPHL
CL = 15pF
5
9
-
-
-
ns
Output Transition Times
(Figure 1)
tTLH, tTHL
CL = 50pF
2
-
75
95
110
ns
4.5
-
15
19
22
ns
6
-
13
16
19
ns
-
-
10
10
10
pF
5
33
-
-
-
pF
Input Capacitance
CIN
Power Dissipation
Capacitance
CPD
CL = 15pF
NOTE:
5. CPD is used to determine the dynamic power consumption per gate, PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output
Load Capacitance, VCC = Supply Voltage.
Test Circuit and Waveform
tr = 6ns
tf = 6ns
VCC
90%
50%
10%
INPUT
GND
tTHL
tTLH
90%
50%
10%
INVERTING
OUTPUT
tPLH
tPHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
4
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