IDT IDT23S08T-1DC 2.5v zero delay clock multiplier, spread spectrum compatible Datasheet

IDT23S08T
2.5V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL TEMPERATURE RANGE
2.5V ZERO DELAY CLOCK
MULTIPLIER, SPREAD
SPECTRUM COMPATIBLE
FEATURES:
IDT23S08T
ADVANCE
INFORMATION
DESCRIPTION:
• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs
to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1/2x, 1x, 2x, 4x output options (see table):
– IDT23S08T-1 1x
– IDT23S08T-2 1x, 2x
– IDT23S08T-3 2x, 4x
– IDT23S08T-4 2x
– IDT23S08T-5 1/2x
• No external RC network required
• Operates at 2.5V VDD
• Spread spectrum compatible
• Available in SOIC package
The IDT23S08T is a high-speed phase-lock loop (PLL) clock multiplier. It
is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT23S08T has two banks of four outputs each that are controlled via
two select addresses. By proper selection of input addresses, both banks can
be put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT23S08T enters power down. In this mode, the device will
draw less than 12µA, and the outputs are tri-stated.
The IDT23S08T is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT23S08T is characterized for Commercial operation.
FUNCTIONAL BLOCK DIAGRAM
(-3, -4)
FBK
16
2
2
CLKA1
PLL
1
REF
2
3
(-5)
CLKA2
14
CLKA3
15
CLKA4
S2
S1
8
9
Control
Logic
(-2, -3)
2
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
NOVEMBER 2003
1
c
2003
Integrated Device Technology, Inc.
DSC - 6510/4
IDT23S08T
2.5V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Supply Voltage Range
–0.5 to +4.6
V
Input Voltage Range (REF)
–0.5 to +5.5
V
VI
Input Voltage Range
–0.5 to
V
IIK (VI < 0)
Input Clamp Current
–50
mA
IO
Continuous Output Current
±50
mA
VDD or GND
Continuous Current
±100
mA
TA = 55°C
Maximum Power Dissipation
0.7
W
–65 to +150
°C
0 to +70
°C
16
FBK
CLKA1
2
15
CLKA4
CLKA2
3
14
CLKA3
VDD
4
13
VDD
GND
5
12
GND
CLKB1
6
11
CLKB4
CLKB3
TSTG
Storage Temperature Range
S1
Operating
Commercial Temperature
Temperature
Range
7
10
S2
8
9
(except REF)
Pin Number
(in still air)(3)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
Functional Description
1
Input Reference Clock, 3.3V Tolerant Input
CLKA1(2)
2
Clock Output for Bank A
CLKA2
3
Clock Output for Bank A
4
2.5V Supply
(2)
VDD
GND
5
Ground
(2)
6
Clock Output for Bank B
CLKB2(2)
7
Clock Output for Bank B
S2(3)
8
Select Input, Bit 2
CLKB1
S1(3)
9
Select Input, Bit 1
CLKB3
(2)
10
Clock Output for Bank B
CLKB4
(2)
11
Clock Output for Bank B
GND
12
Ground
VDD
13
2.5V Supply
CLKA3(2)
14
Clock Output for Bank A
CLKA4(2)
15
Clock Output for Bank A
FBK
16
PLL Feedback Input
VDD+0.5
(VO = 0 to VDD)
PIN DESCRIPTION
(1)
Unit
VI (2)
1
CLKB2
Max.
VDD
REF
SOIC
TOP VIEW
REF
Rating
APPLICATIONS:
•
•
•
•
•
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
2
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
IDT23S08T
2.5V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLE(1) SELECT INPUT DECODING
S2
S1
CLK A
CLK B
Output Source
PLL Shut Down
L
L
Tri-State
Tri-State
PLL
Y
L
H
Driven
Tri-State
PLL
N
H
L
Driven
Driven
REF
Y
H
H
Driven
Driven
PLL
N
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
AVAILABLE OPTIONS FOR IDT23S08T
Device
Feedback From
Bank A Frequency
Bank B Frequency
IDT23S08T-1
Bank A or Bank B
Reference
Reference
IDT23S08T-2(1)
Bank A
Reference
Reference/2
IDT23S08T-2(1)
Bank B
2 x Reference
Reference
IDT23S08T-3(1)
Bank A
2 x Reference
Reference or Reference(2)
IDT23S08T-3(1)
Bank B
4 x Reference
2 x Reference
(1)
IDT23S08T-4
Bank A or Bank B
2 x Reference
2 x Reference
IDT23S08T-5(1)
Bank A or Bank B
Reference/2
Reference/2
NOTES:
1. Contact factory for availability.
2. Output phase is indeterminant (0° or 180° from input clock).
SPREAD SPECTRUM COMPATIBLE
Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter
off the Spread Spectrum feature of the reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature
through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.
ZERO DELAY AND SKEW CONTROL
To close the feedback loop of the IDT23S08T, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin
will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust
the input-output delay.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are
loaded equally, for zero output-output skew.
OPERATING CONDITIONS
Symbol
Parameter
Min.
Max.
Unit
2.3
2.7
V
Operating Temperature (Ambient Temperature)
0
70
°C
CL
Load Capacitance from 10MHz to 133MHz
—
15
pF
CIN
Input Capacitance(1)
—
7
pF
VDD
Supply Voltage
TA
Test Conditions
NOTE:
1. Applies to both REF and FBK.
3
IDT23S08T
2.5V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VIL
Input LOW Voltage Level
VIH
Input HIGH Voltage Level
IIL
Input LOW Current
Conditions
VIN = 0V
Min.
Typ.(1)
Max.
Unit
—
—
0.7
V
1.7
—
—
V
—
—
50
µA
IIH
Input HIGH Current
VIN = VDD
—
—
100
µA
VOL
Output LOW Voltage
IOL = 8mA
—
—
0.3
V
VOH
Output HIGH Voltage
IOH = -8mA
2
—
—
V
IDD_PD
Power Down Current
REF = 0MHz (S2 = S1 = H)
µA
IDD
Supply Current
—
—
12
100MHz CLKA
—
—
45
Unloaded Outputs
66MHz CLKA
—
—
32
Select Inputs at VDD or GND
33MHz CLKA
—
—
18
mA
SWITCHING CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Output Frequency
15pF Load
10
—
133.3
MHz
Duty Cycle = t2 ÷ t1
Measured at VDD/2, FOUT = 66.66MHz, 15pF Load
40
50
60
%
t3
Rise Time
Measured between 0.7V and 1.7V, 15pF Load
—
—
2.5
ns
t4
Fall Time
Measured between 0.7V and 1.7V, 15pF Load
—
—
2.5
ns
t5
Output to Output Skew on same Bank
All outputs equally loaded
—
—
200
ps
Output Bank A to Output Bank B (-1, -4, -5)
All outputs equally loaded
—
—
200
ps
Output Bank A to Output Bank B Skew (-2, -3)
All outputs equally loaded
—
—
400
ps
t6
Delay, REF Rising Edge to FBK Rising Edge
Measured at VDD/2
—
0
±350
ps
t7
Device to Device Skew
Measured at VDD/2 on the FBK pins of devices
—
0
700
ps
tJ
Cycle to Cycle Jitter (-1, -4, -5)
Measured at 66.67 MHz, loaded outputs, 15pF Load
—
—
200
ps
Measured at 133.3 MHz, loaded outputs, 15pF Load
—
—
200
Cycle to Cycle Jitter (-2, -3)
Measured at 66.67 MHz, loaded outputs, 15pF Load
—
—
400
ps
PLL Lock Time
Stable Power Supply, valid clocks presented
—
—
1
ms
t1
(-1, -2, -3, -4, -5)
tJ
tLOCK
on REF and FBK pins
4
IDT23S08T
2.5V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL TEMPERATURE RANGE
SWITCHING WAVEFORMS
t1
t2
VDD/2
VDD/2
VDD/2
Duty Cycle Timing
Output
0.7V
2.5V
0.7V
1.7V 1.7V
0V
t4
t3
All Outputs Rise/Fall Time
VDD/2
VDD/2
Input
Output
VDD/2
Output
VDD/2
FBK
t6
t5
Input to Output Propagation Delay
Output to Output Skew
VDD/2
TEST CIRCUIT
FBK, Device 1
VDD/2
FBK, Device 2
VDD
t7
0.1µF
CLKOUT
OUTPUTS
Device to Device Skew
CLOAD
VDD
0.1µF
GND
GND
Test Circuit for all Parameters
5
IDT23S08T
2.5V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX
Device Type
XX
Package
X
Process
Ordering Code
Blank
Commercial (0oC to +70oC)
DC
Small Outline
23S08T-1
23S08T-2
23S08T-3
23S08T-4
23S08T-5
2.5V Zero Delay Clock Buffer, Spread
Spectrum Compatible
Package Type
Operating Range
IDT23S08T-1DC
16-Pin SOIC
Commercial
IDT23S08T-2DC(1)
16-Pin SOIC
Commercial
IDT23S08T-3DC(1)
16-Pin SOIC
Commercial
IDT23S08T-4DC(1)
16-Pin SOIC
Commercial
IDT23S08T-5DC
16-Pin SOIC
Commercial
(1)
NOTE:
1. Contact factory for availability.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
6
for Tech Support:
[email protected]
(408) 654-6459
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