Linear LS5912C Improved low noise wideband monolithic dual n-channel jfet amplifier Datasheet

LS5911 LS5912 LS5912C
IMPROVED LOW NOISE WIDEBAND
MONOLITHIC DUAL N-CHANNEL
JFET AMPLIFIER
FEATURES
Improved Replacement for SILICONIX, FAIRCHILD, &
NATIONAL: 2N5911 & 2N5912
LOW NOISE (10kHz)
en ~ 4nV/√Hz
HIGH TRANSCONDUCTANCE (100MHz)
SOT-23
TOP VIEW
SOT-23
TOP VIEW
G1
D1
S1
gfs ≥ 4000µS
ABSOLUTE MAXIMUM RATINGS1
1
6
2
5
3
4
S2
D2
G2
@ 25 °C (unless otherwise stated)
TOP VIEW
Maximum Temperatures
Storage Temperature
Operating Junction Temperature
PDIP-B
PDIP-A
-55 to +150 °C
S1
1
8
G2
S1
1
8
NC
-55 to +150 °C
D1
2
7
SS
D1
2
7
G2
SS
3
6
D2
G1
3
6
D2
G1
4
5
S2
NC
4
5
S2
S1
1
8
G2
S1
1
8
NC
D1
2
7
SS
D1
2
7
G2
SS
3
6
D2
G1
3
6
D2
G1
4
5
S2
NC
4
5
S2
Maximum Power Dissipation
Continuous Power Dissipation (Total)4
500mW
SOIC-A
Maximum Currents
Gate Current
50mA
Maximum Voltages
Gate to Drain
-25V
Gate to Source
-25V
SOIC-B
MATCHING ELECTRICAL CHARACTERISTICS @25 °C (unless otherwise stated)
SYMBOL
CHARACTERISTIC
VGS1  VGS2
Differential Gate to Source
Cutoff Voltage
Differential Gate to Source
Voltage Change with
Temperature
Saturation Drain Current
Ratio
Δ VGS1  VGS2
ΔT
IDSS1
IDSS2
IG1  IG2
gfs 1
gfs 2
CMRR
TYP
LS5911
MIN
MAX
0.95
Differential Gate Current
MIN
0.95
85
MAX
LS5912C
MIN
MAX
UNIT
CONDITIONS
10
15
40
mV
VDG = 10V, ID = 5mA
20
40
40
µV/°C
VDG = 10V, ID = 5mA
TA = -55 to +125°C
1
0.95
20
Forward Transconductance
Ratio
Common Mode Rejection
Ratio
LS5912
1
1
0.95
20
0.95
1
1
20
0.95
nA
VDS = 10V, VGS = 0V
Notes 2, 3
VDG = 10V, ID = 5mA
TA = +125°C
VDS = 10V, ID = 5mA
f = 1kHz3
1
dB
VDG = 5V to 10V
ID = 5mA
STATIC ELECTRICAL CHARACTERISTICS @25 °C (unless otherwise stated)
LS5911
LS5912
LS5912C
SYM.
CHARACTERISTIC
TYP
UNIT CONDITIONS
MIN MAX MIN MAX MIN MAX
BVGSS Gate to Source Breakdown
-25
-25
-25
IG = -1µA, VDS = 0V
VGS(off) Voltage
Gate to Source Cutoff Voltage
-1
-5
-1
-5
-1
-5
VDS = 10V, ID = 1nA
V
VGS(F)
Gate to Source Forward Voltage
0.7
IG = 1mA, VDS = 0V
VGS
Gate to Source Voltage
-0.3
-4
-0.3
-4
-0.3
-4
VDG = 10V, IG = 5mA
Drain to Source Saturation
IDSS
7
40
7
40
7
40
mA
VDS = 10V, VGS = 0V
2
Current
IGSS
Gate Leakage Current
-1
-50
-50
-50
VGS = -15V, VDS = 0V
pA
IG
Gate Operating Current
-1
-50
-50
-50
VDG = 10V, ID = 5mA
IG1G2 Gate to Gate Isolation Current
±1
±1
±1
uA VG1-VG2=±25VID = IS = 0
Linear Integrated Systems
•
4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Doc 201132 11/18/15 Rev#A8 ECN# LS5911 LS5912 LS5912C
DYNAMIC ELECTRICAL CHARACTERISTICS @25 °C (unless otherwise stated)
SYM.
CHARACTERISTIC
TYP
f = 1kHz
Forward
Transconductance
gfs
f = 100MHz
gos
Output Conductance
LS5911
MIN
Ciss
Input Capacitance
Crss
Reverse Transfer Capacitance
NF
Noise Figure
en
Equivalent Input
Noise Voltage
MIN
MAX
LS5912C
MIN
MAX
UNIT
7000
100
100
100
µS
VDG = 10V, ID = 5mA
pF
VDG = 10V, ID = 5mA
f = 1MHz
120
5
5
5
1.2
1.2
1.2
1
1
1
f = 100Hz
7
20
20
20
f = 10kHz
4
10
10
10
VDG = 10V, ID = 5mA
f = 10kHz, RG = 100KΩ
VDG = 10V, ID = 5mA
nV/√Hz
f = 100Hz
VDG = 10V, ID = 5mA
nV/√Hz
f = 10kHz
dB
PDIP
SOT-23
0.060
0.95
6
1
1.90
2
5
3
4
0.35
0.50
8
2
7
3
6
4
5
0.100
0.250
0.145
0.170
0.09
0.20
0.00
0.15
1
0.375
0.038
2.80
3.00
1.50
1.75
2.60
3.00
0.90
1.30
CONDITIONS
4000 10000 4000 10000 4000 10000
f = 1kHz
f = 100MHz
MAX
LS5912
0.295
0.320
DIMENSIONS IN
INCHES
SOIC
0.10
0.60
0.014
0.018
DIMENSIONS IN
MILLIMETERS
PDIP-B
PDIP-A
S1
1
8
G2
S1
1
8
NC
D1
2
7
SS
D1
2
7
G2
SS
3
6
D2
G1
3
6
D2
G1
4
5
S2
NC
4
5
S2
SOIC-A
SOIC-B
S1
1
8
G2
S1
1
8
NC
D1
2
7
SS
D1
2
7
G2
SS
3
6
D2
G1
3
6
D2
G1
4
5
S2
NC
4
5
S2
Linear Integrated Systems
•
0.021
1
8
2
7
3
6
4
5
0.150
0.157
0.0075
0.0098
0.050
0.189
0.196
0.0040
0.0098
0.2284
0.2440
DIMENSIONS IN
INCHES
Please contact the factory
regarding the availability of
optional packages.
4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Doc 201132 11/18/15 Rev#A8 ECN# LS5911 LS5912 LS5912C
NOTES
1.
Absolute maximum ratings are limiting values above which serviceability may be impaired.
2.
Pulse Test: PW ≤ 300µs Duty Cycle ≤ 3%
3.
Assumes smaller value in numerator.
4.
Derate 4mW/°C above 25°C.
Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its
use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Linear Integrated Systems.
Linear Integrated Systems (LIS) is a 25-year-old, third-generation precision semiconductor company providing high-quality
discrete components. Expertise brought to LIS is based on processes and products developed at Amelco, Union Carbide, Intersil
and Micro Power Systems by company President John H. Hall. Hall, a protégé of Silicon Valley legend Dr. Jean Hoerni, was the
director of IC Development at Union Carbide, Co-Founder and Vice President of R&D at Intersil, and Founder/President of Micro
Power Systems.
Linear Integrated Systems
•
4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Doc 201132 11/18/15 Rev#A8 ECN# LS5911 LS5912 LS5912C
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