Intersil ICM7218AIJIR5254 8-digit led microprocessor-compatible multiplexed display decoder driver Datasheet

ICM7218
®
Data Sheet
February 15, 2007
8-Digit LED Microprocessor-Compatible
Multiplexed Display Decoder Driver
Features
• Microprocessor Compatible
The ICM7218 series of universal LED driver systems
provide, in a single package, all the circuitry necessary to
interface most common microprocessors or digital systems
to an LED display. Included on chip are an 8-byte static
display memory, two types of 7-segment decoders, multiplex
scan circuitry, and high current digit and segment drivers for
either common-cathode or common-anode displays.
• Total Circuit Integration On Chip Includes:
- Digit and Segment Drivers
- All Multiplex Scan Circuitry
- 8-Byte Static Display Memory
- 7-Segment Hexadecimal and Code B Decoders
• Output Drive Suitable for LED Displays Directly
The lCM7218A and 1CM7218B feature two control lines
(WRITE and MODE) which write either 4 bits of control
information (DATA COMING, SHUTDOWN, DECODE, and
HEXA/CODE B) or 8 bits of display input data. Display data
is automatically sequenced into the 8-byte internal memory
on successive positive going WRITE pulses. Data may be
displayed either directly or decoded in Hexadecimal or Code
B formats.
• Common Anode and Common Cathode Versions
• Single 5V Supply Required
• Data Retention to 2V Supply
• Shutdown Feature - Turns Off Display and Puts Chip Into
Low Power Dissipation Mode
• Sequential and Random Access Versions
• Decimal Point Drive On Each Digit
The ICM7218C and lCM7218D feature two control lines
(WRITE and HEXA/CODE B/SHUTDOWN), 4 separate
display data input lines, and 3 digit address lines. Display
data is written into the internal memory by setting up a digit
address and strobing the WRITE line low. Only Hexadecimal
and Code B formats are available for display outputs.
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
ICM7218C COMMON ANODE
ICM7218D COMMON CATHODE
ICM7218A COMMON ANODE
ICM7218B COMMON CATHODE
ID0-ID7
INPUT
DATA
8
8
ID4-ID7 MODE
CONTROL
INPUTS
WRITE
1
4
FN3159.2
HEXADECIMAL/
CODE B/
SHUTDOWN
1
1
ID0-ID3
ID7
DATA
INPUT
5
DA0-DA2
DIGIT
ADDRESS
WRITE
1
3
DECODE
1
THREE LEVEL
INPUT LOGIC
1
1
8
4
HEXADECIMAL/ 7
CODE B
DECODER
WRITE
ADDRESS
DECODER
8
8-BYTE
STATIC
RAM
1
READ
ADRESS, DIGIT
MULTIPLEXER
8
8
READ
ADRESS
MULTIPLEXER
4
3
5
HEXADECIMAL/
CODE B
DECODER
MULTIPLEX
OSCILLATOR
7
1
MULTIPLEX
OSCILLATOR
1
DECODE/
NO-DECODE
8
7
7
SHUTDOWN
1
WRITE ADDRESS
COUNTER
8
7
1
1
8
8-BYTE
STATIC
RAM
SHUTDOWN
CONTROL
LOGIC
HEXA/CODE B
DECIMAL
POINT
8-SEGMENT
DRIVERS
1
8
8-DIGIT
DRIVERS
DECIMAL
POINT
INTERDIGIT
BLANKING
8-SEGMENT
DRIVERS
1
INTERDIGIT
BLANKING
8-DIGIT
DRIVERS
FIGURE 1. FUNCTIONAL DIAGRAMS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2001, 2007. All Rights Reserved
ICM7218
Ordering Information
PART NUMBER
PART MARKING
DISPLAY TYPE
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
ICM7218AIJI
ICM7218AIJI
Common Anode
-40 to +85
28 Ld CERDIP
F28.6
ICM7218AIJIR5254 (Note)
ICM7218AIJI R5254
Common Anode
-40 to +85
28 Ld CERDIP (Note)
F28.6
ICM7218BIJI
ICM7218BIJI
Common Cathode
-40 to +85
28 Ld CERDIP
F28.6
ICM7218BIJIR5254 (Note)
ICM7218BIJI R5254
Common Cathode
-40 to +85
28 Ld CERDIP (Note)
F28.6
ICM7218CIJI
ICM7218CIJI
Common Anode
-40 to +85
28 Ld CERDIP
F28.6
ICM7218CIJIR5254 (Note)
ICM7218CIJI R5254
Common Anode
-40 to +85
28 Ld CERDIP (Note)
F28.6
ICM7218DIJI
ICM7218DIJI
Common Cathode
-40 to +85
28 Ld CERDIP
F28.6
ICM7218DIJIR5254 (Note)
ICM7218DIJI R5254
Common Cathode
-40 to +85
28 Ld CERDIP (Note)
F28.6
NOTE: Intersil Pb-free hermetic packaged products employ SnAgCu or Au termination finish, which are RoHS compliant termination finishes and
compatible with both SnPb and Pb-free soldering operations. Ceramic dual in-line packaged products (CerDIPs) do contain lead (Pb) in the seal
glass and die attach glass materials. However, lead in the glass materials of electronic components are currently exempted per the RoHS directive.
Therefore, ceramic dual inline packages with Pb-free termination finish are considered to be RoHS compliant.
Pinouts
ICM7218A (28 LD CERDIP)
TOP VIEW
ICM7218B (28 LD CERDIP)
TOP VIEW
Seg c 1
28 VSS
DIGIT 4 1
28 VSS
Seg e 2
27 Seg a
DIGIT 6 2
27 DIGIT 7
Seg b 3
26 Seg g
DIGIT 3 3
26 DIGIT 5
D.P. 4
25 Seg d
DIGIT 1 4
25 DIGIT 2
ID6 (HEXA/CODEB) 5
24 Seg f
ID6 (HEXA/CODEB) 5
24 DIGIT 8
ID5 (DECODE) 6
23 DIGIT 3
ID5 (DECODE) 6
23 Seg g
ID 7 (DATA COMING) 7
22 DIGIT 6
ID 7 (DATA COMING) 7
22 Seg f
WRITE 8
21 DIGIT 7
WRITE 8
21 Seg e
MODE 9
20 DIGIT 4
MODE 9
20 Seg c
19 VDD
ID4 (SHUTDOWN) 10
ID4 (SHUTDOWN) 10
19 VDD
ID1 11
18 DIGIT 8
ID1 11
18 Seg d
ID0 12
17 DIGIT 5
ID0 12
17 Seg b
ID2 13
16 DIGIT 2
ID2 13
16 Seg a
ID3 14
15 DIGIT 1
ID3 14
15 D.P.
ICM7218A (28 LD CERDIP)
TOP VIEW
ICM7218B (28 LD CERDIP)
TOP VIEW
Seg c 1
28 VSS
DIGIT 4 1
28 VSS
Seg e 2
27 Seg a
DIGIT 6 2
27 DIGIT 7
Seg b 3
26 Seg g
DIGIT 3 3
26 DIGIT 5
D.P. 4
25 Seg d
DIGIT 1 4
25 DIGIT 2
DA0 (DIGIT ADDRESS 0) 5
24 Seg f
DA0 (DIGIT ADDRESS 0) 5
24 DIGIT 8
DA1 (DIGIT ADDRESS 1) 6
23 DIGIT 3
DA1 (DIGIT ADDRESS 1) 6
23 Seg g
ID 7 (INPUT D.P.) 7
22 DIGIT 6
ID 7 (INPUT D.P.) 7
22 Seg f
WRITE 8
21 DIGIT 7
WRITE 8
21 Seg e
HEXA/CODE B/SHUTDOWN 9
20 DIGIT 4
HEXA/CODE B/SHUTDOWN 9
20 Seg c
19 VDD
DA2 (DIGIT ADDRESS 2) 10
DA2 (DIGIT ADDRESS 2) 10
19 VDD
ID1 11
18 DIGIT 8
ID1 11
18 Seg d
ID0 12
17 DIGIT 5
ID0 12
17 Seg b
ID2 13
16 DIGIT 2
ID2 13
16 Seg a
15 DIGIT 1
ID3 14
15 D.P.
ID3 14
2
FN3159.2
February 15, 2007
ICM7218
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD to VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
Digit Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA
Segment Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Input Voltage (Any Terminal)(Note 1). . . . VSS -0.3V to VDD + 0.3V
Thermal Resistance (Typical, Note 2)
θJA (°C/W)
θJC (°C/W)
CERDIP Package. . . . . . . . . . . . . . . . .
55
14
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. Due to the SCR structure inherent in the CM0S process used to fabricate these devices, connecting any terminal to a voltage greater than VDD
or less than VSS may cause destructive device latchup. For this reason it is recommended that no inputs from sources operating on a different
power supply be applied to the device before its own supply is established, and when using multiple supply systems the supply to the ICM7218
should be turned on first.
2. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
VDD = 5V, VSS = 0V, TA = +25°C, Display Diode Drop = 1.7V
PARAMETER
SYMBOL
Supply Voltage Range
VSUPPLY
Quiescent Supply Current
IQ
Operating Supply Current - Outputs Open
Circuit
IDD
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating
4
-
6
V
Power Down Mode
2
-
6
V
Shutdown (Note 3)
6
10
300
μA
Common Anode SEGS On (Note 6)
-
-
2.5
mA
Common Anode SEGS Off (Note 6)
-
-
500
μA
Common Cathode SEGS On (Note 6)
-
-
700
μA
-
-
500
μA
Digit Drive Current
IDIG
Common Anode VOUT = VDD -2.0V
140
200
-
mA
Common Cathode VOUT = VSS +1.0V
50
100
-
mA
Digit Leakage Current - Shutdown Mode
IDLK
Common Anode VOUT = 2V
-
-
100
μA
-
-
100
μA
Peak Segment Drive Current
ISEG
Common Anode VOUT = VSS +1.0V
20
40
-
mA
Common Anode VOUT = VDD -2.0V
-10
-20
-
mA
Segment Leakage Current - Shutdown
Mode
ISLK
Common Anode VOUT = VDD
-
-
100
μA
Common Cathode VOUT = VSS
-
-
100
μA
Display Scan Rate
fMUX
Per Digit
-
250
-
Hz
Common Cathode SEGS Off (Note 6)
Common Cathode VOUT = 5V
Three Level Input (Pin 9 ICM7218C/D)
Logical “1” Input Voltage
VIH
Hexadecimal
4.5
-
-
V
Floating Input
VIF
Code B
2.0
-
3.0
V
VIL
Shutdown
-
-
0.4
V
Three Level Input Impedance
ZIN
Note 3
-
100
-
kΩ
Logical “0” Input Voltage
Logical “1” Input Voltage
VIH
3.5
-
-
V
Logical “0” Input Voltage
VIL
-
-
0.8
V
Wrtie Pulse Width (Low)
tWL
7218A, 7218B
550
400
-
ns
7218C, 7218D
400
250
-
ns
Mode Hold Time
tMH
7218A, 7218B
150
-
-
ns
Mode Setup Time
tMS
7218A, 7218B
500
-
-
ns
Data Setup Time
tDS
Data Hold Time
tDH
Digital Address Setup Time
tAS
3
500
-
-
ns
7218A, 7218B
50
-
-
ns
7218C, 7218D
125
-
-
ns
7218C, 7218D
500
-
-
ns
FN3159.2
February 15, 2007
ICM7218
Electrical Specifications
VDD = 5V, VSS = 0V, TA = +25°C, Display Diode Drop = 1.7V (Continued)
PARAMETER
SYMBOL
Digital Address Hold Time
tAH
Data Input Impedance
ZIN
TEST CONDITIONS
MIN
TYP
MAX
UNITS
0
-
-
ns
-
1010
-
Ω
7218C, 7218D
5-10pF Gate Capacitance
Pin Descriptions
INPUT
TERMINAL
LOGIC LEVEL
FUNCTION
WRITE
8
High
Input Not Loaded
Low
Input Loaded
MODE
9
High
Load Control Bits on Write Pulse
Low
Load Input Data on Write Pulse
10
High
Normal Operation
Low
Shutdown (Oscillator, Decoder and Display Disabled)
ID5 (DECODE)
6
High
No Decode
Low
Decode
ID6 (HEXA/CODE B)
5
High
Hexadecimal Decoding
Low
Code B Decoding
ID7 (DATA COMING)
7
High
Data Coming
No Data Coming
ICM7218A AND ICM7218B
ID4 (SHUTDOWN)
MODE High
Low
ID0-ID7
MODE Low
11, 12, 13, 14, 5, 6, 10, 7
} Control Word
Display Data Inputs (Notes 4, 5)
ICM7218C AND ICM7218D
WRITE
HEXA/CODE B/ SHUTDOWN
8
High
Low
Input Loaded into Memory
9 (Note 3)
High
Hexadecimal Decoding
Floating
Low
DA0 - DA2
ID0 - ID3
ID7 (INPUT D.P.)
Input Not Loaded into Memory
Code B Decoding
Shutdown (Oscillator, Decoder and Display Disabled)
10, 6, 5
Digit Address Inputs
14, 13, 11, 12
Display Data Inputs
7
Decimal Point Input
NOTES:
3. In the ICM7218C and D (random access versions) the HEXA/CODE B/SHUTDOWN input (Pin 9) has internal biasing resistors to hold it at VDD/2
when Pin 9 is open-circuited. These resistors consume power and result in a quiescent supply current (IQ) of typically 50μΑ. The ICM7218A,
and B devices do not have these biasing resistors and thus are not subject to this condition.
4. ID0-ID3 = Don’t Care when writing control data.
ID4-ID6 = Don’t Care when writing Hex/Code B data.
ID7 = Decimal Point data.
(The display blanks on ICM7218A/B versions when writing in data).
5. In the No Decode format, “Ones” represents “on” segments for all inputs except for the Decimal Point, where “Zero” represents an “on” segment
(i.e., segments are positive true, decimal point is negative true).
6. Common Anode segment drivers and Common Cathode Digit Drivers have 20kΩ pullup resistors.
4
FN3159.2
February 15, 2007
ICM7218
FIGURE 2. MULTIPLEX TIMING (COMMON CATHODE VERSION)
sign (-), a blank (for leading zero blanking), certain useful
alpha characters and all numeric formats.
The four bit binary code is set up on inputs lD3-lD0, and
decimal point data is set up on ID7.
FIGURE 3. SEGMENT ASSIGNMENTS
Detailed Description
DECODE Operation
For the lCM7218A/B products, there are 3 input data formats
possible; either direct segment and decimal point information (8
bits per digit) or two Binary formats plus decimal point
information (Hexadecimal/Code B formats with 5 bits per digit).
DECIMAL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
15
HEXA
CODE
0 1 2 3 4 5 6 7 8 9 A
B C D E
F
CODE B
0 1 2 3 4 5 6 7 8 9
E H
-
L
P (BLANK)
SHUTDOWN
The 7-segment decoder on chip is disabled when direct
segment information is to be written. In this format, the
inputs directly control the outputs as follows:
SHUTDOWN performs several functions: it puts the device
into a very low dissipation mode (typically 10μA at VDD = 5V),
turns off both the digit and segment drivers, and stops the
multiplex scan oscillator (this is the only way the scan
oscillator can be disabled). However, it is still possible to input
data to the memory during shutdown - only the display output
sections of the device are disabled in this mode.
Input Data:
ID7
lD6
Powerdown
Output Segments:
D.P.
a
ID5 lD4 lD3 lD2 lD1 ID0
b
c
e
g
f
d
Here, "Ones" represent "on" segments for all inputs except
the Decimal Point. For the Decimal Point "zero" represents
an "on" segment.
HEXAdecimal/CODE B Decoding
For all products, a choice of either HEXA or Code B decoding
may be made. HEXA decoding provides 7-segment numeric
plus six alpha characters while Code B provides a negative
5
In the Shutdown Mode, the supply voltage may be reduced to
2V without data in memory being lost. However, data should
not be written into memory if the supply voltage is less than 4V.
Output Drive
The common anode output drive is approximately 200mA per
digit at a 12% duty cycle. With segment peak drive current of
40mA typically, this results in 5mA average drive. The common
cathode drive capability is approximately one-half that of the
common anode drive. If high impedance LED displays are
used, the drive current will be correspondingly less.
FN3159.2
February 15, 2007
ICM7218
Inter Digit Blanking
A blanking time of approximately 10μs occurs between digit
strobes. This ensures that the segment information is correct
before the next digit drive, thereby avoiding display ghosting.
Driving Larger Displays
If a higher average drive current per digit is required, it is
possible to connect digit drive outputs together. For example,
by paralleling pairs of digit drivers together to drive a 4 digit
display, 5mA average segment drive current can be obtained.
Power Dissipation Considerations
Assuming common anode drive at VDD = 5V and all digits on
with an average of 5 segments driven per digit, the average
current would be approximately 200mA. Assuming a 1.8V
drop across the LED display, there will be a 3.2V drop across
the ICM7218. The device power dissipation will therefore be
640mW, rising to about 900mW, for all ‘8’ ‘s displayed.
Caution: Position device in system such that air can
flow freely to provide maximum cooling. The common
cathode dissipation is approximately one-half that of the
common anode dissipation.
Sequential Addressing Considerations
(lCM7218A/B)
lines and are - DECODE/no Decode, type of Decode (if
desired), SHUTDOWN/no Shutdown and DATA COMlNG/not
Coming. After the control word has been written (with the Data
Coming instruction), display data can be written into memory
with each successive negative going WRITE pulse. After all
8-digit memory locations have been written to, additional
transitions of the WRITE input are ignored until a new control
word is written. It is not possible to change one individual digit
without refreshing the data for all the other digits.
Random Access Input Drive Considerations
(ICM7218C/D)
Control instructions are provided to the ICM7218C/D by a
single three level input terminal (Pin 9), which operates
independently of the WRITE pulse.
Data can be written into memory on the lCM7218C/D by
setting up a 3 bit binary code (one of eight) on the digit
address inputs and applying a low level to the WRITE pin.
For example, it is possible to change only digit 7 without
altering the data for the other digits. (See Figure 6).
Supply Capacitor
A 0.1μF plus a 47μF capacitor is recommended between
VDD and VSS to bypass display multiplexed noise.
The control instructions are read from the input bus lines if
MODE is high and WRITE low. The instructions occur on 4
FIGURE 4. TIMING DIAGRAM FOR ICM7218A/B
FIGURE 5. LOAD SEQUENCE ICM7218A/B
6
FN3159.2
February 15, 2007
ICM7218
2
FIGURE 6. TIMING DIAGRAM FOR ICM7218C/D
FIGURE 7. COMMON ANODE DISPLAY FUNCTIONAL TEST CIRCUIT
7
FN3159.2
February 15, 2007
ICM7218
FIGURE 8. COMMON CATHODE DISPLAY FUNCTIONAL TEST CIRCUIT
Typical Performance Characteristics
8
FN3159.2
February 15, 2007
ICM7218
FIGURE 9. 8-DIGIT MICROPROCESSOR DISPLAY
Application Examples
8-Digit Microprocessor Display Application
Figure 9 shows a display interface using the lCM7218A/B
with an 8048 family microcontroller. The 8 bit data bus
(DB0/DB7-lD0/ID7) transfers control and data information to
the 7218 display interface on successive WRITE pulses. The
MODE input to the 7218 is connected to one of the I/O port
pins on the microcontroller, When MODE is high a control
word is transferred; when MODE is low data is transtered.
Sequential locations in the 8-byte static memory are
automatically loaded on each successive WRITE pulse.
After eight WRITE pulses have occurred, further pulses are
ignored until a new control word is transferred (See
Figure 5). This also allows writing to other peripheral devices
without disturbing the lCM7218A/B.
The display digits from both lCM7218s are interleaved to
allow adjacent pairs of digits to be loaded simultaneously
from a single 8 bit data bus.
Decimal point information is supplied to the ICM7218s from
the processor on port lines P26 and P27.
No Decode Application
The lCM7218 can also be used as a microprocessor based
LED status panel driver. The microprocessor selected
control word must include "No Decode" and "Data Coming".
The processor writes "Ones" and "Zeroes" into the lCM7218
which in turn directly drives appropriate discrete LEDs. LED
indicators can be red or green (8 segments x 8 digits = 64
dots/2 per red or green = 32 channels).
16-Digit Microprocessor Display
In this application (see Figure 10), both lCM7218s are
addressed simultaneously with a 3 bit word, DA2-DA0.
Display data from the 8048 I/O bus (DB7-D80) is transferred
to both lCM7218s simultaneously.
9
FN3159.2
February 15, 2007
ICM7218
FIGURE 10. 16-DIGIT DISPLAY
10
FN3159.2
February 15, 2007
ICM7218
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)
28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.232
-
5.92
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
1.490
-
37.85
5
E
0.500
0.610
15.49
5
eA
e
ccc M
C A-B S
eA/2
c
aaa M C A - B S D S
D S
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MILLIMETERS
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
12.70
0.100 BSC
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
-
eA/2
0.300 BSC
7.62 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
28
28
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN3159.2
February 15, 2007
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