HD66137T High-Voltage Durable 240-Channel Common Driver for Dot-Matrix STN LCD ADE-207-291(Z) Rev. 2 Aug. 03, 1999 Description The HD 66137T is a 240-channel common driver which drives a dot matrix STN LCD panel. By changing the mode, this can be applied to 240- and 200- and 160- channel output. Through the use of a 43-V highvoltage CMOS process technology, a high-voltage drive of +21.5 V and –21.5 V, centering on VM is possible. –21.5V generated from +21.5 V with built-in switching circuit and external capacity. Low logicdrive voltage (3 V) is used. This device is used together with the segment driver HD66130, HD66134ST or HD66136. Features • • • • • • • • Display duty: Up to 1/240 LCD drive voltage: 43 V max Built-in switching circuit (to generate –21.5 V) Number of LCD drive circuit: 240 Operating voltage: 2.5 to 5.5 V Intermediate voltage I/F Built-in alternating signal generation circuit Pin programmable Output mode change: 240-output mode 200-output mode 160-output mode • Built-in display-off function • Flex TCP 1 VLCDL VHL VML VLL VEEL VEO C1 C2 DIO2 M RESET MWS4 MWS3 MWS2 MWS1 MWS0 VCC MODE1 MODE0 DOC DISPOFF AMP SHL GND CL CCL M/S DIO1 VEER VLR VMR VHR VLCDR 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 2 236 237 238 239 240 1 2 3 4 5 X236 X237 X238 X239 X240 X1 X2 X3 X4 X5 HD66137T Pin Arrangement Top view Note: The shape above does not indicate the actual outline. HD66137T Block Diagram X1—X240 *2, *3 VHL VLL VML VHR VLR VMR LCD drive circuit *1, *3 VLCDL,R VEEL,R Level shifter DISPOFF Logic Shift register D Q SR SR 221 240 Qφ φD M/S MWS 0 to MWS 4 DOC Alternating signal generating circuit RESET Logic M VEO CCL AMP C2 C1 DIO1 DIO2 SHL MODE0 MODE1 Switch circuit CL Logic Shift register D Q SR SR 201 220 Qφ φ D Logic Logic Shift register D Q SR SR 41 200 Qφ φD Logic Shift register D Q SR SR 21 40 Qφ φD Logic Shift register D Q SR SR 1 20 Qφ φ D VCC GND Logic Level shifter *1 VLCDL and VLCDR, and VEEL and VEER are internally connected. *2 VHL and VHR, VLL and VLR, and VML and VMR are internally connected. 3 HD66137T Internal Block Diagram 1. LCD drive Circuit This circuit selects and outputs the three level signals for the LCD drive. By a combination of the data in the shift register and M, either VH, VL, or VM is selected and transmitted to the output circuit. 2. Level shifter This boosts a 5-V signal to a high-voltage signal for LCD drive. 3. Shift register This is a 240-bit bidirectional shift register circuit. The first line marker signal output from the DIO1 pin and DIO2 pin is sequentially shifted by shift clock CL. The shift direction is determined by the SHL pin. 4. Alternating signal generating circuit This circuit generates an alternating signal (M signal) for LCD display. To suppress cross-talk, the signal is alternated in a unit from several lines to several tens of lines. By connecting MWS0 to MWS4 pins to VCC or GND, the desired number of signals can be alternated. When alternating signals are externally input, all pins (MWS0 to MWS4) are connected to GND. HIFAS Family timing Comparison HD66130/131S/134S/135/136 Input signal Output signal 4 CL1 M Segment Common HD66132/133 HD66137T Pin Function Classification Symbol Connected Pin No. to Power supply VLCDL, R VEEL, R VCC, GND Control signal I/O Functions 273, 241 Power 269, 245 supply 257 250 — VLCDL, R–VEEL, R : Power supply for LCD drive VLCDL, R : Power supply for switch circuit VCC–GND : Power supply for logic circuit VHL, R VLL, R VML, R 272, 242 Power 270, 244 supply 271, 243 Input Power supply for LCD drive level VEO 268 output C1, C2 267, 266 Capacitance — External capacitance should be connected here when using the switch circuit for generate VEE. If built-in switching circuit is not used, don't connect any lines to this pin. CL 249 MPU Input Shift clock input. Data is shifted at the falling edge of shift clock CL of the shift register. M 264 Extension driver or MPU I/O Inputs or outputs the alternating current for LCD drive output. MWS0 MWS1 MWS2 MWS3 MWS4 258 259 260 261 262 — Input This pin specifies the cycle of the alternating signal (M signal) in the unit of the number of lines. The number of lines, which is an integer from 2 to 31, is specified as follows. Usually, specify the number of lines within a range from 10 to 31. When the HD66131T is driven by an external alternating signal, specify the number of lines as zero. VEEL, R VHL, R : Selected level (Set to the same voltage as VLCDL, R.) VLL, R : Selected level (Set to the same voltage as VEEL, R.) VML, R : Non-selected level and Power supply for switch circuit When use built -in switching circuit and generate VEE, VEO pin connect to VEEL, R pins. VM voltage is point of reference and reversed and output the voltage input to the voltage between VLCD and VM. If built-in switching circuit is not used, don't connect any lines to this pin. Number MWS4 MWS3 MWS2 MWS1 MWS0 of lines 0 0 0 0 0 0 0 1 0 0 0 1 0 2 0 0 1 0 0 3 0 0 1 1 • • • • • • • • • • • • 1 31 1 1 1 1 Line alternating M-pin status waveform —— Input Prohibited Output 2 lines alternated 3 lines alternated • • 31 lines alternated 5 HD66137T Pin Functions (cont) Classification Symbol Connected Pin No. to Control signal MODE0 MODE1 256 256 — I/O Function Input Switch terminals for the number of LCD drive output pins. MODE0 MODE1 Shift direction "H" "H" 240 - output (X1, X2, X3......X238, X239, X240) "H" "L" 200 - output (X21, X22, X23......X218, X219, X220) "L" "H" 160 - output (X41, X42, X43......X198, X199, X200) "L" "L" Prohibited DIO1 DIO2 246 265 Extension driver or MPU I/O CCL 248 MPU Input Built-in switching circuit clock input. When use built-in switching circuit and generate VEE, this pin connect CL pin. If built-in switching circuit is not used, CCL must be fixed to GND AMP 252 — Input Built-in swiching circuit on-off control. When use built-in switching circuit, this pin must be fixed to VCC. If built-in switching circuit is not used, this pin must be fixed to GND RESET 263 MPU or VCC Input Setting this pin to GND sets initializes the alternating signal (M signal) circuit. A VCC level RESET is normally used. DISPOFF 253 MPU Input Setting this pin to GND sets LCD drive output X1 to X240 to the VM level. M/S — Input Controls the display-off function, and displayoff signal output from DOC pin. 247 Serial data input output pin SHL "H" level "L" level DIO1 serial output pin seiral input pin DIO2 serial input pin seiral output pin "H" level When DISPOFF is Low level, X1-240 set VM level "L" level Until serial data input 16 times X1-X240 set VM level DOC 254 — Output "H" level When DISPOFF is Low level, output low level When DISPOFF is High level, output High level "L" level Until serial data input 16 times output low level from DOC pin DISPOFF DIO1,2 1 2 3 4 5 141516 DOC When using M/S is low level, DOC pin should be connect to SEG LSI Dispoff control pin. 6 HD66137T Pin Functions (cont) Classification Symbol Connected Pin No. to I/O Function Control signal SHL 251 Input This pin switches shift directions. — SHL "H" level "L" level MODE0 MODE1 "H" "H" "L" "H" "L" "H" "H" "H" "L" "H" "L" "H" Shift direction Right shift DIO2→SR1········SR240→DIO1 DIO2→SR21········SR220→DIO1 DIO2→SR41········SR200→DIO1 Left shift DIO1→SR240········SR1→DIO2 DIO1→SR220········SR21→DIO2 DIO1→SR200········SR41→DIO2 SR1, SR2•••SR240 correspond to X1, X2•••X240. Note: The 40 or 80 pins invalidated at the 200-output or 160-output mode output the non-selected level synchronized every time; release these pins. LCD drive output X1 to X240 1 to 240 LCD Output LCD drive output By a combination of the display data and the M signal, when DISPOFF is set to VCC, either VH, VL, or VM is selected and transmitted to the output circuit. M D Output level 0 1 1 0 1 0 VL VM VH VM Note: Configuring the LCD panel using the HD66137 when using the select SEGMENT driver. The Select SEGMENT driver SEGMENT driver Select HD66130 (320 OUT) ● HD66132 (240 OUT) × HD66134S (240 OUT) ● HD66136 (400 OUT) ● 7 HD66137T Application Example Application Example (1) Figure 1 shows an application example 640 × 3 (collar) × 240 dot Half VGA Size STN color panel. This panel configured HD66137 × 1 piece and HD66136 × 5 pieces. HD66137 generates M signal and DOC signal. M signal pin is connected M signal pin of HD66136 and DOC signal pin is connected DISP signal pin of HD66136. HD66137 is able to generates - voltage by external capacitor. VEO pin is connected VEE pin and VL pin. CA com1 com2 com3 SHL DIO1 VLCDL,R GND VEEL,R VEO VCC X1~X240 LCD panel 640 × 3 (collar) × 240 1/240duty seg1 seg2 seg3 seg1918 seg1919 seg1920 com238 com239 com240 Y384~Y1 Y384~Y1 SHL SHL EIO1 EIO2 MODE GND VCC HD66136 (No.2) EIO1 EIO2 MODE GND Vcc HD66136 (No.5) EIO1 CC1~4 M CL1 CL2 D0~11 BS DISP VML, R V1SL,R V1L, R V0SL,R V0L, R VCC HD66136 (No.1) Y384~Y1 SHL CC1~4 M CL1 CL2 D0~11 BS DISP VML, R V1SL,R V1L, R V0SL,R V0L, R EIO2 MODE GND CC1~4 M CL1 CL2 D0~11 BS DISP VML, R V1SL,R V1L, R V0SL,R V0L, R CC1~4 revised signal VM generate circuit Power supply circuit VLCD V0 V0S VCC VM V1S V1 GND HD66137 – DIO2 C0+ CL CCL RESET DISPOFF AMP M/S DOC M NWS0~4 VHL, R VML, R VLL, R C1 C2 CL1 CL2 D0~11 DISP FLM MWS0~4 Controller Notes : 1. When designing the board, connect a capacitor near the IC to stabilize power supply. Use two capacitors of about 0.1µF for each IC (between Vcc and GND, V0 and GND, VLCD and GND, and VEE and GND). 2. In addition, for the power supply circuit, connect a capacitor of several µF or several tens of µF between the liquid-crystal power supply and GND. For set evaluation, confirm that there is no inversion of liquid-crystal drive power supply and level power supply in the period between when the liquid-crystal drive power supply is turned on and when it is turned off. 3. When using external capacitor to generate VEE, you must connect a capaciter of several µF or several tens of µF between the VEE and GND. Figure 1 Application Example (1) 8 HD66137T Application Example (2) Figure 2 shows an application example 320 × 3 (collar) × 240 dot Quarter VGA Size STN color panel. This panel configured HD66137 × 1 piece and HD66130 × 3 pieces. HD66137 generates M signal and DOC signal. M signal pin is connected M signal pin of HD66130 and DOC signal pin is connected DISP signal pin of HD66136. HD66137 is able to generates - voltage by external capacitor. VEO pin is connected VEE pin and VL pin. CA com1 com2 com3 SHL DIO1 VLCDL,R GND VEEL,R VEO VCC LCD panel 320 × 3 (collar) × 240 1/240duty seg1 seg2 seg3 com238 com239 com240 seg958 seg959 seg960 X1~X240 Y320~Y1 Y320~Y1 SHL SHL EIO1 SHL EIO1 V1L, R VCC HD66130 (No.3) EIO1 M CL1 CL2 D0~7 BS DISP VML, R EIO2 MODE GND V0L, R V1L, R VCC HD66130 (No.2) Y320~Y1 M CL1 CL2 D0~7 BS DISP VML, R EIO2 MODE GND V0L, R V1L, R VCC HD66130 (No.1) M CL1 CL2 D0~7 BS DISP VML, R EIO2 MODE GND V0L, R V1 GND HD66137 VCC VM Power supply circuit VLCD V0 DIO2 C0+ – CL CCL RESET DISPOFF AMP M/S DOC M NWS0~4 VHL, R VML, R VLL, R C1 C2 CL1 CL2 D0~7 DISP FLM NWS0~4 Controller Notes : 1. When designing the board, connect a capacitor near the IC to stabilize power supply. Use two capacitors of about 0.1µF for each IC (between Vcc and GND, V0 and GND, VLCD and GND, and VEE and GND). 2. In addition, for the power supply circuit, connect a capacitor of several µF or several tens of µF between the liquid-crystal power supply and GND. For set evaluation, confirm that there is no inversion of liquid-crystal drive power supply and level power supply in the period between when the liquid-crystal drive power supply is turned on and when it is turned off. 3. When useing external capacitor to generate VEE, you must connect a capacitor of several µF or several tens of µF between the VEE and GND. Figure 2 Application Example (2) 9 HD66137T Power Supply Circuit Example Figure 3 shows a power supply circuit example. VLCD +21.0V VH DC-DC CONVERTER VCC +3.0~5.0V V0 +2.7~5.5V – + GND COM Driver SEG Driver HD66137 VM V1 GND + – External Capacitor (2.2~4.7 µF) VEO VL VEE C1 C2 + – C0 External Capacitor (2.2~4.7 µF) Figure 3 Power Supply Circuit Example 10 HD66137T Absolute Maximum Rating Item Symbol Ratings Unit Notes Power supply Logic circuit VCC –0.3 to +7.0 V 1, 8 voltage VLCD –0.3 to +25.0 V 1, 3, 8 VEE –20.0 to +0.3 V 1, 4, 8 Input voltage (1) VT1 –0.3 to VCC + 0.3 V 1, 2 Input voltage (2) VH –0.3 to VLCD V 1, 5, 8 Input voltage (3) VL +0.3 to VEE V 1, 6, 8 Input voltage (4) VM –0.3 to + 5.0 V 1, 7, 8 Operating temperature Topr –30 to +75 °C Storage temperature Tstg –55 to +110 °C LCD drive circuit Notes: 1. Voltage from GND. 2. Applicable to DIO1, DISPOFF, SHL, M, NWS0, NWS1, NWS2, NWS3, NWS4, RESET, MODE0, MODE1, CL, M/S, AMP, CCL, DIO2. 3. Applicable to VLCDL, R pins. 4. Applicable to VEEL, R pins. 5. Applicable to VHL, R pins. 6. Applicable to VLL , R pins. 7. Applicable to VML, R pins. (Caution) Operating the LSI in excess of the absolute maximum rating will result in permanent damage. Use the LSI observing electrical characteristic conditions in normal operation. Exceeding the conditions will cause malfunctions or will affect LSI reliability. 8. Observe the sequence of activation and inactivation for the following power supplies and signals. And this sequence apply to use built - in switching circuit. If the sequence is not observed, it may cause LSI malfunction, permanent damage, or adverse effects. 11 HD66137T VCC 2.5V 2.5V 0ms VLCD, VH 0ms 0ms VM VEE,VL 0ms 0ms 0ms DISPOFF 0ms Input signal, clock, or data Undefined Initialization (Longer than one frame) 8.1 Power on (1) Turn on the power supply in the order of GND- V CC, GND-VLCD (VH), and VM. VM-VEE is generated automatically. In this case, input GND to the DISPOFF pin. (2) The LCD level forcibely outputs the VM level by the DISPOFF function. (3) The DISPOFF function has a priority even if input signal distortion occurs immediately after V CC input. (4) Then input the predetermined signals to initialize the driver registers. In this case, assure a period for more than one frame. (5) Preparation for normal display is thus completed. Cancel the DISPOFF function by setting the DISPOFF pin to VCC. At this point, the levels of VEE (VL), VLCD (VH) and VM must have reached the predetermined respective voltage. 8.2 Shut down As a rule, shut down in order opposite to that used for power on. (1) Set the DISPOFF pin to GND. (2) At first shut off the LCD power supply GND-VLCD (VH), at same time GND-VEE (VL) get to VM. Next shut off the VM. (3) Set VCC and the input signal to GND. At this point, VEE (VL), VLCD (VH) and VM pin input must completely drop to 0 V. Since the DISPOFF function is inactivated when the VCC level drops to GND, the LCD output may output a level other than VM. Therefore, an incorrect display may appear at shut down or power on. 12 HD66137T Electrical Characteristics DC Characteristics (VCC = 2.5 to 5.5 V, GND = 0 V, VLCD–VEE = 15 to 43 V, Ta = –30 to +75 °C) Item Symbol Applicable Pins Min. Typ. Max. Unit Measurement Conditions Input high-level VIH voltage DIO1, DISPOFF, SHL, M, M/S, MWS0~4, RESET, 0.7 × VCC — VCC V Input low-level voltage VIL CL, MODE0, MODE1, DOC, AMP, CCL, DIO2 0 — 0.3 × VCC V Output highlevel voltage VOH M, DOC, DIO1, DIO2 VCC – 0.4 — — V I OH = –0.4 mA Output lowlevel voltage VOL M, DOC, DIO1, DIO2 — — 0.4 V I OL = 0.4 mA ON resistance between Vi–Yj RON X1 to X240, V pin — 0.7 2.0 kΩ I ON = 150 µA Input leak current (1) I IL1 DIO1, DISPOFF, SHL, M, M/S, MWS0~4, RESET, CL, MODE0, MODE1, DOC, AMP, CCL, DIO2 –5 — 5 µA VIN = VCC to GND Input leak current (2) I IL2 VH, VL, VM, C1, C2 –25 — 25 µA Current consumption (1) I CC1 VCC — 10 40 µA VCC = 3.3 V, VLCD–VEE = 40 V, f CL = 19.2 kHz, f M = 1.5 kHz Current consumption (2) I CC2 VCC — 20 50 µA VCC = 5.0 V, VLCD–VEE = 40 V, f CL = 19.2 kHz, f M = 1.5 kHz Current consumption (3) I LCD VLCD — 25 50 µA VCC = 3.3 V, VLCD–VEE = 40 V, f CL = 19.2 kHz, f M = 1.5 kHz Notes 1 2 Notes: 1. This is a resistance value between the X and V pins (either of VH, VL, or VM) when a load current is applied to one of x1 to x240 pins. These values are regulated under the conditions of VLCD = VH = 21.75 V, VEE = VL = –18.5 V, VM = 1.75 V, GND = 0 V, Use VH, VL, and VM in the range of VLCD – VM≥VH – VM = 21.5 to 7.5 V, VEE – VM≤VL – VM = –21.5 to –7.5 V, with the relation of VH > VM > VL. 2. The current applied between the input and output is excluded. When an input to a CMOS gate is at an intermediate level, through current flows between the power supplies, and the power supply current increases. Therefore, use VIH = VCC and VIL = GND. 3. The voltage relationship of each signal is as follows : 13 HD66137T Segment waveform Segment voltage Common waveform Common voltage VH (23.0 V) V0 (5.0V) VCC (3.3V) VCC (3.3 V) VM (3.0V) VM (3.0 V) V1 (1.0V) GND (0.0V) GND (0.0 V) VL (–17.0 V) Normal display period Off-display period Normal display period Off-display period AC Characteristics (1) (V CC = 2.5 to 5.5 V, GND = 0 V, VLCD–VEE = 15 to 43 V, Ta = –30 to +75 °C) Item Symbol Pin Name min. max. Clock cycle time t CYC CL 400 — ns CL high-level width t CWH CL 25 — ns CL low-level width t CWL CL 370 — ns CL rising time tr CL — 30 ns CL falling time tf CL — 30 ns Data set-up time t DS DIO1, DIO2, CL 100 — ns Data hold time t DH DIO1, DIO2, CL 10 — ns Data output delay time t DD DIO1, DIO2, CL — 200 ns 1 M output delay time t MD M, CL — 200 ns 1 M set-up time t MS M, CL 20 — ns M Hold time t MH M, CL 20 — ns DOC delay time 1 t DOC1 DISPOFF, DOC — 300 ns 2 DOC delay time 2 t DOC2 DIO1, DIO2, DOC — 300 ns 2 14 Dimensions Note HD66137T AC Characteristics (2) (V CC = 2.5 to 4.5 V, GND = 0 V, VLCD–VEE = 43 V, Ta = –30 to +75 °C) Item Symbol Pin Name min. max. Output delay time1 t pd1 X(n), M — 1.2 Dimensions µs Note 2 AC Characteristics (3) (V CC = 4.5 to 5.5 V, GND = 0 V, VLCD–VEE = 43 V, Ta = –30 to +75 °C) Item Symbol Pin Name min. max. Output delay time1 t pd1 X(n), M — 0.7 Dimensions µs Note 2 *1, *2. The following timing is regulated with the circuit at the right connected. test point *1: 30pF *2: 100pF 15 HD66137T tf tr tCWL tCWH tCYC 0.7 × VCC CL 0.3 × VCC tDS DIO1 DIO2 tDH 0.7 × VCC 0.3 × VCC tDD DIO1 DIO2 VOH VOL tMD VOH M (During output) VOL tpd1 0.7 × VH 0.3 × VH 0.3 × VL X (n) 0.7 × VL 0.7 × VCC CL 0.3 × VCC tMS M (During input) DISPOFF 0.7 × VCC 0.3 × VCC 0.3 × VCC 0.3 × VCC tDOC1 16 0.7 × VCC 0.3 × VCC DIO1 DIO2 (During input) DOC tMH tDOC2 0.7 × VCC 0.3 × VCC HD66137T Terminal Configuration Terminal Configuration (1) VLCD VCC I Input Data I GND VEE Input Terminal 1 Applicable terminals : CL, CCL, SHL, MODE0,1, AMP DISPOFF, RESET, MWS0~4, M/S Input Terminal 2 Applicable terminals : VMR, L * VMR terminal connect with VML terminal in LSI. VLCD I VM Level VLCD VH Level VEE I VL Level VEE Input Terminal 3 Applicable terminals : VHR, L Input Terminal 4 Applicable terminals : VLR, L * VHR terminal connect with VHL terminal in LSI. * VLR terminal connect with VLL terminal in SLI. O Output Terminal 1 Applicable terminals : DOC 17 HD66137T Terminal Configuration (2) VCC Input Data VCC GND Data Output enable GND I/O Terminal 1 Applicable terminals : DIO1, DIO2, M, VLCD VLCD VLCD VLCD I/O VM VLCD I/O VEE VEE VLCD VM I/O Terminal 2 Applicable terminals : C1 VH VLCD VEE VM VLCD VEE VL VEE VEE VEE I/O Terminal 3 Applicable terminals : C2 O VM LCD drive Output Terminal Applicable terminals : X1 to X240 18 VEE VM VM HD66137T Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. 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Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 19