NPC CF8223A Fsk decoder and dtmf receiver ic Datasheet

SM8223A
FSK Decoder and DTMF Receiver IC
NIPPON PRECISION CIRCUITS INC.
OVERVIEW
The SM8223A is a FSK (Frequency shift keying) decoder and DTMF (Dual tone multi-frequency) receiver IC.
It is fabricated using a CMOS process and features a power-down function for low power dissipation operation. The FSK decoder and DTMF receiver have the same performance characteristics as dedicated ICs that
perform the same functions, with the added benefit of an FSK decoder/DTMF receiver auto-select function1
using the telephone tip/ring input signal. It also features a ring (call signal) signal detection circuit, making for
easy construction of low power dissipation, high-performance analog telephone-related applications.
FEATURES
■
■
■
■
■
■
■
■
Both FSK signal caller-ID information services
and DTMF signal caller-ID information services
supported
FSK decoder/DTMF receiver auto-select function
Ring (call signal) signal detection circuit built-in
Serial I/O
Input gain adjustment circuit built-in
Power-down mode
Single supply operation: 3.0V ± 10%
3.579545MHz external crystal oscillator frequency
Molybdenum-gate CMOS process
(Top view)
TIP
1
RING
GS
AGND
RDIN
RDRC
RDET
PDWN
16
SM8223AP
■
PINOUT
VDD
DV
DOUT
FSK/DTMF
IC
OSCIN
OSCOUT
9
8
GND
APPLICATIONS
■
■
■
Telephones, fax machines and modems that support caller-ID information services
Adapters for caller-ID information service functions
Telephones, fax machines and modems that support remote operation functions
ORDERING INFORMATION
PINOUT
(Unit: µm)
RING
TIP
VDD
DV
GS
D e vice
P ackag e
SM8223A
16-pin DIP
CF8223A
Chip
(2810, 3160)
DOUT
AGND
FSK/DTMF
RDIN
IC
RDRC
OSCIN
(0, 0)
RDET
PDWN
GND OSCOUT
P ad size : 90 µm × 90 µm
1. Auto-select function operates if the FSK signal conforms to the Bellcore GR-30-CORE standard.
NIPPON PRECISION CIRCUITS—1
SM8223A
PACKAGE DIMENSIONS
8.13 to 9.40
7.49 to 8.13
6.35
(Unit: mm)
2.54
0.46
0.38 to 1.02
3.68 to 4.32
3.18
3.30
0.25
19.05
1.52
BLOCK DIAGRAM
FSK/DTMF
Differential
Amplifier
FSK Decoder
DV
TIP
Band Pass
Filter
RING
FSK
Decoder
Logic
DOUT
GS
FSK/DTMF
Discriminator
Logic
High Group
Filter
DTMF
Decoder
Logic
Dial Tone
Filter
Low Group
Filter
DTMF Receiver
AGND
Bias
Circuit
VDD GND PDWN
OSC
OSCIN
Ring Detect
OSCOUT
RDIN
RDRC
RDET
NIPPON PRECISION CIRCUITS—2
SM8223A
PIN DESCRIPTION
Number
Name
I/O
P ad dimensions ( µm )
Function
X
Y
1
TIP
I
Tip input. Connected to the telephone line through a protection circuit
1046
2934
2
RING
I
Ring input. Connected to the telephone line through a protection circuit
638
2934
3
GS
O
Input-stage amplifier gain-select output. Used to adjust the gain of the inputstage amplifier.
176
2665
4
AG N D
O
Analog ground output. Internal reference voltage (V D D /2) output level
176
1954
5
RDIN
I
Ring detector input. Used for line reversal and ring signal detection.
Connected for ring detection of attenuated ring signals.
176
1534
6
RDRC
I/O
Ring detector RC terminal. Connected to an RC network which sets the ring
detector delay time.
176
492
7
RDET
O
Ring detector output. R D R C -input Schmitt-trigger buffer output. LOW -level
output when ring signal is detected.
596
226
8
PDW N
I
Pow er-down control input. LOW -level for normal operation. HIGH-level for
pow er-down state. In the pow er-down state, pins AG N D , O S C O U T, D O U T,
and DV are HIGH.
1063
226
9
GND
–
Ground. Connected to the system ground potential.
1634
226
10
OSCOUT
O
Cr ystal oscillator output. The crystal oscillator element is connected between
this pin and OSCIN.
2053
226
11
OSCIN
I
Cr ystal oscillator input. The crystal oscillator element is connected between
this pin and OSCOUT.
2634
506
12
IC
I
Test input. Tied LOW for normal operation.
2634
1550
13
FSK/D T M F
O
FSK/DTMF discr iminator output. HIGH-level output when receiving FSK
signal, and LOW -level output when receiving DTMF signal.
2634
1942
14
DOUT
O
Demodulator output. Demodulated FSK or DTMF signal output. HIGH-level
output in pow er-down state.
2634
2623
15
DV
O
Data trigger output. Data is output on DOUT when this pin goes LOW .
2211
2934
16
VDD
–
Supply
1612
2934
NIPPON PRECISION CIRCUITS—3
SM8223A
SPECIFICATIONS
Absolute Maximum Ratings
GND = 0V
P arameter
Symbol
Rating
Unit
Supply voltage range
VDD
−0.5 to 5.0
V
Input voltage range
V IN
− 0.3 to V D D + 0.3
V
DC input current
IIN
±10
mA
Storage temperature range
T stg
−40 to 125
°C
Recommended Operating Conditions
GND = 0V
Rating
P arameter
Symbol
Condition
Unit
min
typ
max
Supply voltage
VDD
2.7
–
3.3
V
Clock frequency
fC L K
–
3.579545
–
MHz
Clock frequency accuracy
∆f C
−0.1
–
+0.1
%
Operating temperature
Ta
−20
–
85
°C
DC Electrical Characteristics
VDD = 3.0V ± 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = −20 to 85°C unless otherwise noted.
Rating
P arameter
Symbol
Condition
Unit
min
typ
max
Supply current consumption
ID D
P D W N = 0 V, RDIN = 0 V,
R D R C = 0 V, all other inputs
open
–
–
4.5
mA
Pow er-down state current
ID P D
P D W N = V D D , RDIN = 0 V,
R D R C = 0 V, all other inputs
open
–
–
15
µA
P D WN, RDIN, R D R C LOW -level
input voltage
V IL1
–
–
0.3V D D
V
P D WN, RDIN, R D R C HIGH-level
input voltage
V IH1
0.7V D D
–
–
V
O S C I N L OW -level input voltage
V IL2
W h e n external clock input
–
–
0.3V D D
V
OSCIN HIGH-level input voltage
V IH2
W h e n external clock input
0.7V D D
–
–
V
D O U T, DV, R D E T, FSK/D T M F LOW level output current
IO L
2
–
–
mA
D O U T, DV, R D E T, FSK/D T M F HIGHlevel output current
IO H
–
–
−0.8
mA
P D WN, RDIN input leakage current
IIN
−1
–
1
µA
IO F F
–
–
1
µA
R D R C output leakage current
NIPPON PRECISION CIRCUITS—4
SM8223A
AC Electrical Characteristics
FSK decoder
VDD = 3.0V ± 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = −20 to 85°C unless otherwise noted.
Rating
P arameter
Symbol
Condition
Unit
min
typ
max
Detection sensitivity
Typical application circuit
−40
−37.5
0
dBm
Noise reduction ratio
M a r k signal and SPA CE
signal are same level.
Noise: Random noise from
200Hz to 3400Hz.
20
–
–
dB
DTMF receiver
VDD = 3.0V ± 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = −20 to 85°C unless otherwise noted.
Rating
P arameter
Symbol
Condition
Unit
min
typ
max
±1.5% ± 2
–
–
Hz
±3.5
–
–
%
−32.0
–
0.0
dBm
Non-detection sensitivity
–
–
−50.0
dBm
Signal level error
–
–
6
dB
–
18
–
dB
Noise rejection ratio
–
12
–
dB
Dial tone rejection ratio
–
20
–
dB
Detection frequency deviation
Non-detection frequency deviation
Typical application circuit
Detection sensitivity
High-frequency rejection ratio
Typical application circuit 1
1. Input signal is up to V D D level.
Input-stage amplifier Characteristics
VDD = 3.0V ± 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = −20 to 85°C unless otherwise noted.
Rating
P arameter
Symbol
Condition
Unit
min
typ
max
Input leakage current
IIN
–
–
1
µA
Input resistance
R IN
–
1
–
MΩ
AVOL
30
–
–
dB
Unity gain frequency
fC
80
–
–
kHz
Load capacitance
CL
–
–
100
pF
Load resistance
RL
50
–
–
kΩ
DC open-loop voltage gain
NIPPON PRECISION CIRCUITS—5
SM8223A
Timing Characteristics
Oscillator
VDD = 3.0V ± 0.3V, GND = 0V, Ta = −20 to 85°C unless otherwise noted.
Rating
P arameter
Symbol
Condition
Unit
min
typ
max
Clock HIGH-level pulsewidth
tW H
110
–
–
ns
Clock LOW -level pulsewidth
tW L
110
–
–
ns
Clock rise time
tr
–
–
30
ns
Clock fall time
tf
–
–
30
ns
FSK decoder
VDD = 3.0V ± 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = −20 to 85°C unless otherwise noted.
Rating
P arameter
Symbol
Condition
Unit
min
typ
max
Pow er-down release time
tD P D
–
8
–
ms
Oscillator start-up time
tD O S C
–
5
–
ms
M a r k signal to DV ON time
tD E D
–
–
3.75
ms
DV = LOW
FSK flag setup time
tA F
–
–
833
(1/1.2kHz)
µs
FSK flag hold time
tA H
–
–
10
ns
Input to DOUT delay time
tA D D
–
1
5
ms
D O U T r ise time
tDr0
–
–
20
ns
D O U T fall time
tDf0
–
–
20
ns
DOUT data rate
tD W L / H
1188
1200
1212
baud
DTMF receiver
VDD = 3.0V ± 0.3V, GND = 0V, fCLK = 3.579545MHz, Ta = −20 to 85°C unless otherwise noted.
Rating
P arameter
Symbol
Condition
Unit
min
typ
max
D O U T, DV rise time
tDr0
–
–
20
ns
D O U T, DV fall time
tDf0
–
–
20
ns
Signal detection time
tR E
DV
–
–
45
ms
Received signal non-detection time
tR E
DV
20
–
–
ms
P ause detection time
tPA
DV
–
–
25
ms
P ause non-detection time
tP R
DV
20
–
–
ms
DV output data delay time
tB D D
–
–
5
ms
Pow er-down release time
tD P D
–
8
–
ms
Oscillator start-up time
tD O S C
–
5
–
ms
DOUT data rate
tD W L / H
1188
1200
1212
baud
tA F
–
–
833
(1/1.2kHz)
µs
D T M F fl ag setup time
NIPPON PRECISION CIRCUITS—6
SM8223A
OSCIN input timing (when external input)
tWL
tWH
VDD
OSCIN
VSS
tf
tr
FSK receive timing (1)
Ch. seizure Mark Data packet
1st Ring
Tip/Ring
1010101... 111...
2nd Ring
Data
RDET
tDED
DV
tAF
tHF
FSK/DTMF
tADD
DOUT
Data output has
no Ch.seizure signal.
Data
tDPD
PDWN
tDOSC
OSCOUT
FSK receive timing (2)
Start bit
Tip/Ring
b6 b7
1
0
LSB
MSB Stop bit
b0 b1 b2 b3 b4 b5 b6 b7
1
0
b0 b1
tADD
DOUT
b4 b5 b6 b7 1
0
b0 b1 b2 b3 b4 b5 b6 b7 1
0
b0 b1
NIPPON PRECISION CIRCUITS—7
SM8223A
DTMF receive timing (1)
tPR
Tip/Ring
tPA
DTMF Data #1
tRE
#1
DTMF Data #2
tRE
DV
tAF
FSK/DTMF
tBDD
Data #1
DOUT
Data #2
tDPD
PDWN
tDOSC
OSCOUT
DTMF receive timing (2)
DV
tBDD
DOUT
0
Q0
Start bit
Q1
Q2
Q3
DTMF data
S0
S1
S2
Checksum
(2'mod16)
S3
1
Stop bit
(FSK/DTMF) DOUT output timing
tDWL
tDWH
90%
DOUT
tDf0
tDr0
10%
NIPPON PRECISION CIRCUITS—8
SM8223A
FUNCTIONAL DESCRIPTION
Ring Signal Detector
The telephone tip and ring signals pass through a
protection circuit and are input to a resistor, capacitor and diode bridge network, shown in figure 1.
C2
a
R3
b
TIP
D1
R2
R4
RDIN
R1
C2
RING
R3
Db
C1
RDRC
RDET
c
d
Figure 1. Ring signal detector circuit
The diode bridge full-wave rectified output signal
(point a) is reduced in level by a resistor voltage
divider comprising R1 and R2 (point b), and then
input on RDIN. When the ring signal input on RDIN
exceeds the Schmitt buffer trigger voltage (0.7VDD),
the output switches the open-drain RDRC pin. The
signal at RDRC (point c) drives a time-constant cir-
cuit comprised by resistor R4 and capacitor C1 connected to the input of a second Schmitt buffer to
generate the detector signal output on RDET (point
d). Thus, RDET goes LOW when the ring or tip signal exceeds the level set by the resistor voltage
divider.
NIPPON PRECISION CIRCUITS—9
SM8223A
VRIG
VDD
VSS
0.7VDD
0.3VDD
Point a Signal
VRIG
VDD
VSS
0.7VDD
0.3VDD
Point b Signal
VDD
VSS
0.7VDD
0.3VDD
Point c Signal
VDD
VSS
0.7VDD
0.3VDD
Point d Signal
Figure 2. Ring signal detector circuit waveform transitions
The voltage divider level and RC time constant are
given by the following equations, respectively.
R1
0.7V DD = -------------------------------- ⋅ V RIG
R1 + R2 + R3
t
C 1 R 4 = ------------------------------------ V DD 
In  --------------------------
 V DD – V T 
where t is the guard time, and the trigger level satisfies the expression 0.3VDD ≤ VT ≤ 0.7VDD.
NIPPON PRECISION CIRCUITS—10
SM8223A
Input Differential Amplifier
The SM8223A uses an input differential amplifier
for input gain adjustment of the tip/ring signal input
to the FSK detector or DTMF receiver. Differential
input configuration and single-ended input configu-
C1
R1
TIP
C1
R1
RING
R2
R3
R4
ration circuits are shown in figure 3. A bypass capacitor should be connected between GND and AGND
in both circuit configurations.
TIP
C1
R1
RING
R2
GS
AGND
GS
AGND
Differntial Input
Single-Ended Input
C
C
Figure 3. Input circuits
The gain for single-ended configurations is given by
the following equation.
R2
A V = -----R1
and the input impedance is given by the following
equation.
2
1 2
Z i = 2 R 1 +  -----------
 ωC 
1
The gain for differential configurations is given by
the following equation,
R2
R2 R4
A V = ------ where R 3 = ------------------R1
R2 + R4
FSK/DTMF Auto-discriminator
The SM8223A examines the tip/ring input signal and
determines the nature of the signal, FSK or DTMF,
and invokes the corresponding circuits, FSK decoder
or DTMF receiver, respectively. It determines
whether the input signal is an FSK signal or DTMF
signal by the presence or otherwise of the channel
seizure information in the FSK signal header. This
function automatically discriminates between the
input signals if the FSK signal conforms to the
Bellcore GR-30-CORE standard.
NIPPON PRECISION CIRCUITS—11
SM8223A
FSK Demodulator
When an FSK signal is received, the FSK/DTMF
signal discriminator circuit sets the FSK/DTMF pin
HIGH and connects the input signal to the FSK
demodulator circuit. Demodulated data is output on
DOUT with the format shown in figure 4. The FSK
signal conforms to the following Bellcore standard.
Start bit
FSK signal
b6 b7
DOUT
1
0
Table 1. FSK signal
P arameter
Description
Modulation type
Continuous-phase binar y frequency-shiftkeying
Logic “1” data (mark)
1200 ± 12 Hz
Logic “0” data (space)
2200 ± 22 Hz
Signal level (mark)
−32 to −1 2 d B m
Signal level (space)
−36 to −1 2 d B m
Data transfer rate
1200 ± 12 baud
LSB
MSB Stop bit
b0 b1 b2 b3 b4 b5 b6 b7
b4 b5 b6 b7 1
0
1
0
b0 b1
b0 b1 b2 b3 b4 b5 b6 b7 1
0
b0 b1
Figure 4. FSK signal to DOUT output
DTMF Demodulator
When a DTMF signal is received, the FSK/DTMF
signal discriminator circuit sets the FSK/DTMF pin
LOW and connects the input signal to the DTMF
demodulator circuit. The DTMF signal is comprised
by a high-group frequency and a low-group frequency which, in combination, represent a point in
the DTMF matrix.
Table 2. DTMF matrix
L o w gro u p
697Hz
High gro u p
1209Hz
1336Hz
1477Hz
1633Hz
1
2
3
A
770Hz
4
5
6
B
852Hz
7
8
9
C
941Hz
*
0
#
D
The DTMF receiver demodulates the received
DTMF signal and outputs data bits Q0 to Q3 and a 4bit (2-mod-16) checksum S0 to S3 in serial format on
DOUT.
Table 3. DTMF signal output (DOUT)
DTMF
Matrix
input
Checksum
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
S0
S1
S2
S3
1
1
0
0
0
1
1
1
1
2
0
1
0
0
0
1
1
1
3
1
1
0
0
1
0
1
1
4
0
0
1
0
0
0
1
1
5
1
0
1
0
1
1
0
1
6
0
1
1
0
0
1
0
1
7
1
1
1
0
1
0
0
1
8
0
0
0
1
0
0
0
1
9
1
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
*
1
1
0
1
1
0
1
0
#
0
0
1
1
0
0
1
0
A
1
0
1
1
1
1
0
0
B
0
1
1
1
0
1
0
0
C
1
1
1
1
1
0
0
0
D
0
0
0
0
0
0
0
0
NIPPON PRECISION CIRCUITS—12
SM8223A
DTMF signal
DOUT
DTMF DATA
0
Q0
Start bit
Q1
Q2
Q3
DTMF data
(LSB first)
S0
S1
S2
Checksum
(2'mod16)
(LSB first)
S3
1
Stop bit
Figure 5. DTMF signal to DOUT output
The DTMF receiver determines whether the received
data (DTMF signal) is valid after an interval of
tREC ≥ 40ms stable reception. If valid, DV goes
LOW and data is output on DOUT. If DTMF data is
not detected after an interval tSPA ≥ 20ms, a data
pause is activated and the next DTMF signal is in a
wait state (see timing diagrams in AC Electrical
Characteristics). The SM8223A DTMF receiver can
be used as a general-purpose DTMF receiver without
the need for the external time constant circuit, in
which case the resistor/capacitor/diode network can
be omitted.
NIPPON PRECISION CIRCUITS—13
SM8223A
TYPICAL APPLICATION CIRCUIT
D1
C1
R2
R1
C5
VDD
TIP
TIP
D1
RING
DV
R3
R4
VS
R5
D1
C1
R1
R2
D1
AGND
FSK/
DTMF
RDIN
IC
RDRC
OSCIN
D1
R6
D2
RDET OSCOUT
D2
R7
C3
DOUT
C2
RING
C3
GS
D2
D2
R8
R9
PDWN
X'tal
GND
C4
R6
Symbol
Rating
Unit
R1
1
240
kΩ
R2
1
34
kΩ
R3
1
464
kΩ
R4
1
53.6
kΩ
R5
1
60.4
kΩ
D1
1N4003
–
C1
22
nF
C2
0.1
µF
R6
2
430
kΩ
R7
2
270
kΩ
R8
2
27
kΩ
R9
2
270
kΩ
C3
22
nF
2
470
nF
D2
1N4004
–
C5
0.1
µF
VS
–
–
X’tal
3.579545
MHz
C4
1. Refer to the Input Differential Amplifier.
2. Refer to the Ring Signal Detector.
NIPPON PRECISION CIRCUITS—14
SM8223A
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NC9909AE
2000.02
NIPPON PRECISION CIRCUITS—15
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