ICs for TV AN2546FH-A Automotive LCD TV signal processor IC ■ Overview Unit: mm ■ Features • Supply voltage: 3 V/5 V/7.5 V • Built-in a 5-volt power-supply source driver for TFT type LCD • Low consumption power (typ. 200 mW) • Supporting the NTSC, PAL, PAL-M and PAL-N systems • Supporting composite, component and color differential signal input • Video signal, analog RGB (2 systems) One is for OSD (analog/digital). • Each mode setting is possible with I2C Bus control. • Electronic volume (D/A converter) built in • Contrast/Brightness/γ correction circuit built in • Horizontal and vertical display position adjustment are possible by serial control. • Improvement of weak electric field characteristics (Compared to AN2526FH/AN2526NFH: −5 dB) • At reverse stop, built-in output gain down function 12.00±0.20 10.00±0.20 48 33 32 (1.25) 10.00±0.20 12.00±0.20 49 64 17 16 0.50 +0.1 0.18–0.05 +0.10 1 0.15–0.05 1.95±0.20 (1.25) 0.10±0.10 The AN2546FH-A is a video signal processing IC built-in a 5-volt power-supply source driver for TFT color LCD (normally white type), and it supports the NTSC, PAL and PAL-M/PAL-N systems. The main circuitry of this IC includes video-signal processing circuit, color signal processing circuit, interface circuit, synchronizing circuit and many color quality adjusting circuits. This IC converts the composite video signal or separated Y/C signal or RGB signals into RGB signals available for TFT color LCD. Seating plane (1.00) 0° to 10° 0.50±0.20 QFP064-P-1010 Note) The package of this product will be changed to lead-free type (QFP064-P-1010A). See the new package dimensions section later of this datasheet. ■ Applications • 4 inches to 7 inches middle size TFT LCD equipment of normally white, of such as an in-car TV and an LCD monitor for car navigation system. Publication date: February 2003 SDB00081BEB 1 2 47 µH Y-in 54 53 SDB00081BEB 58 57 56 3 B-Y out 4 R-Y in B-Y in 5 2 R-Y out 41 8 R-in1 9 G-in1 B-in1 1 µF 12 7 1 µF 29 30 31 32 VCOM VCC3 (3.0 V) PWM VD HD 0.01 µF GND1 VCC2 (7.5 V) 17 18 YS BLAK B-out det. 2.2 µF 19 B-out 20 G-out det. 2.2 µF 21 G-out 22 23 24 25 R-out det. 2.2 µF 26 R-out 27 VCOM 28 PWM Logic SCP R-in2 G-in2 B-in2 R-det. G-det. B-det. • C coupling input in an analog OSD mode. • Connect to GND in case of no use in a digital OSD mode. 1 µF Clamp. OSD SW 13 VCC1 (5.0 V) V REF Int./Ext. SW Matrix Bright Contrast 14 15 µF Reg. G-Y gene. 10 Gamma Limit 35 1 PAL-N Killer GCA 6 YUV SW R-Y, B-Y DEMOD 39 Invert 82 kΩ 680 pF 16 15 µF VXO VXO gene. Tint ACC amp. f det. Logic 11 Logic C-sync. 15 Power supply pin 64 63 62 APC BPF ACC det. GCA Vert. count Phase comp. Reg. POL 100 kΩ 34 Be sure to attach a power supply filter to a power supply pin. 47 µH 1 µF 5.1 kΩ Recommended crystal oscillator SC out NTSC: VSX0160 NTSC (KINSEKI, Limited) PAL: VSX0162 PAL or (KINSEKI, Limited) PAL-M 59 GND3 0.1 µF 60 Kill det. 0.02 µF 61 APC det. VCC1 (5.0 V) C-in 0.1 µF Sharpness Delay HHKILL 1/n 38 15 µF VSS 37 NRGB 0.02 µF 36 ACC det. Sync. cut SW Clamp DAC 43 2 kΩ 4.7 µF 52 VSYNC drop VCO VDD 1 MΩ VCC3 1. Composite signal input NTSC = 39 pF 0.1 µF PAL = 27 pF 55 Y-det. 330 kΩ 1 kΩ DAC Sync. sepa. 46 51 47 I2C Bus 45 SECAM black level adj. 48 Logic AFC 10 kΩ 3.3 kΩ det. NAVI VCC1 sync. (5.0 V) 44 2.2 µF 50 COM DC 49 1 500 pF SDATA SCLCK 42 10 µF 33 kΩ 330 Ω 0.022 µF GND2 40 PONR 4.7 µF 68 kΩ 0.47 µF 50 kΩ 33 Composite signal 15 kΩ VCC1 Sync. in L-det. AN2546FH-A ■ Application Circuit Examples 0.1 µF SDB00081BEB 58 57 3 B-Y out 4 R-Y in B-Y in 5 2 R-Y out 41 8 R-in1 9 G-in1 B-in1 Int./Ext. SW Matrix 1 µF 12 7 1 µF 29 30 31 32 VCOM VCC3 (3.0 V) PWM VD HD 0.01 µF GND1 VCC2 (7.5 V) 17 18 YS BLAK B-out det. 19 2.2 µF B-out 20 G-out det. 21 2.2 µF G-out 22 23 24 25 R-out det. 2.2 µF 26 R-out 27 VCOM 28 PWM Logic SCP R-in2 G-in2 B-in2 R-det. G-det. B-det. • C coupling input in an analog OSD mode. • Connect to GND in case of no use in a digital OSD mode. 1 µF Clamp. OSD SW Bright 13 VCC1 (5.0 V) V REF 10 Contrast 14 15 µF Reg. G-Y gene. 39 Gamma Limit 35 1 PAL-N Killer GCA 6 YUV SW R-Y, B-Y DEMOD 11 Invert Logic 82 kΩ 680 pF 16 15 µF VXO VXO gene. Tint ACC amp. GCA f det. 38 Logic 15 Power supply pin 64 63 62 APC BPF ACC det. Sharpness Delay Vert. count Phase comp. Reg. C-sync. 100 kΩ 34 Be sure to attach a power supply filter to a power supply pin. 47 µH Recommended crystal oscillator NTSC: VSX0160 NTSC (KINSEKI, Limited) PAL: VSX0162 PAL or (KINSEKI, Limited) PAL-M 1 µF 5.1 kΩ SC out 59 GND3 0.1 µF 60 Kill det. 0.02 µF 61 APC det. VCC1 (5.0 V) C-in ACC det. Sync. cut SW VSYNC drop 1/n POL 36 56 55 54 53 Clamp HHKILL 43 0.1 µF Y-in DAC VCO VSS NRGB 0.02 µF 37 15 µF VDD 1 MΩ VCC3 2. Component signal input Y-det. 4.7 µF 52 DAC Sync. sepa. 46 51 47 I2C Bus 45 SECAM black level adj. Logic AFC 10 kΩ 3.3 kΩ det. NAVI VCC1 sync. (5.0 V) 44 2.2 µF 50 COM DC 48 49 1 500 pF SDATA SCLCK 42 330 kΩ 1 kΩ 330 Ω 0.022 µF GND2 40 PONR 4.7 µF 68 kΩ 0.47 µF 50 kΩ 33 10 µF 33 kΩ 15 kΩ Brightness and syncronous signal VCC1 Sync. in L-det. AN2546FH-A ■ Application Circuit Examples (continued) 3 4 SDB00081BEB PAL or PAL-M NTSC VXO APC Killer Reg. G-Y gene. 10 Int./Ext. SW Matrix 9 8 7 5 82 kΩ 29 30 31 VCOM VCC3 (3.0 V) PWM VD HD SCP 0.01 µF GND1 VCC2 (7.5 V) 17 18 YS BLAK B-out det. 2.2 µF 19 B-out 20 G-out det. 2.2 µF 21 G-out 22 23 24 25 R-out det. 2.2 µF 26 R-out 27 VCOM 28 PWM Logic 32 680 pF R-in2 G-in2 B-in2 R-det. G-det. B-det. • C coupling input in an analog OSD mode. • Connect to GND in case of no use in a digital OSD mode. 12 B-in1 13 G-in1 1 µF 14 R-in1 1 µF Clamp. OSD SW Bright Contrast 35 VCC1 (5.0 V) V REF 1 µF 39 Gamma Limit 15 15 µF 4.7 µF 4.7 µF 4.7 µF GCA 6 YUV SW R-Y, B-Y DEMOD Logic 11 Invert 38 Logic C-sync. 34 1 PAL-N VXO gene. Tint ACC amp. f det. Reg. POL 100 kΩ VCC3 16 15 µF Power supply pin 64 63 62 61 60 59 BPF ACC det. GCA Vert. count 41 Be sure to attach a power supply filter to a power supply pin. 47 µH Apply a half VCC1 voltage to pin 42 according to resistance division when not connecting crystal oscillators. Recommended crystal oscillator NTSC: VSX0160 (KINSEKI, Limited) PAL: VSX0162 (KINSEKI, Limited) GND3 58 57 56 Sharpness Delay HHKILL Phase comp. 1/n NRGB 36 55 Sync. cut SW Clamp DAC 43 54 53 52 VSYNC drop VCO VSS 37 15 µF VDD 50 kΩ 3. Analog RGB signal input VCC1 (5.0 V) Possible to change the synchronous signal input pin according to the channnel 10 value. Possible to input to pin 45 by 3 V[p-p] positive polarity pulse. 330 kΩ 1 kΩ DAC Sync. sepa. 46 51 47 I2C Bus 45 SECAM black level adj. 48 Logic GND2 AFC 10 kΩ 3.3 kΩ det. NAVI VCC1 sync. (5.0 V) 44 2.2 µF 50 COM DC 49 1 500 pF SDATA SCLCK 42 10 µF 33 kΩ 330 Ω 0.02 µF L-det. 1 MΩ 40 PONR 4.7 µF 68 kΩ 0.47 µF 510 kΩ Required only when not using crystal oscillators. 33 Synchronous signal 15 kΩ VCC1 Sync. in 0.022 µF 510 kΩ VCC1 AN2546FH-A ■ Application Circuit Examples (continued) 4 3 2 AN2546FH-A ■ Pin Descriptions Pin No. Description Pin No. Description 1 Crystal oscillator connecting pin 3 (PAL-N) 33 Sand castle pulse output pin 2 R-Y output pin 34 Composite synchronous signal output pin 3 B-Y output pin 35 Vertical synchronous signal input pin 4 R-Y input pin 36 1H reverse signal input pin 5 B-Y input pin 37 Clock-system GND (VSS) 6 Signal processing system power supply 38 Analog imposing control signal input pin (VCC1 = 5.0 V) 39 Horizontal clock detection pin Internal reference power supply detection 40 Clock-system power supply (3.0 V) pin (2.0 V) 41 GND 2 8 R-ch. analog signal input pin 42 AFC loop filter connecting pin 9 G-ch. analog signal input pin 43 VCO frequency adjustment pin 10 B-ch. analog signal input pin 44 7 Synchronous system power supply (VCC1 = 5.0 V) 11 R-ch. clamp detection pin 12 G-ch. clamp detection pin 45 NAVI signal synchronous signal input pin 13 B-ch. clamp detection pin 46 Synchronous signal input pin 14 R-ch. OSD input pin 47 Serial data shift clock input pin 15 G-ch. OSD input pin 48 Serial data input pin 16 B-ch. OSD input pin 49 Power-on reset detection pin 17 Character picking up pulse input pin 50 Common DC adjustment voltage output pin 18 Side black control signal input pin 51 DAC output pin 19 B-ch. output pin 52 Luminance signal input pin 20 B-ch. output DC feedback detection pin 53 Chrominance signal trap filter connection pin 1 21 G-ch. output pin 54 Chrominance signal trap filter connection pin 2 22 G-ch. output DC feedback detection pin 55 Y-system clamp detection pin 23 GND 1 56 ACC detection pin 24 Drive output reference voltage input pin 57 Chrominance signal input pin 25 Drive system power supply (VCC2 = 7.5 V) 58 Chrominance processing system power supply (VCC1 = 5.0 V) 26 R-ch. output pin 27 R-ch. output DC feedback detection pin 59 GND 3 28 Common reverse signal output pin 60 Chrominance killer detection pin 29 Pulse output system power supply 61 APC detection pin (VCC3 = 3.0 V) 62 Subcarrier output pin 30 PWM output pin 63 Crystal oscillator connecting pin 1 (NTSC) 31 Vertical synchronous signal output pin 64 32 Horizontal synchronous signal output pin SDB00081BEB Crystal oscillator connecting pin 2 (PAL/PAL-M) 5 AN2546FH-A ■ Absolute Maximum Ratings Parameter Supply voltage Symbol Rating Unit VCC1 5.5 V VCC2 8.5 VCC3 5.2 ICC mA PD 423 mW Topr −30 to +85 °C Tstg −55 to +150 °C Supply current Power dissipation *2 Operating ambient temperature Storage temperature *1 *1 Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C. *2: The power dissipation shown is the value in free air for Topr = 85°C. ■ Recommended Operating Range Parameter Supply voltage Symbol Range Unit VCC1 4.7 to 5.3 V VCC2 7.0 to 8.0 VCC3 2.7 to 3.3 ■ Electrical Characteristics at Ta = 25°C Parameter Symbol Conditions Min Typ Max Unit VCC1-system current consumption ITOTAL1 Refer to product standards 32 44 mA VCC2-system current consumption ITOTAL2 Refer to product standards 1.0 9.0 mA VCC3-system current consumption ITOTAL3 Refer to product standards 2.0 mA GRY Refer to product standards 9.0 15 dB GRYGY Refer to product standards −5.0 −1.0 dB GBY Refer to product standards 9.0 15 dB B-Y/G-Y relative gain GBYGY Refer to product standards −15 −9.0 dB High-level APC pull-in APH Refer to product standards 500 540 Hz Low-level APC pull-in APL Refer to product standards −540 −500 Hz ACC output characteristic 1 GACC1 Refer to product standards −1.0 1.0 dB ACC output characteristic 2 GACC2 Refer to product standards −1.0 1.0 dB Chrominance killer characteristic 1 VKILL1 Refer to product standards 400 mV[p-p] Chrominance killer characteristic 2 VKILL2 Refer to product standards 600 mV[p-p] SCV Refer to product standards 400 mV[p-p] Sharpness control characteristic GSH Refer to product standards 1.0 dB Sharpness frequency characteristic 1 fSH1 Refer to product standards 4.0 dB CTRR1 Refer to product standards 1.5 dB DC Chrominance system R-Y standard gain R-Y/G-Y relative gain B-Y standard gain Subcarrier amplitude Y-system R-ch. contrast adjustment range 1 6 SDB00081BEB AN2546FH-A ■ Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit G-ch. contrast adjustment range 1 CTRG1 Refer to product standards 1.5 dB B-ch. contrast adjustment range 1 CTRB1 Refer to product standards 1.5 dB R-ch. contrast adjustment range 2 CTRR2 Refer to product standards −2.5 dB G-ch. contrast adjustment range 2 CTRG2 Refer to product standards −2.5 dB B-ch. contrast adjustment range 2 CTRB2 Refer to product standards −2.5 dB R-ch. pedestal amplitude minimum VPEDRmin Refer to product standards 2.0 V[p-p] G-ch. pedestal amplitude minimum VPEDGmin Refer to product standards 2.0 V[p-p] B-ch. pedestal amplitude minimum VPEDBmin Refer to product standards 2.0 V[p-p] R-ch. pedestal amplitude maximum VPEDRmax Refer to product standards 3.0 V[p-p] G-ch. pedestal amplitude maximum VPEDGmax Refer to product standards 3.0 V[p-p] B-ch. pedestal amplitude maximum VPEDBmax Refer to product standards 3.0 V[p-p] G-ch. output DC voltage VGDC Refer to product standards 2.35 2.85 V[p-p] R-ch. gamma characteristic 1 GGAMR1 Refer to product standards −9.0 −3.0 dB G-ch. gamma characteristic 1 GGAMG1 Refer to product standards −9.0 −3.0 dB B-ch. gamma characteristic 1 GGAMB1 Refer to product standards −9.0 −3.0 dB R-ch. gamma characteristic 2 GGAMR2 Refer to product standards −8.0 dB G-ch. gamma characteristic 2 GGAMG2 Refer to product standards −8.0 dB B-ch. gamma characteristic 2 GGAMB2 Refer to product standards −8.0 dB R-ch. gamma characteristic 3 GGAMR3 Refer to product standards −5.0 0 dB G-ch. gamma characteristic 3 GGAMG3 Refer to product standards −5.0 0 dB B-ch. gamma characteristic 3 GGAMB3 Refer to product standards −5.0 0 dB R-ch. white limiter high-level VWRRH Refer to product standards 3.0 V[p-p] G-ch. white limiter high-level VWRGH Refer to product standards 3.0 V[p-p] B-ch. white limiter high-level VWRBH Refer to product standards 3.0 V[p-p] R-ch. white limiter low-level VWRRL Refer to product standards 3.2 V[p-p] G-ch. white limiter low-level VWRGL Refer to product standards 3.2 V[p-p] B-ch. white limiter low-level VWRBL Refer to product standards 3.2 V[p-p] R-ch. black limiter low-level VBRRL Refer to product standards 3.0 V G-ch. black limiter low-level VBRGL Refer to product standards 3.0 V B-ch. black limiter low-level VBRBL Refer to product standards 3.0 V R-ch. black limiter high-level VBRRH Refer to product standards 2.7 V G-ch. black limiter high-level VBRGH Refer to product standards 2.7 V B-ch. black limiter high-level VBRBH Refer to product standards 2.7 V R-ch. YS threshold 1 VtYSR1 Refer to product standards 0.8 V[p-p] G-ch. YS threshold 1 VtYSG1 Refer to product standards 0.8 V[p-p] B-ch. YS threshold 1 VtYSB1 Refer to product standards 0.8 V[p-p] Y-system (continued) SDB00081BEB 7 AN2546FH-A ■ Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit R-ch. YS threshold 2 VtYSR2 Refer to product standards 0.5 V[p-p] G-ch. YS threshold 2 VtYSG2 Refer to product standards 0.5 V[p-p] B-ch. YS threshold 2 VtYSB2 Refer to product standards 0.5 V[p-p] R-ch. black level CHRRB Refer to product standards −1.0 1.0 V G-ch. black level CHRGB Refer to product standards −1.0 1.0 V B-ch. black level CHRBB Refer to product standards −1.0 1.0 V R-ch. black level width WCHRRB Refer to product standards 2.0 4.0 µs G-ch. black level width WCHRGB Refer to product standards 2.0 4.0 µs B-ch. black level width WCHRBB Refer to product standards 2.0 4.0 µs R-ch. CHR threshold 1 VtCHR1 Refer to product standards 1.5 V[p-p] G-ch. CHR threshold 1 VtCHG1 Refer to product standards 1.5 V[p-p] B-ch. CHR threshold 1 VtCHB1 Refer to product standards 1.5 V[p-p] R-ch. CHR threshold 2 VtCHR2 Refer to product standards 3.0 V[p-p] G-ch. CHR threshold 2 VtCHG2 Refer to product standards 3.0 V[p-p] B-ch. CHR threshold 2 VtCHB2 Refer to product standards 3.0 V[p-p] R-ch. white level CHRRW Refer to product standards 2.0 V[p-p] G-ch. white level CHRGW Refer to product standards 2.0 V[p-p] B-ch. white level CHRBW Refer to product standards 2.0 V[p-p] R-ch. white level width WCHRRW Refer to product standards 2.0 4.0 µs G-ch. white level width WCHRGW Refer to product standards 2.0 4.0 µs B-ch. white level width WCHRBW Refer to product standards 2.0 4.0 µs R-ch. RGB2 relative amplitude VRGB2R Refer to product standards − 0.45 0.45 V[p-p] B-ch. RGB2 relative amplitude VRGB2B Refer to product standards − 0.45 0.45 V[p-p] Horizontal sync. pulse low-level VHDL Refer to product standards 0.4 V Horizontal sync. pulse amplitude VHD Refer to product standards 2.4 V[p-p] Horizontal sync. pulse width tHD Refer to product standards 3.6 6.0 µs Vertical sync. pulse low-level VVDL Refer to product standards 0.4 V Vertical sync. pulse amplitude VVD Refer to product standards 2.4 V[p-p] Y-system (continued) Synchronous system 8 Horizontal sync. separation pulse high-level VHSSH SG2 (NTSC) 2.4 V Horizontal sync. separation pulse amplitude VHSS SG2 (NTSC) 2.4 V[p-p] Horizontal sync. separation pulse width tHSS SG2 (NTSC) 3.6 6.0 µs SDB00081BEB AN2546FH-A ■ Terminal Equivalent Circuits Pin No. Equivalent circuit 1 Pin 58 VCC1 190 Ω 1 1 kΩ Description Voltage · Waveform VXO3: PAL-N crystal oscillator connecting pin Use the capacitor with temperature characteristics (N750) to connect to the crystal oscillator. R-Y out: Output pin of R-Y signal demodulated from video signal R-Y signal Pin 59 GND 2 Pin 58 VCC1 2 kΩ 1H 2 Pin 59 GND 3 Pin 58 VCC1 B-Y out: Output pin of B-Y signal demodulated from video signal 2 kΩ B-Y signal 1H 3 Pin 59 GND 4 5 kΩ 5 kΩ 2 kΩ Pin 58 VCC1 R-Y in: R-Y signal input pin in a color difference mode and in the standard PAL R-Y signal 17.5 kΩ 4 1H 5 kΩ Pin 7 VREF 5 kΩ 5 kΩ Pin 59 GND SDB00081BEB 9 AN2546FH-A ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 5 Pin 58 VCC1 5 kΩ 5 kΩ 2 kΩ Description Voltage · Waveform B-Y in: B-Y signal input pin in a color difference mode and in the standard PAL B-Y signal 17.5 kΩ 5 1H 5 kΩ Pin 7 VREF 5 kΩ 5 kΩ Pin 59 GND 6 7 Pin 6 VCC1 60 Ω 7 VCC1: Drive block 5.0 V-system power supply pin VREF: Reference voltage output pin 2.0 V typ. 1 kΩ 200 Ω 30 kΩ 8 26 kΩ Pin 23 GND Pin 6 VCC1 R-in 1: Analog R signal input Analog R signal 0.7 V[p-p] typ. 8 5 kΩ Pin 7 VREF 9 Pin 23 GND Pin 6 VCC1 G-in 1: Analog G signal input Analog G signal 0.7 V[p-p] typ. 9 5 kΩ Pin 7 VREF 10 Pin 23 GND SDB00081BEB AN2546FH-A ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 10 Description Pin 6 VCC1 B-in 1: Analog B signal input Voltage · Waveform Analog B signal 0.7 V[p-p] typ. 10 5 kΩ Pin 7 VREF Pin 23 GND 11 1 kΩ 11 Pin 6 VCC1 1 kΩ R-ch. det.: R-ch. clamping capacitor coupling pin G-ch. det.: G-ch. clamping capacitor coupling pin B-ch. det.: B-ch. clamping capacitor coupling pin 500 Ω HSS Pin 23 GND 12 1 kΩ 12 Pin 6 V 1 kΩ CC1 500 Ω HSS Pin 23 GND 13 1 kΩ 13 Pin 6 VCC1 1 kΩ 500 Ω HSS Pin 23 GND SDB00081BEB 11 AN2546FH-A ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 14 Pin 6 VCC1 Digital OSD circuit Description Voltage · Waveform R-in 2: Character insertion signal input for R-ch., supporting analog and digital OSD Analog OSD Digital OSD 5 kΩ 14 0.7 V[p-p] typ. VDD Pin7 VREF GND Pin 23 GND 15 Pin 6 VCC1 Digital OSD circuit G-in 2: Character insertion signal input for G-ch., supporting analog and digital OSD 0.7 V[p-p] typ. Digital OSD 5 kΩ 15 Analog OSD VDD Pin7 VREF GND Pin 23 GND 16 Pin 6 VCC1 Digital OSD circuit B-in 2: Character insertion signal input for B-ch., supporting analog and digital OSD 0.7 V[p-p] typ. Digital OSD 5 kΩ 16 Analog OSD VDD Pin7 VREF 17 17 GND Pin 23 GND YS: Character picking up signal input 15 kΩ VDD 100 kΩ GND 10 kΩ 18 18 Pin 23 GND BLAK: Black level indication control signal input pin 15 kΩ 100 kΩ 10 kΩ 12 VDD GND Pin 23 GND SDB00081BEB AN2546FH-A ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 19 Pin 6 VCC1 Description Pin 25 VCC2 100 Ω Voltage · Waveform B-out: B signal output pin 19 16 kΩ 20 Pin 23 GND Pin 6 VCC1 19 B-ch. AVE det.: B-ch. output DC feedback detection pin 100 kΩ 20 2 kΩ Pin 23 GND 21 Pin 6 VCC1 100 Ω Pin 25 VCC2 G-out: G signal output pin 21 16 kΩ 22 Pin 23 GND Pin 6 VCC1 21 G-ch. AVE det.: G-ch. output DC feedback detection pin GND 1: Drive circuits system GND 100 kΩ 22 2 kΩ Pin 23 GND 23 SDB00081BEB 13 AN2546FH-A ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 24 Pin 6 VCC1 100 kΩ 24 Description Voltage · Waveform AVE : R,G,B output DC reference voltage pin VCC2: 7.5 V system power supply 2 kΩ 100 kΩ 8 kΩ Pin 23 GND 25 26 Pin 6 VCC1 100 Ω Pin 25 VCC2 R-out: R signal output pin 26 16 kΩ 27 Pin 23 GND Pin 6 VCC1 26 R-ch. AVE det.: R-ch. output DC feedback detection pin 100 kΩ 27 2 kΩ Pin 23 GND 28 Pin 25 VCC2 200 Ω Common out: Voltage output pin for common. Output impedance; Approx. 150 Ω 15 kΩ ch.1 28 ch.1 100 kΩ Pin 23 GND 14 SDB00081BEB AN2546FH-A ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage · Waveform 29 VCC3: Logic output circuits system power supply 3.0 V typ. 30 Pin 29 VCC3 PWM: PWM signal output pin Output waveform VCC3 30 Pin 37 VSS 31 0V Pin 23 GND Pin 29 VCC3 VD: Vertical synchronous signal output pin Output waveform VCC3 31 Pin 37 VSS 32 0V Pin 23 GND Pin 29 VCC3 HD: Horizontal synchronous signal output pin Output waveform VCC3 32 Pin 37 VSS 33 100 Ω 100 Ω 0V Pin 23 GND Pin 44 VCC1 SCP out: Sand castle pulse output pin Burst time 4.0 V[p-p] typ. 2.0 V[p-p] typ. 33 350 Ω 41.3 kΩ 34 Vertical/Horizontal blanking time Pin 41 GND Pin 29 VCC3 HSS: Composite synchronous signal output pin Output waveform VCC3 34 Pin 37 VSS 0V Pin 23 GND SDB00081BEB 15 AN2546FH-A ■ Terminal Equivalent Circuits (continued) Pin No. 35 Equivalent circuit Description Voltage · Waveform VDB in: Vertical synchronous pulse input pin High or Low 15 kΩ Ext. pol.: 1H reverse signal input pin High or Low 35 100 kΩ 10 kΩ 36 Pin 23 GND 36 15 kΩ 100 kΩ 10 kΩ Pin 23 GND 37 VSS : MOS system GND 38 38 15 kΩ 100 kΩ 10 kΩ Pin 23 GND 39 Pin 44 VCC1 200 Ω 60 Ω 39 PRGB: Analog OSD signal input Mode start-up signal input pin Valid only in the analog OSD mode High = Analog OSD start up High or Low LDET: Capacitor coupling pin for the horizontal unlock detecting circuit 10 kΩ 60 Ω 12 kΩ Pin 41 GND 40 VDD: Capacitor connection pin for MOS part power supply 3.0 V typ. 41 GND 2: Pulse system GND 42 Pin 44 VCC1 2 kΩ AFC det.: AFC filter connecting pin Input impedance; 100 kΩ or more 1H 1 kΩ 42 2 kΩ 16 1 kΩ Pin 41 GND SDB00081BEB AN2546FH-A ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 43 Pin 44 VCC1 10 kΩ 10 kΩ 5 pF Description Voltage · Waveform H fO: VCO oscillation frequency adjusting resistor connection pin VCC1: Pulse system power supply 5.0 V 43 2 kΩ Pin 41 GND 44 45 45 15 kΩ 100 kΩ 10 kΩ Pin 23 GND 46 Pin 44 21.7 kΩ 32.5 kΩ VCC1 850 Ω 50 kΩ NAVI sync-in: Synchronous signal input pin for the signal of car navigation system Negative polarity input HSS in: Sync. signal input pin Separates a sync. signal from luminance signal (video signal) VDD 0V Input signal example: Video signal 85 Ω 46 Pin 41 GND 47 SCLK: Serial clock input pin 47 15 kΩ 100 kΩ 10 kΩ Pin 23 GND 48 Pin 44 VCC4 DAT: Serial data input pin 48 15 kΩ 100 kΩ 10 kΩ Pin 23 GND SDB00081BEB 17 AN2546FH-A ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 49 Pin 44 VCC1 5 kΩ 500 Ω 49 100 kΩ Description Voltage · Waveform RST: Capacitor coupling pin for power-on reset Com. DC: DC voltage output pin DC DAC-out: DC voltage output pin DC 50 kΩ Pin 37 VSS Pin 41 GND 50 Pin 44 VCC1 1.5 pF 46 kΩ 50 40 kΩ 36 kΩ Pin 41 GND 51 Pin 44 VCC1 1.5 pF 46 kΩ 51 40 kΩ 36 kΩ Pin 41 GND 52 50 kΩ 52 53 Pin 58 VCC1 Input signal example: Video signal Trap-out: Trap connecting pin Trapping a chrominance signal by connecting external inductor and capacitor. Not necessary in case that an input signal is a component. 50 Ω 2 kΩ 2 kΩ 53 Pin 59 GND 18 Y-in: Luminance signal input pin Input luminance signal (video signal) SDB00081BEB AN2546FH-A ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 54 Description Pin 58 VCC1 54 2 kΩ Voltage · Waveform Trap-in: Trap connecting pin The pair with pin 53 Y-det.: Capacitor coupling pin for luminance signal clamping ACC det.: ACC capacitor connecting pin, adjusting the amplitude of a burst signal automatically Pin 59 GND 55 1 kΩ Pin 58 V 1 kΩ CC1 55 2 kΩ Pin 59 GND 56 1 kΩ 2 kΩ 1 kΩ Pin 58 VCC1 1 kΩ 56 5 kΩ 5 kΩ 1 kΩ 57 Pin 59 GND Pin 58 VCC1 57 50 kΩ C-in: Input signal example: Chrominance signal input pin Video signal Input chrominance signal (video signal) Pin 59 GND 58 VCC1: Power supply 5.0 V typ. Chrominance and luminance signal processing system. 59 GND 3: GND for chrominance and luminance signal processing system SDB00081BEB 19 AN2546FH-A ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 60 Pin 58 VCC1 72 kΩ 60 1.5 kΩ Pin 58 VCC1 31 kΩ 1 kΩ 1 kΩ Voltage · Waveform Kill det.: Killer capacitor coupling pin To prevent degradation of image in a small amplitude of a burst signal, this pin stops a chrominance signal and the mode changes to black and white mode. APC det.: APC capacitor coupling pin Matching the phase of a crystal oscillation to that of burst signal SCP out: Subcarrier pulse output pin NTSC 3.58 MHz PAL 4.43 MHz VXO1: NTSC crystal oscillator connecting pin Use the capacitor with temperature characteristics (N750) to connect to the crystal oscillator. Pin 59 GND 90 kΩ 61 Description 41 kΩ 61 5 kΩ 50 kΩ 5 kΩ 45 kΩ 100 kΩ 2 kΩ 1 kΩ 50 kΩ 2 kΩ Pin 59 GND 62 Pin 58 VCC1 10 kΩ 62 10 kΩ Pin 59 GND 63 Pin 58 VCC1 63 190 Ω 1 kΩ Pin 59 GND 20 SDB00081BEB AN2546FH-A ■ Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit 64 Pin 58 VCC1 190 Ω 64 1 kΩ Description Voltage · Waveform VXO2: PAL and PAL-M crystal oscillator connecting pin Use the capacitor with temperature characteristics (N750) to connect to the crystal oscillator. Pin 59 GND ■ Usage Notes • The supply voltage applied to pin 6, pin 25, pin 29, pin 44, and pin 58 must be brought up at the same time. • The crystal oscillator used must be evaluated thoroughly, because chrominance signal processing system characteristics change by the crystal oscillator type. • The conversion of the analog RGB signals and the analog OSD signals with synchronous signals is not supported. • Input the analog RGB signals and the analog OSD signals after filtering the pedestal parts of these signals. • Evaluated thoroughly on the application of this device in PAL. ■ Technical Data 1. Serial interface description 1) I2C bus control mode A serial data is capable of transferring 9-bit unit of 8-bit transfer data and 1-bit answering data using two kinds of signal lines of data and shift clock. When a slave address after setting a start condition matches the address on the IC side, you can receive the data to be transmitted from then. Once the stop condition is set up, the next transmitting data will be ignored until the start condition is set up. There are two kinds of transfer mode: an auto-increment mode which does not transmit subaddress, and data upgrade mode which transmits subaddress + data by 2 bytes. The typical models of communication sequence are shown below: (1) Start condition When the S-data changes from high level to low level at SCLK = high level, a data receiving mode becomes available. (2) Slave address transfer The slave address of the AN2546FH-A is 88h. Pin 48 S-data 1 2 3 4 5 6 7 8 9 1 2 Pin 47 SCLK Subaddress transfer Start condition Acknowledge bit SDB00081BEB 21 AN2546FH-A ■ Technical Data (continued) 1. Serial interface description (continued) 1) I2C bus control mode (continued) (3) Subaddress transfer When a data transfer mode bit is 0, all the serial data columns transferred until a stop condition is set is regarded as the data block. Pin 48 S-data 8 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 9 1 2 Pin 47 SCLK Data transfer Slave address transfer Acknowledge bit Data transfer mode bit "1": Data update mode "0": Auto increment mode (4) Data transfer Pin 48 S-data 8 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 9 1 2 Pin 47 SCLK Acknowledge bit At auto increment mode: Data transfer At data update mode: Stop condition (5) Stop condition When S-data changes from low level to high level at SCLK = high level, data reception is halted. (6) Pulse timing Timing chart expanded diagram Pin 48 S-data tBUF tHDDAT tLOW tf Pin 47 SCLK tSUSTO tHDSTA tr Parameter tSUDAT tHIGH Symbol Min Typ Max Unit SCLK clock frequency tSCL 0 400 kHz Bus free-time for stop condition and start condition tBUF 1.3 µs tHDSTA 0.6 µs tLOW 1.3 µs Hold time start condition SCLK clock low-state hold time tHIGH 0.6 µs Data hold time tHDDAT 0 µs Data setup time tSUDAT 100 ns tr 300 ns SCLK clock high-state hold time S-data and SCLK signal rise time S-data and SCLK signal fall time Stop condition setup time 22 SDB00081BEB tf 300 ns tSUSTO 0.6 µs AN2546FH-A ■ Technical Data (continued) 1. Serial interface description (continued) 2) Mode setting channel bits table ch. Sub- Initial value address (HEX) D7 D6 D5 D4 D3 1 01 80 Common amplitude 2 02 80 Luminance gain 3 03 80 Color gain 4 04 80 Hue 5 05 40 6 06 80 7 07 80 8 08 80 R-ch. sub-brightness 9 09 80 B-ch. sub-brightness 10 0A C0 11 0B 80 Gamma 1 12 0C 80 Gamma 2 13 0D 80 Contrast 14 0E 80 R-ch. sub-contrast 15 0F 80 B-ch. sub-contrast 16 10 80 VCO free-run *1 17 11 03 DFVD 18 12 00 MACRON 19 13 80 HOSEI 20 14 80 21 15 80 22 16 7F 23 17 80 24 18 80 HGA D2 D1 D0 DUV DCINT Black limiter Brightness DBOSC Aperture DCLP White peak limiter DFSC DPALM DPALN DSECAM DVMODE PLL stop position adjustment PWMT4 KOTEI Vertical position adjustment Horizontal position adjustment PWM frequency adjustment BLAK Burst cleaning pulse position adjustment PWM duty EXTTEST DHTS EXCHFI POLSW DMOSD Common DC DSC DCPS DQPAL *2 DC output adjustment Note) *1: VCO free-run adjustment; ch.23 = 02h or more, EXTTEST = High *2: 00h, 01h are prohibition of use because of test mode. SDB00081BEB 23 AN2546FH-A ■ Technical Data (continued) 1. Serial interface description (continued) 2) Mode setting channel bits table (continued) (1) ch.5: Black limiter adjustment Subaddress 05 D7 HGA D6 D5 0 Output gain down mode 1 Gain mode D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 (2) ch.7: Aperture adjustment Subaddress D7 DCLP D6 D5 07 0 VD free-run: NTSC = 265H, PAL = 315H 1 VD free-run : NTSC = 263H, PAL = 313H (3) ch.10: White peak limiter adjustment Subaddress D7 DCLP D6 D5 0A 0 NAVI sync. mode (Pin 45) 1 Video sync. mode (Pin 46) D4 D3 D2 D1 D0 D3 D2 D1 D0 DUV DCINT (4) ch.17: Mode setup 1 Subaddress D7 D6 D5 D4 11 DFVD DFSC DPALM DPALN Mode DFVD DFSC • at NTSC selection Function DFVD/DFSC/DPALM/DPALN/DSECAM = Low DVMODE = High 0 VD cycle: 60 Hz 1 VD cycle: 50 Hz 0 Subcarrier: 3.58 MHz 1 Subcarrier: 4.43 MHz DPALM High = PALM mode on DPALN High = PALN mode on DSECAM High = SECAM mode on DVMODE High = Burst swing off DUV DCINT DSECAM DVMODE • at PAL selection DFVD/DFSC = High DPALM/DPALN/DSECAM/DVMODE = Low • at PALM selection DPALM/DFVD = High DPALN/DSECAM/DVMODE = Low • at PALN selection DPALN = High 0 Chrominance input 1 Color difference signal input 0 RGB signal input 1 Video signal input DPALM/DSECAM/DVMODE/DFVD = Low (5) ch.18: PLL stop position and vertical sync. output position adjustment Sub- D7 address MACRON 12 24 D6 D5 D4 PLL stop position adjustment 0 AFC normal operation 1 Copy guard signal correspondence SDB00081BEB D3 D2 D1 D0 Vertical position adjustment AN2546FH-A ■ Technical Data (continued) 1. Serial interface description (continued) 2) Mode setting channel bits table (continued) (5) ch.18: PLL stop position and vertical sync. position adjustment (continued) <Vertical synchronous output timing adjustment range> Composite sync. signal odd number field Pin 35 input Pin 31 output odd number field FIXHD = "0" 8H 2H to 9H (D0 to D2) Pin 31 output odd number field FIXHD = "1" 3Η Composite sync. signal even number field Pin 31 output EXCHF = "1" FIXHD = "0" 8H 1.5H to 8.5H (D0 to D2) Pin 31 output EXCHF = "1" FIXHD = "1" 3Η Pin 31 output EXCHF = "0" FIXHD = "0" 8H 2.5H to 9.5H (D0 to D2) The above timing chart indicates (D2,D1,D0) = "101". For (D2,D1,D0) = "000", the pin 32 output width is 9H. 3Η Pin31 output EXCHF = "0" FIXHD = "1" The pin 31 timing is synchronous with the pin 35 input timing. The above timing chart is just for reference <Horizontal PLL start position adjustment range> 0-line 1 2 3 Composite sync. signal odd number field Pin 35 input 6H to 9H (D3 to D4) Odd number field Horizontal PLL off Horizontal PLL on Composite sync. signal even number field 5.5H to 8.5H (D3 to D4) EXCHF = "1" Horizontal PLL off EXCHF = "0" Horizontal PLL off Horizontal PLL on 6.5H to 9.5H (D3 to D4) Horizontal PLL on The above timing chart indicates (D4,D3) = "01". PLL stop line number: 254-line (NTSC) 302-line (PAL) SDB00081BEB 25 AN2546FH-A ■ Technical Data (continued) 1. Serial interface description (continued) 2) Mode setting channel bits table (continued) (6) ch.19: Horizontal sync. output position adjustment Subaddress D7 HOSEI D6 PWMT4 13 D5 KOTEI D4 D3 D2 0 Sync. output variable mode 1 Sync. output fixation mode D1 D0 PWM frequency adjustment 0 VCO automatic adjustment off 1 VCO automatic adjustment on Composite sync. signal input (video signal) Sync. signal separation delay time (Approximately 1 µs) Pin 34 Composite sync. signal output 27fy Pin 32 Horizontal sync. signal output (D4,D3,D2,D1,D0) = (00000) Pin 32 Horizontal sync. signal output (D4,D3,D2,D1,D0) = (11111) Pin 32 Horizontal sync. signal output (D5) = "1" 31fy 27fy 1 (NTSC/PAL) 347fh fh: Horizontal sync. frequency Delay time (Approximately 400 ns) 18fy 1fy = The delay time of pin 34 output to video signal is likely to vary according to an external constant connected to pin 46. For an external constant, the characteristics in weak electric field must be evaluated adequately. Though the horizontal sync. signal output adjustment range is designed by referring to the center of pin 34 output pulse, there would be some error according to VCO free-run frequency. (7) ch.20: PWM frequency and burst cleaning pulse width adjustment Subaddress D7 D6 D5 D4 PWM frequency adjustment 14 26 SDB00081BEB D3 BLAK D2 D1 D0 Burst cleaning pulse adjustment 0 Black level variable mode 1 Black level fixation mode AN2546FH-A ■ Technical Data (continued) 1. Serial interface description (continued) 2) Mode setting channel bits table (continued) (8) ch.22: Mode setup 2 Subaddress D7 D6 D5 D4 D3 D2 D1 D0 16 EXTTEST DHTS EXCHFI POLSW DMOSD DSC DCPS DQPAL Mode EXTTEST DHTS EXCHFI POLSW DMOSD DSC DCPS DQPAL Function 0 Normal mode 1 Test mode 0 1H reverse stop 1 1H reverse 0 Odd number field: Advance phase 1 Even number field: Advance phase 0 Internal POL 1H reverse mode 1 External POL 1H reverse mode 0 Analog OSD signal input 1 Digital OSD signal input 0 Subcarrier output stop 1 Subcarrier output 0 Component input mode 1 Composite input mode 0 STD PAL mode 1 Quasi PAL mode 2. Recommended Operating Conditions Parameter Symbol Condition Min Typ Max Unit Composite video input signal YIN Sync. chip - White 0.9 1.0 1.1 V[p-p] Y-input signal voltage YIN Pedestal - White 0.6 0.7 0.8 V[p-p] C-input signal voltage CIN Burst signal amplitude 200 300 400 mV[p-p] 0 0.9 V 2.1 *1 V MOS input signal low-level voltage VMOSL MOS input signal high-level voltage VMOSH Sync. signal input HSYNC Pedestal - Sync. chip 0.2 0.3 0.4 V[p-p] Analog RGB signal input RGBIN Pedestal - White 0.6 0.7 0.8 V[p-p] Note) *1: Set it lower than VCC1 (Pin 6 voltage). SDB00081BEB 27 AN2546FH-A ■ Technical Data (continued) 3. Power dissipation of package QFP064-P-1010 PD T a 1.600 1.576 Mounted on standard board (glass epoxy: 75 × 75 × t0.8 mm3) Rth(j-a) = 79.3°C/W 1.400 Power dissipation PD (W) 1.200 1.000 0.814 0.800 0.600 Independent IC without a heat sink Rth(j-a) = 153.5°C/W 0.400 0.200 0.000 0 25 50 75 100 125 150 Ambient temperature Ta (°C) ■ New Package Dimensions (Unit: mm) • QFP064-P-1010A (Lead-free package) 12.00±0.20 10.00±0.20 48 33 1 16 0.18±0.05 0.50 0.10 Seating plane 0.15±0.05 (1.00) 0° to 10° 0.50±0.20 28 SDB00081BEB 0.10 M 1.95±0.20 17 0.10±0.10 (1.25) 12.00±0.20 (1.25) 64 10.00±0.20 32 49 Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. 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Consult our sales staff in advance for information on the following applications: • Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. • Any applications other than the standard applications intended. (5) The products and product specifications described in this material are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd. 2002 JUL This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.