ISSI IS62LV2568LL 256k x 8 low power and low vcc cmos static ram Datasheet

ISSI
®
IS62LV2568LL
256K x 8 LOW POWER and LOW Vcc
CMOS STATIC RAM
APRIL 2000
FEATURES
DESCRIPTION
• Access times of 70 and 85 ns
• CMOS low power operation:
— 120 mW (typical) operating
— 6 µW (typical) standby
• Low data retention voltage: 2V (min.)
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• TTL compatible inputs and outputs
• Fully static operation:
— No clock or refresh required
• Single 2.5V to 3.0V power supply
• Available in 32-pin TSOP (Type I), STSOP (Type I),
and 36-pin mini BGA
The ISSI IS62LV2568LL is a low voltage, 262,144 words
by 8 bits, CMOS SRAM. It is fabricated using ISSI’s low
voltage, six transistor (6T), CMOS technology. The device is
targeted to satisfy the demands of the state-of-the-art
technologies such as cell phones and pagers.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels. Additionally, easy memory
expansion is provided by using Chip Enable and Output
Enable inputs, CE and OE. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS62LV2568LL is available in 32-pin TSOP (Type I),
STSOP (Type I), and 36-pin mini BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
CE1
CE2
OE
WE
CONTROL
CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
1
ISSI
IS62LV2568LL
®
PIN CONFIGURATION
36-pin mini BGA (B)
1
2
PIN DESCRIPTIONS
3
4
5
6
A0-A17
Address Inputs
CE1
Chip Enable 1 Input
CE2
Chip Enable 2 Input
OE
Output Enable Input
WE
Write Enable Input
A
A0
A1
CE2
A3
A6
A8
I/O0-I/O7
Input/Output
B
I/O4
A2
WE
A4
A7
I/O0
NC
No Connection
C
I/O5
NC
A5
I/O1
Vcc
Power
D
GND
Vcc
GND
Ground
E
Vcc
GND
F
I/O6
G
I/O7
H
A9
NC
A17
I/O2
OE
CE1
A16
A15
I/O3
A10
A11
A12
A13
A14
32-Pin TSOP (Type I), STSOP (Type I)
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
ISSI
IS62LV2568LL
®
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
CE1
CE2
OE
X
X
H
H
L
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
I/O Operation
High-Z
High-Z
High-Z
DOUT
DIN
Vcc Current
ISB1, ISB2
ISB1, ISB2
ICC
ICC
ICC
OPERATING RANGE
Range
Commercial
Ambient Temperature
0°C to +70°C
VCC
2.5V to 3.0V
–40°C to +85°C
2.5V to 3.0V
Industrial
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
VCC
TBIAS
TSTG
PT
Parameter
Terminal Voltage with Respect to GND
Vcc related to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
Value
–0.5 to Vcc + 0.5
–0.3 to +4.6
–40 to +85
–65 to +150
0.7
Unit
V
V
°C
°C
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
3
ISSI
IS62LV2568LL
®
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
VOL
VIH
VIL
ILI
ILO
VCC = Min., IOH = –1.0 mA
VCC = Min., IOL = 2.1 mA
2.0
—
2.2
–0.3
–1
–1
—
0.4
VCC + 0.3
0.4
1
1
V
V
V
V
µA
µA
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Output Leakage
GND ≤ VIN ≤ VCC
GND ≤ VOUT ≤ VCC
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-70
Min.
Max.
-85
Min.
Max.
Symbol Parameter
Test Conditions
Unit
I CC
Vcc Dynamic
Operating
Supply Current
VCC = Max., CE = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
30
35
—
—
25
30
mA
ISB1
TTL Standby
Current
(TTL Inputs)
VCC = Max.,
Com.
VIN = VIH or VIL,
Ind.
CE1 ≥ VIH or CE2 ≤ VIL, f = 0
—
—
0.4
1.0
—
—
0.4
1.0
mA
ISB2
CMOS Standby
Current
(CMOS Inputs)
VCC = Max., f = 0
Com.
CE1 ≥ VCC – 0.2V,
Ind.
CE2 ≤ 0.2V,
or VIN ≥ VCC – 0.2V, VIN ≤ 0.2V
—
—
5
5
—
—
5
5
µA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
ISSI
IS62LV2568LL
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-70
Symbol
Parameter
-85
Min.
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
70
—
85
—
ns
tAA
Address Access Time
—
70
—
85
ns
tOHA
Output Hold Time
10
—
15
—
ns
tACE1
CE1 Access Time
—
70
—
85
ns
tACE2
CE2 Access Time
—
70
—
85
ns
OE Access Time
—
35
—
45
ns
(2)
OE to High-Z Output
—
25
—
25
ns
(2)
OE to Low-Z Output
5
—
5
—
ns
tLZCE1(2)
CE1 to Low-Z Output
10
—
10
—
ns
tLZCE2
CE2 to Low-Z Output
10
—
10
—
ns
CE1 or CE2 to High-Z Output
0
25
0
25
ns
tDOE
tHZOE
tLZOE
tHZCE
(2)
(2)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0.4V to 2.2V
5 ns
1.3V
See Figures 1 and 2
AC TEST LOADS
3070 Ω
3070 Ω
2.8V
2.8V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1
3150 Ω
5 pF
Including
jig and
scope
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
3150 Ω
5
ISSI
IS62LV2568LL
®
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
tRC
ADDRESS
tAA
tOHA
tOHA
DOUT
DATA VALID
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
tOHA
OE
tHZOE
tDOE
CE1
tLZOE
tACE1/tACE2
CE2
DOUT
tLZCE1/
tLZCE2
tHZCE
HIGH-Z
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
ISSI
IS62LV2568LL
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power)
-70
Symbol
Parameter
-85
Min.
Max.
Min.
Max.
Unit
tWC
Write Cycle Time
70
—
85
—
ns
tSCE1
CE1 to Write End
65
—
70
—
ns
tSCE2
CE2 to Write End
65
—
70
—
ns
tAW
Address Setup Time to Write End
65
—
70
—
ns
tHA
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
tPWE
WE Pulse Width
60
—
60
—
ns
tSD
Data Setup to Write End
30
—
35
—
ns
tHD
Data Hold from Write End
0
—
0
—
ns
tHZWE(2)
WE LOW to High-Z Output
—
33
—
25
ns
tLZWE
WE HIGH to Low-Z Output
5
—
5
—
ns
tSA
(4)
(2)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE = HIGH or LOW)
tWC
ADDRESS
tHA
tSCE1
CE1
tSCE2
CE2
tAW
tPWE(4)
WE
tSA
DOUT
tHZWE
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
tHD
DATA-IN VALID
7
ISSI
IS62LV2568LL
®
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCE1
CE1
tSCE2
CE2
tAW
tPWE1, 2
WE
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCE1
CE1
tSCE2
CE2
tAW
tPWE1, 2
WE
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
8
tHD
DATA-IN VALID
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
ISSI
IS62LV2568LL
®
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Max.
Unit
VDR
Vcc for Data Retention
See Data Retention Waveform
2.0
3.6
V
I DR
Data Retention Current
Vcc = 2.0V, CE1 ≥ Vcc – 0.2V
—
—
2
5
µA
µA
t SDR
Data Retention Setup Time
See Data Retention Waveform
0
—
ns
t RDR
Recovery Time
See Data Retention Waveform
t RC
—
ns
Com.
Ind.
DATA RETENTION WAVEFORM (CE1 Controlled)
Data Retention Mode
tSDR
3.0V
2.2V
tRDR
VCC
VDR
CE1 ≥ VCC Ð 0.2V
CE1
GND
DATA RETENTION WAVEFORM (CE2 Controlled)
Data Retention Mode
3.0
VCC
CE2
2.2V
tSDR
tRDR
VDR
0.4V
CE2 ≤ 0.2V
GND
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
9
ISSI
IS62LV2568LL
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
70
IS62LV2568LL-70B
IS62LV2568LL-70T
IS62LV2568LL-70H
mini BGA (6mm x 8mm)
TSOP, Type I
STSOP, Type I
85
IS62LV2568LL-85B
IS62LV2568LL-85T
IS62LV2568LL-85H
mini BGA (6mm x 8mm)
TSOP, Type I
STSOP, Type I
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Package
70
IS62LV2568LL-70BI
IS62LV2568LL-70TI
IS62LV2568LL-70HI
mini BGA (6mm x 8mm)
TSOP, Type I
STSOP, Type I
85
IS62LV2568LL-85BI
IS62LV2568LL-85TI
IS62LV2568LL-85HI
mini BGA (6mm x 8mm)
TSOP, Type I
STSOP, Type I
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
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