Video Camera LSIs MN6732741 Signal-processing IC for surveillance cameras and cameras for PC input ■ Overview The MN6732741 is camera signal-processing IC appropriate for a wide variety of applications, including surveillance cameras and cameras used for input to personal computers. In addition to the basic functions of luminance and chrominance signal processing, it also integrates the ALC, AWB, and AGC functions that were previously implemented using microcontroller signal processing. Furthermore, it also integrates on a single chip, including SSG, CG, and I2C-bus functions. ■ Features • Input: • Outputs: Analog signal (A/D converter input) Digital output 8-bit YUV signal Analog outputs Luminance signal Chrominance signal Composite video signal output RGB output • Operating supply voltage: 3.3 V ± 0.3 V • Operating clock frequency: 9.5 MHz to 28.7 MHz • Main functions • 10-bit A/D converter • Single-channel 10-bit D/A converter • Two-channel 8-bit D/A converter • Supports analog AGC (NN2038 or NN2039) • CG and SSG circuits • Supports 510 and 768 horizontal lines (NTSC and PAL) • Supports VGA progressive scan readout CCDs (complementary color filters) • Also supports black-and-white CCD signal processing • CCD white defect/black defect correction circuit • Digital AGC gain: up to 24 dB • Left/right reversing function • Variable gamma correction (γ = 0.3 to 1) • ZV port standard mode, BT656 standard mode • Modes: LL, SYNC, VD2, and HD/VD external synchronization support • Built-in I2C-bus circuit • ALC and AGC (Also supports external AGC) • Two white balance modes (manual and ATW) with ATW lock function • Automatic OB correction function ■ Applications • Surveillance cameras, PC input cameras, multimedia cameras Publication date: August 2001 SDB00060AEM 1 MN6732741 ■ Block Diagram YUVOE YUV0 to YUV7 Y VIN 10-bit A/D AGC Luminance processing Y/C MPX 10-bit D/A C Chrominance processing Y COMP output G ENC 8-bit D/A RGB CNV (2-ch) R C output, B WB gain Horizontal drive pulse output Register R/W for each block CG Vertical system drive Sync system pulse output FCK 2FCK FCK 2FCK DATA Carrier signal YLPF Digital AGC control ALC ATN SSG SUB control 2 I2C-bus BLK CSYNC WE RE control SCL SDA PWM PWM0 PWM PWM1 PWM PWM2 PWM PWM3 YUVOE ■ Function Descriptions (by circuit block) 1. ADC Converts the post-CDS CCD signal to a 10-bit digital signal. 2. PATGEN Generates test pattern signals. This circuit generates horizontal and vertical patterns with a color bar (3 colors) format. Since it simulates the output of the CCD 4-color complementary color filters, it conveniently allows problems in the analog block, from the CCD to the A/D converter, and IC internal problems, to be isolated. It can also be used to temporarily halt CCD image output and generate a blue background signal. 3. AGC (AGC, pixel mixing, mirror reversal, and OB clamping functions) Performs AGC control (up to +24 dB) digitally by linking with the ALC. Since the IC also provides an interface output to an external analog AGC (NN2038 or NN2039), over 24 dB of gain can be provided. When a VGA CCD is used, since progressive scan is used, the photodiode mixing operation used with earlier interlaced CCDs is not required. The AGC circuit includes an internal pixel mixing circuit, and is designed for both progressive and interlaced scan at the circuit level. In the mirror mode provided by 510 H and 768 H CCDs, it is possible to generate a reversed video signal by controlling RAM. OB correction is also performed in this block, and this function has both a digital mode, in which processing is performed internally to the IC, and an analog mode that controls the external CDS and AGC IC clamp voltage. 2 SDB00060AEM MN6732741 ■ Function Descriptions (by circuit block) (continued) 4. ALC The ALC block controls the exposure electronically by inputting the luminance signal, taking an averaged but center weighted exposure reading over the whole image, and comparing that to the target value. That result is used to control the CCD's electronic shutter. In ELC mode, since the step size of the electronic shutter accumulation time is discrete, the AGC system is used in conjunction with the ALC function to create a smoothly operating control system. This block also performs a 3field averaging flicker correction operation as well. 5. Luminance system After generating the luminance signal from the complementary color filter CCD output using a low-pass filter, this block generates the horizontal and vertical aperture signals and performs coring/low-luminance suppression, gamma correction, and blanking processing. This block includes a defect correction circuit that corrects for defective pixels in the CCD. One of two outline correction levels can be selected with the APGAIN pin. The IC also includes a defect correction circuit that corrects for missing pixels in the CCD. The gamma correction is continuously variable from γ = 0.3 to 1. The luminance signal low-pass filter can be bypassed to allow this device to handle black-and-white CCDs. 6. Chrominance system This block performs white balance processing, carrier balance, color temperature correction, and low-luminance/ high-luminance chrominance suppression processing. 7. AWB This block generates the auto white balance control signal. This white balance function operates so that the state of the immediately prior and proper illumination level will be held in case of low illumination levels. 8. ENC This block converts between NTSC and PAL. A digital technique in which 4fSC is created from FSC is adopted, and the clock system is unified into a single system. To create the composite video signal, clock rate conversion is also applied to the Y signal and the signals are mixed digitally. The sync signal can also be mixed digitally. 9. RGBCNV The YUV signal generated from the luminance and chrominance signals is converted to RGB using a matrix. However, since the band of the UV signal is dropped to around 800 kHz at a relatively early stage relative to the chrominance signal, this is not a signal in which all three channels have the same wide band as the Y signal, such as the signals used in 3-CCD video cameras. 10. YCMPX This block takes the FCK rate luminance and UV signals and outputs them as an 8-bit time-division multiplexed signal with a 2FCK rate. In BT656 standard mode, SAV and EAV are embedded in the signal. 11. D/A converters One D/A converter block converts the digital input to analog output. There are three channels, and one channel with a 10-bit resolution is provided for each of the composite, Y, and G signals. The circuit is designed so that the sync can be mixed digitally. The remaining D/A converter is a two-channel 8-bit device used for the chrominance, R, and B signals. 12. PWM Provides an independently controllable 4-channel PWM output circuit that can be used to control analog circuits peripheral to the IC. These outputs can be used, for example, for VREF adjustment of D/A converter. 13. CG This circuit generates the high-speed pulse signals (H1, H2, DS1, and DS2) used by the CCD. This block's logic system power supply is isolated from the other IC internal logic circuits to minimize noise. SDB00060AEM 3 MN6732741 ■ Function Descriptions (by circuit block) (continued) 14. SSG This block generates both low-speed pulse signals used by the CCD and various kinds of pulse signals used for signal processing. (However, note that VBSGEN locking is not supported.) 15. I2C-bus When power is first applied, the contents of an external EEPROM are read out and used to set the IC internal registers. Since this circuit does not support multi-master operation, no external devices will have become bus master when power is first applied. This I2C-bus also can be used by external devices to read or write the IC internal registers. (Note that certain limitations apply.) 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 FCK2O FCKO VSS3 VDD3 YUV7 YUV6 YUV5 YUV4 YUV3 YUV2 YUV1 YUV0 PWM3 PWM2 PWM1 PWM0 VSS2 VDD2 A2 A1 A0 SCL SDA RESET CCDSEL2 CCDSEL1 CCDSEL0 TEST0 TEST1 TEST2 TEST3 TEST4 ■ Pin Arrangement 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 N.C. V4 V3 VSS5 VDD5 V2 N.C. V1 N.C. SUB N.C. CH2 N.C. CH1 OSCCNT CXIN CXOUT OSCVDD OSCVSS TESTDC1 WHD FVD FWHD CPOB PBLK HCLR LLDET FLC VDD1 VSS1 EXTIN0 EXTIN1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 COIN OBCTL EXTAGC IRIS ALCELC ATWLOCK APGAIN BLCSW DIN8 DIN7 DIN6 DIN5 DIN4 VDD4 VSS4 DIN3 DIN2 DIN1 DIN0 DS2 DS1 TESTDC2 TESTSW5 R N.C. TGVDD TGVSS N.C. H2 N.C. H1 N.C. (TOP VIEW) 4 SDB00060AEM VIN VREFL VREFML ADVDD ADVSS VREFM VREFHM VREFH VREF23 IREF23 COMP23 BSIG DAVSS1 DAVDD1 RSIG VREF1 IREF1 COMP1 GSIG DAVSS2 DAVDD2 VCXO LPFI FVR MINTEST SCANT HREFCBLK VCSYNCVD YUVOE NTPL PCO EXTMOD MN6732741 ■ Pin Descriptions Pin No. Pin I/O Description 1 N.C. 2 V4 O φV4 charge pulse 3 V3 O φV3 charge pulse 4 VSS5 VSS Digital system ground 5 VDD5 VDD Digital system power supply (3.3 V) 6 V2 O 7 N.C. 8 V1 O 9 N.C. 10 SUB O 11 N.C. 12 CH2 O 13 N.C. 14 CH1 O V1 charge pulse 15 OSCCNT O Oscillator control test 16 CXIN I Synchronization oscillator (crystal oscillator) 17 CXOUT O Synchronization oscillator (crystal oscillator) 18 OSCVDD VDD Oscillator cell power supply 19 OSCVSS VSS Oscillator cell ground 20 TESTDC1 I Test input (Normally connect to low.) 21 WHD O WHD signal that is in proper phase relative to the sync signal 22 FVD O VD signal that is in proper phase relative to the sync signal 23 FWHD O WHD for TG drive 24 CPOB O A/D converter input signal clamp pulse, or D/A converter output clamp pulse 25 PBLK O Pre-blanking pulse 26 HCLR O Horizontal reference signal 27 LLDET I Power supply synchronization switching signal φV2 charge pulse φV1 charge pulse Vertical removal pulse V3 charge pulse Low: internal synchronization, High: LL synchronization 28 FLC I Flicker correction (pulled up). High: Flicker correction on 29 VDD1 VDD Digital system power supply (3.3 V) 30 VSS1 VSS Digital system ground 31 EXTIN0 I External sync signal input 1 32 EXTIN1 I External sync signal input 2 33 EXTMOD I Monitor/automotive mode switch (pulled up) High: Automotive mode (HDVD/SYNC synchronization mode) 34 PCO O Phase comparator output 35 NTPL I NTSC/PAL switching. Low: NTSC, High: PAL (pulled down) SDB00060AEM 5 MN6732741 ■ Pin Descriptions (continued) Pin No. Pin I/O Description 36 YUVOE I Digital output system output enable 37 VCSYNCVD O VCSYNC output/VD output (VGA mode CSYNC/IT mode register switching) 38 HREFCBLK O HREF output/CBLK output (VGA mode HREF/IT mode register switching) 39 SCANT I Test input (Normally connect to low.) 40 MINTEST I Test input (Normally connect to low.) 41 FVR I Frequency control DC input 42 LPFI I Low-pass filter analog switch input 43 VCXO O Analog switch output. LC oscillator 44 DAVDD2 VDD D/A converter power supply 45 DAVSS2 VSS D/A converter ground 46 GSIG O Video signal output (composite/luminance signal/G signal) (Connect RL between this pin and DAVSS2.) 6 47 COMP1 I Phase compensation (Connect a 1 µF capacitor between this pin and DAVSS2.) 48 IREF1 I Bias current setting resistor connection (Connect RIREF between this pin and DAVSS2.) 49 VREF1 I Reference voltage input 50 RSIG O Video signal output (R signal) 51 DAVDD1 VDD D/A converter power supply 52 DAVSS1 VSS D/A converter ground 53 BSIG O Video signal output (Chrominance signal/B signal) 54 COMP23 I Phase compensation (Connect a 1 µF capacitor between this pin and DAVSS1.) 55 IREF23 I Bias current setting resistor connection (Connect RIREF between this pin and DAVSS1.) 56 VREF23 I Reference voltage input 57 VREFH I High-level reference voltage input 58 VREFHM I Mid-level reference voltage (Connect this pin to ADVSS through a capacitor.) 59 VREFM I Mid-level reference voltage (Connect this pin to ADVSS through a capacitor.) 60 ADVSS VSS A/D converter ground 61 ADVDD VDD A/D converter power supply 62 VREFML I Mid-level reference voltage (Connect this pin to ADVSS through a capacitor.) 63 VREFL I Low-level reference voltage input 64 VIN I Analog signal input 65 TEST4 I Test input (Normally connect to low.) 66 TEST3 I Test input (Normally connect to low.) 67 TEST2 I Test input (Normally connect to low.) 68 TEST1 I Test input (Normally connect to low.) 69 TEST0 I Test input (Normally connect to low.) 70 CCDSEL0 I CCD switching 71 CCDSEL1 I CCD switching SDB00060AEM MN6732741 ■ Pin Descriptions (continued) Pin No. Pin I/O Description 72 CCDSEL2 I CCD switching 73 RESET I Logic system initial reset 74 SDA I/O I2C-bus (data) 75 SCL I/O I2C-bus (clock) 76 A0 I EEPROM address setting (pulled down) 77 A1 I EEPROM address setting (pulled down) 78 A2 I EEPROM address setting (pulled down) 79 VDD2 VDD Digital system power supply (3.3 V) 80 VSS2 VSS Digital system ground 81 PWM0 O PWM signal output 82 PWM1 O PWM signal output 83 PWM2 O PWM signal output 84 PWM3 O PWM signal output 85 YUV0 O Digital Y/UV output (LSB) 86 YUV1 O Digital Y/UV output 87 YUV2 O Digital Y/UV output 88 YUV3 O Digital Y/UV output 89 YUV4 O Digital Y/UV output 90 YUV5 O Digital Y/UV output 91 YUV6 O Digital Y/UV output 92 YUV7 O Digital Y/UV output (MSB) 93 VDD3 VDD Digital system power supply (3.3 V) 94 VSS3 VSS Digital system ground 95 FCKO O FCK output 96 FCK2O O 2FCK output 97 COIN I Synchronization oscillator cell (LC oscillator) 98 OBCTL O OB automatic correction output 99 EXTAGC O External AGC control 100 IRIS O Mechanical iris fixation (PWM output) 101 ALCELC I Fixed/ELC switching. Low: ELC, High: Fixed 102 ATWLOCK I ATW/Stop. Low: Normal, High: ATWLOCK 103 APGAIN I Aperture gain switching. Low: Register value High: One half of the register value 104 BLCSW I Backlighting correction. Low: Normal, High: ATWLOCK 105 DIN8 I Digital signal input (MSB) 106 DIN7 I Digital signal input 107 DIN6 I Digital signal input 108 DIN5 I Digital signal input SDB00060AEM 7 MN6732741 ■ Pin Descriptions (continued) Pin No. Pin I/O Description 109 DIN4 I 110 VDD4 VDD Digital system power supply (3.3 V) 111 VSS4 VSS Digital system ground 112 DIN3 I Digital signal input 113 DIN2 I Digital signal input 114 DIN1 I Digital signal input 115 DIN0 I Digital signal input (LSB) 116 DS2 O CDS pulse 1 117 DS1 O CDS pulse 2 118 TESTDC2 I Test input (Normally connect to low.) 119 TESTSW5 I Test input (Normally connect to low.) 120 R O φR pulse 121 N.C. 122 TGVDD VDD TG power supply 123 TGVSS VSS TG ground 124 N.C. 125 H2 O 126 N.C. 127 H1 O 128 N.C. Digital signal input φH1 transfer pulse φH2 transfer pulse ■ Electrical Characteristics 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Supply voltage (digital) VDD − 0.3 to +4.6 V Supply voltage (analog) AVDD − 0.3 to +4.6 V Input voltage VI − 0.3 to VDD+0.3 V Output voltage VO − 0.3 to VDD+0.3 V Output current IO ±48 mA Power dissipation PD 750 mW Operating temperature Topr −20 to +70 °C Storage temperature Tstg −55 to +150 °C Note) 1. The absolute maximum ratings are limit values for stresses applied to the chip so that the chip will not be destroyed. Operation is not guaranteed within these ranges. 2. Always apply the identical potential to the following pins: VDD1, VDD2, VDD3, VDD4, VDD5, VDDTG, ADVDD, DAVDD1, and DAVDD2. Always apply the identical potential to the following pins: VSS1, VSS2, VSS3, VSS4, VSS5, VSSTG, ADVSS, DAVSS1, and DAVSS2. 8 SDB00060AEM MN6732741 ■ Electrical Characteristics (continued) 2. Recommended Operating Conditions at VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V Parameter Symbol Supply voltage (digital) Min Typ Max Unit 3.0 3.3 3.6 V TGVDD TG power supply 3.0 3.3 3.6 OSCVDD Oscillator power supply 3.0 3.3 3.6 ADVDD A/D converter power supply 3.3 DAVDD D/A converter power supply 3.3 9.5 28.7 VDD Supply voltage (analog) Operating frequency fosc Condition Digital system power supply duty 50% V MHz 3. DC Characteristics at VDD = TGVDD = OSCVDD = 3.0 V to 3.6 V, ADVDD = DAVDD = 3.0 V to 3.6 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = -20°C to +70°C Parameter Operating supply current Symbol Condition Min Typ Max Unit IDD VDD = TGVDD = OSCVDD = 3.6 V, 80 120 mA DAIDD ADVDD = DAVDD = 3.6 V, 23 33 ADIDD fCLK = 28.7 MHz, Ta = 25°C 20 40 1) Input pins 1-1: Standard input pins LLDET, EXTIN0, EXTIN1, YUVOE, CCDSEL0 to CCDSEL2, RESET, COIN, ALCELC, ATWLOCK, APGAIN, BLCSW, DIN8 to DIN0, TESTDC2, TESTSW5 Input voltage High level VIH VDD × 0.8 VDD Low level VIL 0 VDD × 0.2 −5 5 µA V Input leakage current ILIPD VI = VDD or VSS 2) Input pins 1-2: Pulled-up input pins Input voltage V FLC, EXTMOD High level VIH VDD × 0.8 VDD Low level VIL 0 VDD × 0.2 Input leakage current ILIPD VI = VDD −10 10 µA Pull-up resistance RPU1 VDD = 3.3 V, VI = VSS 10 30 90 kΩ 3) Input pins 1-3: Pulled-down input pins Input voltage TESTDC1, NTPL, SCANT, A0 to A2, MINTEST, TEST4 to TEST0 High level VIH VDD × 0.8 VDD Low level VIL 0 VDD × 0.2 V Input leakage current ILIPD VI = VSS −10 10 µA Pull-down resistance RPD1 VI = VDD 10 30 90 kΩ 4) Output pins 1-1 V4 to V1, SUB, CH2, CH1, OSCCNT, WHD, CPOB, PBLK, HCLR, PCO, PWM0 to PWM3, OBCTL, EXTAGC, IRIS Output voltage High level VOH IO = −1 mA VDD − 0.6 Low level VOL IO = 1 mA 0.4 5) Output pins 1-2 Output voltage V YUV0 to YUV7 High level VOH IO = −2 mA VDD − 0.6 Low level VOL IO = 2 mA 0.4 SDB00060AEM V 9 MN6732741 ■ Electrical Characteristics (continued) 3. DC Characteristics at VDD = TGVDD = OSCVDD = 3.0 V to 3.6 V, ADVDD = DAVDD = 3.0 V to 3.6 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = -20°C to +70°C (continued) Parameter 6) Output pins 1-3 Output voltage 9) I/O pins 1 Min Typ Max Unit V High level VOH IO = −4 mA VDD − 0.6 Low level VOL IO = 4 mA 0.4 FVD, FWHD, FCKO, FCK2O High level VOH IO = −8 mA VDD − 0.6 Low level VOL IO = 8 mA 0.4 8) Output pins 1-5 Output voltage Condition VCSYNCVD, HREFCBLK 7) Output pins 1-4 Output voltage Symbol V DS2, DS1, R, H2, H1 High level VOH IO = −16 mA VDD − 0.6 Low level VOL IO = 16 mA 0.4 V SDA, SCL TTL Schmitt trigger input voltage Input threshold voltage VT+ VDD = 3.0 V to 3.6 V Vref5 = 4.75 V to 5.25 V 1.6 2.2 VT− (Vref5 is an external reference voltage.) 0.6 1.2 Output voltage Low level VOL IO = 4 mA 0.4 V ILO VO = VDD or VSS −10 10 µA 15 30 MHz Output leakage current 10) Oscillator pins 1 V CXIN, CXOUT Standard oscillator frequency fOSC VDD = 3.3 V, with an external crystal Internal feedback resistance RFB VDD = 3.3 V VI (XI) = VDD or VSS 0.73 2.2 6.6 kΩ Output current High level IOH VDD = 3.3 V VI = VSS , VO = VSS −57.5 −23 −9.2 mA Low level IOL VDD = 3.3 V VI = VDD , VO = VDD 9.6 24 60 Min Typ Max Unit 4. AC Characteristics Parameter Input pins 2-1 Symbol Condition CXIN Clock waveform Period Clock duty tcyc See figure 1 34.8 105.3 ns dclk See figure 1 dclk = thi /tcyc 50 % tcyc thi Clock CLK Vclk /2 Figure 1. Clock waveform 10 SDB00060AEM Vclk MN6732741 ■ Electrical Characteristics (continued) 5. A/D converter at VDD = TGVDD = OSCVDD = 3.3 V, ADVDD = DAVDD = 3.3 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = 25°C Pins: VIN, VREFH, VREFL, VREFM, VREFML, VREFHM Parameter Symbol Condition Min Typ Max Unit 1) A/D converter recommended operating conditions Analog input voltage VAIN VIN VREFL VREFH V Analog input pin capacitance CAI VIN 330 pF High-level reference voltage VREFH VREFH 2.5 V Low-level reference voltage VREFL VREFL 0.5 V Reference resistance (VREFL to VREFH) RREF 440 Ω 10 bit 2) A/D converter characteristics Resolution RES Nonlinearity error INL fADCK = 14.3 MHz ±5.0 ±7.5 LSB Differential nonlinearity error DNL VREFH = 2.5 V VREFL = 0.5 V ±2.0 ±6.5 LSB Analog input dynamic range VAIN VREFH − VREFL V[p-p] Min Typ Max Unit 6. D/A converter at VDD = TGVDD = OSCVDD = 3.3 V, ADVDD = DAVDD = 3.3 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = 25°C 1) Pins: VREF23, IREF23, COMP23, BSIG, RSIG Parameter (1) Symbol Condition D/A converter recommended operating conditions Reference voltage VREF RL = 75 Ω RIREF23 = 820 Ω 1.37 V External phase compensation capacitor CCOMP Connected between COMP23 and AVDD. 1.0 µF Connect output resistors between each of the BSIG and RSIG pins and AVSS. 75 Ω Connect this resistor between IREF23 and AVSS. 820 Ω 8 bit External output resistors External bias current setting resistor (2) RL RIREF D/A converter characteristics Resolution RES Nonlinearity error INL RL = 75 Ω ±2.5 LSB Differential nonlinearity error DNL VREF23 = 1.37 V RIREF23 = 820 Ω ±2.5 LSB Full-scale voltage VOFS 1.0 V Zero-scale voltage VOZS 0 V SDB00060AEM 11 MN6732741 ■ Electrical Characteristics (continued) 6. D/A converter at VDD = TGVDD = OSCVDD = 3.3 V, ADVDD = DAVDD = 3.3 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = 25°C (continued) 2) Pins: VREF1, IREF1, COMP1, GSIG Parameter Symbol Condition Min Typ Max Unit (1) D/A converter recommended operating conditions Reference voltage VREF RL = 75 Ω RIREF1 = 1.13 kΩ 1.5 V External phase compensation capacitor CCOMP Connect between COMP1 and AVDD. 1.0 µF RL Connect an output resistor between GSIG and AVSS. 75 Ω Connect this resistor between IREF1 and AVSS. 1.13 kΩ 10 bit External output resistor External bias current setting resistor RIREF (2) D/A converter characteristics Resolution RES Nonlinearity error INL RL = 75 Ω ±2.5 LSB Differential nonlinearity error DNL VREF1 = 1.5 V RIREF1 = 1.13 kΩ ±2.5 LSB Full-scale voltage VOFS 1.0 V Zero-scale voltage VOZS 0 V 12 SDB00060AEM MN6732741 ■ Application System Examples 1. Example A (Minimum configuration) • Internal synchronization • Composite video output EEPROM Color CCD CDS MN6732741 75 Ω driver Vertical driver EEPROM 2. Example B • Internal synchronization • RGB output Color CCD CDS MN6732741 Vertical driver 75 Ω driver R 75 Ω driver G 75 Ω driver B EEPROM 3. Example C (Surveillance camera) • External synchronization • YC output LL pulse Color CCD CDS AGC MN6732741 YC mixer 75 Ω driver VD2 separation Vertical driver Analog switch 4. Example D (PC camera) • Internal synchronization • Digital output VCXO VCO EEPROM Color CCD CDS YUV MN6732741 8-bit Vertical driver 5. Example E • Internal synchronization • Y output EEPROM Black-andwhite CCD CDS MN6732741 75 Ω driver Vertical driver SDB00060AEM 13 MN6732741 ■ Package Dimensions (Units: mm) • LQFP128-P-1818C 20.00±0.20 18.00±0.10 96 65 64 128 33 18.00±0.10 20.00±0.20 (1.25) 97 0.10 M 14 Seating plane SDB00060AEM 0.10±0.10 1.70 max. 0.10 0.25 32 0.20±0.05 1.40±0.10 0.50 0.15±0.05 1 (1.25) (1.00) 0° to 10° 0.50±0.20 (0.60) Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: • Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. • Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company. Please read the following notes before using the datasheets A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited. 2001 MAR