ISSI IS62LV1288LL-55QI 128k x 8 low power and low vcc cmos static ram Datasheet

ISSI
®
IS62LV1288LL
128K x 8 LOW POWER and LOW Vcc
CMOS STATIC RAM
FEBUARY 2001
FEATURES
DESCRIPTION
• Access times of 45, 55, and 70 ns
• Low active power: 60 mW (typical)
• Low standby power: 15 µW (typical) CMOS
standby
• Low data retention voltage: 2V (min.)
• Ultra Low Power
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• TTL compatible inputs and outputs
• Single 2.5V (min.) to 3.45V (max.) power supply
• Industrial temperature available
• Available in 32-pin TSOP (Type I), 32-pin
STSOP, and 450-mil SOP
The ISSI IS62LV1288LL is a low power and low
Vcc,131,072-word by 8-bit CMOS static RAM. It is
fabricated using ISSI 's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields higher
performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the
device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip
Enable inputs, CE1 and CE2. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62LV1288LL is available in 32-pin TSOP (Type I),
STSOP (8 x 13.4mm), and 450-mil plastic SOP (525-mil
pin to pin) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
512 X 2048
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
CE1
CE2
OE
WE
CONTROL
CIRCUIT
This document contISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no
responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/01
1
ISSI
IS62LV1288LL
PIN CONFIGURATION
PIN CONFIGURATION
32-Pin SOP (Q)
32-Pin TSOP (Type I) (T) and STSOP (Type 1) (H)
NC
1
32
VCC
A16
2
31
A15
A14
3
30
CE2
A12
4
29
WE
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE
A2
10
23
A10
A1
11
22
CE1
A0
12
21
I/O7
I/O0
13
20
I/O6
I/O1
14
19
I/O5
I/O2
15
18
I/O4
GND
16
17
I/O3
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
®
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
PIN DESCRIPTIONS
A0-A16
Address Inputs
CE1
Chip Enable 1 Input
CE2
Chip Enable 2 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
NC
No Connection
Vcc
Power
GND
Ground
OPERATING RANGE
Range
Commercial
Industrial
2
Ambient Temperature
0°C to +70°C
Speed
-45 ns
-55 ns
-70 ns
VCC MIN.
2.85V
2.5V
2.5V
VCC MAX.
3.15V
3.45V
3.45V
–40°C to +85°C
-45 ns
-55 ns
-70 ns
2.85V
2.5V
2.5V
3.15V
3.45V
3.45V
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/01
ISSI
IS62LV1288LL
®
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
CE1
CE2
OE
X
X
H
H
L
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
I/O Operation
High-Z
High-Z
High-Z
DOUT
DIN
Vcc Current
ISB1, ISB2
ISB1, ISB2
I CC
I CC
I CC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
VCC
TBIAS
TSTG
PT
Parameter
Terminal Voltage with Respect to GND
Vcc related to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
Value
–0.5 to Vcc + 0.5
–0.3 to +3.6
–40 to +85
–65 to +150
0.7
Unit
V
V
°C
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/01
3
ISSI
IS62LV1288LL
®
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
VOL
VIH
VIL
ILI
ILO
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Output Leakage
VCC = Min., IOH = –1.0 mA
VCC = Min., IOL = 2.1 mA
2.2
—
2.0
–0.2
–1
–1
—
0.4
VCC + 0.2
0.4
1
1
V
V
V
V
µA
µA
GND ≤ VIN ≤ VCC
GND ≤ VOUT ≤ VCC
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-45
Min. Max.
-55
Min. Max.
-70
Min. Max.
Symbol Parameter
Test Conditions
Unit
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max., CE = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
35
40
—
—
30
35
—
—
25
30
mA
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
VIN = VIH or VIL, CE1 ≥ VIH Ind.
or CE2 ≤ VIL, f = 0
—
—
0.4
1
—
—
0.4
1
—
—
0.4
1
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max., f = 0
Com.
CE1 ≥ VCC – 0.2V,
Ind.
CE2 ≤ 0.2V,
or VIN ≥ VCC – 0.2V, VIN ≤ 0.2V
—
—
8
10
—
—
8
10
—
—
8
10
µA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/01
ISSI
IS62LV1288LL
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-45
Symbol
Parameter
-55
-70
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
45
—
55
—
70
—
ns
tAA
Address Access Time
—
45
—
55
—
70
ns
tOHA
Output Hold Time
10
—
10
—
10
—
ns
tACE1
CE1 Access Time
—
45
—
55
—
70
ns
tACE2
CE2 Access Time
—
45
—
55
—
70
ns
tDOE
OE Access Time
—
20
—
25
—
35
ns
OE to Low-Z Output
0
—
5
—
5
—
ns
tHZOE(2) OE to High-Z Output
0
15
0
20
0
25
ns
tLZCE1(2) CE1 to Low-Z Output
5
—
7
—
10
—
ns
tLZCE2
CE2 to Low-Z Output
5
—
7
—
10
—
ns
tHZCE
CE1 or CE2 to High-Z Output
0
15
0
20
0
25
ns
tLZOE
(2)
(2)
(2)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0.4V to 2.2V
5 ns
1.3V
See Figures 1 and 2
AC TEST LOADS
1213 Ω
1213 Ω
3.0V
3.0V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1.
1378 Ω
5 pF
Including
jig and
scope
Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/01
1378 Ω
5
ISSI
IS62LV1288LL
®
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
tRC
ADDRESS
tAA
tOHA
tOHA
DOUT
DATA VALID
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
tOHA
OE
tHZOE
tDOE
CE1
tLZOE
tACE1/tACE2
CE2
DOUT
tLZCE1/
tLZCE2
tHZCE
HIGH-Z
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/01
ISSI
IS62LV1288LL
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power)
Symbol
-45
Min.
Max.
Parameter
-55
Min.
Max.
-70
Min.
Max.
Unit
tWC
Write Cycle Time
45
—
55
—
70
—
ns
tSCE1
CE1 to Write End
35
—
50
—
60
—
ns
tSCE2
CE2 to Write End
35
—
50
—
60
—
ns
tAW
Address Setup Time to Write End
35
—
50
—
60
—
ns
tHA
Address Hold from Write End
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
0
—
ns
tPWE1,2
WE Pulse Width
35
—
40
—
55
—
ns
tSD
Data Setup to Write End
25
—
25
—
30
—
ns
tHD
Data Hold from Write End
0
—
0
—
0
—
ns
tHZWE(2)
WE LOW to High-Z Output
—
15
—
20
0
25
ns
tLZWE
WE HIGH to Low-Z Output
5
—
5
—
5
—
ns
(2)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE1, CE2 Controlled, OE = HIGH or LOW)(1,2)
tWC
ADDRESS
tHA
tSCE1
CE1
tSCE2
CE2
tAW
tPWE(4)
WE
tSA
DOUT
tHZWE
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/01
tHD
DATA-IN VALID
7
ISSI
IS62LV1288LL
®
WRITE CYCLE NO. 2 (WE, Controlled: OE is HIGH during Write Cycle)(1,2)
tWC
ADDRESS
OE
tHA
tSCE1
CE1
tSCE2
CE2
tAW
tPWE1, 2
WE
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW during Write Cycle)(1,2)
tWC
ADDRESS
OE
tHA
tSCE1
CE1
tSCE2
CE2
tAW
tPWE1, 2
WE
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
tHD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/01
ISSI
IS62LV1288LL
®
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
Test Condition
Min.
Max.
Unit
2.0
3.45
V
—
—
8
10
µA
µA
VDR
Vcc for Data Retention
See Data Retention Waveform
I DR
Data Retention Current
Vcc = 2.0V, CE1 ≥ Vcc – 0.2V
tSDR
Data Retention Setup Time
See Data Retention Waveform
0
—
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC
—
ns
Com.
Ind.
DATA RETENTION WAVEFORM (CE1 Controlled)
Data Retention Mode
tSDR
3.0V
2.2V
tRDR
VCC
VDR
CE1 ≥ VCC – 0.2V
CE1
GND
DATA RETENTION WAVEFORM (CE2 Controlled)
Data Retention Mode
3.0
VCC
CE2
2.2V
tRDR
tSDR
VDR
0.4V
CE2 ≤ 0.2V
GND
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/01
9
ISSI
IS62LV1288LL
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.Package
45
IS62LV1288LL-45Q
IS62LV1288LL-45T
IS62LV1288LL-45H
450-mil Plastic SOP
TSOP, Type I
STSOP, Type I
55
IS62LV1288LL-55Q
IS62LV1288LL-55T
IS62LV1288LL-55H
450-mil Plastic SOP
TSOP, Type I
STSOP, Type I
70
IS62LV1288LL-70Q
IS62LV1288LL-70T
IS62LV1288LL-70H
450-mil Plastic SOP
TSOP, Type I
STSOP, Type I
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Package
45
IS62LV1288LL-45QI
IS62LV1288LL-45TI
IS62LV1288LL-45HI
450-mil Plastic SOP
TSOP, Type I
STSOP, Type I
55
IS62LV1288LL-55QI
IS62LV1288LL-55TI
IS62LV1288LL-55HI
450-mil Plastic SOP
TSOP, Type I
STSOP, Type I
70
IS62LV1288LL-70QI
IS62LV1288LL-70TI
IS62LV1288LL-70HI
450-mil Plastic SOP
TSOP, Type I
STSOP, Type I
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/01
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