AN2011S Correlated Double Sampling IC ■ Overview 15 3 14 4 13 5 12 6 11 7 10 8 9 0.3 1.5±0.2 0.1±0.1 • Available for CCD of up to 768H by using the highspeed sampling circuit • The sampling pulse corresponds to CMOS level. • The gain is fixed to 6dB. • Compatible with the AN2010S 16 2 0.15 0.65 0.4 0.4±0.25 1.27 ■ Features 1 10.1±0.3 Unit:mm The AN2011S is an integrated circuit that outputs video-signal made from output-signal of CCD imageelement by correlated double sampling. 4.2±0.3 6.5±0.3 16-Pin PANAFLAT package (SOP016-P-0225) ■ Block Diagram VCC1 16 14 13 15 2 Sample Hold Limiter Sample Hold + Sub & GC Amp. Sample Hold 10 12 – 8 9 11 GND3 5 6 7 4 1 3 GND1 GND2 VCC2