Others
DN8667NS
8-Bit Shift Register Latch Constant Current Driver IC
■ Overview
16
6
15
7
14
8
13
9
12
10
11
1.27
12.63±0.3
17
5
5.5±0.3
7.6±0.3
(0.4)
2.05±0.2
18
4
0.1
0.2 +– 0.05
0.9±0.25
3
0.4±0.25
20
19
0.9±0.25
• Serial-in, serial-out/parallel-out
• Cascade connection possible
• Constant current output (0 to 100 mA able to be set by
one external resistor)
• Output-forced ON/OFF terminal attached (EN)
• Input/Output CMOS compatible
1
2
0.1±0.1
■ Features
(0.4)
Unit : mm
The DN8667NS is a semiconductor integrated circuit
which incorporates a 8-bit shift register, a latch driver and
a constant current driver to satisfy the demand for equalization of LED panel brightness. It also incorporates the
serial-in and serial-out/parallel-out functions. It employs
the Bi-CMOS process : The 8-step shift register block
and latch block consist of CMOS while the 8-step parallel
driver block is bipolar.
20-pin SOP Package (SOP020-P-0300A)
■ Application
• LED panel drive
■ Block Diagram
1
2
8
Constant
Current
Output
Constant
Current
Output
Constant
Current
Output
Gate Control Sig.
Gate
Latch Control Sig.
Latch
External
Resistor
Current Set.
Data Input
Data Output
Shift
Register
Shift
Register
Shift
Register
Clock Input
1
DN8667NS
Others
■ Absolute Maximum Rating (Ta = 25˚C)
Symbol
Rating
Supply voltage
Parameter
VCC
0 to + 7.0
Unit
Output voltage
VO
0 to + 14
Output current
IO
150
V
V
mA
Power dissipation*
PD
1.28
W
Operating ambient temperature
Topr
–20 to + 85
˚C
Storage temperature
Tstg
–55 to + 150
˚C
* For printed board SM, it decreases with rate of 10.24 mW/˚C from Ta = 25 ˚C.
■ Recommended Operation Range (Ta=25 ˚C)
Parameter
Operating supply voltage
Symbol
Range
VCC
4.5V to 5.5V
■ Electrical Characteristics (VCC=5V,Ta=25 ± 2˚C)
Parameter
Symbol
Positive direction
VT+
Negative direction
VT–
{
{
IIH
V1H = 5.0V
Input voltage
Input current
min
typ
max
0.7VCC
V
0.2VCC
0.55VCC
V
25
µA
4.0
V
0.5
VO (Qn) = 0.5V
Output current 2 (Qn)
IOI
Output current error between bits
DIO
VCC = 5.0V, Iref = –12mA
VO (Qn) = 1.0V
100
117
Output leak current
IOLK
VO= 14V (Output OFF)
Supply current
ICC1
ICC2
Clock frequency
Input pulse width
Setting-up time
fCLK
tw
tsu
ON
ICC3
OFF
IOL = 1.6mA
IOI
Total Driver Output
VOL
VCC=5.5V
CLK
µA
– 25
V1L = 0V
IOH = – 0.4mA
Output current 1 (Qn)
Unit
0.35VCC
IIL
VOH
Output voltage (SOUT)
83
V
mA
mA
±6
%
25
µA
Iref = 0mA
Iref = –2.5mA
2
20
mA
mA
Iref = –2.5mA
30
mA
20
MHZ
Input Duty 40 to 60%
CLK
20
ns
STB
20
ns
20
ns
15
ns
20
ns
SIN
STB
SIN
VCC=5.0V
RL=50Ω
CL=15pF
Holding time
th
Clock pulse rise time
tr
500
ns
Clock pulse fall time
tf
500
ns
Note) VCC= 5V unless otherwise specified.
2
Condition
VSOUT = 0.1, VCC – 0.1V
ISOUT = 20µA
IO (Qn) = –10µA, 90mA
VO (Qn) = 0.6V Iref = –2.5mA
STB
ns
10
Others
DN8667NS
■ Pin Descriptions
Pin No.
Symbol
1
DGND
Pin name
Description
Digital ground
Digital ground
2
SIN
Serial data input
It is the serial data input terminal for shift register.
3
CLK
Clock input
The value of shift register shifts at the rising edge of clock input.
4
STB
Strobe input
Setting the STB input to "H" forwards the data of shift register to the latch.
When the STB input is set to "L" , even if the value of shift register changes,
the value of latch is not changed.
Qn
Driver output
It outputs signals by using the polarity opposite to that of data taken into the
latch. For example, when the value of serial input is "H" , the output becomes
"L" level and the output is turned on. The output takes open collector form of
NPN transistor.
9,12
15
PGND
Output ground
Output ground
17
EN
Enabling input
When the EN input is set to "H" , all the outputs are turned off, independent of
condition of shift register or latch driver.
18
SOUT
Serial data output
It is the terminal which performs the serial-output of data inputted from the SIN.
5
7,8
10,11
13,14
16
6
It connects the external resistor between RC and GND and sets the current of
output block.
* Output current calculation :
** RC terminal setting calculation :
19
RC
Constant current setting input
20
VCC
VCC
20 × VCC (V)
IO (Qn) ≈
R
RC (Ω) + 90
(A)
1 VCC (V)
or RRC ≈
–180
IRC (A)
2
(Ω)
VCC (V)
IRC ≈
2
×
R
RC (Ω) +180
(A)
Supply terminal
20 × 5
* Calculation example
IO (Qn) ≈ 910 + 90
VCC = 5V
RRC = 910Ω
IO (Qn) ≈ 100mA
1
5
** Calculation example
RRC ≈ 2 0.0025 –180
VCC = 5V
IRC = 0.0025A
RRC ≈ 910 (Ω)
3
DN8667NS
Others
■ Application Circuit
SIN
DN8667NS LED Panel Block Diagram
VCC
(20)
SIN
(2)
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
CLK
(3)
Logic
input
DN8667NS
SOUT
(18)
DGND
(1)
ST B
(4)
L D
Q
EN
(17)
L D
Q
L D
Q
L D
Q
L D
Q
PGND
(6) (9) (12) (15)
Current
setting
circuit
(5)
(7)
Q0
(8)
Q1
(10)
Q2
VLED
RC
(19)
GND
LED
(16)
Q3
Q7
LED
Scan input
GND
LED
■ Function Table (Note)
Input
Output
CLK
STB
EN
SIN
QO
Qm
Q7
SOUT
↑
H
L
Qn
Qn
Qm-1
Q6
Q6
↑
L
L
Qn
nc
nc
nc
Q6
↑
×
H
Qn
H
H
H
Q6
↓
×
×
Qn
nc
nc
nc
nc
■ Characteristics Curve
PD — Ta
Power Dissipation PD (mW)
1600
Glass epoxy printed board
(50mm × 50mm × t0.8mm)
Rthj-a=97.7˚C/W
PD=1280 mW (25˚C)
1400
1280
1200
1000
Single unit
Rthj-a=174.1˚C/W
PD=718 mW (25˚C)
800
718
600
400
200
0
0
25
50
75
100
125
150
Ambient Temperature Ta (˚C)
4
(Note)
H : High level,
L : Low level,
× : H or L
Qm, Qn : H or L.
However, for Qn, "H"= OFF, "L"= ON.
↑ : Shift from L to H,
↓ : Shift from H to L
nc : No change
Others
DN8667NS
■ Timing Chart
2.Transmission delay time
1.Input timing
1/fCLK
tWL(CLK)
tWH (CLK)
5V
90%
CLK
5V
90%
2.5V
2.5V
10%
2.5V
CLK
0V
tr(CLK)
tf(CLK)
tsu(SIN)
th(SIN)
5V
2.5V 2.5V
2.5V 2.5V
0V
2.5V
0V
5V
SIN
2.5V
10%
tsu(SIN)
EN
th(SIN)
2.5V
2.5V
0V
th(STB)
5V
STB
tsu(STB)
VOH
2.5V
2.5V
tPLH
tPLH
50%
Qn
50% 50%
tPHL
0V
tw(STB)
(VIL= 0V,VIH= 5.0V)
50%
tPHL
VOL
(VIL= 0V,VIH= 5.0V)
5