ON MC74VHCT14AD Hex schmitt inverter Datasheet

SEMICONDUCTOR TECHNICAL DATA
The MC74VHCT14A is an advanced high speed CMOS Schmitt inverter
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
Pin configuration and function are the same as the MC74VHCT04A, but
the inputs have hysteresis and, with its Schmitt trigger function, the
VHCT14A can be used as a line receiver which will receive slow input
signals.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS
level output swings.
The VHCT14A input structures provide protection when voltages between
0V and 5.5V are applied, regardless of the supply voltage. The output
structures also provide protection when VCC = 0V. These input and output
structures help prevent device destruction caused by supply voltage –
input/output voltage mismatch, battery backup, hot insertion, etc.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
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D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
DT SUFFIX
14–LEAD TSSOP PACKAGE
CASE 948G–01
High Speed: tPD = 5.5ns (Typ) at VCC = 5V
Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C
TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2V to 5.5V Operating Range
Low Noise: VOLP = 0.8V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 60 FETs or 15 Equivalent Gates
M SUFFIX
14–LEAD SOIC EIAJ PACKAGE
CASE 965–01
ORDERING INFORMATION
MC74VHCTXXAD
MC74VHCTXXADT
MC74VHCTXXAM
FUNCTION TABLE
LOGIC DIAGRAM
A1
A2
1
2
3
4
5
6
Y1
Y2
Pinout: 14–Lead Packages (Top View)
A3
Y3
Y=A
A4
A5
A6
9
8
11
10
13
12
VCC
A6
Y6
A5
Y5
A4
Y4
14
13
12
11
10
9
8
1
2
3
4
5
6
7
A1
Y1
A2
Y2
A3
Y3
GND
Y4
Y5
Y6
4/99
 Motorola, Inc. 1999
1
SOIC
TSSOP
SOIC EIAJ
REV 0
Inputs
Outputs
A
Y
L
H
H
L
MC74VHCT14A
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MAXIMUM RATINGS*
Symbol
Value
Unit
DC Supply Voltage
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to VCC + 0.5
V
IIK
Input Diode Current
– 20
mA
IOK
Output Diode Current
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
VCC
Parameter
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
v
v
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
Max
Unit
4.5
5.5
V
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
– 40
+ 85
_C
TA
Operating Temperature, All Package Types
DC ELECTRICAL CHARACTERISTICS
S b l
Symbol
P
Parameter
T
Test
C
Conditions
di i
VCC
V
Min
VT+
Positive Threshold Voltage
3.0
4.5
5.5
VT–
Negative Threshold Voltage
3.0
4.5
6.0
0.35
0.5
0.6
VH
Hysteresis Voltage
3.0
4.5
5.5
0.30
0.40
0.50
VIN = VIH or VIL
IOH = – 50µA
2.0
3.0
4.5
1.9
2.9
4.4
IOH = – 4mA
IOH = – 8mA
VIN = VIH or VIL
IOL = 50µA
4.5
5.5
2.58
3.94
IOL = 4mA
IOL = 8mA
VIN = 5.5V or GND
VOH
VOL
Minimum High–Level
Output Voltage
IOH = –50µA
Maximum Low–Level
Output Voltage
2.0
3.0
4.5
TA ≤ 85°C
TA = 25°C
Typ
Max
Min
1.7
2.0
2.0
Max
2.0
3.0
4.5
0.0
0.0
0.0
Min
1.6
2.0
2.0
0.35
0.5
0.6
1.20
1.40
1.60
TA ≤ 125°C
0.30
0.40
0.50
Max
U i
Unit
1.6
2.0
2.0
V
0.35
0.5
0.6
1.20
1.40
1.60
0.30
0.40
0.50
1.9
2.9
4.4
1.9
2.9
4.4
2.48
3.80
2.34
3.66
V
1.20
1.40
1.60
V
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
5.5
0.36
0.36
0.44
0.44
0.52
0.52
0 to 5.5
± 0.1
± 1.0
± 1.0
µA
V
IIN
Maximum Input Leakage
Current
ICC
Maximum Quiescent Supply
Current
VIN = VCC or GND
5.5
2.0
20
40
µA
Quiescent Supply Current
Input: VIN = 3.4V
5.5
1.35
1.50
1.65
mA
Output Leakage Current
VOUT = 5.5V
0.0
0.5
5.0
10
µA
ICCT
IOPD
MOTOROLA
2
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
MC74VHCT14A
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA ≤ 85°C
TA = 25°C
S b l
Symbol
tPLH,
tPHL
CIN
P
Parameter
T
Test
C
Conditions
di i
Maximum Propagation
Delay, A to Y
Min
TA ≤ 125°C
Typ
Max
Min
Max
Min
Max
U i
Unit
ns
VCC = 3.3 ± 0.3 V
CL = 15pF
CL = 50pF
8.3
10.8
12.8
16.3
1.0
1.0
15.0
18.5
1.0
1.0
17.0
20.5
VCC = 5.0 ± 0.5 V
CL = 15pF
CL = 50pF
5.5
7.0
8.6
10.6
1.0
1.0
10.0
12.0
1.0
1.0
11.5
13.5
4
10
Maximum Input
Capacitance
10
10
pF
Typical @ 25°C, VCC = 5.0 V
CPD
P
Power
Dissipation
Di i i C
Capacitance
i
(N
(Note 1
1.))
pF
F
21
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 6 (per buffer). CPD is used to determine the no–load
dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0 V)
TA = 25°C
S b l
Symbol
Ch
Characteristic
i i
Typ
Max
U i
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.4
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
– 0.4
– 0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
3.5
V
VILD
Maximum Low Level Dynamic Input Voltage
1.5
V
TEST POINT
3.0V
A
1.5V
OUTPUT
GND
tPLH
DEVICE
UNDER
TEST
tPHL
VOH
Y
CL*
1.5V
VOL
* Includes all probe and jig capacitance
Figure 1. Switching Waveforms
Figure 2. Test Circuit
(a) A Schmitt–Trigger Squares Up Inputs With Slow Rise and Fall Times
VH
Vin
(b) A Schmitt–Trigger Offers Maximum Noise Immunity
VCC
VH
VT+
VT–
Vin
VCC
VT+
VT–
GND
GND
VOH
VOH
Vout
Vout
VOL
VOL
Figure 3. Typical Schmitt–Trigger Applications
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
3
MOTOROLA
MC74VHCT14A
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
14
8
P 7 PL
–B–
1
0.25 (0.010)
7
G
D
0.25 (0.010)
MOTOROLA
M
T
F
J
M
K
14 PL
B
S
M
R X 45°
C
SEATING
PLANE
B
M
A
S
4
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.75
8.55
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7°
0°
0.228 0.244
0.010 0.019
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
MC74VHCT14A
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
–U–
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
A
–V–
K1
J J1
SECTION N–N
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
D
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
G
H
DETAIL E
5
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.020
0.024
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MOTOROLA
MC74VHCT14A
OUTLINE DIMENSIONS
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 965–01
ISSUE O
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
L
7
1
M_
DETAIL P
Z
D
VIEW P
A
e
c
A1
b
0.13 (0.005)
MOTOROLA
M
0.10 (0.004)
6
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
–––
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
–––
1.42
INCHES
MIN
MAX
–––
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
–––
0.056
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
MC74VHCT14A
NOTES
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
7
MOTOROLA
MC74VHCT14A
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MC74VHCT14A/D
8
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
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