ICST ICS952801YFT Programmable timing control hubtm for k8tm processor Datasheet

ICS952801
Advance Information
Integrated
Circuit
Systems, Inc.
Programmable Timing Control Hub™ for K8™ processor
Recommended Application:
SiS755/760 style chipset for AMD K8 Processor
Output Features:
•
2 - Pairs of differential push-pull K8CPU outputs
•
8 - PCICLK @ 3.3V
•
2 - AGPCLK @ 3.3V
•
3 - REF @ 3.3V
•
2 - ZCLK @ 3.3V
•
1 - 24_48MHz @ 3.3V
•
1 - 48MHz @ 3.3V
Key Specifications:
•
CPU Output Jitter <250ps
•
AGP Output Jitter <250ps
•
ZCLK Output Jitter <250ps
•
PCI Output Jitter <500ps
Features/Benefits:
•
QuadRomTM frequency selection.
•
Selectable synchronous/asynchronous AGP/PCI/ZCLK
frequency
•
Linear Programmable CPU output frequency.
•
Linear Programmable AGP/PCI output frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system if system
malfunctions.
•
Programmable watch dog safe frequency.
•
Support I2C Index read/write and block read/write
operations.
•
Uses external 14.318MHz referience input.
Functionality
Pin Configuration
Bit3
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit2
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit0
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
200.00
200.00
200.00
200.00
233.33
233.33
233.33
233.33
266.67
266.67
266.67
266.67
293.34
293.34
293.34
293.34
133.33
133.33
133.33
133.33
166.67
166.67
166.67
166.67
202.00
202.00
202.00
202.00
220.00
220.00
220.00
220.00
ZCLK
MHz
66.67
100.00
133.33
166.67
66.67
93.33
133.33
175.00
66.67
106.67
133.33
160.00
73.34
117.34
146.66
176.00
66.67
100.00
133.33
166.67
66.67
100.00
133.33
166.67
67.34
101.00
134.66
168.34
73.34
110.00
146.66
183.34
AGP
MHz
66.67
66.67
66.67
66.67
66.67
66.67
66.67
70.00
66.67
66.67
66.67
66.67
73.33
73.33
73.33
73.33
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
67.33
67.33
67.33
67.33
73.33
73.33
73.33
73.33
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
35.00
33.33
33.33
33.33
33.33
36.66
36.66
36.66
36.66
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
36.66
36.66
36.66
36.66
VDDREF 1
48 CPU_STOP#*
**FS0/REF0 2
47 GNDCPU
**FS1/REF1 3
46 CPUCLK8T1
**FS2/REF2 4
45 CPUCLK8C1
44 VDDCPU
GNDREF 5
X1 6
43 VDDCPU
X2 7
42 CPUCLK8T0
GNDZ 8
41 CPUCLK8C0
40 GNDCPU
ZCLK0 9
ZCLK1 10
VDDZ 11
*PCI_STOP# 12
**FS3/PCICLK_F0 13
**FS4/PCICLK_F1 14
VDDPCI 15
ICS952801
Bit4
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GNDPCI 16
39 AGND
38 AVDD
37 PD#*
36 GNDAGP
35 AGPCLK0
34 AGPCLK1
33 VDDAGP
32 SCLK
31 AVDD48
PCICLK0 17
PCICLK1 18
30 48MHz
29 24_48MHz/SEL24_48MHz*
PCICLK2 19
PCICLK3 20
PCICLK5 22
28 GND48
27 SDATA
GNDPCI 23
26 PCICLK7
VDDPCI 24
25 PCICLK6
PCICLK4 21
48-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
0719—01/22/03
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
General Description
The ICS952801 is a two chip clock solution for desktop designs using SIS 755/760 style chipsets. When used with a zero
delay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks
signals for such a system.
The ICS952801 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
Frequency
Dividers
PLL2
48MHz
24_48MHz
X1
X2
XTAL
REF (2:0)
CPUCLK8T (1:0)
CPUCLK8C (1:0)
Programmable
Spread
PLL1
PD#
CPU_STOP#
PCI_STOP#
FS (4:0)
SEL24_48MHZ
Programmable
Frequency
Dividers
Control
Logic
PCICLK (5:0)
PCICLKF (1:0)
ZCLK (1:0)
Power Groups
Pin Number
VDD
AGPCLK (1:0)
STOP
Logic
GND
Description
1
5
REF Output, Crystal
31
28
24/48MHz, Fix Analog, Fix Digital
38
36
CPU PLL, CPU Analog, MCLK
0719—01/22/03
2
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
Pin Description
PIN
PIN
PIN
#
NAME
TYPE
1
VDDREF
2
3
4
5
6
7
8
9
10
11
**FS0/REF0
**FS1/REF1
**FS2/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
ZCLK1
VDDZ
DESCRIPTION
PWR Ref, XTAL power supply, nominal 3.3V
I/O
I/O
I/O
PWR
IN
OUT
PWR
OUT
OUT
PWR
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ground pin for the REF outputs.
Crystal input,nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin for the ZCLK outputs
3.3V Hyperzip clock output.
3.3V Hyperzip clock output.
Power supply for ZCLK clocks, nominal 3.3V
PCI clock output, this output is activated by the Mode selection pin / Stops all PCICLKs
12
I/O
*PCI_STOP#
besides the PCICLK_F clocks at logic 0 level, when input low.
13 **FS3/PCICLK_F0
I/O Frequency select latch input pin / 3.3V PCI free running clock output.
14 **FS4/PCICLK_F1
I/O Frequency select latch input pin / 3.3V PCI free running clock output.
15 VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
16 GNDPCI
PWR Ground pin for the PCI outputs
17 PCICLK0
OUT PCI clock output.
18 PCICLK1
OUT PCI clock output.
19 PCICLK2
OUT PCI clock output.
20 PCICLK3
OUT PCI clock output.
21 PCICLK4
OUT PCI clock output.
22 PCICLK5
OUT PCI clock output.
23 GNDPCI
PWR Ground pin for the PCI outputs
24 VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
25 PCICLK6
OUT PCI clock output.
26 PCICLK7
OUT PCI clock output.
27 SDATA
I/O Data pin for I2C circuitry 5V tolerant
28 GND48
PWR Ground pin for the 48MHz outputs
24/48MHz clock output / Latched select input for 24/48MHz output. 0=24mHz, 1 =
29 24_48MHz/SEL24_48MHz* I/O
48MHz.
30 48MHz
OUT 48MHz clock output.
31 AVDD48
PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
32 SCLK
IN Clock pin of I2C circuitry 5V tolerant
33 VDDAGP
PWR Power supply for AGP clocks, nominal 3.3V
34 AGPCLK1
OUT AGP clock output
35 AGPCLK0
OUT AGP clock output
36 GNDAGP
PWR Ground pin for the AGP outputs
Asynchronous active low input pin used to power down the device into a low power
37 PD#*
IN state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 1.8ms.
38 AVDD
PWR 3.3V Analog Power pin for Core PLL
39 AGND
PWR Analog Ground pin for Core PLL
40 GNDCPU
PWR Ground pin for the CPU outputs
41 CPUCLK8C0
OUT "Complementary" clocks of differential 3.3V push-pull K8 pair.
42 CPUCLK8T0
OUT "True" clocks of differential 3.3V push-pull K8 pair.
43 VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
44 VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
45 CPUCLK8C1
OUT "Complementary" clocks of differential 3.3V push-pull K8 pair.
46 CPUCLK8T1
OUT "True" clocks of differential 3.3V push-pull K8 pair.
47 GNDCPU
PWR Ground pin for the CPU outputs
48 CPU_STOP#*
IN Stops all CPUCLK besides the free running clocks
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
0719—01/22/03
3
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
General I2C serial interface information for the ICS952801
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each
byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
0719—01/22/03
4
Not acknowledge
stoP bit
Integrated
Circuit
Systems, Inc.
Table1: QuadRom Frequency Selection Table
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
X
X
FS4
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
0
1
0
1
1
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
0
0
1
1
0
1
0
0
0
1
1
0
1
1
0
0
1
1
1
0
0
0
0
1
1
1
0
1
0
0
1
1
1
1
0
0
0
1
1
1
1
1
ICS952801
Advance Information
CPU
MHz
200.00
200.00
200.00
200.00
233.33
233.33
233.33
233.33
266.67
266.67
266.67
266.67
293.34
293.34
293.34
293.34
133.33
133.33
133.33
133.33
166.67
166.67
166.67
166.67
202.00
202.00
202.00
202.00
220.00
220.00
220.00
220.00
ZCLK
MHz
66.67
100.00
133.33
166.67
66.67
93.33
133.33
175.00
66.67
106.67
133.33
160.00
73.34
117.34
146.66
176.00
66.67
100.00
133.33
166.67
66.67
100.00
133.33
166.67
67.34
101.00
134.66
168.34
73.34
110.00
146.66
183.34
0719—01/22/03
5
AGP
MHz
66.67
66.67
66.67
66.67
66.67
66.67
66.67
70.00
66.67
66.67
66.67
66.67
73.33
73.33
73.33
73.33
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
67.33
67.33
67.33
67.33
73.33
73.33
73.33
73.33
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
35.00
33.33
33.33
33.33
33.33
36.66
36.66
36.66
36.66
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
36.66
36.66
36.66
36.66
Spread
%
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
B24b2:1 =11
B24b2:1 =11
B24b2:1 =11
B24b2:1 =11
Spread Off
Spread Off
Spread Off
Spread Off
Integrated
Circuit
Systems, Inc.
Table1: QuadRom Frequency Selection Table Continued
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CPU
X
X
FS4
FS3
FS2
FS1
FS0
MHz
0
1
0
0
0
0
0
206.00
0
1
0
0
0
0
1
206.00
0
1
0
0
0
1
0
206.00
0
1
0
0
0
1
1
206.00
0
1
0
0
1
0
0
240.33
0
1
0
0
1
0
1
240.33
0
1
0
0
1
1
0
240.33
0
1
0
0
1
1
1
240.33
0
1
0
1
0
0
0
274.67
0
1
0
1
0
0
1
274.67
0
1
0
1
0
1
0
274.67
0
1
0
1
0
1
1
274.67
0
1
0
1
1
0
0
302.14
0
1
0
1
1
0
1
302.14
0
1
0
1
1
1
0
302.14
0
1
0
1
1
1
1
302.14
0
1
1
0
0
0
0
137.33
0
1
1
0
0
0
1
137.33
0
1
1
0
0
1
0
137.33
0
1
1
0
0
1
1
137.33
0
1
1
0
1
0
0
171.67
0
1
1
0
1
0
1
171.67
0
1
1
0
1
1
0
171.67
0
1
1
0
1
1
1
171.67
0
1
1
1
0
0
0
208.06
0
1
1
1
0
0
1
208.06
0
1
1
1
0
1
0
208.06
0
1
1
1
0
1
1
208.06
0
1
1
1
1
0
0
226.60
0
1
1
1
1
0
1
226.60
0
1
1
1
1
1
0
226.60
0
1
1
1
1
1
1
226.60
ICS952801
Advance Information
ZCLK
MHz
68.67
103.00
137.33
171.67
68.67
96.13
137.33
180.25
68.67
109.87
137.33
164.80
75.54
120.86
151.06
181.28
68.67
103.00
137.33
171.67
68.67
103.00
137.33
171.67
69.36
104.03
138.70
173.39
75.54
113.30
151.06
188.84
0719—01/22/03
6
AGP
MHz
68.67
68.67
68.67
68.67
68.67
68.67
68.67
72.10
68.67
68.67
68.67
68.67
75.53
75.53
75.53
75.53
68.67
68.67
68.67
68.67
68.67
68.67
68.67
68.67
69.35
69.35
69.35
69.35
75.53
75.53
75.53
75.53
PCI
MHz
34.33
34.33
34.33
34.33
34.33
34.33
34.33
36.05
34.33
34.33
34.33
34.33
37.76
37.76
37.76
37.76
34.33
34.33
34.33
34.33
34.33
34.33
34.33
34.33
34.67
34.67
34.67
34.67
37.76
37.76
37.76
37.76
Spread
%
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Integrated
Circuit
Systems, Inc.
Table1: QuadRom Frequency Selection Table Continued
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CPU
X
X
FS4
FS3
FS2
FS1
FS0
MHz
1
0
0
0
0
0
0
214.00
1
0
0
0
0
0
1
214.00
1
0
0
0
0
1
0
214.00
1
0
0
0
0
1
1
214.00
1
0
0
0
1
0
0
249.66
1
0
0
0
1
0
1
249.66
1
0
0
0
1
1
0
249.66
1
0
0
0
1
1
1
249.66
1
0
0
1
0
0
0
285.34
1
0
0
1
0
0
1
285.34
1
0
0
1
0
1
0
285.34
1
0
0
1
0
1
1
285.34
1
0
0
1
1
0
0
313.87
1
0
0
1
1
0
1
313.87
1
0
0
1
1
1
0
313.87
1
0
0
1
1
1
1
313.87
1
0
1
0
0
0
0
142.66
1
0
1
0
0
0
1
142.66
1
0
1
0
0
1
0
142.66
1
0
1
0
0
1
1
142.66
1
0
1
0
1
0
0
178.34
1
0
1
0
1
0
1
178.34
1
0
1
0
1
1
0
178.34
1
0
1
0
1
1
1
178.34
1
0
1
1
0
0
0
216.14
1
0
1
1
0
0
1
216.14
1
0
1
1
0
1
0
216.14
1
0
1
1
0
1
1
216.14
1
0
1
1
1
0
0
235.40
1
0
1
1
1
0
1
235.40
1
0
1
1
1
1
0
235.40
1
0
1
1
1
1
1
235.40
ICS952801
Advance Information
ZCLK
MHz
71.34
107.00
142.66
178.34
71.33
99.86
142.66
187.25
71.34
114.14
142.66
171.20
78.47
125.55
156.93
188.32
71.34
107.00
142.66
178.34
71.34
107.00
142.66
178.34
72.05
108.07
144.09
180.12
78.47
117.70
156.93
196.17
0719—01/22/03
7
AGP
MHz
71.33
71.33
71.33
71.33
71.33
71.33
71.33
74.90
71.33
71.33
71.33
71.33
78.47
78.47
78.47
78.47
71.33
71.33
71.33
71.33
71.33
71.33
71.33
71.33
72.05
72.05
72.05
72.05
78.47
78.47
78.47
78.47
PCI
MHz
35.66
35.66
35.66
35.66
35.66
35.66
35.66
37.45
35.66
35.66
35.66
35.66
39.23
39.23
39.23
39.23
35.66
35.66
35.66
35.66
35.66
35.66
35.66
35.66
36.02
36.02
36.02
36.02
39.23
39.23
39.23
39.23
Spread
%
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Integrated
Circuit
Systems, Inc.
Table1: QuadRom Frequency Selection Table Continued
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CPU
X
X
FS4
FS3
FS2
FS1
FS0
MHz
1
1
0
0
0
0
0
220.00
1
1
0
0
0
0
1
220.00
1
1
0
0
0
1
0
220.00
1
1
0
0
0
1
1
220.00
1
1
0
0
1
0
0
256.66
1
1
0
0
1
0
1
256.66
1
1
0
0
1
1
0
256.66
1
1
0
0
1
1
1
256.66
1
1
0
1
0
0
0
293.34
1
1
0
1
0
0
1
293.34
1
1
0
1
0
1
0
293.34
1
1
0
1
0
1
1
293.34
1
1
0
1
1
0
0
322.67
1
1
0
1
1
0
1
322.67
1
1
0
1
1
1
0
322.67
1
1
0
1
1
1
1
322.67
1
1
1
0
0
0
0
146.66
1
1
1
0
0
0
1
146.66
1
1
1
0
0
1
0
146.66
1
1
1
0
0
1
1
146.66
1
1
1
0
1
0
0
183.34
1
1
1
0
1
0
1
183.34
1
1
1
0
1
1
0
183.34
1
1
1
0
1
1
1
183.34
1
1
1
1
0
0
0
222.20
1
1
1
1
0
0
1
222.20
1
1
1
1
0
1
0
222.20
1
1
1
1
0
1
1
222.20
1
1
1
1
1
0
0
242.00
1
1
1
1
1
0
1
242.00
1
1
1
1
1
1
0
242.00
1
1
1
1
1
1
1
242.00
ICS952801
Advance Information
ZCLK
MHz
73.34
110.00
146.66
183.34
73.33
102.66
146.66
192.50
73.34
117.34
146.66
176.00
80.67
129.07
161.33
193.60
73.34
110.00
146.66
183.34
73.34
110.00
146.66
183.34
74.07
111.10
148.13
185.17
80.67
121.00
161.33
201.67
0719—01/22/03
8
AGP
MHz
73.33
73.33
73.33
73.33
73.33
73.33
73.33
77.00
73.33
73.33
73.33
73.33
80.67
80.67
80.67
80.67
73.33
73.33
73.33
73.33
73.33
73.33
73.33
73.33
74.07
74.07
74.07
74.07
80.67
80.67
80.67
80.67
PCI
MHz
36.66
36.66
36.66
36.66
36.66
36.66
36.66
38.50
36.66
36.66
36.66
36.66
40.33
40.33
40.33
40.33
36.66
36.66
36.66
36.66
36.66
36.66
36.66
36.66
37.03
37.03
37.03
37.03
40.33
40.33
40.33
40.33
Spread
%
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
2
I C Table: Function Control Register
Byte 0
Pin #
Name
26
25
-
PDEN
PCICLK7
WDS_EN
PCICLK6
AFS1
AFS0
Bit 1
-
AEN1
Bit 0
-
AEN0
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
Control
Function
PD# Enable
Output Control
WD Soft Enable
Output Control
Async Rom SEL_1
Async Rom SEL_0
Type
Zclk/Agp/Pci Freq
Source Select Control
Table 3: Asynchronous ZCLK Frequency Selection Table
0
1
PWD
RW
RW
RW
RW
RW
RW
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
See Table 3: Async Z-CLK
Frequency Selection Table
1
1
1
1
0
0
RW
See Table 4 : ZCLK, AGP &
PCI Frequency Source
Decode Table
0
RW
0
Table 4: ZCLK, AGP & PCI Frequency Source Decode Table
Byte0 Bit3
Byte0 Bit2
ZCLK Frequency
Byte0 Bit1
Byte0 Bit0
0
0
64.01
0
0
0
1
72.01
0
1
1
0
82.30
1
0
1
1
144.02
1
1
ZCLK & AGP & PCI
See Table 1, QuadRom
Frequency Table
N-Programming for
AGP/PCI/ZCLK
See Table 1 for AGP/PCI,
Table 3 for ZCLK
N-Programming for AGP/PCI,
Table 3 for ZCLK
2
I C Table: Async N-Programming Frequency Select Register
Byte 1
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Pin #
-
7
6
5
4
3
2
1
0
Name
Control
Function
Type
0
1
PWD
N PLL3 Div7
N PLL3 Div6
N PLL3 Div5
N PLL3 Div4
N PLL3 Div3
N PLL3 Div2
N PLL3 Div1
N PLL3 Div0
The decimal
representation of N
PLL2 Div (7:0) + 8 is
equal to VCO divider
value for PLL2. Default
at power up =
66.67MHz
RW
RW
RW
RW
RW
RW
RW
RW
-
-
0
1
0
0
0
1
1
1
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
RW
RW
-
-
1
1
1
1
1
1
1
1
2
I C Table: Reserved Register
Byte 2
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0719—01/22/03
9
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
2
I C Table: Reserved Register
Byte 3
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Pin #
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
7
6
5
4
3
2
1
0
-
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
RW
RW
-
-
1
1
1
1
1
1
1
1
Type
0
1
PWD
2
I C Table: Frequency Select Register
Byte 4
Pin #
Name
7
6
5
4
-
FS3
FS2
FS1
FS0
Bit 3
-
FS Source
Bit 2
Bit 1
Bit 0
-
FS4
SS_EN
Outputs
Bit
Bit
Bit
Bit
Control
Function
Freq Select Bit 7
Freq Select Bit 6
Freq Select Bit 5
Freq Select Bit 4
Frequency HW/IIC
Select
Freq Select Bit 2
Spread Enable
Output Control
RW
RW
RW
RW
See Table1 : Quad Rom
Frequency Selection Table
0
0
0
0
RW
Latch Input
0
RW
RW
RW
IIC
See Table1
OFF
ON
Running
Tri-state
0
1
0
2
I C Table: Read Back Register
Byte 5
Pin #
Name
Bit 7
-
WDHRB
Bit 6
-
WDSRB
Bit
Bit
Bit
Bit
Bit
Bit
-
MULTISEL
FS4RB
FS3RB
FS2RB
FS1RB
FS0RB
5
4
3
2
1
0
Control
Function
WD Hard Alarm Status
Read back
WD Soft Alarm Status
Read back
Multisel Read back
FS4 Read back
FS3 Read back
FS2 Read back
FS1 Read back
FS0 Read back
Type
0
1
PWD
R
Normal
Alarm
X
R
Normal
Alarm
X
R
R
R
R
R
R
-
-
X
X
X
X
X
X
Type
0
1
PWD
2
I C Table: Output Control Register
7
6
5
4
3
10
9
13
14
42, 41
ZCLK_1
ZCLK_0
PCICLK_F0
PCICLK_F1
CPUCLK8T0/C0
Control
Function
Output Control
Output Control
PCI_STOP# Control
PCI_STOP# Control
CPU_STOP# Control
Bit 2
Bit 1
Bit 0
46, 45
42, 41
46, 45
CPUCLK8T1/C1
CPUCLK8T0/C0
CPUCLK8T1/C1
CPU_STOP# Control
Output Control
Output Control
Byte 6
Bit
Bit
Bit
Bit
Bit
Pin #
Name
0719—01/22/03
10
RW
RW
RW
RW
RW
Disable
Enable
Disable
Enable
Stop Disable Stop Enable
Stop Disable Stop Enable
Stop Disable Stop Enable
1
1
0
0
1
RW
RW
RW
Stop Disable Stop Enable
Disable
Enable
Disable
Enable
1
1
1
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
2
I C Table: Output Control Register
Byte 7
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Pin #
14
13
22
21
20
19
18
17
7
6
5
4
3
2
1
0
Name
PCICLK_F1
PCICLK_F0
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Control
Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Control
Function
Type
0
1
PWD
Writing to this register
will configure how
many bytes will be read
back, default is 0F = 15
bytes.
RW
RW
RW
RW
RW
RW
RW
RW
-
-
0
0
0
0
1
1
1
1
Control
Function
Type
0
1
PWD
These bits represent
X*290ms the watchdog
timer will wait before it
goes to alarm mode.
Default is 16 X 290ms
=4.64 seconds
RW
RW
RW
RW
RW
RW
RW
RW
-
-
0
0
0
1
0
0
0
0
2
I C Table: Byte Count Register
Byte 8
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Pin #
-
7
6
5
4
3
2
1
0
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
2
I C Table: Watchdog Timer Register
Byte 9
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
-
2
I C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Name
Control
Function
Type
0
1
PWD
M/N Programming
Enable
RW
Disable
Enable
0
R
RW
RW
RW
RW
RW
RW
Disable
-
Enable
-
0
0
0
0
0
0
1
Bit 7
-
M/NEN
Bit
Bit
Bit
Bit
Bit
Bit
Bit
-
WDEN
Reserved
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
6
5
4
3
2
1
0
Watchdog Enable
Reserved
Writing to these bit will
configure the safe
frequency as Byte4bit
2, (7:4), Byte 24bit(6:5)
0719—01/22/03
11
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
2
I C Table: VCO Frequency Control Register
Byte 11
Pin #
Bit 7
-
N Div8
Bit 6
-
M Div6
Bit
Bit
Bit
Bit
Bit
Bit
-
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
5
4
3
2
1
0
Control
Function
N Divider Bit 8
Name
The decimal
representation of M Div
(6:0) + 2 is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
Type
0
1
PWD
RW
-
-
X
RW
-
-
X
RW
RW
RW
RW
RW
RW
-
-
X
X
X
X
X
X
2
I C Table: VCO Frequency Control Register
Byte 12
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
Control
Function
Type
0
1
PWD
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
The decimal
representation of N Div
(8:0) + 8 is equal to
VCO divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
RW
RW
RW
RW
RW
RW
RW
RW
-
-
X
X
X
X
X
X
X
X
2
I C Table: Spread Spectrum Control Register
Byte 13
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
Control
Function
Type
0
1
PWD
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
These Spread
Spectrum bits will
program the spread
pecentage. It is
recommended to use
ICS Spread % table for
spread programming.
RW
RW
RW
RW
RW
RW
RW
RW
-
-
X
X
X
X
X
X
X
X
Type
0
1
PWD
R
R
RW
RW
RW
RW
RW
RW
-
-
0
0
X
X
X
X
X
X
2
I C Table: Spread Spectrum Control Register
Byte 14
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
Reserved
Reserved
SSP13
SSP12
SSP11
SSP10
SSP9
SSP8
Control
Function
Reserved
Reserved
It is recommended to
use ICS Spread %
table for spread
programming.
0719—01/22/03
12
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
2
I C Table: Output Divider Control Register
Byte 15
Pin #
7
6
5
4
3
2
-
Reserved
Reserved
Reserved
Reserved
CPU Div3
CPU Div2
Bit 1
-
CPU Div1
Bit 0
-
CPU Div0
Bit
Bit
Bit
Bit
Bit
Bit
Control
Function
Reserved
Reserved
Reserved
Reserved
Name
CPU divider ratio can
be configured via these
4 bits individually.
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
-
-
X
X
X
X
X
X
RW
See Table 5: Divider Ratio
Combination Table
X
RW
X
Table 5: CPU Divider Ratio Combination Table
Divider (3:2)
Bit
00
01
10
Divider (1:0)
1
2
11
MSB
8
4
00
0000
2
0100
4
1000
8
1100
16
01
0001
3
0101
6
1001
12
1101
24
10
0010
5
0110
10
1010
20
1110
40
11
0011
7
0111
14
1011
28
1111
56
LSB
Address
Div
Address
Div
Address
Div
Address
Div
2
I C Table: Output Divider Control Register
Byte 16
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
RW
RW
-
-
X
X
X
X
X
X
X
X
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
RW
RW
Default
-
Inverse
-
X
X
X
X
X
X
X
X
2
I C Table: Output Divider Control Register
Byte 17
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
Reserved
Reserved
Reserved
CPUINV
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
CPU Phase Invert
Reserved
Reserved
Reserved
Reserved
0719—01/22/03
13
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
2
I C Table: Group Skew Control Register
Byte 18
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Pin #
Name
-
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
RW
RW
-
-
X
X
X
X
X
X
X
X
Type
0
1
PWD
2
I C Table: Group Skew Control Register
Byte 19
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Pin #
Name
-
7
6
5
4
3
2
1
0
ZCLKSkw1
ZCLKSkw0
Reserved
Reserved
AGPSkw1
AGPSkw0
Reserved
Reserved
Control
Function
CPU-ZCLK Skew
Control
Reserved
Reserved
CPU-AGP Skew
Control
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
See Table 6: 4-Steps Skew
Programming Table
See Table 6: 4-Steps Skew
Programming Table
-
0
0
0
0
0
0
0
0
2
I C Table: Group Skew Control Register
Byte 20
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Pin #
Name
PCI_FSkw1
PCI_FSkw0
Reserved
Reserved
PCISkw1
PCISkw0
Reserved
Reserved
-
7
6
5
4
3
2
1
0
Control
Function
CPU-PCI_F Skew
Control
Reserved
Reserved
CPU-PCI Skew Control
Reserved
Reserved
Table 6: 4-Steps Skew Programming Table
4 Step
0
1
LSB
0
0ps
250ps
-
1
500ps
750ps
-
MSB
-
-
-
0719—01/22/03
14
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
See Table 6: 4-Steps Skew
Programming Table
See Table 6: 4-Steps Skew
Programming Table
-
PWD
0
0
0
0
0
0
0
0
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
2
I C Table: Slew Rate Control Register
Byte 21
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
24/48Slw1
24/48Slw0
AGPSlw1
AGPSlw0
ZCLKSlw1
ZCLKSlw0
REFSlw1
REFSlw0
Control
Function
24/48 Slew Rate
Control
AGP Slew Rate Control
ZCLK Slew Rate
Control
REF Slew Rate Control
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
RW
RW
-
-
0
0
0
0
0
0
0
0
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
-
Enable
Enable
-
0
0
1
1
0
0
0
RW
-
-
0
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
RW
RW
48MHz
Disable
Disable
Disable
Disable
Disable
24MHz
Enable
Enable
Enable
Enable
Enable
0
1
1
1
1
1
1
1
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
RW
RW
-
-
0
0
0
0
0
0
0
0
2
I C Table: Slew Rate Control Register
Byte 22
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
34
35
-
Name
SDSlw1
SDSlw0
AGPCLK1
AGPCLK0
PCI_FSlw1
PCI_FSlw0
PCISlw1
PCISlw0
Control
Function
SD Slew Rate Control
Output Control
Output Control
PCI_F Slew Rate
Control
PCI Slew Rate Control
2
I C Table: Output Control Register
Byte 23
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
30
29
4
3
2
Name
Reserved
SEL24_48
Reserved
48MHz
24_48MHz
REF2
REF1
REF0
Control
Function
Reserved
24MHz or 48MHz
Reserved
Output Control
Output Control
Output Control
Output Control
Output Control
2
I C Table: Reserved Register
Byte 24
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
Reserved
FS6
FS5
Reserved
Reserved
SS_SEL
SS_SEL
Reserved
Control
Function
Reserved
Freq Select bit 6
Freq Select bit 5
Reserved
Reserved
SS Scheme Select1
SS Scheme Select1
Reserved
0719—01/22/03
15
See Table 1
See Table 2: Spread
Spectrum Selection Table
-
-
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
Table2: Spread Spectrum Select Table
SS1
(Byte 24 bit 2)
SS0
(Byte 24 bit 1)
For Spreadable
Frequency Only
0
0
0.35%
0
1
0.50%
1
0
0.75%
1
1
2.50%
0719—01/22/03
16
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . .
4.6 V
3.6V
GND –0.5 V to VDD +0.5 V
0°C to +70°C
–65°C to +150°C
115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating Supply
Current
Power Down Supply
Current
Input frequency
Input Capacitance1
1
Transition Time
Clk Stabilization1
Skew1
SYMBOL
CONDITIONS
MIN
2
VIH
VSS - 0.3
VIL
VIN = VDD
IIH
VIN = 0 V; Inputs with no pull-up resistors
-5
IIL1
VIN = 0 V; Inputs with pull-up resistors
-200
IIL2
IDD(op)
IDDPD
Fi
CIN
CINX
Ttrans
TSTAB
TCPU-PCI
CL = 0 pF; Select @ 100MHz
CL = 0 pF; With input address to Vdd or
GND
VDD = 3.3 V;
Logic Inputs
X1 & X2 pins
To 1st crossing of target Freq.
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V
1
Guaranteed by design, not 100% tested in production.
0719—01/22/03
17
11
27
1.5
TYP
MAX
UNITS
VDD + 0.3
V
0.8
V
5
mA
mA
mA
180
mA
40
mA
16
5
45
3
3
4
MHz
pF
pF
ms
ms
ns
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
Electrical Characteristics - ZCLK
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
SYMBOL
FO1
Output Impedance
RDSP11
Output High Voltage
Skew
V OH1
V OL1
I OH1
I OL1
t r11
t f11
dt11
t sk11
Jitter
t jcyc-cyc 1
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
CONDITIONS
MIN
V O = V DD*(0.5)
12
I OH = -1 mA
2.4
I OL = 1 mA
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
V OL @MIN = 1.95 V, V OL @MAX = 0.4 V
TYP
MAX UNITS
MHz
55
Ω
V
-33
30
0.55
-33
38
V
mA
mA
V OL = 0.4 V, V OH = 2.4 V
0.5
2
ns
V OH = 2.4 V, V OL = 0.4 V
V T = 1.5 V
0.5
45
2
55
ns
%
250
ps
250
ps
V T = 1.5 V
V T = 1.5 V 3V66
Electrical Characteristics - AGPCLK, ZCLK
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
SYMBOL
FO1
Output Impedance
RDSP11
Output High Voltage
V OH1
V OL1
I OH1
I OL1
t r11
t f11
dt11
t sk11
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
Jitter
t jcyc-cyc
1
CONDITIONS
MIN
V O = V DD*(0.5)
12
I OH = -1 mA
2.4
TYP
MAX UNITS
MHz
55
Ω
V
mA
mA
V
I OL = 1 mA
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
V OL @MIN = 1.95 V, V OL @MAX = 0.4 V
-33
30
0.55
-33
38
V OL = 0.4 V, V OH = 2.4 V
0.5
2
ns
V OH = 2.4 V, V OL = 0.4 V
V T = 1.5 V
0.5
45
2
55
ns
%
250
ps
250
ps
V T = 1.5 V
V T = 1.5 V 3V66
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V,+/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
1
SYMBOL
V OH1
V OL1
I OH1
I OL1
CONDITIONS
I OH = -18 mA
I OL = 9.4 mA
V OH = 2.0 V
V OL = 0.8 V
MIN
2.1
16
t r1
V OL = 0.4 V, V OH = 2.4 V
Fall Time1
t f1
V OH = 2.4 V, V OL = 0.4 V
Duty Cycle1
dt1
V T = 1.5 V
Skew1
t sk1
Jitter
t jcyc-cyc 1
t jabs1
TYP
MAX UNITS
V
0.4
V
-22
mA
57
mA
2
ns
2
ns
55
%
V T = 1.5 V
500
ps
V T = 1.5 V
V T = 1.5 V
500
500
ps
ps
45
Guaranteed by design, not 100% tested in production.
0719—01/22/03
18
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
Electrical Characteristics - 48MHz, 24_48MHz
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
1
Output Impedance
V O = V DD*(0.5)
RDSP1
1
IOH = -1 mA
Output High Voltage
VOH
1
Output Low Voltage
V OL
Output High Current
IOH1
Output Low Current
IOL1
Rise Time
tr11
tf11
dt11
Fall Time
Duty Cycle
Jitter
tjcyc-cyc
MIN
20
TYP
2.4
OH@MIN
= 1.0 V
V OH@MAX = 3.135 V
VOL @MIN = 1.95 V
UNITS
Ω
V
IOL = 1 mA
V
MAX
60
0.4
V
-23
mA
mA
ns
-29
29
V OL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
0.5
27
1
VOH = 2.4 V, VOL = 0.4 V
0.5
1
ns
VT = 1.5 V
45
55
%
350
ps
1
VT = 1.5 V
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
VOL5
I OH5
I OL5
tr5
VOL = 0.4 V, VOH = 2.4 V
4
ns
Fall Time1
tf5
VOH = 2.4 V, V OL = 0.4 V
4
ns
Duty Cycle
dt5
Jitter1
tjcyc-cyc5
tjabs5
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
55
1000
800
%
ps
ps
1
CONDITIONS
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.6
16
45
0719—01/22/03
19
TYP
MAX UNITS
V
0.4
V
-22
mA
mA
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output High Voltage
Output Low Voltage
Output Low Current
CONDITIONS
VO = VX
MIN
15
1
V OL = 0.3 V
18
Rise Edge Rate
Measured from 20-80%
1
Measured from 80-20%
1
Fall Edge Rate
VDIFF
DVDIFF
VCM
DVCM
SYMBOL
ZO
V OH2B
V OL2B
IOL2B
Differential Voltage,
Measured @ the Hammer
test load (single-ended
measurement)
Change in VDIFF_DC
magnitude, Measured @
the Hammer test load
(single-ended
measurement)
Common Mode Voltage,
Measured @ the Hammer
test load (single-ended
measurement)
Change in Common Mode
Voltage, Measured @ the
Hammer test load (singleended measurement)
TYP
MAX
55
1.2
0.4
UNITS
W
V
V
mA
2
7
V/ns
2
7
V/ns
0.4
2.3
V
-150
150
mV
1.05
1.45
V
-200
200
mV
dt2B
V T = 50%
45
53
%
Duty Cycle1
t jcyc-cyc2B
VT = VX
0
200
ps
Jitter, Cycle-to-cycle1
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (V TR-V CP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level.
3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max=(Vpullup(external)/2)+150mV
0719—01/22/03
20
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K)
resistor is used to provide both the solid CMOS programming
voltage needed during the power-up programming period and to
provide an insignificant load on the output clock during the
subsequent operating period.
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
0719—01/22/03
21
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
c
N
SYMBOL
L
E1
E
INDEX
AREA
1 2
α
h x 45°
D
A
A
A1
b
c
D
E
E1
e
h
L
N
α
A1
-Ce
b
SEATING
PLANE
.10 (.004) C
N
48
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
VARIATIONS
D mm.
MIN
MAX
15.75
16.00
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
D (inch)
MIN
.620
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS952801yFT
Example:
ICS XXXXX y F - T
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0719—01/22/03
22
MAX
.630
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