Sharp LH543601M-20 256 x 36 x 2 bidirectional fifo Datasheet

LH543601
256 × 36 × 2 Bidirectional FIFO
FEATURES
FUNCTIONAL DESCRIPTION
• Fast Cycle Times: 20/25/30/35 ns
• Pin-Compatible and Functionally-Compatible
The LH543601 contains two FIFO buffers, FIFO #1
and FIFO #2. These operate in parallel, but in opposite
directions, for bidirectional data buffering. FIFO #1 and
FIFO #2 each are organized as 256 by 36 bits. The
LH543601 is ideal either for wide unidirectional applications or for bidirectional data applications; component
count and board area are reduced.
0.7µ-Technology Replacement for Sharp LH5420
•
•
•
•
Two 256 × 36-bit FIFO Buffers
Full 36-bit Word Width
Selectable 36/18/9-bit Word Width on Port B
Independently-Synchronized (‘Fully-Asynchronous’)
Operation of Port A and Port B
• ‘Synchronous’ Enable-Plus-Clock Control at
Both Ports
• R/W, Enable, Request, and Address Control Inputs
are Sampled on the Rising Clock Edge
• Synchronous Request/Acknowledge ‘Handshake’
Capability; Use is Optional
• Device Comes Up Into a Known Default State at
Reset; Programming is Allowed, but is not Required
• Asynchronous Output Enables
• Five Status Flags per Port: Full, Almost-Full,
Half-Full, Almost-Empty, and Empty
• Almost-Full Flag and Almost-Empty Flag are
Programmable
•
•
•
•
•
Mailbox Registers with Synchronized Flags
Data-Bypass Function
Data-Retransmit Function
Automatic Byte Parity Checking
8 mA-IOL High-Drive Three-State Outputs with
Built-In Series Resistor
• TTL/CMOS-Compatible I/O
• Space-Saving PQFP and TQFP Packages
• PQFP to PGA Package Conversion 1
The LH543601 has two 36-bit ports, Port A and Port B.
Each port has its own port-synchronous clock, but the two
ports may operate asynchronously relative to each other.
Data flow is initiated at a port by the rising edge of the
appropriate clock; it is gated by the corresponding edgesampled enable, request, and read/write control signals.
At the maximum operating frequency, the clock duty cycle
may vary from 40% to 60%. At lower frequencies, the
clock waveform may be quite asymmetric, as long as the
minimum pulse-width conditions for clock-HIGH and
clock-LOW remain satisfied; the LH543601 is a fully-static
part.
Conceptually, the port clocks CKA and CKB are freerunning, periodic ‘clock’ waveforms, used to control other
signals which are edge-sensitive. However, there actually
is not any absolute requirement that these ‘clock’ waveforms must be periodic. An ‘asynchronous’ mode of
operation is possible, in one or both directions, independently, if the appropriate enable and request inputs
are continuously asserted, and enough aperiodic ‘clock’
pulses of suitable duration are generated by external logic
to cause all necessary actions to occur.
A synchronous request/acknowledge handshake
facility is provided at each port for FIFO data access. This
request/ acknowledge handshake resolves FIFO full and
empty boundary conditions, when the two ports are operated asynchronously relative to each other.
FIFO status flags monitor the extent to which each
FIFO buffer has been filled. Full, Almost-Full, Half-Full,
Almost-Empty, and Empty flags are included for each
FIFO. The Almost-Full and Almost-Empty flags are programmable over the entire FIFO depth, but are automatically initialized to eight locations from the respective FIFO
boundaries at reset. A data block of 256 or fewer words
may be retransmitted any desired number of times.
NOTE:
1. For PQFP-to-PGA conversion for thru-hole board designs, Sharp
recommends ITT Pomona Electronics’ SMT/PGA Generic
Converter model #5853.® This converter maps the LH543601
132-pin PQFP to a generic 13 × 13, 132-pin PGA (100-mil
pitch). For more information, contact Sharp or ITT Pomona
Electronics at 1500 East Ninth Street, Pomona, CA 91766,
(909) 469-2900.
1
256 × 36 × 2 Bidirectional FIFO
LH543601
FUNCTIONAL DESCRIPTION (cont’d)
Two mailbox registers provide a separate path for
passing control words or status words between ports.
Each mailbox has a New-Mail-Alert Flag, which is synchronized to the reading port’s clock. This mailbox function facilitates the synchronization of data transfers
between asynchronous systems.
Data-bypass mode allows Port A to directly transfer
data to or from Port B at reset. In this mode, the device
acts as a registered transceiver under the control of
Port A. For instance, a master processor on Port A can
use the data bypass feature to send or receive initializa-
tion or configuration information directly, to or from a
peripheral device on Port B, during system startup.
A word-width-select option is provided on Port B for
36-bit, 18-bit, or 9-bit data access. This feature allows
word-width matching between Port A and Port B, with no
additional logic needed. It also ensures maximum utilization of bus bandwidths.
A Byte Parity Check Flag at each port monitors data
integrity. Control-Register bit 0 (zero) selects the parity
mode, odd or even. This bit is initialized for odd data parity
at reset; but it may be reprogrammed for even parity, or
back again to odd parity, as desired.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CHAMFERED
EDGE
TOP VIEW
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
VCCO
D24A
D25A
D26A
VSSO
D27A
D28A
D29A
VCCO
D30A
D31A
D32A
VSSO
D33A
D34A
D35A
RT2
VSS
D35B
D34B
VSSO
D33B
D32B
D31B
VCCO
D30B
D29B
D28B
VSSO
D27B
D26B
D25B
VCCO
D12B
D13B
D14B
D15B
VSSO
D16B
D17B
MBF1
AE1
EF1
ACKB
VSS
REQB
ENB
R/WB
CKB
A0B
WS0
WS1
OEB
VCC
FF2
AF2
HF2
PFB
D18B
D19B
D20B
VSSO
D21B
D22B
D23B
D24B
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
VCCO
D10A
D9A
D8A
VSSO
D7A
D6A
D5A
VCCO
D4A
D3A
D2A
VSSO
D1A
D0A
RS
RT1
D0B
D1B
D2B
VSSO
D3B
D4B
D5B
VCCO
D6B
D7B
D8B
VSSO
D9B
D10B
D11B
VCCO
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Pin 1
Pin 132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
D11A
D12A
D13A
D14A
VSSO
D15A
D16A
D17A
PFA
HF1
AF1
FF1
VCC
OEA
A2A
A1A
A0A
CKA
R/WA
ENA
REQA
VSS
ACKA
EF2
AE2
MBF2
D18A
D19A
VSSO
D20A
D21A
D22A
D23A
PIN CONNECTIONS
543601-30
Figure 1. Pin Connections for 132-Pin PQFP Package
(Top View)
2
256 × 36 × 2 Bidirectional FIFO
TOP VIEW
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
NC
D23A
D22A
D21A
D20A
VSSO
D19A
D18A
MBF2
AE2
EF2
ACKA
VSS
REQA
ENA
R/WA
CKA
NC
A0A
A1A
A2A
OEA
VCC
FF1
AF1
HF1
PFA
D17A
D16A
D15A
VSSO
D14A
D13A
D12A
D11A
NC
144-PIN TQFP
LH543601
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
NC
VCCO
D10A
D9A
D8A
VSSO
D7A
D6A
D5A
VCCO
D4A
D3A
D2A
VSSO
D1A
D0A
RS
RT1
NC
D0B
D1B
D2B
VSSO
D3B
D4B
D5B
VCCO
D6B
D7B
D8B
VSSO
D9B
D10B
D11B
VCCO
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NC
D24B
D23B
D22B
D21B
VSSO
D20B
D19B
D18B
PFB
HF2
AF2
FF2
VCC
OEB
WS1
WS0
NC
A0B
CKB
R/WB
ENB
REQB
VSS
ACKB
EF1
AE1
MBF1
D17B
D16B
VSSO
D15B
D14B
D13B
D12B
NC
NC
VCCO
D24A
D25A
D26A
VSSO
D27A
D28A
D29A
VCCO
D30A
D31A
D32A
VSSO
D33A
D34A
D35A
RT2
NC
VSS
D35B
D34B
VSSO
D33B
D32B
D31B
VCCO
D30B
D29B
D28B
VSSO
D27B
D26B
D25B
VCCO
NC
543601-38
Figure 2. Pin Connections for 144-Pin TQFP Package
(Top View)
3
256 × 36 × 2 Bidirectional FIFO
LH543601
PIN LIST
SIGNAL
NAME
A0A
A1A
A2A
OEA
FF1
AF1
HF1
PFA
D17A
D16A
D15A
D14A
D13A
D12A
D11A
D10A
D9A
D8A
D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A
RS
RT1
D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B
D11B
D12B
D13B
D14B
D15B
PQFP
PIN NO.
TQFP
PIN NO.
1
2
3
4
6
7
8
9
10
11
12
14
15
16
17
19
20
21
23
24
25
27
28
29
31
32
33
34
35
36
37
39
40
41
43
44
45
47
48
49
51
52
53
54
126
125
124
123
121
120
119
118
117
116
115
113
112
111
110
106
105
104
102
101
100
98
97
96
94
93
92
91
89
88
87
85
84
83
81
80
79
77
76
75
71
70
69
68
SIGNAL
NAME
D16B
D17B
MBF1
AE1
EF1
ACKB
REQB
ENB
R/WB
CKB
A0B
WS0
WS1
OEB
FF2
AF2
HF2
PFB
D18B
D19B
D20B
D21B
D22B
D23B
D24B
D25B
D26B
D27B
D28B
D29B
D30B
D31B
D32B
D33B
D34B
D35B
RT2
D35A
D34A
D33A
D32A
D31A
D30A
D29A
PQFP
PIN NO.
TQFP
PIN NO.
56
57
58
59
60
66
65
64
63
62
61
59
58
57
56
55
53
52
51
49
48
47
46
45
44
43
41
40
39
38
34
33
32
30
29
28
26
25
24
22
21
18
17
16
15
13
12
11
9
61
63
64
65
66
67
68
69
70
72
73
74
75
76
77
78
80
81
82
83
85
86
87
89
90
91
93
94
95
97
98
100
101
102
103
105
106
107
109
SIGNAL
NAME
D28A
D27A
D26A
D25A
D24A
D23A
D22A
D21A
D20A
D19A
D18A
MBF2
AE2
EF2
ACKA
REQA
ENA
R/WA
CKA
VCC
VSSO
NC
NC
VCCO
VSSO
VCCO
VSSO
NC
VSSO
VCCO
VSSO
VCCO
NC
NC
VSSO
VSS
NC
VCC
VSSO
NC
NC
VCCO
VSSO
VCCO
PQFP
PIN NO.
TQFP
PIN NO.
110
111
113
114
115
117
118
119
120
122
123
124
125
126
127
129
130
131
132
5
13
8
7
5
4
3
143
142
141
140
138
137
136
135
134
133
131
130
129
128
122
114
109
108
107
103
99
95
90
86
82
78
74
73
72
67
60
54
50
42
37
36
35
31
27
18
22
26
30
38
42
46
50
55
62
71
79
84
88
92
NOTE:
PINS
COMMENTS
VCC
Supply internal logic. Connected to each other.
VSS
Supply internal logic. Connected to each other.
VCCO
Supply output drivers only. Connected to each
other.
VSSO
Supply output drivers only. Connected to each
other.
4
PINS
COMMENTS
256 × 36 × 2 Bidirectional FIFO
LH543601
WRITE
PORT A
I/O
FIFO 1
READ
READ
FIFO 2
WRITE
PORT A
CONTROL
PORT B
I/O
PORT B
CONTROL
543601-36
Figure 3a. Simplified LH543601 Block Diagram
BYPASS
MBF1
RS
MAILBOX
REGISTER
#1
RESET
LOGIC
MBF2
A2A
A1A
A0A
COMMAND
PORT AND
REGISTER
MAILBOX
REGISTER
#2
COMMAND
PORT AND
REGISTER
A0B
PORT B
SYNCHRONOUS
CONTROL
LOGIC
CKB
R/WB
ENB
REQB
ACKB
FIFO #1
MEMORY ARRAY
256 x 36
CKA
R/WA
ENA
REQA
ACKA
PORT A
SYNCHRONOUS
CONTROL
LOGIC
WRITE
POINTER
FF1
AF1
READ
POINTER
FIXED AND
PROGRAMMABLE
STATUS FLAGS
HF1
EF1
AE1
RT1
RT2
OEA
READ
POINTER
WRITE
POINTER
OEB
PORT B
I/O
PORT A
I/O
D0A - D35A
PFA
FF2
AF2
HF2
FIXED AND
PROGRAMMABLE
STATUS FLAGS
EF2
AE2
WS0, WS1
FIFO #2
MEMORY ARRAY
256 x 36
PARITY
CHECKING
RESOURCE
REGISTERS
D0B - D35B
PARITY
CHECKING
PFB
543601-6
Figure 3b. Detailed LH543601 Block Diagram
5
256 × 36 × 2 Bidirectional FIFO
LH543601
PIN DESCRIPTIONS
PIN
PIN TYPE 1
DESCRIPTION
GENERAL
VCC, VSS
V
Power, Ground
RS
I
Reset
PORT A
CKA
I
Port A Free-Running Clock
R/WA
I
Port A Edge-Sampled Read/Write Control
ENA
I
Port A Edge-Sampled Enable
A0A, A1A, A2A
I
Port A Edge-Sampled Address Pins
OEA
I
Port A Level-Sensitive Output Enable
REQA
I
Port A Request/Enable
RT2
I
FIFO #2 Retransmit
D0A – D35A
I/O/Z
Port A Bidirectional Data Bus
FF1
O
FIFO #1 Full Flag (Write Boundary)
AF1
O
FIFO #1 Programmable Almost-Full Flag (Write Boundary)
HF1
O
FIFO #1 Half-Full Flag
AE2
O
FIFO #2 Programmable Almost-Empty Flag (Read Boundary)
EF2
O
FIFO #2 Empty Flag (Read Boundary)
MBF2
O
New-Mail-Alert Flag for Mailbox #2
PFA
O
Port A Parity Flag
ACKA
O
Port A Acknowledge
PORT B
CKB
I
Port B Free-Running Clock
R/WB
I
Port B Edge-Sampled Read/Write Control
ENB
I
Port B Edge-Sampled Enable
A0B
I
Port B Edge-Sampled Address Pin
OEB
I
Port B Level-Sensitive Output Enable
WS 0, WS1
I
Port B Word-Width Select
REQB
I
Port B Request/Enable
RT1
I
FIFO #1 Retransmit
D0B – D35B
I/O/Z
Port B Bidirectional Data Bus
FF2
O
FIFO #2 Full Flag (Write Boundary)
AF2
O
FIFO #2 Programmable Almost-Full Flag (Write Boundary)
HF2
O
FIFO #2 Half-Full Flag
AE1
O
FIFO #1 Programmable Almost-Empty Flag (Read Boundary)
EF1
O
FIFO #1 Empty Flag (Read Boundary)
MBF1
O
New-Mail-Alert Flag for Mailbox #1
PFB
O
Port B Parity Flag
ACKB
O
Port B Acknowledge
NOTE:
1. I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level
6
256 × 36 × 2 Bidirectional FIFO
LH543601
ABSOLUTE MAXIMUM RATINGS 1
PARAMETER
RATING
Supply Voltage to VSS Potential
Signal Pin Voltage to VSS Potential 3
DC Output Current 2
Storage Temperature Range
Power Dissipation (Package Limit)
–0.5 V to 7 V
–0.5 V to VCC + 0.5 V
± 40 mA
–65oC to 150oC
2 Watts (Quad Flat Pack)
NOTES:
1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause
permanent damage to the device. This is a stress rating for transient conditions only.
Functional operation of the device at these or any other conditions outside those indicated
in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Outputs should not be shorted for more than 30 seconds. No more than one output should be
shorted at any time.
3. Negative undershoot of 1.5 V in amplitude is permitted for up to 10 ns, once per cycle.
OPERATING RANGE
SYMBOL
TA
VCC
VSS
VIL
VIH
PARAMETER
MIN
MAX
UNIT
0
70
oC
4.5
5.5
V
0
0
V
–0.5
0.8
V
2.2
Vcc +
0.5
V
Temperature,
Ambient
Supply Voltage
Supply Voltage
Logic LOW
Input Voltage 1
Logic HIGH
Input Voltage
FROM PORT
15 Ω
INTERNAL
DATA BUS
(OR CONTROL
GATE)
TO ASSOCIATED
INPUT BUFFER,
IF ANY (SEE NOTE)
DnA/B (OR FLAG)
NOTE: Output-only pins have no
associated input buffer.
543601-39
Figure 4. Structure of Series Resistor
Input/Output Interface
NOTE:
1. Negative undershoot of 1.5 V in amplitude is permitted
for up to 10 ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ILI
Input Leakage Current
VCC = 5.5 V, VIN = 0 V To VCC
–10
10
µA
ILO
I/O Leakage Current
OE ≥ VIH, 0 V ≤ VOUT ≤ VCC
–10
10
µA
VOL
Logic LOW Output Voltage
IOL = 8.0 mA
0.4
VOH
ICC
Logic HIGH Output Voltage
Average Supply Current 1, 2
Average Standby Supply
Current 1, 3
Power-Down Supply
Current 1
Power-Down Supply
Current 1, 3
IOH = –8.0 mA
Measured at fCC = max
V
V
180
280
mA
13
25
mA
0.002
0.4
mA
6
10
mA
ICC2
ICC3
ICC4
All Inputs = VIHMIN (Clocks idle)
All Inputs = VCC – 0.2 V (Clocks idle)
All Inputs = VCC – 0.2 V
(Clocks at fcc = max)
2.4
NOTES:
1. I CC, I CC2, ICC3, and I CC4 are dependent upon actual output loading, and I CC and ICC4 are also dependent on cycle rates. Specified values are
with outputs open (for ICC: CL = 0 pF); and, for ICC and I CC4, operating at minimum cycle times.
2. I CC (MAX.) using worst case conditions and data pattern. ICC (TYP.) using VCC = 5 V and and ‘average’ data pattern.
3. I CC2 (TYP.) and ICC4 (TYP.) using VCC = 5 V and TA = 25°C.
7
256 × 36 × 2 Bidirectional FIFO
LH543601
AC TEST CONDITIONS
PARAMETER
Input Pulse Levels
RATING
Input Rise and Fall Times
(10% to 90%)
5 ns
Output Reference Levels
1.5 V
Input Timing Reference Levels
1.5 V
Output Load, Timing Tests
+5 V
VSS to 3 V
470 Ω
DEVICE
UNDER
TEST
240 Ω
30 pF *
Figure 5
CAPACITANCE 1,2
PARAMETER
RATING
CIN (Input Capacitance)
8 pF
COUT (Output Capacitance)
8 pF
NOTES:
1. Sample tested only.
2. Capacitances are maximum values at 25oC, measured at 1.0MHz,
with VIN = 0 V.
8
* INCLUDES JIG AND SCOPE CAPACITANCES
Figure 5. Output Load Circuit
543601-7
256 × 36 × 2 Bidirectional FIFO
LH543601
AC ELECTRICAL CHARACTERISTICS 1 (VCC = 5 V ± 10%, TA = 0°C to 70°C)
SYMBOL
–20
DECRIPTION
–25
–30
–35
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fCC
Clock Cycle Frequency
—
50
—
40
—
33
—
28.5
MHz
tCC
Clock Cycle Time
20
—
25
—
30
—
35
—
ns
tCH
Clock HIGH Time
8
—
10
—
12
—
15
—
ns
tCL
Clock LOW Time
8
—
10
—
12
—
15
—
ns
tDS
Data Setup Time
10
—
12
—
13
—
15
—
ns
tDH
Data Hold Time
0
—
0
—
0
—
0
—
ns
tES
Enable Setup Time
10.4
—
13
—
15
—
15
—
ns
tEH
Enable Hold Time
0
—
0
—
0
—
0
—
ns
tRWS
Read/Write Setup Time
10.4
—
13
—
15
—
18
—
ns
tRWH
Read/Write Hold Time
0
—
0
—
0
—
0
—
ns
tRQS
Request Setup Time
12
—
15
—
18
—
21
—
ns
tRQH
Request Hold Time
0
—
0
—
0
—
0
—
ns
6
tAS
Address Setup Time
12
—
15
—
18
—
21
—
ns
tAH
Address Hold Time 6
0
—
0
—
0
—
0
—
ns
tA
Data Output Access Time
—
12.8
—
16
—
20
—
25
ns
tACK
Acknowledge Access Time
—
12
—
15
—
20
—
25
ns
tOH
Output Hold Time
2.0
—
2.0
—
2.0
—
2.0
—
ns
tZX
Output Enable Time, OE LOW to D0
– D35 Low-Z 2
1.5
—
2.0
—
3.0
—
3.0
—
ns
tXZ
Output Disable Time, OE HIGH to
2
D0 – D35 High-Z
—
9
—
12
—
15
—
20
ns
tEF
Clock to EF Flag Valid (Empty Flag)
—
17.6
—
22
—
25
—
30
ns
tFF
Clock to FF Flag Valid (Full Flag)
—
17.6
—
22
—
25
—
30
ns
tHF
Clock to HF Flag Valid (Half-Full)
—
17.6
—
22
—
25
—
30
ns
tAE
Clock to AE Flag Valid (AlmostEmpty)
—
16
—
20
—
25
—
30
ns
tAF
Clock to AF Flag Valid (Almost-Full)
—
16
—
20
—
25
—
30
ns
tMBF
Clock to MBF Flag Valid (Mailbox
Flag)
—
12
—
15
—
20
—
25
ns
tPF
Data to Parity Flag Valid
tRS
Reset/Retransmit Pulse Width 7
tRSS
Reset/Retransmit Setup Time
tRSH
Reset/Retransmit Hold Time
3
3
—
13.6
—
17
—
20
—
25
ns
32/20
—
40/25
—
52/30
—
65/35
—
ns
16
—
20
—
25
—
30
—
ns
8
—
10
—
15
—
20
—
ns
tRF
Reset LOW to Flag Valid
—
28
—
35
—
40
—
45
ns
tFRL
First Read Latency 4
20
—
25
—
30
—
35
—
ns
tFWL
First Write Latency 5
20
—
25
—
30
—
35
—
ns
tBS
Bypass Data Setup
12
—
15
—
18
—
21
—
ns
tBH
Bypass Data Hold
3
—
5
—
5
—
5
—
ns
tBA
Bypass Data Access
—
18
—
20
—
25
—
30
ns
NOTES:
1. Timing measurements performed at ‘AC Test Condition’ levels.
2. Values are guaranteed by design; not currently production tested.
3. t RSS and/or t RSH need not be met unless a rising edge of CKA occurs while ENA is being asserted, or else a rising edge of CKB occurs while
ENB is being asserted.
4. t FRL is the minimum first-write-to-first-read delay, following an empty condition, which is required to assure valid read data.
5. t FWL is the minimum first-read-to-first-write delay, following a full condtion, which is required to assure successful writing of data.
9
256 × 36 × 2 Bidirectional FIFO
LH543601
OPERATIONAL DESCRIPTION
Reset
The device is reset whenever the asynchronous Reset
(RS) input is taken LOW, and at least one rising edge and
one falling edge of both CKA and CKB occur while RS is
LOW. A reset operation is required after power-up, before
the first write operation may occur. The LH543601 is fully
ready for operation after being reset. No device programming is required if the default states described below are
acceptable.
A reset operation initializes the read-address and
write-address pointers for FIFO #1 and FIFO #2 to those
FIFO’s first physical memory locations. If the respective
outputs are enabled, the initial contents of these first
locations appear at the outputs. FIFO and mailbox status
flags are updated to indicate an empty condition. In
addition, the programmable-status-flag offset values are
initialized to eight. Thus, the AE1/AE2 flags get asserted
within eight locations of an empty condition, and the
AF1/AF2 flags likewise get asserted within eight locations
of a full condition, for FIFO #1/FIFO #2 respectively.
Bypass Operation
During reset (whenever RS is LOW) the device acts
as a registered transceiver, bypassing the internal FIFO
memories. Port A acts as the master port. A write or read
operation on Port A during reset transfers data directly to
or from Port B. Port B is considered to be the slave, and
cannot perform write or read operations independently on
its own during reset.
The direction of the bypass data transmission is determined by th R/WA control input, which does not get
overridden by the RS input. Here, a ‘write’ operation
means passing data from Port A to Port B, and a ‘read’
operation means passing data from Port B to Port A.
The bypass capability may be used to pass initialization or configuration data directly between a master processor and a peripheral device during reset.
Address Modes
Address pins select the device resource to be
accessed by each port. Port A has three resource-register-select inputs, A0A, A1A, and A2A, which select between
FIFO access, mailbox-register access, control-register
access (write only), and programmable flag-offset-valueregister access. Port B has a single address input, A0B,
to select between FIFO access or mailbox-register access.
The status of the resource-register-select inputs is
sampled at the rising edge of an enabled clock (CK A or
CK B). Resource-register select-input address definitions
are summarized in Table 1.
FIFO Write
Port A writes to FIFO #1, and Port B writes to FIFO #2.
A write operation is initiated on the rising edge of a clock
10
(CKA or CKB) whenever: the appropriate enable (ENA or
ENB) is held HIGH; the appropriate request (REQA or
REQB) is held HIGH; the appropriate Read/Write control
(R/WA or R/WB) is held LOW; the FIFO address is
selected for the address inputs (A2A – A0A or A0B); and
the prescribed setup times and hold times are observed
for all of these signals. Setup times and hold times must
also be observed on the data-bus pins (D 0A – D35A or
D0B – D35B).
Normally, the appropriate Output Enable signal (OEA
or OEB) is HIGH, to disable the outputs at that port, so
that the data word present on the bus from external
sources gets stored. However, a ‘loopback’ mode of
operation also is possible, in which the data word supplied
by the outputs of one internal FIFO is ‘turned around’ at
the port and read back into the other FIFO. In this mode,
the outputs at the port are not disabled. To remain within
specification for all timing parameters, the Clock Cycle
Frequency must be reduced slightly below the value
which otherwise would be permissible for that speed
grade of LH543601.
When a FIFO full condition is reached, write operations
are locked out. Following the first read operation from a
full FIFO, another memory location is freed up, and the
corresponding Full Flag is deasserted (FF = HIGH). The
first write operation should begin no earlier than a First
Write Latency (tFWL) after the first read operation from a
full FIFO, to ensure that correct read data are retrieved.
FIFO Read
Port A reads from FIFO #2, and Port B reads from FIFO
#1. A read operation is initiated on the rising edge of
a clock (CKA or CKB) whenever: the appropriate enable
(ENA or EN B) is held HIGH; the appropriate request
(REQA or REQB) is held HIGH; the appropriate
Read/Write control (R/WA or R/WB) is held HIGH;
the FIFO address is selected for the address inputs
(A2A – A0A or A0B); and the prescribed setup times and
hold times are observed for all of these signals. Read data
Table 1. Resource-Register Addresses
A2A
A1A
A0A
H
H
H
H
H
L
H
L
H
H
L
L
L
L
L
H
H
L
L
L
H
L
H
L
A0B
H
L
RESOURCE
PORT A
FIFO
Mailbox
AF2, AE2, AF1, AE1 Flag Offsets
Register (36-Bit Mode)
Control Register (Parity Mode)
AE1 Flag Offset Register
AF1 Flag Offset Register
AE2 Flag Offset Register
AF2 Flag Offset Register
RESOURCE
PORT B
FIFO
Mailbox
256 × 36 × 2 Bidirectional FIFO
OPERATIONAL DESCRIPTION (cont’d)
becomes valid on the data-bus pins (D0A – D35A or
D0B – D35B) by a time tA after the rising clock (CKA or
CK B) edge, provided that the data outputs are enabled.
OEA and OEB are assertive-LOW, asynchronous, Output Enable control input signals. Their effect is only to
enable or disable the output drivers of the respective port.
Disabling the outputs does not disable a read operation;
data transmitted to the corresponding output register will
remain available later, when the outputs again are enabled, unless it subsequently is overwritten.
When an empty condition is reached, read operations
are locked out until a valid write operation(s) has loaded
additional data into the FIFO. Following the first write to
an empty FIFO, the corresponding empty flag (EF) will be
deasserted (HIGH). The first read operation should begin
no earlier than a First Read Latency (tFRL) after the first
write to an empty FIFO, to ensure that correct read data
words are retrieved.
Dedicated FIFO Status Flags
Six dedicated FIFO status flags are included for Full
(FF1 and FF2), Half-Full (HF1 and HF2), and Empty (EF1
and EF2). FF1, HF1, and EF1 indicate the status of FIFO
#1; and FF2, HF2, and EF2 indicate the status of FIFO #2.
A Full Flag is asserted following the first subsequent
rising clock edge for a write operation which fills the FIFO.
A Full Flag is deasserted following the first subsequent
falling clock edge for a read operation to a full FIFO. A
Half-Full Flag is updated following the first subsequent
rising clock edge of a read or write operation to a FIFO
which changes its ‘half-full’ status. An Empty Flag is
asserted following the first subsequent rising clock edge
for a read operation which empties the FIFO. An Empty
Flag is deasserted following the falling clock edge for a
write operation to an empty FIFO.
Programmable Status Flags
Four programmable FIFO status flags are provided,
two for Almost-Full (AF1 and AF2), and two for AlmostEmpty (AE1 and AE2). Thus, each port has two programmable flags to monitor the status of the two internal FIFO
buffer memories. The offset values for these flags are
initialized to eight locations from the respective FIFO
boundaries during reset, but can be reprogrammed over
the entire FIFO depth.
An Almost-Full Flag is asserted following the first subsequent rising clock edge after a write operation which
has partially filled the FIFO up to the ‘almost-full’ offset
point. An Almost-Full Flag is deasserted following the first
subsequent falling clock edge after a read operation
which has partially emptied the FIFO down past the
‘almost-full’ offset point. An Almost-Empty Flag is asserted following the first subsequent rising clock edge
after a read operation which has partially emptied the
FIFO down to the ‘almost-empty’ offset point. An AlmostEmpty Flag is deasserted following the first subsequent
LH543601
falling clock edge after a write operation which has partially filled the FIFO up past the ‘almost-empty’ offset
point.
Flag offsets may be written or read through the Port A
data bus. All four programmable FIFO status flag offsets
can be set simultaneously through a single 36-bit status
word; or, each programmable flag offset can be set
individually, through one of four eight-bit status words.
Table 3 illustrates the data format for flag-programming
words .
Also, Table 4 defines the meaning of each of the five
flags, both the dedicated flags and the programmable
flags, for the LH543601.
WARNING: Control inputs which may affect the computation of flag values at a port generally should not change
while the clock for that port is HIGH, since some updating
of flag values takes place on the falling edge of the clock.
Mailbox Operation
Two mailbox registers are provided for passing system
hardware or software control/status words between ports.
Each port can read its own mailbox and write to the other
port’s mailbox. Mailbox access is performed on the rising
edge of the controlling FIFO’s clock, with the mailbox
address selected and the enable (EN A or ENB) HIGH.
That is, writing to Mailbox Register #1, or reading from
Mailbox Register #2, is synchronized to CKA; and writing
to Mailbox Register #2, or reading from Mailbox Register
#1, is synchronized to CKB.
The R/WA/B and OEA/B pins control the direction and
availability of mailbox-register accesses. Each mailbox
register has its own New-Mail-Alert Flag (MBF1 and
MBF2), which is synchronized to the reading port’s clock.
These New-Mail-Alert Flags are status indicators only,
and cannot inhibit mailbox-register read or write operations.
Request Acknowledge Handshake
A synchronous request-acknowledge handshake feature is provided for each port, to perform boundary synchronization between asynchronously-operated ports.
The use of this feature is optional. When it is used, the
Request input (REQA/B) is sampled at a rising clock edge.
With REQA/B HIGH, R/WA/B determines whether a FIFO
read operation or a FIFO write operation is being requested. The Acknowledge output (ACKA/B) is updated
during the following clock cycle(s). ACK A/B meets the
setup and hold time requirements of the Enable input
(ENA or ENB). Therefore, ACKA/B may be tied back to the
enable input to directly gate FIFO accesses, at a slight
decrease in maximum operating frequency.
The assertion of ACKA/B signifies that REQA/B was
asserted. However, ACKA/B does not depend logically on
ENA/B; and thus the assertion of ACKA/B does not prove
that a FIFO write access or a FIFO read access actually
took place. While REQA/B and ENA/B are being held
HIGH, ACKA/B may be considered as a synchronous,
predictive boundary flag. That is, ACK A/B acts as a syn11
256 × 36 × 2 Bidirectional FIFO
LH543601
OPERATIONAL DESCRIPTION (cont’d)
chronized predictor of the Almost-Full Flag AF for write
operations, or as a synchronized predictor of the AlmostEmpty Flag AE for read operations.
Outside the ‘almost-full’ region and the ‘almost-empty’
region, ACKA/B remains continuously HIGH whenever
REQA/B is held continuously HIGH. Within the ‘almost-full’
region or the ‘almost-empty’ region, ACKA/B occurs only
on every third cycle, to prevent an overrun of the FIFO’s
actual full or empty boundaries and to ensure that the tFWL
(first write latency) and tFRL (first read latency) specifications are satisfied before ACKA/B is received.
The ‘almost-full region’ is defined as ‘that region, where
the Almost-Full Flag is being asserted’; and the ‘almostempty region’ as ‘that region, where the Almost-Empty
Flag is being asserted.’ Thus, the extent of these ‘almost’
regions depends on how the system has programmed the
offset values for the Almost-Full Flags and the AlmostEmpty Flags. If the system has not programmed them,
then these offset values remain at their default values,
eight in each case.
If a write attempt is unsuccessful because the corresponding FIFO is full, or if a read attempt is unsuccessful
because the corresponding FIFO is empty, ACKA/B is not
asserted in response to REQA/B.
If the REQ/ACK handshake is not used, then the
REQA/B input may be used as a second enable input, at
a possible minor loss in maximum operating speed. In this
case, the ACKA/B output may be ignored.
WARNING: Whether or not the REQ/ACK handshake is
being used, the REQA/B input for a port must be asserted
for that port to function at all – for FIFO, mailbox, or
data-bypass operation.
Data Retransmit
A retransmit operation resets the read-address pointer of
the corresponding FIFO (#1 or #2) back to the first FIFO
physical memory location, so that data may be reread. The
write pointer is not affected. The status flags are updated;
and a block of up to 256 data words, which previously had
been written into and read from a FIFO, can be retrieved.
The block to be retransmitted is bounded by the first FIFO
memory location, and the FIFO memory location addressed
by the write pointer. FIFO #1 retransmit is initiated by
strobing the RT1 pin LOW. FIFO #2 retransmit is initiated by
strobing the RT2 pin LOW. Read and write operations to a
FIFO should be stopped while the corresponding Retransmit signal is being asserted.
Parity Checking
The Parity Check Flags, PFA and PFB, are asserted
(LOW) whenever there is a parity error in the data word
present on the Port A data bus or the Port B data bus
respectively. The inputs to the parity-evaluation logic
come directly (via isolation transistors) from the data-bus
bonding pads, in each case. Thus, PFA and PFB provide
12
parity-error indications for whatever 36-bit words are
present at Port A and Port B respectively, regardless of
whether those words originated within the LH543601 or
in the external system.
The four bytes of a 36-bit data word are grouped as D0 –
D8, D9 – D17, D18 – D26, and D27 – D35. The parity of each
nine-bit byte is individually checked, and the four single-bit
parity indications are logically inclusive-ORed and inverted,
to produce the Parity-Flag output. Parity checking is initialized for odd parity at reset, but can be reprogrammed for
even parity or for odd parity during operation. Control-Register bit 00 (zero) selects the parity mode, odd or even.
(See Table 3.)
All nine bits of each byte are treated alike by the parity
logic. The byte parity over the nine bits is compared with
the Parity Mode bit in the Control Register, to generate a
byte-parity-error indication. Then, the four byte-parityerror signals are NORed together, to compute the assertive-LOW parity-flag value.
Word-Width Selection on Port B
The word width of data access on Port B is selected
by the WS 0 and WS1 control inputs. WS0 and WS1 both
are tied HIGH for 36-bit access; they both are tied LOW
for single-byte access. For double-byte access, WS0 is
tied HIGH and WS1 is tied LOW. (See Table 2.)
In the single-byte-access or double-byte-access modes,
FIFO write operations on Port B essentially pack the data to
form 36-bit words, as viewed from Port A. Similarly, singlebyte or double-byte FIFO read operations on Port B essentially unpack 36-bit words through a series of shift
operations. FIFO status flags are updated following the last
access which forms a complete 36-bit transfer.
Since the values for each status flag are computed by
logic directly associated with one of the two FIFO-memory
arrays, and not by logic associated with Port B, the flag
values reflect the array fullness situation in terms of complete 36-bit words, and not in terms of bytes or double bytes.
However, there is no such restriction for switching from
writing to reading, or from reading to writing, at Port B. As
long as tRWS, tDS, and tA are satisfied, R/WB may change
state after any single-byte or double-byte access, and not
only after a full 36-bit-word access.
Also, the word-width-matching feature continues to
operate properly in ‘loopback’ mode.
Note that the programmable word-width-matching feature is only supported for FIFO accesses. Mailbox and
Data Bypass operations do not support word-width
matching between Port A and Port B. Tables 2, 3, and 4,
and Figures 6a, 6b, 7a, and 7b summarize word-width
selection for Port B.
Table 2. Port B Word-Width Selection
WS1
WS0
PORT B DATA WIDTH
H
H
L
L
H
L
H
L
36-Bit
(Reserved)
18-Bit
9-Bit
256 × 36 × 2 Bidirectional FIFO
LH543601
Table 3. Resource-Register Programming
RESOURCEREGISTER
ADDRESS
A2A
A1A
RESOURCE-REGISTER CONTENTS
A0A
NORMAL FIFO OPERATION
H
H
H
D35A
D0A
X...
...X
MAILBOX
H
H
L
D35A
D0A
X...
...X
AF2, AE2, AF1, AE1 FLAG OFFSETS REGISTER (36-BIT MODE)
H
L
H
D35A
D34A . . . D27A
D26A
D25A . . . D18A
D17A
D16A . . . D9A
D8A
D7A . . . D0A
X
AF 2 Offset 1
X
AE2 Offset 1
X
AF1 Offset 1
X
AE 1 Offset 1
CONTROL REGISTER: (WRITE-ONLY) PARITY EVEN/ODD
D35A
H
L
L
D1A
D0A
...X
Parity Mode 2
D35A
D8A
D7A . . . D0A
X...
...X
AE 1 Offset 1
D35A
D8A
D7A . . . D0A
X...
...X
AF1 Offset 1
D35A
D8A
D7A . . . D0A
X...
...X
AE 2 Offset 1
D35A
D8A
D7A . . . D0A
X...
...X
AF2 Offset 1
X...
8-BIT AE1 FLAG OFFSET REGISTER
L
H
H
8-BIT AF1 FLAG OFFSET REGISTER
L
H
L
8-BIT AE2 FLAG OFFSET REGISTER
L
L
H
8-BIT AF2 FLAG OFFSET REGISTER
L
L
L
NOTES:
1. All four programmable-flag-offset values are initialized to eight (8) during a reset operation.
2. Odd parity = HIGH; even parity = LOW. The parity mode is initialized to odd during a reset operation.
13
256 × 36 × 2 Bidirectional FIFO
LH543601
Table 4. Flag Definition Table 1
VALID READ CYCLES REMAINING
FLAG
FLAG = LOW
VALID WRITE CYCLES REMAINING
FLAG = HIGH
FLAG = HIGH
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
FF
256
256
0
255
0
0
1
256
AF
256-p
256
0
255-p
0
p
p+1
256
HF
129
256
0
128
0
127
128
256
AE
0
q
q+1
256
256-q
256
0
255-q
EF
0
0
1
256
256
256
0
255
NOTES:
1. q = Programmable-Almost-Empty Offset value. (Default value: q = 8.)
2. p = Programmable-Almost-Full Offset value. (Default value: p = 8.)
14
FLAG = LOW
256 × 36 × 2 Bidirectional FIFO
LH543601
PORT B WORD-WIDTH SELECTION
36-Bit Data Stream
18-Bit Data Streams
Bits 18-35
(2nd Halfword)
D35A
18
D18A
Bits
(2n 18-35
dH
alfw
ord
D35B
2nd Halfword, then 1st Halfword
18
D18B
7
0-1 ord)
Bits Halfw
t
s
(1
)
PORT
A
PORT
B
D17A
D17B
18
1st Halfword, then 2nd Halfword
18
Bits 0-17
(1st Halfword)
D0A
D0B
543601-32
Figure 6a. 36-to-18 Funneling Through FIFO #1
36-Bit Data Stream
D35A
9
9-Bit Data Streams
Bits 27-35
(4th Byte)
D35B
9
D27A
4th Byte, then 1st Byte, then 2nd Byte, then 3rd Byte
D27B
D26A
9
Bits 18-26
(3rd Byte)
D26B
9
D18A
3rd Byte, then 4th Byte, then 1st Byte, then 2nd Byte
D18B
PORT
A
D17A
9
Bits 9-17
(2nd Byte)
D17B
9
D9A
PORT
B
2nd Byte, then 3rd Byte, then 4th Byte, then 1st Byte
D9B
D8A
9
Bits 0-8
(1st Byte)
D0A
D8B
9
1st Byte, then 2nd Byte, then 3rd Byte, then 4th Byte
D0B
543601-34
Figure 6b. 36-to-9 Funneling Through FIFO #1
NOTES:
1. The heavy black borders on register segments indicate the main
data path, suitable for most applications. Alternate paths feature
a different ordering of bytes within a word, at Port B.
2. The funneling process does not change the ordering of bits within
a byte. Halfwords (Figure 6a) or bytes (Figure 6b) are transferred in parallel form from Port A to Port B.
3. The word-width setting may be changed during system operation;
however, two clock intervals should be allowed for these signals
to settle, before again attempting to read D0B – D35B, and three
dummy words should be passed through initially. Also, incomplete data words may occur, when the word width is changed
from shorter to longer at an inappropriate point in the data block
passing through the FIFO.
15
256 × 36 × 2 Bidirectional FIFO
LH543601
PORT B WORD-WIDTH SELECTION
36-Bit Data Stream
18-Bit Data Stream
D35A
D35B
Bits
(2n 18-35
dH
alfw
ord
18
D18A
18
D18B
)
PORT
A
PORT
B
D17A
D17B
18
1st Halfword, then 2nd Halfword
18
Bits 0-17
(1st Halfword)
D0A
D0B
543601-33
Figure 7a. 18-to-36 Defunneling Through FIFO #2
36-Bit Data Stream
9-Bit Data Stream
D35A
D35B
9
Bits 27-35
(4th Byte)
9
D27A
D27B
D26A
D26B
9
Bits 18-26
(3rd Byte)
9
D18A
D18B
PORT
A
D17A
D17B
9
Bits 9-17
(2nd Byte)
9
D9A
D9B
D8A
D8B
9
Bits 0-8
(1st Byte)
9
D0A
PORT
B
1st Byte, then 2nd Byte, then 3rd Byte, then 4th Byte
D0B
543601-35
Figure 7b. 9-to-36 Defunneling Through FIFO #2
NOTES:
1. The heavy black borders on register segments indicate the only
data paths used. The other byte segments of Port B do not participate in the data path during defunneling.
2. The defunneling process does not change the ordering of bits
within a byte. Halfwords (Figure 7a) or bytes (Figure 7b) are
transferred in parallel form from Port B to Port A.
16
3. The word-width setting may be changed during system operation;
however, two clock intervals should be allowed for these signals
to settle, before again attempting to send data, and three
dummy words should be passed through initially. Also, incomplete data words may occur, when the word width is changed
from shorter to longer at an inappropriate point in the data block
passing through the FIFO.
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS
t RS
RS
t RSS
t RSH
t RSS
CKA
t ES
t EH
t ES
t EH
tRQS
tRQH
tRQS
tRQH
EN A
REQA
t RSS
t RSH
t RSS
CK B
t ES
t EH
t ES
t EH
tRQS
tRQH
tRQS
tRQH
EN B
REQB
t RF
EF, AE
t RF
HF, AF, FF, MBF
NOTES:
1. RS overrides all other input signals, except for R/WA, ENA, and REQA. It operates
asynchronously. RS operates whether or not ENA and/or ENB are asserted. However,
at least one rising edge and one falling edge of both CKA and CKB must occur while
RS is being asserted (is LOW), with timing as defined by tRSS and tRSH.
2. Otherwise, tRSS, tRSH need not be met unless the rising edge of CKA and/or CKB
occurs while that clock is enabled.
3. The parity-check even/odd selection (Control Register bit 00) is initialized to odd byte
parity at reset (HIGH).
4. The AE and AF flag offsets are initialized to eight locations from the boundary at reset.
543601-26
Figure 8. Reset Timing
17
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
RS
t RSS
t RSH
CKA
tRWS
t RWH
tRWS
t RWH
t ES
t EH
t ES
t EH
t RQS
t RQH
tRQS
tRQH
t BS
t BH
R/WA
ENA
REQ A
OEB
D0B - D35B
tA
t BA
t ZX
t OH
BYPASS DATA OUT
BYPASS IN
OEA
t BA
t OH
D0A - D35A
PREVIOUS DATA
t BS
tBH
t XZ
BYPASS
OUT
BYPASS
IN
NOTES:
1. tRSS, tRSH need not be met unless the rising edge of CKA or CKB occurs while that clock is enabled.
2. Port A is considered the master port for bypass operation. Thus, CKA, R/WA, ENA, and REQA control
the transmission of data between ports at reset.
543601-27
Figure 9. Data Bypass Timing
18
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
READ FROM
FIFO #2
WRITE TO
FIFO #1
t CC
t CH
t CL
CKA
tRWS
t RWH
tRWS
t RWH
tES
tEH
t ES
t EH
tRQS
tRQH
tRQS
tRQH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
t DS
t DH
R/WA
ENA
REQA
A2A
A1A
A0A
OEA
tA
tA
tZX
D0A - D35A
PREVIOUS
DATA
t PF
PFA
t XZ
t OH
DATA OUT
t PF
VALID PF
DATA IN
t PF
VALID PF
VALID PF
NOTES:
1. The Port A Parity Error Flag (PFA) reflects the parity status of data present on the data bus.
2. The status of OEA does not gate read or write operations.
3. If OEA is left LOW during a write operation, then the previous data held in the output latch is
written back into FIFO #1.
543601-24
Figure 10. Port A FIFO Read/Write
19
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
READ FROM
FIFO #1
WRITE TO
FIFO #2
t CC
t CH
t CL
CK B
tRWS
t RWH
tRWS
t RWH
t ES
t EH
t ES
t EH
t RQS
t RQH
t RQS
t RQH
t AS
t AH
t AS
t AH
t DS
t DH
R/WB
EN B
REQ B
A0B
OE B
D0B - D35B
tA
tA
t ZX
t OH
PREVIOUS
DATA
DATA OUT
t PF
t PF
PF B
t XZ
VALID PF
DATA IN
t PF
VALID PF
VALID PF
NOTES:
1. The Port B Parity Error Flag (PFB) reflects the parity status of data present on the data bus.
2. The status of OEB does not gate read or write operations.
3. If OEB is left LOW during a write operation, then the previous data held in the output latch is
written back into FIFO #2.
543601-25
Figure 11. Port B FIFO Read/Write
20
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
WRITE TO
MAILBOX #1
READ FROM
MAILBOX #2
CK A
tRWS
t RWH
tRWS
t RWH
t ES
t EH
t ES
t EH
tRQS
tRQH
tRQS
tRQH
t AS
t AH
t AS
t AH
t AS
t AH
t AS
t AH
t AS
t AH
t AS
t AH
R/WA
EN A
REQA
A2A
A1A
A0A
t MBF
MBF2
MAXIMUM OF 2 CK B
CYCLES LATENCY
CK B
t MBF
MBF1
OEA
tA
tA
t DS
D0A - D35A
t DH
t ZX
t OH
MAILBOX IN
MAILBOX OUT
NOTES:
1. Both edges of MBF2 are synchronized to the Port A clock, CKA.
2. Both edges of MBF1 are synchronized to the Port B clock, CKB.
3. There is a maximum of two CKB clock cycles of synchronization latency before MBF1
is asserted to indicate valid new mailbox data.
4. The status of mailbox flags does not prevent mailbox read or write operations.
543601-22
Figure 12. Port A Mailbox Access
21
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
WRITE TO
MAILBOX #2
READ FROM
MAILBOX #1
CKB
tRWS
t RWH
tRWS
t RWH
t ES
t EH
t ES
t EH
tRQS
tRQH
tRQS
tRQH
R/WB
ENB
REQB
t AS
t AH
t AS
t AH
A0B
t MBF
MBF1
MAXIMUM OF 2 CKA
CYCLES LATENCY
CKA
t MBF
MBF2
OEB
tA
t DS
D0B - D35B
t DH
t ZX
tA
t OH
MAILBOX IN
MAILBOX OUT
NOTES:
1. Both edges of MBF2 are synchronized to the Port A clock, CKA.
2. Both edges of MBF1 are synchronized to the Port B clock, CKB.
3. There is a maximum of two CKA clock cycles of synchronization latency before MBF2
is asserted to indicate valid new mailbox data.
4. The status of mailbox flags does not prevent mailbox read or write operations.
543601-23
Figure 13. Port B Mailbox Access
22
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
LOAD FLAG
POSITIONS
READ FLAG
POSITIONS
CK A
tRWS
t RWH
tRWS
t RWH
t ES
t EH
t ES
t EH
tRQS
tRQH
tRQS
tRQH
t AS
t AH
t AS
t AH
t AS
t AH
tAS
t AH
t AS
t AH
t AS
t AH
R/WA
EN A
REQA
A2A
A1A
A0A
OEA
tA
t DS
D0A - D35A
t DH
tZX
tA
tOH
FLAG DATA IN
FLAG DATA OUT
t RF
AE1, AE2, AF1, AF2
NOTES:
1. For valid flag address codes and data formats, see Table 3.
2. If flag status is altered by flag programming, the updated flags will be valid within a time tRF.
3. The Control Register may be loaded as shown here, with A2A, A1A, A0A = HLL. However, it
is not available for reading back.
543601-18
Figure 14. Flag Programming
23
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CKA (CKB )
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WA (R/WB )
ENA (EN B)
REQA (REQB)
t EF
t EF
EF2 (EF1)
CKB (CK A)
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WB (R/WA)
ENB (ENA )
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Assertion of the Empty Flags is controlled by rising clock edges,
whereas deassertion of the Empty Flags is controlled by falling
clock edges.
543601-1
Figure 15. Empty Flag Timing
24
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CKA (CKB )
tRWS
t RWH
t ES
t EH
t RQS
t RQH
R/WA (R/WB )
ENA (ENB )
REQA (REQB )
t AE
t AE
AE2 (AE1)
CKB (CKA )
tRWS
t RWH
t ES
t EH
t RQS
t RQH
R/WB (R/WA )
ENB (ENA )
REQ B (REQA )
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Assertion of the Almost-Empty Flags is controlled by rising clock
edges, whereas deassertion of the Almost-Empty Flags is controlled
by falling clock edges.
543601-2
Figure 16. Almost-Empty Flag Timing
25
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CKA (CKB )
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WA (R/WB )
ENA (ENB )
REQA (REQB)
t FF
t FF
FF1 (FF2)
CKB (CKA )
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WB (R/WA )
ENB (ENA )
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Assertion of the Full Flags is controlled by rising clock edges,
whereas deassertion of the Full Flags is controlled by falling
clock edges.
Figure 17. Full Flag Timing
26
543601-3
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CKA (CKB )
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WA (R/WB )
ENA (ENB )
REQA (REQB)
t AF
t AF
AF1 (AF2)
CKB (CKA )
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WB (R/WA )
ENB (ENA )
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Assertion of the Almost-Full Flags is controlled by rising clock edges,
whereas deassertion of the Almost-Full Flags is controlled by falling
clock edges.
543601-4
Figure 18. Almost-Full Flag Timing
27
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CKA (CKB )
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WA (R/WB )
ENA (ENB )
REQA (REQB)
t HF
t HF
HF1 (HF2)
CKB (CKA )
tRWS
t RWH
t ES
t EH
tRQS
tRQH
R/WB (R/WA )
ENB (ENA )
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Both assertion and deassertion of the Half-Full Flags are controlled
entirely by rising clock edges, rather than by falling clock edges.
Figure 19. Half-Full Flag Timing
28
543601-5
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CK A
tRWS
R/WA
t ES
t EH
t EH
t ES
tRQS tRQH
tRQS
t ES
EN A
tRQS tRQH
REQA
t RSS
t RSH
t RS
RT2
t RSS
t RSH
CK B
tRWS
R/WB
t ES
t EH
t ES
t EH
t ES
EN B
tRQS tRQH
tRQS tRQH
tRQS
REQB
NOTES:
1. tRSS and tRSH need not be met unless a rising edge of CKA or CKB occurs while that clock is enabled.
2. tRSS is the time needed to deassert RT2 before returning to a normal FIFO cycle.
3. tRSH is the time needed before asserting RT2 after a normal FIFO cycle.
4. Read and write operations to FIFO #2 should be disabled while RT2 is being asserted.
543601-20
Figure 20. FIFO #2 Retransmit
29
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CKB
tRWS
R/WB
t ES
t EH
t ES
t EH
t ES
EN B
tRQS tRQH
tRQS tRQH
tRQS
REQB
t RSH
tRSS
t RS
RT1
t RSH
t RSS
CKA
tRWS
R/WA
t ES
t EH
t EH
t ES
tRQS tRQH
tRQS
t ES
EN A
tRQS tRQH
REQA
NOTES:
1. tRSS and tRSH need not be met unless a rising edge of CKA or CKB occurs while that clock is enabled.
2. tRSS is the time needed to deassert RT1 before returning to a normal FIFO cycle.
3. tRSH is the time needed before asserting RT1 after a normal FIFO cycle.
4. Read and write operations to FIFO #1 should be disabled while RT1 is being asserted.
Figure 21. FIFO #1 Retransmit
30
543601-21
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CK A
t RWH
t RWH
tRWS
tRWS
R/WA
t EH
t EH
t ES
t ES
EN A
tRQH
tRQH
tRQS
tRQS
REQA
t DH
D0A - D35A
t DS
t DS
N1
N2
t DH
t EF
EF1
t EF
t FRL
CK B
t RWH
t RWH
tRWS
tRWS
R/W B
t EH
t EH
t ES
t ES
EN B
tRQH
tRQH
tRQS
tRQS
REQB
tA
tA
t OH
D0B - D35B
PREVIOUS DATA
t OH
N1
N2
NOTES:
1. A2A, A1A, A0A, and A0B are all held HIGH for FIFO access.
2. OEA is held HIGH.
3. OEB is held LOW.
4. tFRL (First Read Latency) - The first read following an empty condition
may begin no earlier than tFRL after the first write to an empty FIFO,
to ensure that valid read data is retrieved.
543601-16
Figure 22. FIFO #1 Write and Read Operation in
Near-Empty Region
31
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CK B
t RWH
t RWH
tRWS
tRWS
R/WB
t EH
t EH
t ES
t ES
EN B
tRQH
tRQH
tRQS
tRQS
REQB
t DH
t DH
t DS
D0B - D35B
t DS
N1
N2
t EF
EF2
t FRL
t EF
CK A
t RWH
t RWH
tRWS
t RWS
R/W A
t EH
t EH
t ES
t ES
EN A
tRQH
tRQH
tRQS
tRQS
REQA
D0A - D35A
PREVIOUS DATA
tA
tA
tOH
tOH
N1
N2
NOTES:
1. A2A, A1A, A0A, and A0B are all held HIGH for FIFO access.
2. OEB is held HIGH.
3. OEA is held LOW.
4. tFRL (First Read Latency) - The first read following an empty condition
may begin no earlier than tFRL after the first write to an empty FIFO,
to ensure that valid read data is retrieved.
543601-17
Figure 23. FIFO #2 Write and Read Operation in
Near-Empty Region
32
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CK A
t RWH
t RWH
tRWS
tRWS
R/WA
t EH
t EH
t ES
t ES
EN A
tRQH
tRQH
tRQS
tRQS
REQA
t DH
t DH
t DS
tDS
D0A - D35A
t FF
t FWL
FF1
t FF
CK B
t RWH
tRWS
t RWH tRWS
R/W B
t EH
tEH
t ES
t ES
EN B
tRQH
tRQH
tRQS
tRQS
REQB
tA
t OH
D0B - D35B
tA
t OH
PREVIOUS DATA
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. OEA is held HIGH.
3. OEB is held LOW.
4. tFWL (First Write Latency) - The first write following a full condition
may begin no earlier than tFWL after the first read from a full FIFO,
to ensure that valid write data is written.
543601-14
Figure 24. FIFO #1 Read and Write Operation in
Near-Full Region
33
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CK B
t RWH
t RWH
tRWS
tRWS
R/WB
t EH
t EH
t ES
t ES
EN B
tRQH
tRQH
tRQS
tRQS
REQB
t DH
t DH
t DS
tDS
D0B - D35B
t FF
t FWL
FF2
t FF
CK A
t RWH
tRWS
t RWH tRWS
R/W A
t EH
tEH
t ES
t ES
EN A
tRQH
tRQH
tRQS
tRQS
REQA
tA
t OH
D0A - D35A
tA
t OH
PREVIOUS DATA
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. OEB is held HIGH.
3. OEA is held LOW.
4. tFWL (First Write Latency) - The first write following a full condition
may begin no earlier than tFWL after the first read from a full FIFO,
to ensure that valid write data is written.
Figure 25. FIFO #2 Read and Write Operation in
Near-Full Region
34
543601-15
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CK B
tRWS
R/WB
t ES
EN B
t RQS
REQ B
tA
D0B - D17B
BITS
0-17
BITS
18-35
WORD # n+1
WORD # n
D18B - D35B
BITS
18-35
BITS
0-17
BITS
0-17
WORD # n
BITS
18-35
WORD # n+1
BITS
18-35
BITS
0-17
WORD # n+2
BITS
0-17
BITS
18-35
WORD # n+2
NOTES:
1. A0B is held HIGH for FIFO access.
2. OEB is held LOW.
3. WS0 is held HIGH and WS1 is held LOW for double-byte access.
4. Data-access time tA, after the rising edge of CKB, shown for the
first read cycle, applies similarly for all subsequent read cycles.
543601-13
Figure 26. Port B Double-Byte FIFO #1 Read Access for
36-to-18 Funneling
35
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CK B
tRWS
R/WB
t ES
EN B
t RQS
REQ B
t DS
D0B - D17B
t DH
BITS
0-17
WORD # n
BITS
18-35
BITS
0-17
WORD # n+1
BITS
18-35
BITS
0-17
WORD # n+2
NOTES:
1. A0B is held HIGH for FIFO access.
2. OEB is held HIGH.
3. WS0 is held HIGH and WS1 is held LOW for double-byte access.
4. Data-setup time tDS and data-hold time tDH, before and after
the rising edge of CKB, shown for the first write cycle, apply
similarly for all subsequent write cycles.
Figure 27. Port B Double-Byte FIFO #2 Write Access for
18-to-36 Defunneling
36
BITS
18-35
543601-12
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CK B
tRWS
R/WB
t ES
EN B
t RQS
REQ B
tA
D0B - D8B
BITS
0-8
BITS
9-17
BITS
18-26
WORD # n
D9B - D17B
BITS
9-17
BITS
18-26
BITS
18-26
BITS
27-35
BITS
27-35
BITS
0-8
BITS
9-17
WORD # n+1
BITS
27-35
BITS
0-8
WORD # n
D27B - D35B
BITS
0-8
WORD # n+1
WORD # n
D18B - D26B
BITS
27-35
BITS
9-17
BITS
18-26
WORD # n+1
BITS
0-8
WORD # n
BITS
9-17
BITS
18-26
BITS
27-35
WORD # n+1
NOTES:
1. A0B is held HIGH for FIFO access.
2. OEB is held LOW.
3. WS0 and WS1 both are held LOW for single-byte access.
4. Data-access time tA, after the rising edge of CKB, shown for the
first read cycle, applies similarly for all subsequent read cycles.
543601-11
Figure 28. Port B Single-Byte FIFO #1 Read Access for
36-to-9 Funneling
37
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
CK B
tRWS
R/WB
t ES
EN B
t RQS
REQ B
t DS
D0B - D8B
t DH
BITS
0-8
BITS
9-17
WORD # n
BITS
18-26
BITS
27-35
BITS
0-8
WORD # n+1
NOTES:
1. A0B is held HIGH for FIFO access.
2. OEB is held HIGH.
3. WS0 and WS1 both are held LOW for single-byte access.
4. Data-setup time tDS and data-hold time tDH, before and after
the rising edge of CKB, shown for the first write cycle, apply
similarly for all subsequent write cycles.
Figure 29. Port B Single-Byte FIFO #2 Write Access for
9-to-36 Defunneling
38
BITS
9-17
543601-10
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
Outside the 'almost-full' region,
acknowledge is continuous
for a continuous request.
*
*
*
Starting at the third cycle after entering the
'almost-full' region, acknowledge
occurs on every third cycle to prevent overrun
of the full condition.
*
*
CKA (CKB )
tRWS
R/WA (R/WB )
t RQS
REQ A (REQB )
t ACK
ACK A (ACKB )
t ACK
t ACK
t ACK
1
t AF
2
AF1 (AF2)
NOTES:
1. For a FIFO access to occur, REQ and EN must be held HIGH for the required setup and hold times.
2. ACK can be tied directly to EN to directly gate FIFO accesses.
Indicates where a write would take place, if ACK were tied to EN.
3. REQ must be maintained HIGH throughout the entire clock cycle for ACK to be generated.
4. When the REQ/ACK handshake is not used, ACK can be ignored,
and REQ may be tied HIGH or used as a second enable.
5. Parameters without parentheses apply to Port A. Parameters with parentheses apply to Port B.
*
543601-8
Figure 30. Write Request/Acknowledge Handshake
39
256 × 36 × 2 Bidirectional FIFO
LH543601
TIMING DIAGRAMS (cont’d)
Outside the 'almost-empty' region,
acknowledge is continuous
for a continuous request.
*
*
*
Starting at the third cycle after entering the
'almost-empty' region, acknowledge
occurs on every third cycle to prevent underrun
of the empty condition.
*
*
CKA (CKB )
tRWS
R/WA (R/WB )
t RQS
REQ A (REQB )
t ACK
ACK A (ACKB )
t ACK
t ACK
t ACK
1
t AE
2
AE2 (AE1)
NOTES:
1. For a FIFO access to occur, REQ and EN must be held HIGH for the required setup and hold times.
2. ACK can be tied directly to EN to directly gate FIFO accesses.
Indicates where a read would take place, if ACK were tied to EN.
3. REQ must be maintained HIGH throughout the entire clock cycle for ACK to be generated.
4. When the REQ/ACK handshake is not used, ACK can be ignored,
and REQ may be tied HIGH or used as a second enable.
5. Parameters without parentheses apply to Port A. Parameters with parentheses apply to Port B.
*
Figure 31. Read Request/Acknowledge Handshake
40
543601-9
256 × 36 × 2 Bidirectional FIFO
LH543601
PACKAGE DIAGRAMS
132PQFP (PQFP132-P-S950)
SECTION
0° - 8°
0.15 [0.006]
0.25 [0.010] TYP.
45°
CHAMFER
0.51 [0.020] MIN.
0.10 [0.004]
0.635
[0.025] TYP
NON-ACCUM
28.02 [1.103]
27.86 [1.097]
27.69 [1.090]
27.18 [1.070]
TOP VIEW
24.21 [0.953]
24.05 [0.947]
24.21 [0.953]
24.05 [0.947]
27.69 [1.090]
27.18 [1.070]
28.02 [1.103]
27.86 [1.097]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
0.51 [0.020]
MIN.
4.57 [0.180]
4.06 [0.160]
132 PQFP
132-pin PQFP
41
256 × 36 × 2 Bidirectional FIFO
LH543601
144TQFP (TQFP-144-P-2020)
0.50 [0.020]
TYP.
0.20 [0.008]
0.09 [0.004]
0.27 [0.010]
0.17 [0.007]
20.0
[0.787]
BASIC
22.0
[0.866]
BASIC
20.0 [0.787]
BASIC
DETAIL
22.0 [0.866]
BASIC
1.60 [0.063]
REF. MAX
1.45 [0.057]
1.35 [0.053]
0.15 [0.006]
0.05 [0.002]
0.75 [0.030]
0.47 [0.019]
1.00
[0.039]
REF.
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
144TQFP
144-pin TQFP
42
256 × 36 × 2 Bidirectional FIFO
LH543601
ORDERING INFORMATION
LH543601
Device Type
X
Package
- ##
Speed
20
25 Cycle Times (ns)
30
35
M 144-Pin, Thin Quad Flat Package (TQFP144-P-2020)
P 132-Pin, Plastic Quad Flat Package (PQFP132-P-S950)
256 x 36 x 2 Bidirectional FIFO
Example: LH543601P-20 (256 x 36 x 2 Bidirectional FIFO, 20 ns, 132-Lead, Plastic Quad Flat Package)
543601-37
43
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