Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design ISO1540, ISO1541 SLLSEB6C – JULY 2012 – REVISED JUNE 2015 ISO154x Low-Power Bidirectional I2C Isolators 1 Features • 1 • • • • • • • 3 Description 2 Isolated Bidirectional, I C Compatible, Communication Supports up to 1-MHz Operation 3-V to 5.5-V Supply Range Open-Drain Outputs With 3.5-mA Side 1 and 35mA Side 2 Sink Current Capability –40°C to +125°C Operating Temperature ±50-kV/µs Transient Immunity (Typical) HBM ESD Protection of 4 kV on All Pins; 8 kV on Bus Pins Safety and Regulatory Approvals – 4242-VPK Isolation per DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 – 2500-VRMS Isolation for 1 Minute per UL 1577 – CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 61010-1 End Equipment Standards – CQC Basic Insulation per GB4943.1-2011 This isolation technology provides for function, performance, size, and power consumption advantages when compared to optocouplers. The ISO1540 and ISO1541 devices enable a complete isolated I2C interface to be implemented within a small form factor. The ISO1540 has two isolated bidirectional channels for clock and data lines while the ISO1541 has a bidirectional data and a unidirectional clock channel. The ISO1541 is useful in applications that have a single Master while the ISO1540 is ideally fit for multimaster applications. Isolated bidirectional communications is accomplished within these devices by offsetting the Side 1 Low-Level Output Voltage to a value greater than the Side 1 High-Level Input Voltage, thus preventing an internal logic latch that otherwise would occur with standard digital isolators. 2 Applications • • • • • • The ISO1540 and ISO1541 devices are low-power, bidirectional isolators that are compatible with I2C interfaces. These devices have their logic input and output buffers separated by TI’s Capacitive Isolation technology using a silicon dioxide (SiO2) barrier. When used with isolated power supplies, these devices block high voltages, isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitive circuitry. Isolated I2C Buses SMBus and PMBus Interfaces Open-Drain Networks Motor Control Systems Battery Management I2C Level Shifting Device Information(1) PART NUMBER ISO1540 ISO1541 PACKAGE SOIC (8) BODY SIZE (NOM) 4.90 mm × 3.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic VCC2 Isolation Capacitor VCC1 SDA1 or SCL1 GND1 SDA2 or SCL2 GND2 VREF 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISO1540, ISO1541 SLLSEB6C – JULY 2012 – REVISED JUNE 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 3 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 3 4 4 4 5 6 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information ................ 10 Detailed Description ............................................ 12 9.1 Overview ................................................................. 12 9.2 Functional Block Diagrams ..................................... 12 9.3 Feature Description................................................. 14 9.4 Device Functional Modes........................................ 16 10 Application and Implementation........................ 17 10.1 Application Information.......................................... 17 10.2 Typical Application ................................................ 20 11 Power Supply Recommendations ..................... 22 12 Layout................................................................... 23 12.1 Layout Guidelines ................................................. 23 12.2 Layout Example .................................................... 23 13 Device and Documentation Support ................. 24 13.1 13.2 13.3 13.4 13.5 13.6 Documentation Support ........................................ Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 24 24 24 24 24 24 14 Mechanical, Packaging, and Orderable Information ........................................................... 24 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (May 2013) to Revision C Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 • VDE Standard changed to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 .................................................................... 1 Changes from Revision A (October 2012) to Revision B Page • Change Safety Feature From: (VDE 0884 Part 2) (Pending) To: (VDE 0884 Part 2) (Approved)......................................... 1 • Changed, VDE column From: File number: 40016131 (pending) To: File number: 40016131............................................ 16 Changes from Original (July 2012) to Revision A Page • Changed From: CSA Component Acceptance Notice 5A (Pending) To: CSA Component Acceptance Notice 5A (Approved) .............................................................................................................................................................................. 1 • Changed From: IEC 60950-1 and IEC 61010-1 End Equipment Standards (Pending) To: IEC 60950-1 and IEC 61010-1 End Equipment Standards (Approved)..................................................................................................................... 1 • Changed Regulatory Information, CSA column From: File number: 220991 (pending) To: File number: 220991 .............. 16 2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6C – JULY 2012 – REVISED JUNE 2015 5 Device Comparison Table PRODUCT RATED ISOLATION ISO1540 4242-VPK and 2500-VRMS (1) ISO1541 (1) PACKAGE CHANNEL DIRECTION Both SDA and SCL are bidirectional D-8 SDA is bidirectional SCL is unidirectional See Regulatory Information for detailed Isolation specifications. 6 Pin Configuration and Functions D Package 8-Pin SOIC Top View ISO1540 SDA1 2 SCL1 3 GND1 4 Side 1 8 VCC2 VCC1 1 7 SDA2 SDA1 2 6 SCL2 SCL1 3 5 GND2 GND1 4 Side 2 8 VCC2 Isolation Isolation VCC1 1 ISO1541 7 SDA2 6 SCL2 5 GND2 Side 1 Side 2 Pin Functions PIN I/O DESCRIPTION NAME NO. ISO1540 ISO1541 ISO1540 ISO1541 GND1 4 — — Ground, Side 1 Ground, Side 1 GND2 5 — — Ground, Side 2 Ground, Side 2 SCL1 3 I/O I Serial Clock Input/Output, Side 1 Serial Clock Input, Side 1 SCL2 6 I/O O Serial Clock Input/Output, Side 2 Serial Clock Output, Side 2 SDA1 2 I/O I/O Serial Data, Side 1 Input/Output Serial Data, Side 1 Input/Output SDA2 7 I/O I/O Serial Data Input/Output, Side 2 Serial Data Input/Output, Side 2 VCC1 1 — — Supply Voltage, Side 1 Supply Voltage, Side 1 VCC2 8 — — Supply Voltage, Side 2 Supply Voltage, Side 2 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN V Voltage VCC1, VCC2 –0.5 6 SDA1, SCL1 –0.5 VCC1 + 0.5 (3) SDA2, SCL2 –0.5 VCC2 + 0.5 (3) SDA1, SCL1 –20 20 SDA2, SCL2 –100 100 IO Output current TJ(MAX) Maximum junction temperature Tstg Storage temperature (1) (2) (3) MAX –65 UNIT V mA 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values here within are with respect to the local ground pin (GND1 or GND2) and are peak voltage values. Maximum voltage must not exceed 6 V. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 3 ISO1540, ISO1541 SLLSEB6C – JULY 2012 – REVISED JUNE 2015 www.ti.com 7.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) V(ESD) (1) (2) Electrostatic discharge Bus pins ±8000 All pins ±4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1500 Machine Model JEDEC JESD22-A115-A, all pins ±200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions MIN MAX VCC1, VCC2 Supply Voltage 3 5.5 V VSDA1, VSCL1 Input and Output Signal Voltages, Side 1 0 VCC1 V VSDA2, VSCL2 Input and Output Signal Voltages, Side 2 0 VCC2 V VIL1 Low-Level Input Voltage, Side 1 0 0.5 V VIH1 High-Level Input Voltage, Side 1 0.7 × VCC1 VCC1 V VIL2 Low-Level Input Voltage, Side 2 0 0.3 x VCC2 V VIH2 High-Level Input Voltage, Side 2 0.7 × VCC2 VCC2 IOL1 Output Current, Side 1 0.5 3.5 mA IOL2 Output Current, Side 2 0.5 35 mA Cb1 Maximum Capacitive Load, Side 1 40 pF Cb2 Maximum Capacitive Load, Side 2 400 pF (1) V fMAX Maximum Operating Frequency TA Ambient Temperature –40 125 °C TJ Junction Temperature –40 136 °C TSD Thermal Shutdown 139 171 °C (1) 1 UNIT MHz This represents the maximum frequency with the maximum bus load (Cb) and the maximum current sink (IO). If the system has less bus capacitance, then higher frequencies can be achieved. 7.4 Thermal Information ISO1540, ISO1541 THERMAL METRIC (1) D [SOIC] UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 114.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 69.6 °C/W RθJB Junction-to-board thermal resistance 55.3 °C/W ψJT Junction-to-top characterization parameter 27.2 °C/W ψJB Junction-to-board characterization parameter 54.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6C – JULY 2012 – REVISED JUNE 2015 7.5 Electrical Characteristics over recommended operating conditions, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.4 3.6 mA 2.1 3.3 mA 1.7 2.7 mA 2.5 3.8 mA 2.3 3.6 mA 1.9 3.1 mA 3.1 4.7 2.8 4.4 2.3 3.7 3.1 4.7 2.9 4.5 2.5 4 mA SUPPLY CURRENT (3 V ≤ VCC1, VCC2 ≤ 3.6 V) ICC1 Supply Current, Side 1 ICC2 Supply Current, Side 2 ICC1 Supply Current, Side 1 ICC2 Supply Current, Side 2 ISO1540 ISO1541 ISO1540 and ISO1541 ISO1540 ISO1541 ISO1540 and ISO1541 VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2 VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2 See Figure 18; R1,R2 = Open, C1,C2 = Open SUPPLY CURRENT (4.5 V ≤ VCC1, VCC2 ≤ 5.5 V) ICC1 Supply Current, Side 1 ICC2 Supply Current, Side 2 ICC1 Supply Current, Side 1 ICC2 Supply Current, Side 2 ISO1540 ISO1541 ISO1540 and ISO1541 ISO1540 ISO1541 ISO1540 and ISO1541 VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2 VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2 See Figure 18; R1,R2 = Open, C1,C2 = Open mA mA mA SIDE 1 (ONLY) VILT1 Voltage Input Threshold “Low”, Side 1 (SDA1, SCL1) 500 550 660 mV VIHT1 Voltage Input Threshold “High”, Side 1 (SDA1, SCL1) 540 610 700 mV VHYST1 Voltage Input Hysteresis, Side 1 VIHT1- VILT1 40 60 VOL1 (1) Low-Level Output Voltage, Side 1 (SDA1,SCL1) ΔVOIT1 (1) (2) Low-Level Output Voltage to High-Level Input Voltage Threshold Difference, Side 1 (SDA1, SCL1) 650 mV 800 mV 0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA 50 mV SIDE 2 (ONLY) VILT2 Voltage Input Threshold “Low”, Side 2 (SDA2, SCL2) 0.3 x VCC2 0.4 x VCC2 V VIHT2 Voltage Input Threshold “High”, Side 2 (SDA2, SCL2) 0.4 x VCC2 0.5 x VCC2 V VHYST2 Voltage Input Hysteresis, Side 2 VIHT2 - VILT2 0.05 x VCC2 VOL2 Low-Level Output Voltage, Side 2 (SDA2, SCL2) 0.5 mA ≤ (ISDA2 and ISCL2) ≤ 35 mA |II| Input Leakage Currents (SDA1, SCL1, SDA2, SCL2) VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2 CI Input Capacitance to Local Ground (SDA1, SCL1, SDA2, SCL2) VI = 0.4 x sin(2E6πt) + 2.5 V CMTI Common-Mode Transient Immunity See Figure 20 VCCUV (3) VCC Undervoltage Lockout Threshold (Side 1 and Side 2) V 0.4 V 10 µA BOTH SIDES (1) (2) (3) 0.01 7 pF 25 50 kV/µs 2.1 2.5 2.8 V This parameter does not apply to the ISO1541 SCL1 line as it is unidirectional. ∆VOIT1 = VOL1 – VIHT1. This represents the minimum difference between a Low-Level Output Voltage and a High-Level Input Voltage Threshold to prevent a permanent latch condition that would otherwise exist with bidirectional communication. Any VCC voltages, on either side, less than the minimum will ensure device lockout. Both VCC voltages greater than the maximum will prevent device lockout. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 5 ISO1540, ISO1541 SLLSEB6C – JULY 2012 – REVISED JUNE 2015 www.ti.com 7.6 Timing Requirements tSP Input Noise Filter tUVLO Time to recover from Undervoltage Lock-out See Figure 21 2.7 V to 0.9 V MIN TYP 5 12 30 50 MAX UNIT ns 110 µs 7.7 Switching Characteristics over recommended operating conditions, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3 V ≤ VCC1, VCC2 ≤ 3.6 V Output Signal Fall Time (SDA1, SCL1) See Figure 18 R1 = 953 Ω, C1 = 40 pF 0.7 × VCC1 to 0.3 × VCC1 8 17 29 tf1 0.9 × VCC1 to 900 mV 16 29 48 Output Signal Fall Time (SDA2, SCL2) See Figure 18 R2 = 95.3 Ω, C2 = 400 pF 0.7 × VCC2 to 0.3 × VCC2 14 23 47 tf2 0.9 × VCC2 to 400 mV 35 50 100 tpLH1-2 Low-to-High Propagation Delay, Side 1 to Side 2 0.55 V to 0.7 × VCC2 33 65 ns tPHL1-2 High-to-Low Propagation Delay, Side 1 to Side 2 0.7 V to 0.4 V 90 181 ns PWD1-2 Pulse Width Distortion |tpHL1-2 – tpLH1-2| 55 123 ns tPLH2-1 (1) Low-to-High Propagation Delay, Side 2 to Side 1 0.4 × VCC2 to 0.7 × VCC1 47 68 ns tPHL2-1 (1) High-to-Low Propagation Delay, Side 2 to Side 1 0.4 × VCC2 to 0.9 V 67 109 ns PWD2-1 (1) Pulse Width Distortion |tpHL2-1 – tpLH2-1| 20 49 ns tLOOP1 (1) Round-trip propagation delay on Side 1 100 165 ns See Figure 18 R1 = 953 Ω, R2 = 95.3 Ω, C1, C2 = 10 pF See Figure 19; R1 = 953 Ω, C1 = 40 pF R2 = 95.3 Ω, C2 = 400 pF 0.4 V to 0.3 × VCC1 ns ns 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V Output Signal Fall Time (SDA1, SCL1) See Figure 18 R1 = 1430 Ω, C1 = 40 pF 0.7 × VCC1 to 0.3 × VCC1 6 11 20 tf1 0.9 × VCC1 to 900 mV 13 21 39 Output Signal Fall Time (SDA2, SCL2) See Figure 18 R2 = 143 Ω, C2 = 400 pF 0.7 × VCC2 to 0.3 × VCC2 10 18 35 tf2 0.9 × VCC2 to 400 mV 28 41 76 tpLH1-2 Low-to-High Propagation Delay, Side 1 to Side 2 0.55 V to 0.7 × VCC2 31 62 ns tPHL1-2 High-to-Low Propagation Delay, Side 1 to Side 2 0.7 V to 0.4 V 70 139 ns PWD1-2 Pulse Width Distortion |tpHL1-2 – tpLH1-2| 38 80 ns tPLH2-1 (1) Low-to-High Propagation Delay, Side 2 to Side 1 0.4 × VCC2 to 0.7 × VCC1 55 80 ns tPHL2-1 (1) High-to-Low Propagation Delay, Side 2 to Side 1 0.4 × VCC2 to 0.9 V 47 85 ns PWD2-1 (1) Pulse Width Distortion |tpHL2-1 – tpLH2-1| 8 21 ns tLOOP1 (1) Round-trip propagation delay on Side 1 110 180 ns (1) 6 See Figure 18 R1 = 1430 Ω, R2 = 143 Ω, C1, 2 = 10 pF See Figure 19; R1 = 1430 Ω, C1 = 40 pF R2 = 143 Ω, C2 = 400 pF 0.4 V to 0.3 × VCC1 ns ns This parameter does not apply to the ISO1541 SCL1 line as it is unidirectional. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6C – JULY 2012 – REVISED JUNE 2015 7.8 Typical Characteristics 3.0 0.800 o 0.760 0.740 IOL1 = 3.5 mA 0.720 0.700 TA = 25 C 2.5 Output Current, IOL1 (mA) Output Voltage, VOL1 (V) 0.780 IOL1 = 0.5 mA 0.680 0.660 0.640 2.0 1.5 1.0 0.5 0.0 0.620 -0.5 0.600 −40 −25 −10 5 20 35 50 65 80 Free−Air Temperature (°C) 95 110 125 0 18 16 16 14 14 Fall Time, tf1 (ns) Fall Time, tf1 (ns) 20 18 12 10 8 2 VCC1 = 3.3 V C1 = 40 pF Fall Time measured from 70% to 30% VCC1 0 −40 −25 −10 95 G001 0.8 0.9 25 20 15 10 95 110 125 110 125 G002 15 10 VCC2 = 5 V C2 = 400 pF Fall Time measured from 70% to 30% VCC2 0 −40 −25 −10 G003 Figure 5. Side 2: Output Fall Time vs Free-Air Temperature 95 20 5 R2 = 95.3 Ω R2 = 2.2 kΩ 5 20 35 50 65 80 Free-Air Temperature (°C) R1 = 1430 Ω R1 = 2.2 kΩ Figure 4. Side 1: Output Fall Time vs Free-air Temperature 25 5 20 35 50 65 80 Free-Air Temperature (°C) 0.7 VCC1 = 5 V C1 = 40 pF Fall Time measured from 70% to 30% VCC1 0 −40 −25 −10 110 125 Fall Time, tf2 (ns) Fall Time, tf2 (ns) 6 30 0 −40 −25 −10 0.6 8 30 5 0.5 10 2 Figure 3. Side 1: Output Fall Time vs Free-Air Temperature VCC2 = 3.3 V C2 = 400 pF Fall Time measured from 70% to 30% VCC2 0.4 12 4 R1 = 953 Ω R1 = 2.2 kΩ 5 20 35 50 65 80 Free-Air Temperature (°C) 0.3 Figure 2. Side 1: Output Low Current vs SDA1 or SCL1 Applied Voltage 20 4 0.2 Applied Voltage, VSDA1, VSCL1 (V) Figure 1. Side 1: Output Low Voltage vs Free-Air Temperature 6 0.1 5 20 35 50 65 80 Free-Air Temperature (°C) R2 = 143 Ω R2 = 2.2 kΩ 95 110 125 G004 Figure 6. Side 2: Output Fall Time vs Free-Air Temperature Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 7 ISO1540, ISO1541 SLLSEB6C – JULY 2012 – REVISED JUNE 2015 www.ti.com Typical Characteristics (continued) 40 120 C2 = 10 pF C2 = 10 pF Propagation Delay, tPHL1−2 (ns) Propagation Delay, tPLH1−2 (ns) 45 35 30 25 20 15 10 VCC1 and VCC2 = 3.3 V, R2 = 95.3 Ω VCC1 and VCC2 = 5 V, R2 = 143 Ω 5 0 −40 −25 −10 5 20 35 50 65 80 Free-Air Temperature (°C) 95 80 60 40 20 G005 80 Propagation Delay, tPHL1−2 (ns) 90 1045 1040 1035 1030 1025 1020 1015 1010 1005 1000 −40 −25 −10 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 5 20 35 50 65 80 Free-Air Temperature (°C) 95 110 125 G006 60 50 40 30 20 10 R2 = 2.2 kΩ C2 = 400 pF 0 −40 −25 −10 110 125 G007 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 5 20 35 50 65 80 Free-Air Temperature (°C) 95 110 125 G008 Figure 10. tPHL1-2 Propagation Delay vs Free-Air Temperature 70 80 C1 = 10 pF C1 = 10 pF 60 Propagation Delay, tPHL2−1 (ns) Propagation Delay, tPLH2−1 (ns) 95 70 Figure 9. tPLH1-2 Propagation Delay vs Free-Air Temperature 50 40 30 20 VCC1 and VCC2 = 3.3 V, R1 = 953 Ω VCC1 and VCC2 = 5 V, R1 = 1430 Ω 10 0 −40 −25 −10 5 20 35 50 65 80 Free-Air Temperature (°C) 95 110 125 Figure 11. tPLH2-1 Propagation Delay vs Free-Air Temperature 8 5 20 35 50 65 80 Free-Air Temperature (°C) Figure 8. tPHL1-2 Propagation Delay vs Free-Air Temperature 1050 R2 = 2.2 kΩ C2 = 400 pF VCC1 and VCC2 = 3.3 V, R2 = 95.3 Ω VCC1 and VCC2 = 5 V, R2 = 143 Ω 0 −40 −25 −10 110 125 Figure 7. tPLH1-2 Propagation Delay vs Free-Air Temperature Propagation Delay, tPLH1−2 (ns) 100 70 60 50 40 30 20 VCC1 and VCC2 = 3.3 V, R1 = 953 Ω VCC1 and VCC2 = 5 V, R1 = 1430 Ω 10 0 −40 −25 −10 G009 5 20 35 50 65 80 Free-Air Temperature (°C) 95 110 125 G010 Figure 12. tPHL2-1 Propagation Delay vs Free-Air Temperature Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6C – JULY 2012 – REVISED JUNE 2015 Typical Characteristics (continued) 146 80 R1 = 2.2 kΩ C1 = 40 pF Propagation Delay, tPHL2−1 (ns) Propagation Delay, tPLH2−1 (ns) 148 144 142 140 138 136 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 134 132 −40 −25 −10 5 20 35 50 65 80 Free-Air Temperature (°C) 95 60 50 40 30 20 10 G011 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 5 20 35 50 65 80 Free-Air Temperature (°C) 95 110 125 G012 Figure 14. tPHL2-1 Propagation Delay vs Free-Air Temperature 140 600 C1 = 40 pF C2 = 400 pF 595 tLOOP1 (ns) 100 tLOOP1 (ns) R1 = 2.2 kΩ C1 = 40 pF 0 −40 −25 −10 110 125 Figure 13. tPLH2-1 Propagation Delay vs Free-Air Temperature 120 70 80 60 R1 = 2.2 kΩ C1 = 40 pF R2 = 2.2 kΩ C2 = 400 pF 590 585 40 20 580 VCC1 and VCC2 = 3.3 V, R1 = 953Ω, R2 = 95.3Ω VCC1 and VCC2 = 5 V, R1 = 1430Ω, R2 = 143Ω 0 −40 −25 −10 5 20 35 50 65 80 Free-Air Temperature (°C) 95 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 110 125 Figure 15. tLOOP1 vs Free-Air Temperature 575 −40 −25 −10 G013 5 20 35 50 65 80 Free-Air Temperature (°C) 95 110 125 G014 Figure 16. tLOOP1 vs Free-Air Temperature 70 60 CMTI (kV/µs) 50 40 30 20 10 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 0 −40 −25 −10 5 20 35 50 65 80 Free-Air Temperature (°C) 95 110 125 G015 Figure 17. CMTI vs Free-Air Temperature Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 9 ISO1540, ISO1541 SLLSEB6C – JULY 2012 – REVISED JUNE 2015 www.ti.com 8 Parameter Measurement Information VCC1 R1 + + R1 R2 VCC2 R2 SDA1 SDA2 ISO1540/1 SCL1 SCL2 C1 C1 C2 C2 Figure 18. Test Diagram VCC1 + SDA1 or SCL1 Output - R1 C1 R2 Isolation VCC1 GND1 VCC2 SDA1 SCL1 [ISO1540 Only] C2 tLOOP 1 0.3VCC1 0.4V GND1 GND2 Figure 19. tLoop1 Setup and Timing Diagram VCCx VCCy 2 kW 2 kW Isolation Input + Output GNDx GNDy VCMTI Figure 20. Common-Mode Transient Immunity Test Circuit 10 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6C – JULY 2012 – REVISED JUNE 2015 Parameter Measurement Information (continued) VCCx VCCy VCCx Ry SDAx or SCLx Isolation 0V Side x, Side y VCCx,VCCy Ry 1, 2 3.3 V, 3.3 V 95.3 Ω 2, 1 3.3 V, 3.3 V 953 Ω + Output - GNDx GNDy or VCCx VCCy VCCy Ry 0V Isolation SDAx or SCLx + Output - GNDx GNDy VCCx or VCCy 2.7 V tUVLO 0.9 V Output Figure 21. tUVLO Test Circuit and Timing Diagrams Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 11 ISO1540, ISO1541 SLLSEB6C – JULY 2012 – REVISED JUNE 2015 www.ti.com 9 Detailed Description 9.1 Overview The I2C bus is used in a wide range of applications because it is simple to use. The bus consists of a two-wire communication bus that supports bidirectional data transfer between a master and several slaves. The master or processor controls the bus – in particular, the serial clock (SCL) line. Data is transferred between the master and slave through a serial data (SDA) line. This data can be transferred in four speeds: standard mode (0 to 100 kbps), fast mode (0 to 400 kbps), fast-mode plus (0 to 1 Mbps), and high-speed mode (0 to 3.4 Mbps). The most common speeds are the standard and fast modes. The I2C Bus operates in bidirectional, half-duplex mode, while standard digital isolators are unidirectional devices. To make efficient use of one technology supporting the other, external circuitry is required that separates the bidirectional bus into two unidirectional signal paths without introducing significant propagation delay. These devices have their logic input and output buffers separated by TI's capacitive isolation technology using a silicon dioxide (SiO2) barrier. When used in conjunction with isolated power supplies, these devices block high voltages, isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitive circuitry. 9.2 Functional Block Diagrams VCC1 VCC2 SDA2 VREF SCL1 Isolation Capacitor SDA1 SCL2 GND1 GND2 VREF Figure 22. ISO1540 Block Diagram 12 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6C – JULY 2012 – REVISED JUNE 2015 Functional Block Diagrams (continued) VCC2 SDA1 VREF SCL1 Isolation Capacitor VCC1 GND1 SDA2 SCL2 GND2 Figure 23. ISO1541 Block Diagram Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 13 ISO1540, ISO1541 SLLSEB6C – JULY 2012 – REVISED JUNE 2015 www.ti.com 9.3 Feature Description The ISO device enables a complete isolated I²C interface to be implemented within a small form factor having following features: Table 1. Features List ISO1540 ISO1541 UL 1577 Isolation Voltage (Single) (Vrms) FEATURES DESCRIPTION 2500 2500 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Transient Overvoltage Rating (Vpk) 4242 4242 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Working Voltage Rating (Vpk) 566 566 CSA Isolation Rating (Vrms) 2800 2800 CSA 60950-1 Basic Working (Vrms) 390 390 CSA 61010-1 Basic Working (Vrms) 300 300 CSA 61010-1 Reinforced Working (Vrms) 150 150 1 1 Data Rate (Mbps) Number of Channels 2 2 Serial Clock Bidirectional Unidirectional Serial Data Bidirectional Bidirectional –40 to 125 –40 to 125 SOIC (8) SOIC (8) Operating Temperature (°C) Pin/Package 9.3.1 Insulation and Safety-Related Specification for D-8 Package over recommended operating conditions, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (Clearance) Shortest terminal-to-terminal distance through air L(I02) Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the package surface CTI Tracking resistance (comparative tracking index) DIN IEC 60112 / VDE 0303 Part 1 >400 V Minimum internal gap (internal clearance) Distance through the insulation 0.014 mm RIO Isolation resistance, input to output (1) CIO Barrier capacitance, input to output (1) CI Input capacitance (2) (1) (2) 4.8 mm 4.3 mm VIO = 500 V, TA = 25°C >1012 Ω VIO = 500 V, 100°C ≤ TA ≤ TA max >1011 Ω 1 pF VIO = 0.4 x sin(2E6πt) See Electrical Characteristics pF All pins on each side of the barrier tied together creating a 2-terminal device. Measured from input pin to ground. space NOTE Creepage and clearance requirements should be applied according to the specific application isolation standards. Care should be taken to maintain these distances on a board design to ensure that the mounting pads for the isolator do not reduce this distance. Creepage and clearance on the printed-circuit-board (PCB) become equal in certain cases. Techniques such as inserting grooves and/or ribs on the PCB are used to help increase these specifications. 14 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6C – JULY 2012 – REVISED JUNE 2015 9.3.2 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics (3) over recommended operating conditions, unless otherwise noted PARAMETER VIORM VPR TEST CONDITIONS SPECIFICATION UNIT 566 VPEAK Maximum working insulation voltage Input-to-Output test voltage Method a, After environmental tests subgroup 1, VPR = VIORM × 1.6, t = 10 s, Partial Discharge < 5 pC 906 Method b1, After environmental tests subgroup 1, VPR = VIORM × 1.875, t = 1 s (100% production), Partial Discharge < 5 pC 1062 After Input/Output safety test subgroup 2/3, VPR = VIORM × 1.2, t = 10 s, Partial Discharge < 5 pC 680 VPEAK VIOTM Transient overvoltage VTEST = VOITM t = 60 s (qualification) t = 1 s (100% production) 4242 VPEAK RS Insulation resistance VIO = 500 V at TS >109 Ω Pollution degree (3) 2 Climatic Classification 40/125/21 9.3.3 IEC 60664-1 Ratings Table PARAMETER Basic isolation group Installation classification TEST CONDITIONS SPECIFICATION Material group II Rated mains voltage ≤ 150 VRMS I–IV Rated mains voltage ≤ 300 VRMS I–III Rated mains voltage ≤ 400 VRMS I–II 9.3.4 Safety Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current-limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER IS Safety input, output, or supply current TS Maximum case temperature TEST CONDITIONS D-8 MIN TYP MAX RθJA = 114.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 198 RθJA = 114.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C 303 150 UNIT mA °C The safety-limiting constraint is the absolute maximum junction temperature specified in Absolute Maximum Ratings. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in Thermal Information is that of a device installed on a High-K Test Board for Leaded Surface Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 15 ISO1540, ISO1541 SLLSEB6C – JULY 2012 – REVISED JUNE 2015 www.ti.com 350 VCC1 = VCC2 = 3.6 V Safety Limiting Current (mA) 300 250 200 VCC1 = VCC2 = 5.5 V 150 100 50 0 0 50 100 150 200 o Case Temperature ( C) Figure 24. ISO154x Thermal Derating Curve 9.3.5 Regulatory Information VDE CSA UL CQC Certified according to DIN V VDE V 0884-10 (VDE V 088410):2006-12 and DIN EN 61010-1 Certified according to CSA Component Acceptance Notice 5A, CSA/IEC 60950-1 and CSA/IEC 61010-1 Basic Insulation Maximum Transient Overvoltage, 4242 VPK Maximum Working Voltage, 566 VPK Basic insulation per CSA 60950-1-07 and IEC 60950-1 (2nd Ed), 390 VRMS maximum working voltage Basic insulation per CSA 61010-1-04 Single Protection Isolation and IEC 61010-1 (2nd Ed), 300 VRMS Voltage, 2500 VRMS (1) maximum working voltage Reinforced insulation per CSA 610101-04 and IEC 61010-1 (2nd Ed), 150 VRMS maximum working voltage Basic Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage Certificate number: 40016131 Master contract number: 220991 Certificate number : CQC14001109540 (1) Recognized under UL 1577 Component Recognition Program File number: E181974 Certified according to GB4943.12011 Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577. 9.4 Device Functional Modes ISO154x functional modes are shown in Table 2. Table 2. Function Table (1) (1) (2) 16 POWER STATE INPUT OUTPUT VCC1 or VCC2 < 2.1 V X Z VCC1 and VCC2 > 2.8 V L L VCC1 and VCC2 > 2.8 V H Z VCC1 and VCC2 > 2.8 V Z (2) ? H = High Level; L = Low Level; Z = High Impedance or Float; X = Irrelevant; ? = Indeterminate Invalid input condition as an I2C system requires that a pullup resistor to VCC is connected. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6C – JULY 2012 – REVISED JUNE 2015 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information 10.1.1 I2C Bus Overview The Inter-Integrated Circuit (I2C) bus is a single-ended, multi-master, 2-wire bus for efficient inter-IC communication in half-duplex mode. I2C uses open-drain technology, requiring two lines, Serial Data (SDA) and Serial Clock (SCL), to be connected to VDD by resistors (see Figure 25). Pulling the line to ground is considered a logic Zero while letting the line float is a logic One. This is used as a channel access method. Transitions of logic states must occur while SCL is Low, transitions while SCL is high indicate START and STOP conditions. Typical supply voltages are 3.3 V and 5 V, although systems with higher or lower voltages are permitted. VDD RPU RPU RPU RPU RPU RPU RPU RPU SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL GND GND GND GND μC Master ADC Slave DAC Slave μC Slave Figure 25. I2C Bus I2C communication uses a 7-bit address space with 16 reserved addresses, so a theoretical maximum of 112 nodes can communicate on the same bus. In praxis, however, the number of nodes is limited by the specified, total bus capacitance of 400 pF, which restricts communication distances to a few meters. The specified signaling rates for the ISO1540 and ISO1541 are 100 kbps (Standard mode), 400 kbps (Fast mode), 1 Mbps (Fast mode plus). The bus has two roles for nodes: master and slave. A master node issues the clock, slave addresses, and also initiates and ends data transactions. A slave node receives the clock and addresses and responds to requests from the master. Figure 26 shows a typical data transfer between master and slave. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 17 ISO1540, ISO1541 SLLSEB6C – JULY 2012 – REVISED JUNE 2015 www.ti.com Application Information (continued) 7-bit ADDRESS SDA SCL R/W ACK 8 9 1 -7 8-bit DATA 8-bit DATA ACK 1 -8 9 ACK / NACK 1 -8 9 S P START Condition STOP condition Figure 26. Timing Diagram of a Complete Data Transfer The master initiates a transaction by creating a START condition, following by the 7-bit address of the slave it wishes to communicate with. This is followed by a single Read/Write bit, representing whether the master wishes to write to (0), or to read from (1) the slave. The master then releases the SDA line to allow the slave to acknowledge the receipt of data. The slave responds with an acknowledge bit (ACK) by pulling SDA low during the entire high time of the 9th clock pulse on SCL, after which the master continues in either transmit or receive mode (according to the R/W bit sent), while the slave continues in the complementary mode (receive or transmit, respectively). The address and the 8-bit data bytes are sent most significant bit (MSB) first. The START bit is indicated by a high-to-low transition of SDA while SCL is high. The STOP condition is created by a low-to-high transition of SDA while SCL is high. If the master writes to a slave, it repeatedly sends a byte with the slave sending an ACK bit. In this case, the master is in master-transmit mode and the slave is in slave-receive mode. If the master reads from a slave, it repeatedly receives a byte from the slave, while acknowledging (ACK) the receipt of every byte but the last one (see Figure 27). In this situation, the master is in master-receive mode and the slave is in slave-transmit mode. The master ends the transmission with a STOP bit, or may send another START bit to maintain bus control for further transfers. S Slave Address W A From Master to Slave DATA A DATA AP A = acknowledge A = not acknowledge Master Transmitter writing to Slave Receiver S = Start From Slave to Master P = Stop S Slave Address R A DATA A DATA Master Receiver reading from Slave Transmitter AP R = Read W = Write Figure 27. Transmit or Receive Mode Changes During a Data Transfer When writing to a slave, a master mainly operates in transmit-mode and only changes to receive-mode when receiving acknowledgment from the slave. When reading from a slave, the master starts in transmit-mode and then changes to receive-mode after sending a READ request (R/W bit = 1) to the slave. The slave continues in the complementary mode until the end of a transaction. Note, that the master ends a reading sequence by not acknowledging (NACK) the last byte received. This procedure resets the slave state machine and allows the master to send the STOP command. 18 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6C – JULY 2012 – REVISED JUNE 2015 Application Information (continued) 10.1.2 Isolator Functional Principle To isolate a bidirectional signal path (SDA or SCL), the ISO1540 internally splits a bidirectional line into two unidirectional signal lines, each of which is isolated through a single-channel digital isolator. Each channel output is made open-drain to comply with the open-drain technology of I2C. Side 1 of the ISO1540 connects to a lowcapacitance I2C node, while Side 2 is designed for connecting to a fully loaded I2C bus with up to 400 pF capacitance. VCC1 VCC2 A RPU1 VC-out RPU2 B SDA1 SDA2 ISO1540 Cnode 40mV Cbus C 50mV D GND1 VSDA1 GND2 VREF VILT1 VIHT1 VOL1 Figure 28. SDA Channel Design and Voltage Levels at SDA1 At first sight, the arrangement of the internal buffers suggests a closed signal loop that is prone to latch-up. However, this loop is broken by implementing an output buffer (B) whose output low-level is raised by a diode drop to approximately 0.75 V, and the input buffer (C) that consists of a comparator with defined hysteresis. The comparator’s upper and lower input thresholds then distinguish between the proper low-potential of 0.4 V maximum driven directly by SDA1 and the buffered output low-level of B. Figure 29 demonstrate the switching behavior of the I2C isolator, ISO1540, between a master node at SDA1 and a heavy loaded bus at SDA2. VCC2 SDA2 VCC1 VCC1 VCC2 VOL1 SDA1 50% VIHT1 30% receive delay VCC1 receive delay receive delay transmit delay VCC1 VCC2 VCC2 transmit delay SDA1 VIHT2 SDA2 50% 30% Figure 29. SDA Channel Timing in Receive and Transmit Directions 10.1.2.1 Receive Direction (Left Diagram of Figure 29) When the I2C bus drives SDA2 low, SDA1 follows after a certain delay in the receive path. Its output low will be the buffered output of VOL1 = 0.75 V, which is sufficiently low to be detected by Schmitt-trigger inputs with a minimum input-low voltage of VIL = 0.9 V at 3 V supply levels. Once SDA2 is released, its voltage potential increases towards VCC2 following the time-constant formed by RPU2 and Cbus. After the receive delay, SDA1 is released and also rises towards VCC1, following the time-constant RPU1 × Cnode. Because of the significant lower time-constant, SDA1 may reach VCC1 before SDA2 reaches VCC2 potential. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 19 ISO1540, ISO1541 SLLSEB6C – JULY 2012 – REVISED JUNE 2015 www.ti.com Application Information (continued) 10.1.2.2 Transmit Direction (Right Diagram of Figure 29) When a master drives SDA1 low, SDA2 follows after a certain delay in the transmit direction. When SDA2 turns low it also causes the output of buffer B to turn low but at a higher 0.75 V level. This level cannot be observed immediately as it is overwritten by the master’s lower low-level. However, when the master releases SDA1, its voltage potential increases and first must pass the upper input threshold of the comparator, VIHT1, to release SDA2. SDA1 then increases further until it reaches the buffered output level of VOL1 = 0.75 V, maintained by the receive path. Once comparator C turns high, SDA2 is released after the delay in transmit direction. It takes another receive delay until B’s output turns high and fully releases SDA1 to move toward VCC1 potential. 10.2 Typical Application In Figure 30, the ultra low-power micro controller, MSP430G2132, controls the I2C data traffic of configuration data and conversion results for the analog inputs and outputs. Low-power data converters build the analog interface to sensors and actuators. The ISO1541 provides the necessary isolation between different ground potentials of the system controller, remote sensor, and actuator circuitry to prevent ground loop currents that otherwise may falsify the acquired data. The entire circuit operates from a single 3.3-V supply. A low-power push-pull converter, SN6501, drives a centertapped transformer whose output is rectified and linearly regulated to provide a stable 5-V supply for the data converters. VS 3.3V 0.1μF 2 Vcc D2 3 1:2.2 MBR0520L 1 SN6501 GND D1 10μF 0.1μF OUT 5 ON GND 5VISO 0.1μF 9 2 10 1Ω 10μF 8 VDD 10μF LP2981-50 3 1 4,5 IN 1 MBR0520L SDA 0.1μF 0.1μF 1.5k 2 5 6 DVcc XOUT MSP430 XIN G2132 SDA SCL DVss 4 9 8 0.1μF 1.5k 1.5k 1.5k 1 8 VCC1 VCC2 2 7 SDA1 SDA2 ISO1541 3 6 SCL1 SCL2 GND1 GND2 4 5 SCL SDA 5VISO 4 4 Analog Inputs SCL ADS1115 ADDR GND RDY 3 ISO-BARRIER AIN0 AIN3 7 2 5VISO 6 22μF 0.1μF VOUT REF5040 15 4 12 3 A2 VDD IOVDD VREFH 11 1 SDA VOUTA 10 SCL DAC8574 9 LDAC 14 A1 VOUTD 8 A0 A3 GND VREFL 13 16 6 5VISO 2 VIN 1μF GND 4 4 Analog Outputs 5 Figure 30. Isolated I2C Data Acquisition System 10.2.1 Design Requirements Recommended power supply voltages (VCC1 and VCC2) must be from 3 V to 5.5 V. Recommended decoupling capacitor of 0.1-µF is required between both VCC1 to GND1 and VCC2 to GND2, to take care of power supply voltages transient and to ensure reliable operation at all data rates. 20 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6C – JULY 2012 – REVISED JUNE 2015 Typical Application (continued) 10.2.2 Detailed Design Procedure The power supply capacitor of 0.1-µF must be placed as close to the power supply pins as possible. Recommended placement of capacitors must be 2-mm maximum from input and output power supply pins (VCC1 and VCC2). Maximum load permissible on input SDA1 and SCL1 lines is ≤ 40 pF and on output lines SDA2 and SCL2 is ≤ 400 pF. Minimum pullup resistors on input SDA1 and SCL1 lines to VCC1 must be chosen in such a way that input current drawn is ≤ 3.5 mA. Minimum pullup resistors on input SDA2 and SCL2 lines to VCC2 must be chosen in such a way that output current drawn is ≤ 35 mA. Whereas maximum pullup resistors on input lines (SDA1 and SCL1) to VCC1 and on output lines (SDA1 and SCL1) to VCC2, will depend on load and rise time requirements on respective lines. ISO1540 2mm max Isolation Capacitor 2mm max VCC1 1 0.1PF 1k: 1k: SDA1 2 SCL1 3 GND1 4 Side 1 VCC2 8 0.1PF 1k: 1k: SDA2 7 SCL2 6 GND2 ` 5 Side 2 Figure 31. Typical ISO1540 Circuit Hookup ISO1541 2mm max Isolation Capacitor 2mm max VCC1 1 0.1PF 1k: 1k: SDA1 2 SCL1 3 GND1 4 Side 1 VCC2 8 0.1PF 1k: 1k: SDA2 7 SCL2 6 GND2 5 Side 2 Figure 32. Typical ISO1541 Circuit Hookup Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 21 ISO1540, ISO1541 SLLSEB6C – JULY 2012 – REVISED JUNE 2015 www.ti.com Typical Application (continued) 10.2.3 Application Curve o 500 mV/div TA = 25 C VCC1 = 3.6 V 900 mV VOL1 GND1 Time - 50 ns/div Figure 33. Side 1: Low-to-High Transition 11 Power Supply Recommendations To ensure reliable operation at all data rates and supply voltages, TI recommends a 0.1-µF bypass capacitor at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as TI's SN6501. For such applications, detailed power supply design and transformer selection recommendations are available in SN6501 data sheet (SLLSEA0). 22 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6C – JULY 2012 – REVISED JUNE 2015 12 Layout 12.1 Layout Guidelines A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 34). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane, and low-frequency signal layer. • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in2. • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. NOTE For detailed layout recommendations, see Application Note Digital Isolator Design Guide, SLLA284. 12.1.1 PCB Material For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the requirements of Underwriters Laboratories UL94-V0, and is preferred over less expensive alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics. 12.2 Layout Example High-speed traces 10 mils Ground plane 40 mils Keep this space free from planes, traces , pads, and vias FR-4 0r ~ 4.5 Power plane 10 mils Low-speed traces Figure 34. Recommended Layer Stack Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 23 ISO1540, ISO1541 SLLSEB6C – JULY 2012 – REVISED JUNE 2015 www.ti.com 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation For related documentation see the following: • SLLSEA0, Transformer Driver for Isolated Power Supplies • SLLA284, Digital Isolator Design Guide • SLLA353, TI Isolation Glossary 13.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 3. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ISO1540 Click here Click here Click here Click here Click here ISO1541 Click here Click here Click here Click here Click here 13.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 24 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ISO1540D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 IS1540 ISO1540DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 IS1540 ISO1541D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 IS1541 ISO1541DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 IS1541 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ISO1540DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO1541DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO1540DR SOIC D 8 2500 367.0 367.0 38.0 ISO1541DR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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