Infineon ADM6992F Fiber to fast ethernet converter Datasheet

Data Sheet, Rev. 1.02, Nov. 2005
NINJA F/FX (ADM6992F/FX)
Fiber to Fast Ethernet Converter
Communications
N e v e r
s t o p
t h i n k i n g .
Edition 2005-11-25
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Fiber to Fast Ethernet Converter
Revision History: 2005-11-25, Rev. 1.02
Previous Version:
Page/Date
Subjects (major changes since last revision)
2004-04-02 Rev.1.0, First release of NINJA F (ADM6992F)
2005-09-09 Changed to the new Infineon format
2005-09-09 Rev.1.01 when changed to the new Infineon format
2005-11-25 Rev. 1.01 changed to Rev. 1.02
Minor change. Included Green package information
Trademarks
ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®, FALC®, GEMINAX®, IDEC®,
INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®, MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®,
QUAT®, QuadFALC®, SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®,
10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™,
VDSLite™ are trademarks of Infineon Technologies AG. Microsoft® is a registered trademark of Microsoft
Corporation, Linux® of Linus Torvalds, Visio® of Visio Corporation, and FrameMaker® of Adobe Systems
Incorporated.
Template: template_A4_3.0.fm / 3 / 2005-01-17
NINJA F/FX
ADM6992F/FX
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1
1.1
1.2
1.3
1.4
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Lengths Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.3
Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Type and Buffer Type Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
11
12
3
3.1
3.2
3.3
3.3.1
3.3.2
3.4
3.4.1
3.4.2
3.4.3
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
3.5.10
3.5.11
3.5.12
3.5.13
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
3.7
3.7.1
3.7.2
Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OAM Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10/100M PHY Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Negotiation and Speed Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Store & Forward Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modified Cut-through Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII cut-through Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAC Address Learning & Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hash Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Recognition and Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Back off Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inter-Packet Gap (IPG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Illegal Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Half Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bandwidth Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto TP MDIX function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Converter Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OAM Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OAM frame transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic User Frame Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic User Frame Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Remote Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Management Interface (SMI) Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preamble Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read EEPROM Register via SMI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
19
20
20
20
21
21
22
22
22
22
22
22
23
23
23
23
23
23
24
24
24
24
24
24
25
25
25
26
26
26
27
28
28
Data Sheet
4
8
8
8
9
9
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Table of Contents
3.7.3
3.8
3.8.1
Write EEPROM Register via SMI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Write EEPROM Register via EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4
4.1
4.2
4.2.1
4.3
4.4
4.4.1
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Management Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serail Management Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5.1
5.2
Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DC Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
AC Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Data Sheet
5
30
30
32
34
57
59
60
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Data Sheet
NINJA F/FX (ADM6992F/FX) Block Diagram 9
NINJA F/FX (ADM6992F/FX) 64-Pin Assignment 10
SMI Read Operation 27
SMI Write Operation 28
Power on Reset Timing 78
EEPROM Interface Timing 78
SMI Timing 79
128 pin QFP Outside Dimension 80
6
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
List of Tables
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Data Sheet
Data Lengths Conventions 9
NINJA F/FX (ADM6992F/FX)Abbreviations for Pin Type 11
Abbreviations for Buffer Type 11
Port 0/1 Twisted Pair Interface (8 Pins) 12
LED Interface (12 Pins) 12
EEPROM Interface (4 Pins) 15
Configuration Interface (28 Pins) 16
Ground/Power Interface (27 Pins) 17
Miscellaneous (14 Pins) 18
Speed Configuration 21
OAM Delivery Between CO and CPE 26
SMI Read/Write Command Format 27
EEPROM Register Map 30
Registers Address Space 32
Registers Overview 32
Register Access Types 33
Registers Clock DomainsRegisters Clock Domains 34
Other Packet Filter Control Regsiters 45
Other Filter Regsiters 47
Other Tag Port Rule 0 Registers 50
Other Tag Port Rule 1 Regsiters 51
Serial Management Register Map 57
Registers Address SpaceRegisters Address Space 59
Registers Overview 59
Register Access Types 60
Registers Clock DomainsRegisters Clock Domains 60
Other Counter Registers 62
Electrical Absolute Maximum Rating 77
Recommended Operating Conditions 77
DC Electrical Characteristics for 3.3 V Operation 77
Power on Reset Tming 78
EEPROM Interface Timing 78
SMI Timing 79
Dimensions for 128 PQFP Outside Dimension 81
7
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Product Overview
1
Product Overview
Features and the block diagram.
1.1
Overview
The NINJA F/FX (ADM6992F/FX) is a single chip integrating two 10/100 Mbps MDIX TX/FX transceivers with a
two-port 10/100M Ethernet L2 switch controller. Features include a converter mode to meet demanding
applications, such as Fiber-to-Ethernet media converters and FTTH (Fiber to the Home), on the CPE and CO
sides. The ADM6992FX is the environmentally friendly “green” package version.
The NINJA F/FX (ADM6992F/FX) supports 16 entries of packet classification and marking or filtering for TCP/UDP
port numbering, IP protocol ID and Ethernet Types. These can be configured either using the EEPROM or on the
fly using a small, low-cost micro controller.
On the media side, the NINJA F/FX (ADM6992F/FX)’s ports 0 and 1 support auto-MDIX 10Base-T/100Base-TX
and 100Base-FX as specified by the IEEE 802.3 committee through uses of digital circuitry and high speed A/D.
The NINJA F/FX (ADM6992F/FX) also supports a serial management interface (SMI), which is initialized and
configured using a small low-cost micro controller. It also provides the port status for remote agent monitoring and
a smart counter for reporting port statistics. Users can implement TS-1000 CO side functions through this SMI
interface.
1.2
Features
Main features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2-port10/100M switch integrated with a 2-port PHY (10/100TX and 100FX )
Embedded OAM engine complying with TS1000 for CPE and CO functions
Supports remote control via an OAM frame.
Provides TX<-->FX Converter modes with Link Pass Through (LPT)
Built-in data buffer 6Kx64bit SRAM
Up to 1k of Unicast. MAC addresses with a 4-way associative hashing table
MAC address learning table with aging function
Supports store & forward frame forwarding, modify cut-through frame forwarding, and fast cut-through frame
forwarding.
Forwarding and filtering at non-blocking full wire speed
802.3x flow control for full duplex and back-pressure for half duplex
Supports Auto-Negotiation
Supports Auto Cross-Over
Packet lengths up to 9216 bytes.
16 entries of packet classification and marking or filtering for TCP/UDP Port Numbering, IP Protocol ID and
Ethernet Type
Serial Management Interface for low-end CPUs
OAM frame can be monitored/generated via SMI interface
Hardware bandwidth control support for both ingress/egress traffic
Provides port status for remote agent monitoring
Provides smart counters for port statistics reporting
128 PQFP packaging with 1.8 V/3.3 V power supply
Data Sheet
8
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Product Overview
1.3
Block Diagram
Figure 1
NINJA F/FX (ADM6992F/FX) Block Diagram
1.4
Data Lengths Conventions
Table 1
Data Lengths Conventions
qword
64 bits
dword
32 bits
word
16 bits
byte
8 bits
nibble
4 bits
Data Sheet
9
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Interface Description
2
Interface Description
This chapter describes Pin Diagram, Pin Type and Buffer Type Abbreviations, and Pin Descriptionss.
2.1
Pin Diagram
Figure 2
NINJA F/FX (ADM6992F/FX) 64-Pin Assignment
Data Sheet
10
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Interface Description
2.2
Pin Type and Buffer Type Abbreviations
Standardized abbreviations:
Table 2
NINJA F/FX (ADM6992F/FX)Abbreviations for Pin Type
Abbreviations
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
AO
Output. Analog levels.
AI/O
Input or Output. Analog levels.
PWR
Power
GND
Ground
MCL
Must be connected to Low (JEDEC Standard)
MCH
Must be connected to High (JEDEC Standard)
NU
Not Usable (JEDEC Standard)
NC
Not Connected (JEDEC Standard)
Table 3
Abbreviations for Buffer Type
Abbreviations
Description
Z
High impedance
PU1
Pull up, 10 kΩ
PD1
Pull down, 10 kΩ
PD2
Pull down, 20 kΩ
TS
Tristate capability: The corresponding pin has 3 operational states: Low, high and highimpedance.
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR. An external pull-up is required to sustain the
inactive state until another agent drives it, and must be provided by the central resource.
OC
Open Collector
PP
Push-Pull. The corresponding pin has 2 operational states: Active-low and active-high
(identical to output with no type attribute).
OD/PP
Open-Drain or Push-Pull. The corresponding pin can be configured either as an output with
the OD attribute or as an output with the PP attribute.
ST
Schmitt-Trigger characteristics
TTL
TTL characteristics
Data Sheet
11
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Interface Description
2.3
Pin Descriptions
NINJA F/FX (ADM6992F/FX) pins are categorized into one of the following groups:
•
•
•
•
•
•
Port 0/1 Twisted Pair Interface, 8 pins
LED Interface, 12 pins
EEPROM Interface, 4 pins
Configuration Interface, 28 pins
Ground/Power Interface, 27 pins
Miscellaneous, 14 pins
Note: If not specified, all signals default to digital signals.
Table 4
Port 0/1 Twisted Pair Interface (8 Pins)
Pin or Ball No. Name
Pin
Type
40
TXP_0
AI/O
50
TXP_1
AI/O
41
TXN_0
AI/O
49
TXN_1
AI/O
43
RXP_0
AI/O
47
RXP_1
AI/O
44
RXN_0
AI/O
46
RXN_1
AI/O
Table 5
Buffer
Type
Function
Twisted Pair Transmit
Output Positive.
Twisted Pair Transmit
Output Negative.
Twisted Pair Receive
Input Positive.
Twisted Pair Receive
Input Negative.
LED Interface (12 Pins)
Pin or
Ball
No.
Name
Pin
Type
Buffer Function
Type
113
LNKACT_0
I/O
TTL
PD
8mA
PORT0 Link & Active LED/Link LED.
If LEDMODE_0 is 1, this pin indicates both link status and RX/TX
activity. When link status is LINK_UP, LNKACT_0 will be turned
on. While PORT0 is receiving/transmitting data, LNKACT_0 will
be off for 100ms and then on for 100ms.
If LEDMODE_0 is 0, this pin only indicates RX/TX activity.
LED_DATA_0
LEDMODE_0
Data Sheet
LED mode for LINK/ACT LED of PORT0.
During power on reset, value will be latched by NINJA F/FX
(ADM6992F/FX) at the rising edge of RESETL as LEDMODE_0.
12
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Interface Description
Table 5
LED Interface (12 Pins) (cont’d)
Pin or
Ball
No.
Name
Pin
Type
Buffer Function
Type
114
LNKACT_1
I/O
TTL
PD
8mA
PORT1 Link & Active LED/Link LED.
If LEDMODE_2 is 1, this pin indicates both link status and RX/TX
activity. When link status is LINK_UP, LNKACT_1 will be turned
on. While PORT1 is receiving/transmitting data, LNKACT_1 will
be off for 100ms and then on for 100ms.
If LEDMODE_2 is 0, this pin only indicates RX/TX activity.
LED_DATA_1
LEDMODE_1
124
125
DUPCOL_0
LED mode DUPLEX/COL LED of PORT0 & PORT1.
During power on reset, value will be latched by NINJA F/FX
(ADM6992F/FX) at the rising edge of RESETL as LEDMODE_1.
If LEDMODE_1 is 1, DUPCOL[1:0] will display both duplex
condition and collision status.
If LEDMODE[1] is 0, only collision status will be displayed.
I/O
TTL
PD
8mA
PORT0 Duplex LED
If LEDMODE_1 is 1, this pin indicates both duplex condition and
collision status. When FULL_DUPLEX, this pin will be turned on
for PORT0. When HALF_DUPLEX and no collision occurs, this
pin will be turned off. When HALF_DUPLEX and a collision
occurs, this pin will be off for 100ms and then on for 100ms.
If LEDMODE_1 is 0, this pin indicates collision status. When in
HALF_DUPLEX and a collision occurs, this pin will be off for
100ms and turn on for 100ms.
LED_COL_0
Port0 Collision LED
DIS_LEARN
Disable Address Learning.
During power on reset, value will be latched by NINJA F/FX
(ADM6992F/FX) at the rising edge of RESETL as DIS_LEARN. If
DIS_LEARN is 1, MAC address learning will be disabled.
DUPCOL_1
I/O
TTL
PU
8mA
PORT1 Duplex
If LEDMODE_1 is 1, this pin indicates both duplex condition and
collision status. When FULL_DUPLEX, this pin will be turned on
for PORT1. When HALF_DUPLEX and no collision occurs, this
pin will be turned off. When HALF_DUPLEX and a collision
occurs, this pin will be off for 100ms and then on for 100ms. If
LEDMODE_1 is 0, this pin indicates collision status. When
HALF_DUPLEX and a collision occurs, this pin will be off for
100ms and turn on for 100ms.
LED_COL_1
Port1 Collision LED
EN_OAM
Enable Internal OAM Frame Processor.
During power on reset, value will be latched by NINJA F/FX
(ADM6992F/FX) at the rising edge of RESETL as EN_OAM. If
EN_OAM is 0, the internal OAM engine will be disabled.
Data Sheet
13
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Interface Description
Table 5
LED Interface (12 Pins) (cont’d)
Pin or
Ball
No.
Name
Pin
Type
Buffer Function
Type
122
LDSPD_0
I/O
TTL
PD
8mA
FXMODE0
123
128
LDSPD_1
FXMODE0
During power on reset, value will be latched by NINJA F/FX
(ADM6992F/FX) at the rising edge of RESETL as bit 0 of
FXMODE.
I/O
TTL
PD
8mA
PORT1 Speed LED
Used to indicate speed status of PORT1. When operating in
100Mbps this pin is turned on, and when operating in 10Mbps this
pin is off.
LED_FIBER_SD
LED_FIBER_SD.
Used to indicate signal status of PORT1 when NINJA F/FX
(ADM6992F/FX) is operating in converter mode.
LEDMODE2
LED mode for LINK/ACT LED of PORT1.
During power on reset, value will be latched by NINJA F/FX
(ADM6992F/FX) at the rising edge of RESETL as LEDMODE2.
0B
TBD, ACT
1B
TBD, LINK/ACT
LED_LINK_0
I/O
TTL
PU
8mA
FXMODE1
1
PORT0 Speed LED
Used to indicate speed status of PORT0. When operating in
100Mbps this pin is turned on, and when operating in 10Mbps this
pin is off.
LED_LINK_1
BYPASS_PAUS
E
Data Sheet
PORT0 Link LED
This pin indicates link status. When Port0 link status is LINK_UP,
this pin will be turned on.
FXMODE1
During power on reset, value will be latched by NINJA F/FX
(ADM6992F/FX) at the rising edge of RESETL as bit 1 of
FXMODE.
FXMODE [1:0] Interface
00B TBD, Both Port0 & Port1 are TP port
01B TBD, Port0 is TP port and Port1 is FX port
10B TBD, Port0 is TP port and Port1 is FX port (converter mode)
11B TBD, Both Port0 & Port1 are FX port
I/O
TTL
PU
8mA
PORT1 Link LED
This pin indicates link status. When Port1 link status is LINK_UP,
this pin will be turned on.
Bypass frame
Which destination address is reserved IEEE MAC address.
During power on reset, value will be latched by NINJA F/FX
(ADM6992F/FX) at the rising edge of RESETL as
BYPASS_PAUSE.
0B
D, Disable
1B
E, Enable
14
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Interface Description
Table 5
LED Interface (12 Pins) (cont’d)
Pin or
Ball
No.
Name
Pin
Type
Buffer Function
Type
2
LED_FULL_0
I/O
TTL
PU
8mA
CHIPID_0
3
LED_FULL_1
Chip ID Bit 0.
During power on reset, value will be latched by NINJA F/FX
(ADM6992F/FX) at the rising edge of RESETL as CHIPID_0.
I/O
TTL
PU
8mA
CHIPID_1
4
LED_LPBK
I/O
LED_WAN_FAIL O
TTL
PU
8mA
Loop Back Test LED
While performing loop back test this pin is turned on.
TTL
PU
8mA
WAN Fail LED
When receiving an OAM frame which has a S2 bit = 1, this pin is
turned on.
DISBP
Table 6
PORT1 Full Duplex LED
This pin indicates current duplex condition of PORT1. When
FULL_DUPLEX, this pin will be turned on. When HALF_DUPLEX
this pin will be turned off.
Chip ID Bit 1
During power on reset, value will be latched by NINJA F/FX
(ADM6992F/FX) at the rising edge of RESETL as CHIPID_1.
CHIPID_1:CHIPID_0]
00B TBD, Master Device
01B TBD, Slave Device
1XB TBD, Slave Device
CHIPID_2
5
PORT0 Full Duplex LED
This pin indicates current duplex condition of PORT0. When
FULL_DUPLEX, this pin will be turned on. When HALF_DUPLEX
this pin will be turned off.
Chip ID Bit 2
During power on reset, value will be latched by NINJA F/FX
(ADM6992F/FX) at the rising edge of RESETL as CHIPID_2.
Disable Back Pressure
During power on reset, value will be latched by NINJA F/FX
(ADM6992F/FX) at the rising edge of RESETL as DISBP.
E, Enable back-pressure (Default)
0B
1B
D, Disable back-pressure
EEPROM Interface (4 Pins)
Pin or
Ball
No.
Name
Pin
Type
Buffer Function
Type
7
EEDO
I
TTL
PU
EEPROM Data Output
Serial data input from EEPROM. This pin is internal pull-up.
12
EECS/IFSEL
I/O
PD
4mA
EEPROM Chip Select
This pin is an active high chip enabled for EEPROM. When
RESETL is low, it will be tristate.
0B
SM, Select Serial Management Interface
1B
EE, Select EEPROM interface
Data Sheet
15
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Interface Description
Table 6
EEPROM Interface (4 Pins) (cont’d)
Pin or
Ball
No.
Name
Pin
Type
Buffer Function
Type
11
EECK/SDC
I/O
TTL
PU
4mA
Serial Clock
This pin is the EEPROM clock source. When RESETL is low, it will
be tristate. This pin is internal pull-up.
If IFSEL is 1, this pin is used as EECK.
If IFSEL is 0, this pin is used as SDC.
8
EEDI
I/O
TTL
PU
4mA
EEPROM Serial Data Input
This pin is the output for serial data transfer. When RESETL is
low, it will be tristate.
If IFSEL is 1, this pin is used as EEDI.
If IFSEL is 0, this pin is used as SDIO.
Table 7
Configuration Interface (28 Pins)
Pin or
Ball
No.
Name
Pin
Type
Buffer
Type
Function
16
P0_ANDIS
I
TTL
PD
Auto-Negotiation Disable for PORT0
0B
E, Enable
1B
D, Disable
17
P0_RECHALF
I
TTL
PD
Recommend Half Duplex Communication for PORT0
0B
F, Full
1B
H, Half
18
P0_REC10
I
TTL
PD
Recommend 10M for PORT0
0B
100, 100M
1B
10, 10M
19
P0_FCDIS
I
TTL
PD
Flow Control Disable for PORT0
0B
E, Enable
D, Disable
1B
22
P1_ANDIS
I
TTL
PD
Auto-Negotiation Disable for PORT1
0B
E, Enable
1B
D, Disable
23
P1_RECHALF
I
TTL
PD
Recommend Half Duplex Communication for PORT1
0B
F, Full
1B
H, Half
24
P1_REC10
I
TTL
PD
Recommend 10M for PORT1
0B
100, 100M
1B
10, 10M
25
P1_FCDIS
I
TTL
PD
Flow Control Disable for PORT1
0B
E, Enable
1B
D, Disable
67
XOVEN
I
TTL
PD
Auto-MDIX Enable.
0B
D, Disable
1B
E, Enable
Data Sheet
16
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Interface Description
Table 7
Configuration Interface (28 Pins) (cont’d)
Pin or
Ball
No.
Name
Pin
Type
Buffer
Type
Function
68
P0_MDI
I
TTL
PU
MDI/MDIX Control for PORT0
This setting will be ignored if enables Auto-MDIX.
0B
MDIX, MDIX
1B
MDI, MDI
69
D_PD_DETECT I
TTL
PD
Digital Power Failure Detected
0B
N, Normal
1B
TX, NINJA F/FX (ADM6992F/FX) will transmit an OAM
frame to indicate power failure.
71
MC_FAILURE
I
TTL
PD
Media Converter (MC) Failure Detected
0B
N, Normal
1B
TX, NINJA F/FX (ADM6992F/FX) will transmit an OAM
frame to indicate MC failure.
102
LPT_DIS
I
TTL
PD
Link Pass Through Disable
0B
E, Enable
1B
D, Disable
Table 8
Ground/Power Interface (27 Pins)
Pin or
Ball
No.
Name
Pin
Type
42, 48
GNDTR
GND, A
Ground
Used by AD receiver/transmitter block.
39, 51
VCCA2
PWR, A
1.8 V used for Analogue block
45
VCCAD
PWR, A
3.3 V used for TX line driver
36
GNDBIAS
GND, A
Ground
Used by digital substrate
38
VCCBIAS
PWR, A
3.3 V used for bios block
33
GNDPLL
GND, A
Ground used by PLL
32
VCCPLL
PWR, A
1.8 V used for PLL
13, 52, GNDIK
64, 89,
109,
110
GND, D
Ground used by digital core and pre-driver
VCCIK
9, 10,
57, 91,
115,
116
PWR, D
1.8 V used for digital core and pre-driver
77,
118,
119
GNDO
GND, D
Ground used by digital pad
79,
126,
127
VCC3O
PWR, D
3.3 V used for digital pad.
Data Sheet
Buffer
Type
Function
17
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Interface Description
Table 9
Miscellaneous (14 Pins)
Pin or
Ball
No.
Name
Pin
Type
Buffer
Type
Function
6
INT
O
TTL
OD
4mA
Interrupt
This pin will be used to interrupt external management device.
When EEPROM register 0x5 Bit [15] is 0, this pin is low-active.
When EEPROM register 0x5 Bit [15] is 1, this pin is high-active.
34
CONTROL
AO
FET Control Signal
The pin is used to control FET for 3.3 V to 1.8 V regulator.
37
RTX
A
TX Resistor
35
A_PD_DETECT A
26
RC
I
27
XI
AI
25M Crystal Input
25M Crystal Input. Variation is limited to +/- 50ppm.
28
XO
AO
25M Crystal Output
When connected to oscillator, this pin should left unconnected.
72
TEST
I
TTL
PD
Test pin
During power on reset, value will be latched by NINJA F/FX
(ADM6992F/FX) at the rising edge of RESETL as TEST.
Connect to GND at normal application.
73
SCAN_MD
I
TTL
PD
Scan Mode
For Test Only. Connect to GND at normal application.
Data Sheet
Analog Power Failure Detected
<B
TBD, 1.2 V NINJA F/FX (ADM6992F/FX) will transmit
an OAM frame to indicate power failure.
>B
TBD, 1.2 V Normal
TTL
ST
RC Input for Power On Reset
NINJA F/FX (ADM6992F/FX) sample pin RC as RESETL with
the clock input from pin XI.
18
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Function Description
3
Function Description
The NINJA F/FX (ADM6992F/FX) integrates a two 100Base-X physical layer device (PHY), two complete
10BaseT modules, a two-port 10/100 switch controller and memory into a single chip for both 10Mbps and 100
Mbps Ethernet switch operations. It also supports 100Base-FX operations through external fiber-optic
transceivers. The device is capable of operating in either Full-Duplex or Half-Duplex mode in both 10 Mbps and
100 Mbps operations. Operation modes can be selected by hardware configuration pins, software settings of
management registers, or determined by the on-chip auto negotiation logic.
The NINJA F/FX (ADM6992F/FX) consists of four major blocks:
•
•
•
•
OAM Engine
10/100M PHY Block
Switch Controller Block
Built-in 6Kx64 SSRAM
3.1
OAM Engine
An OAM packet is used for exchanging the status between two end points of a fiber line. An OAM packet is not in
the Ethernet packet format. The NINJA F/FX (ADM6992F/FX) supports OAM packets which follow TS-1000
standard Version 1. The OAM engine module locates between the MAC and fiber PHY. It’s in charge of OAM
packet transmission and reception. In transmission, it inserts the OAM packet in MII traffic, leaving a 96 bit-time
gap between packets. If an OAM packet insertion request occurs when fiber port (port 1) is transmitting a user
frame, the OAM engine will wait until the user frame transmission is complete and then insert the OAM packet.
When receiving, the OAM engine module can detect the OAM packet from MII traffic. If the received packet is
identified as an OAM packet, this packet will not be passed to the MAC.
After power up, the NINJA F/FX (ADM6992F/FX) will start to load the initial settings from the EEPROM and
perform LED self test. By default, the NINJA F/FX (ADM6992F/FX) will mask all events which request a state
notification indication about 3 to 4 seconds after satisfactory power and fiber port link up. After this, the NINJA
F/FX (ADM6992F/FX) will issue a state notification indication frame with its current status. The mask duration can
be adjusted from 0 to 8 seconds via the EEPROM register 35H Bit [10:8].
3.2
10/100M PHY Block
The 100Base-X section of the device implements the following functional blocks:
•
•
•
100Base-X physical coding sub-layer (PCS)
100Base-X physical medium attachment (PMA)
100Base-X physical medium dependent (PMD)
The 10Base-T section of the device implements the following functional blocks:
•
•
10Base-T physical layer signaling (PLS)
10Base-T physical medium attachment (PMA)
The 100Base-X and 10Base-T sections share the following functional blocks:
•
•
•
Clock synthesizer module
MII Registers
IEEE 802.3u auto negotiation
The interfaces used for the communication between the PHY block and switch core is a MII interface.
An Auto MDIX function is supported. This function can be Enabled/Disabled using the hardware pin. A digital
approach for the integrated PHY of the NINJA F/FX (ADM6992F/FX) has been adopted.
Data Sheet
19
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Function Description
3.3
Auto Negotiation and Speed Configuration
3.3.1
Auto Negotiation
The Auto Negotiation function provides a mechanism for exchanging configuration information between two ends
of a link segment and automatically selecting the highest performance mode of operations supported by both
devices. Fast Link Pulse (FLP) Bursts provide the signaling used to communicate auto negotiation abilities
between two devices at each end of a link segment. For further details regarding auto negotiation, refer to Clause
28 of the IEEE 802.3u specification. The NINJA F/FX (ADM6992F/FX) supports four different Ethernet protocols,
so the inclusion of auto negotiation ensures that the highest performance protocol will be selected based on the
ability of the link partner.
The auto negotiation function within the NINJA F/FX (ADM6992F/FX) can be controlled either by internal register
access or by the use of configuration pins. If disabled, auto negotiation will not occur until software enables bit 12
in MII Register 0. If auto negotiation is enabled, the negotiation process will commence immediately.
When auto negotiation is enabled, the NINJA F/FX (ADM6992F/FX) transmits the abilities programmed into the
auto negotiation advertisement register at address 04H via FLP bursts. Any combination of 10 Mbps, 100 Mbps,
half duplex, and full duplex modes may be selected. Auto negotiation controls the exchange of configuration
information. Upon successfully auto negotiating, the abilities reported by the link partner are stored in the auto
negotiation link partner ability register at address 05H.
The contents of the “auto negotiation link partner ability register” are used to automatically configure the highest
performance protocol between the local and far-end nodes. Software can determine which mode has been
configured by auto negotiation, by comparing the contents of register 04H and 05H and then selecting the
technology whose bit is set in both registers of highest priority relative to the following list:
1.
2.
3.
4.
100Base-TX full duplex (highest priority)
100Base-TX half duplex
10Base-T full duplex
10Base-T half duplex (lowest priority)
The basic mode control register at address 0H controls the enabling, disabling and restarting of the auto
negotiation function. When auto negotiation is disabled, the speed selection bit (bit 13) controls switching between
10 Mbps or 100 Mbps operation, while the duplex mode bit (bit 8) controls switching between full duplex operation
and half duplex operation. The speed selection and duplex mode bits have no effect on the mode of operations
when the auto negotiation enable bit (bit 12) is set.
The basic mode status register at address 1H indicates the set of available abilities for technology types (bit 15 to
bit 11), auto negotiation ability (bit 3), and extended register capability (bit 0). These bits are hardwired to indicate
the full functionality of the NINJA F/FX (ADM6992F/FX). The BMSR also provides status on:
•
•
•
Whether auto negotiation is complete (bit 5)
Whether the Link Partner is advertising that a remote fault has occurred (bit 4)
Whether a valid link has been established (bit 2)
The auto negotiation advertisement register at address 4H indicates the auto negotiation abilities to be advertised
by the NINJA F/FX (ADM6992F/FX). All available abilities are transmitted by default, but writing to this register or
configuring external pins can suppress any ability.
The auto negotiation link partner ability register at address 05H indicates the abilities of the Link Partner as
indicated by auto negotiation communication. The contents of this register are considered valid when the auto
negotiation complete bit (bit 5, register address 1H) is set.
3.3.2
Speed Configuration
The twelve sets of four pins listed in Table 10 configure the speed capability of each channel of the NINJA F/FX
(ADM6992F/FX). The logic states of these pins are latched into the advertisement register (register address 4H)
Data Sheet
20
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Function Description
for auto negotiation purpose. These pins are also used for evaluating the default value in the base mode control
register (register 0H) according to Table 10.
In order to make these pins with the same Read/Write priority as software, they should be programmed to
11111111B in case a user wishes to update the advertisement register through software.
Table 10
Speed Configuration
Advertis
e all
capabilit
y
Advertis
e single
capabili
ty
Paralle
l detect
follow
IEEE
std.
Auto
Negotiation
(Pin &
EEPROM)
Speed
(Pin &
EEPROM
)
Auto
Duplex
Negot
(Pin &
EEPROM iation
)
Advertise
Capability
1
0
0
1
X
X
1
1
1
1
1
1
0
1
0
1
0
1
1
X
X
1
1
1
1
1
0
1
0
1
1
1
0
1
X
X
1
1
0
0
0
1
0
0
0
1
1
1
1
X
X
1
1
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
X
1
1
0
1
0
1
0
1
0
1
0
1
0
1
X
1
1
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
0
1
1
1
0
1
1
0
0
1
0
0
0
0
1
0
X
X
1
0
0
1
0
0
0
1
0
0
0
1
X
X
X
0
1
1
0
1
—
—
—
—
—
—
—
X
X
X
0
1
0
0
—
1
—
—
—
—
—
—
X
X
X
0
0
1
0
—
—
1
—
—
—
—
—
X
X
X
0
0
0
0
—
—
—
1
—
—
—
—
3.4
Parallel Detect
Capability
10 10 10 10 10 10 10 10
0F 0H F H 0F 0H F H
Switch Functional Description
The NINJA F/FX (ADM6992F/FX) supports three types of data forwarding mode, store & forward mode, modified
and MII cut-through.
3.4.1
Store & Forward Mode
The NINJA F/FX (ADM6992F/FX) allows switching between different speed media (e.g. 10BaseX and 100BaseX)
in store & forward mode. The entire received frame will be stored into its packet buffer. The NINJA F/FX
(ADM6992F/FX) checks the length and frame check sequence (FCS) of the received frame to prevent the
forwarding of corrupted packets before forwarding to the destination port. A MAC address filtering process can be
enabled to filter local traffic to improve overall network performance. The maximum packet length is up to 9216
bytes in this mode. The maximum packet length is defined in Bit [13:0] of EEPROM register 03H.
Data Sheet
21
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Function Description
3.4.2
Modified Cut-through Mode
The NINJA F/FX (ADM6992F/FX) begins to forward the received packet when it receives the first 64 bytes of the
packet. The latency is about 512 bits time width. The NINJA F/FX (ADM6992F/FX) will not forward fragment
packets. The MAC address learning & filtering should be disabled in this mode, because the received packets may
be corrupted. The maximum packet length is up to 9216 bytes in this mode. The maximum packet length is defined
in Bit [13:0] of EEPROM register 03H.
3.4.3
MII cut-through Mode
The NINJA F/FX (ADM6992F/FX) begins to forward the received packet at the beginning of the received packet.
It provides the minimum latency in this mode. The maximum packet length is 9216 bytes if the clock difference
between MII receive clock and MII transmit clock is 200Ppm.
3.5
Basic Operations
3.5.1
MAC Address Learning & Filtering
The NINJA F/FX (ADM6992F/FX) adopts 4-way associative hash architecture to store the MAC address table. It
can store up to a maximum 1K of MAC addresses.
In store & forward mode, the NINJA F/FX (ADM6992F/FX) receives incoming packets from one of its ports,
searches in the Address Table for the Destination MAC Address and then forwards the packet to the other port, if
appropriate. If the destination address is not found in the address table, the NINJA F/FX (ADM6992F/FX) treats
the packet as a broadcast packet and forwards the packet to the other ports. If the destination port is the same
with the port where the packet received from, the NINJA F/FX (ADM6992F/FX) treats the packet as a local traffic
packet and discards it.
3.5.2
Address Learning
The NINJA F/FX (ADM6992F/FX) searches for the Source Address (SA) of an incoming packet in the Address
Table and acts as below:
1. The NINJA F/FX (ADM6992F/FX) automatically learns the port number of attached network devices by
examining the Source MAC Address of all incoming packets at wire speed
2. If the SA was not found in the Address Table (a new address), the NINJA F/FX (ADM6992F/FX) waits until the
end of the packet (non-error packet) and updates the Address Table
3. If the SA was found in the Address Table, then the aging value of each corresponding entry will be reset to 0
4. When the DA is in PAUSE mode, then the learning process will be disabled automatically by the NINJA F/FX
(ADM6992F/FX)
3.5.3
Hash Algorithm
The NINJA F/FX (ADM6992F/FX) supports two types of hash algorithms for address learning & filtering. The first
is the CRC-CCITT polynomial method. The 48 bits MAC address is reduced to a 16 bits CRC hash value. Bit [7:0]
of the CRC are used to index the 1K address table. The CRC-CCITT polynomial is
The second is direct-map method. The 48-bit MAC address is mapped into a 8 bits address space by XOR-method
to index the 1K address table.
The hash type can be selected using bit [15] of EEPROM register 03H.
Data Sheet
22
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Function Description
3.5.4
Address Recognition and Packet Forwarding
The address learning & filtering process forwards the incoming packets between bridged ports according to the
Destination Address (DA) as below.
1. If the DA is a UNICAST address and the address was found in the Address Table, the NINJA F/FX
(ADM6992F/FX) will check the port number and act as follows:
a) If the port number is equal to the port on which the packet was received, the packet is discarded.
b) If the port number is different from the port on which the packet was received, the packet is forwarded across
the bridge.
2. If the DA is a UNICAST address and the address was not found, the NINJA F/FX (ADM6992F/FX) treats it as
a multicast packet and forwards it across the bridge.
3. If the DA is a Multicast address, the packet is forwarded across the bridge.
4. If the DA is PAUSE Command (01-80-C2-00-00-01), then this packet will be dropped by the NINJA F/FX
(ADM6992F/FX). The NINJA F/FX (ADM6992F/FX) can issue and learn PAUSE commands.
5. The NINJA F/FX (ADM6992F/FX) will forward by default or filter out the packet with DA of (01-80-C2-00-0000), discard the packet with DA of (01-80-C2-00-00-01), filter out the packet with DA of (01-80-C2-00-00-02 ~
01-80-C2-00-00-0F), and forward the packet with DA of (01-80-C2-00-00-10 ~ 01-80-C2-00-00-FF) decided
by EEPROM Reg.0x0e.
3.5.5
Address Aging
Address aging is supported for topology changes such as an address moving from one port to the other. When
this happens, the NINJA F/FX (ADM6992F/FX) internally has 300 seconds timer, after which the address will be
“aged out” (removed) from the address table. Aging function can be enabled/disabled by the user. Normally,
disabling the aging function is for security purposes.
3.5.6
Back off Algorithm
The NINJA F/FX (ADM6992F/FX) implements the truncated exponential back off algorithm compliant to the 802.3
CSMA-CD standard. The NINJA F/FX (ADM6992F/FX) will restart the back off algorithm by choosing 0-9 collision
counts. The NINJA F/FX (ADM6992F/FX) resets the collision counter after 16 consecutive retransmit trials.
3.5.7
Inter-Packet Gap (IPG)
IPG is the idle time between any two successive packets from the same port. The typical number is 96 bits time.
The value is 9.6µs for 10Mbps ETHERNET, 960ns for 100Mbps fast ETHERNET, and 96ns for 1000M. The NINJA
F/FX (ADM6992F/FX) provides an option of 92 bit-time gaps in the EEPROM to prevent packet loss when Flow
Control is turned off and the clock P.P.M. value differs.
3.5.8
Illegal Frames
In store & forward mode, the NINJA F/FX (ADM6992F/FX) will discard all illegal frames such as small packets
(less than 64 bytes), oversized packets (greater than the value which is defined in Bit [13:0] of EEPROM register
03H) and bad CRC. Dribbling packing with good CRC value will accept by NINJA F/FX (ADM6992F/FX).
In modified cut-through mode, the NINJA F/FX (ADM6992F/FX) will forward all received packets except for small
packets (less than 64 bytes).
In MII cut-through mode, the NINJA F/FX (ADM6992F/FX) will forward all received packets.
3.5.9
Half Duplex Flow Control
A Back Pressure function is supported for half-duplex operation. When the NINJA F/FX (ADM6992F/FX) cannot
allocate a received buffer for an incoming packet (buffer full), the device will transmit a jam pattern on the port,
thus forcing a collision. Back Pressure is disabled by DISBP which is set during RESETL assertion. A proprietary
Data Sheet
23
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Function Description
algorithm is implemented inside the NINJA F/FX (ADM6992F/FX) to prevent the back pressure function causing
HUB partition under a heavy traffic environment and reduce the packet lost rate to increase the whole system
performance.
3.5.10
Full Duplex Flow Control
When a full duplex port runs out of its received buffer space, a PAUSE packet command will be issued by the
NINJA F/FX (ADM6992F/FX) to notify the packet sender to pause transmission. This frame based flow control is
totally compliant to IEEE 802.3x. The NINJA F/FX (ADM6992F/FX) can issue or receive pause packets.
3.5.11
Bandwidth Control
NINJA F/FX (ADM6992F/FX) supports hardware-based bandwidth control for both ingress and egress traffic.
Ingress and egress rates can be limited independently on a per port base. The NINJA F/FX (ADM6992F/FX) uses
8ms as the scale, and the minimum bandwidth control unit is 4 kbit/s so users can configure the rate equal to K *
4 kbit/s, 1<=K<=25000. The NINJA F/FX (ADM6992F/FX) maintains two counters (input and output) for each port.
For example, if users want to limit the rate to 64 kbit/s, they should configure the bandwidth control threshold to
16. For each time unit, the NINJA F/FX (ADM6992F/FX) will add 64 to the counter and decrease the byte length
when receiving a packet during this period. When the counter is decreased to zero, we can divide the control
behavior into two parts:
1. For the ingress control, the ingress port will not stop receiving packets. If flow control is enabled, Pause packets
will be transmitted, if Back Pressure is enabled, Jam packets will be transmitted, and if the above functions are
not enabled, the packet will be discarded.
2. For the egress control, the egress port will not transmit any packets. The port receiving packets that are
forwarded to the egress port will transmit Pause packets if flow control is enabled, transmit Jam packets if Back
Pressure is enabled and will discard packets if all the above functions are not enabled.
3.5.12
Interrupt
With the use of external CPU support, the NINJA F/FX (ADM6992F/FX) can issue an interrupt to the CPU if any
event defined in SMI interrupt register 10H and SMI interrupt mask register 11H occur.
3.5.13
Auto TP MDIX function
The normal application in which a Switch connects to a NIC card is by a one-to-one TP cable. If the Switch
connects to other devices such as another Switch, it can be done by two ways. The first is to use a Cross Over TP
cable and the second way is to use an extra RJ45 connector by internally crossing over the TXP/TXN and
RXP/RXN signals. By using the second way, customers can use a one-to-one cable to connect two Switch
devices. All these efforts add extra costs and are not a good solution. The NINJA F/FX (ADM6992F/FX) provides
an Auto MDIX function, which adjusts the TXP/TXN and RXP/RXN automatically on the correct pins. Users can
use one-to-one cabling between the NINJA F/FX (ADM6992F/FX) and other devices either switches or NICs.
3.6
Converter Functional Description
3.6.1
OAM Buffer
The embedded OAM buffer can store up to 4 received OAM frames (the 2 oldest received OAM frames and the 2
newest received OAM frames). This OAM buffer can be read through an SMI interface. It can be used to extend
the NINJA F/FX (ADM6992F/FX)’s OAM handling capability. Both known and unknown OAM frames can be stored
into the OAM buffer. Users can set Bit [12:11] to 1 to prevent the NINJA F/FX (ADM6992F/FX) store unknown or
known frames into the OAM buffer.
Data Sheet
24
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Function Description
3.6.2
OAM frame transmit
The NINJA F/FX (ADM6992F/FX) transmits OAM frames when the following condition occurs.
1. State Notification required in TS-1000.
a) Power failure
b) Receive light error
c) Normal receive light
d) MC failure
e) MC failure recover
f) Terminal side link disconnection
g) Terminal side link establishment
h) Time-out of timer 2(T2 timer)
i) Terminal side link setting state change (option B)
2. Power failure recover
3. OAM request frame is received
a) Loop back test start request
b) Loop back test end request
c) State notification request
4. OAM frame transmitted request via Bit [9] of SMI OAM control register 14H.
The content of the transmitted frame requested via the SMI interface is defined in the SMI transmit OAM register
17H, 18H and 19H. Besides the PREAMBLE field, users can assign each bit in the C field, S field, M field, and CRC
field. The NINJA F/FX (ADM6992F/FX) will discard the M field and pad pre-defined M field defined in EEPROM
register 36H, 37H and 38H if Bit [2] of SMI OAM control register 14H is 0. The NINJA F/FX (ADM6992F/FX) will
discard the CRC field and pad the CRC calculating it by using its internal CRC engine based on the content of the
transmitted OAM frame if Bit [1] of the SMI OAM control register 14H is 0.
After power is up and port 1 links up, the NINJA F/FX (ADM6992F/FX) starts a 3 seconds timer. The NINJA F/FX
(ADM6992F/FX) will mask all state notification requests until the timer expires. A Power-Up state notification frame
will be transmitted after the timer expires.
If power failure is detected, the NINJA F/FX (ADM6992F/FX) will transmit a power failure state notification frame
and mask all state notification requests. If the power failure recovers and port 1 links up, the NINJA F/FX
(ADM6992F/FX) will start a 3 seconds timer. The NINJA F/FX (ADM6992F/FX) will mask all state notification
requests until the timer expires. A power-up state notification frame will be transmitted after the timer expires.
3.6.3
Power failure detection
For a 128 pin package, the NINJA F/FX (ADM6992F/FX) supports 2 schemes to detect the power status. In the
first scheme the NINJA F/FX (ADM6992F/FX) detects the voltage of pin A_PD_DETECT. If the voltage of pin
A_PD_DETECT is greater than 1.2 V, the NINJA F/FX (ADM6992F/FX) will enter a good power state. If the
voltage of pin A_PD_DETECT is smaller than 1.2 V, the NINJA F/FX (ADM6992F/FX) will enter a power failure
state. The second scheme involves the NINJA F/FX (ADM6992F/FX) detecting the logical level of pin
D_PD_DETECT. If the logical level of pin D_PD_DETECT is 0, the NINJA F/FX (ADM6992F/FX) will enter a good
power state. If the logical level of pin D_PD_DETECT is 1, the NINJA F/FX (ADM6992F/FX) will enter a power
failure state. For a 64-pin package, only A_PD_DETECT can be used to detect the power status. There is a 1
second filter applied to prevent the bouncing effect of the A_PD_DETECT and D_PD_DETECT.
3.6.4
Automatic User Frame Generation
Users can set Bit [10] of the SMI OAM control register to 1 to request the NINJA F/FX (ADM6992F/FX) transmit a
pre-defined Ethernet frame from port 1. The NINJA F/FX (ADM6992F/FX) will transmit a broadcast frame with the
packet length and SA defined in the SMI source address register 15H and 16H. The background of the frame is
“increase byte”. The NINJA F/FX (ADM6992F/FX) will calculate and pad the CRC to the frame automatically. The
CRC will be stored into its internal register for comparably purposes.
Data Sheet
25
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Function Description
3.6.5
Automatic User Frame Comparison
The NINJA F/FX (ADM6992F/FX) automatically compares the CRC registered in section 2.5.3 with port 1 received
Ethernet frames if Bit [8:5] of SMI OAM control register 14H is not 0000. The NINJA F/FX (ADM6992F/FX) will
compare every received Ethernet frame to find the first CRC matched frame during the period of time defined in
Bit [8:5] of SMI OAM control register 14H. The NINJA F/FX (ADM6992F/FX) will generate an interrupt request if
the frame is found or the timer expires.
3.6.6
Fault Propagation
The NINJA F/FX (ADM6992F/FX) Media Converter incorporates a Fault Propagation feature, which allows indirect
sensing of a Fiber Link Loss via the 10/100Base-TX UTP connection. Whenever the NINJA F/FX (ADM6992F/FX)
Media Converter detects a Link Loss condition on the Receive fiber (Fiber LNK OFF), it disables its UTP link pulse
so that a Link Loss condition will be sensed on the UTP port to which the NINJA F/FX (ADM6992F/FX) Media
Converter is connected. This link loss can then be sensed and reported by a Network Management agent in the
remote UTP port’s host equipment. This feature will affect the NINJA F/FX (ADM6992F/FX) UTP LNK LED.
The NINJA F/FX (ADM6992F/FX) Media Converter also incorporates a Far End Fault feature, which allows the
stations on both ends of a pair of fibers to be informed when there is a problem with one of the fibers. Without
Far End Fault, it is impossible for a fiber interface to detect a problem that affects only its Transmit fiber.
When Far End Fault is supported and enabled, a loss of received signal (link) will cause the transmitter to generate
a Far End Fault pattern in order to inform the device at the far end of the fiber pair that a fault has occurred. Unless
Fiber Link Loss occurs or if the UTP port link fails, the NINJA F/FX (ADM6992F/FX) Media Converter will also
generate a Far End Fault pattern in order to inform the device at the far end of the fiber pair that a fault has
occurred.
3.6.7
Remote Control
The remote control function can be enabled by setting Bit [5] of EEPROM register 35H to 1. When setting up the
UTP link of the CPE from CO, the OAM is sent out from the CO to CPE. The CPE which receives the OAM changes
the UTP setup according to the OAM, and sends out an OAM which assigns the setting value to CO. A setup
performed in OAM is confirmed until it receives the next OAM.
When this function is enabled, all setup of DIPSW becomes invalid and follows only a remote setup from CO. Not
the setting value of DIPSW but the remote setting value from CO is assigned also to the UTP link setting value
field (S7-S10) of the state notice OAM.
Details of OAM delivered and carried out between CO and CPE are shown in Table 11
Table 11
OAM Delivery Between CO and CPE
CO
CPE
Remote Control
Start
Remote Control
Stop
Remote Control
Start
Remote Control
Stop
C1
Direction
1: Down side
1: Down side
0: Down side
0: Down side
C2-C3
Order
10: Request
10: Request
11: Response
11: Response
C8-C15
Control
signal
EEPROM register
36H Bit [7:0]
EEPROM register
36H Bit [15:8]
EEPROM register
36H Bit [7:0]
EEPROM register
36H Bit [15:8]
S7-S8
Speed
00: 10Mbit/s
01: 100Mbit/s
Don’t care
Real status after
remote control
Current status of
CPE (no remote
control)
Data Sheet
26
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Function Description
Table 11
OAM Delivery Between CO and CPE (cont’d)
CO
CPE
Remote Control
Start
Remote Control
Stop
Remote Control
Start
Remote Control
Stop
S9
Duplex
0: Half
1: Full
Don’t care
Real status after
remote control
Current status of
CPE (no remote
control)
S10
Autonego
0: OFF
1: ON
Don’t care
Real status after
remote control
Current status of
CPE (no remote
control)
3.7
Serial Management Interface (SMI) Register Access
The SMI consists of two pins, management data clock (SDC) and management data input/output (SDIO). The
NINJA F/FX (ADM6992F/FX) is designed to support an SDC frequency up to 25 MHz. The SDIO line is bidirectional and may be shared with other devices.
The SDIO pin requires a 1.5 KΩ pull-up which, during idle and turn around periods, will pull SDIO to a logic “1“
state. NINJA F/FX (ADM6992F/FX) requires a single initialization sequence of 35 bits of preamble following
power-up/hardware reset. The first 35 bits are preamble consisting of 35 contiguous logic “1“ bits on SDIO and 35
corresponding cycles on SDC. Following preamble, the start-of-frame field is indicated by a <01> pattern. The next
field signals the operation code (OP): <10> indicates read from management register operation, and <01>
indicates write to management register operation. The next field is management register address. It is 10 bits wide
and the most significant bit is transferred first.
Table 12
SMI Read/Write Command Format
Operation
Preamble
SFD
OP CHIPID[1:0]
Unused
Register
Address
TA Data
Read
35”1”s
01
10
2 bits CHIPID
00
6 bits Address
Z0
32 bits Data
Read
Write
35”1”s
01
01
2 bits CHIPID
00
6 bits Address
10
32 bits Data
Write
During Read operation, a 2-bit turn around (TA) time spacing between the register address field and data field is
provided for the SDIO to avoid contention. Following the turnaround time, a 32-bit data stream is read from or
written into the management registers of the NINJA F/FX (ADM6992F/FX).
Figure 3
Data Sheet
SMI Read Operation
27
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Function Description
Figure 4
SMI Write Operation
3.7.1
Preamble Suppression
The SMI of NINJA F/FX (ADM6992F/FX) supports a preamble suppression mode. If the station management
entity (i.e. MAC or other management controller) determines that all devices which are connected to the same
SDC/SDIO in the system support preamble suppression, then the station management entity needs not to
generate preamble for each management transaction. The NINJA F/FX (ADM6992F/FX) requires a single
initialization sequence of 35 bits of preamble following power-up/hardware reset. This requirement is generally met
by pulling-up the resistor of SDIO. While the NINJA F/FX (ADM6992F/FX) will respond to management accesses
without preamble, a minimum of one idle bit between management transactions is required.
When NINJA F/FX (ADM6992F/FX) detects that there is address match, then it will enable Read/Write capability
for external access. When an address is mismatched, then NINJA F/FX (ADM6992F/FX) will tri-state the SDIO pin.
3.7.2
Read EEPROM Register via SMI Register
The following 2 steps are for reading the data of EEPROM Register via SMI Interface.
Write the address of the desired EEPROM Register and READ command to SMI Register 013H
EX. <35”1”s><01><01><00000><10011><10><000 0000000 000001 0000000000000000>
CMD ADDRESS DATA
Read NINJA F/FX (ADM6992F/FX) Internal EEPROM mapping Reg.1H. Read SMI Register 013H. The data of
desired EEPROM Register will be in bit [15:0].
EX. <35”1”s><01><10><00000><10011><z0><000 0000000 000000 0001000001001111>
CMD ADDRESS DATA
Get NINJA F/FX (ADM6992F/FX) Internal EEPROM mapping Reg.1H. value 104f.
Data Sheet
28
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Function Description
3.7.3
Write EEPROM Register via SMI Register
To write data into desired EEPROM Register, write the address of the EEPROM Register.
EX. <35”1”s><01><01><00000><00100><10><001 0000000 000001 0001000001000000>
CMD ADDRESS DATA
Write NINJA F/FX (ADM6992F/FX) Internal EEPROM mapping Reg.1H. with value 820f.
3.8
Reset Operation
The NINJA F/FX (ADM6992F/FX) can be reset either by hardware or software. A hardware reset is accomplished
by applying a negative pulse, with duration of at least 100 ms to the RC pin of the NINJA F/FX (ADM6992F/FX)
during normal operation to guarantee internal SSRAM is reset properly.
Hardware reset operation samples the pins and initializes all registers to their default values. This process includes
re-evaluation of all hardware configurable registers. A hardware reset affects all embedded PHYs in the device.
Software reset can reset all embedded PHY and it does not latch the external pins nor reset the registers to their
respective default value. This can be achieved by writing FF to EEPROM Reg.3FH.
Logic levels on several I/O pins are detected during a hardware reset to determine the initial functionality of NINJA
F/FX (ADM6992F/FX). Some of these pins are used as output ports after reset operation.
Care must be taken to ensure that the configuration setup will not interfere with normal operations. Dedicated
configuration pins can be tied to VCC or Ground directly. Configuration pins multiplexed with logic level output
functions should be either weakly pulled up or weakly pulled down through external resistors.
3.8.1
Write EEPROM Register via EEPROM Interface
To write data into desired EEPROM Register via EEPROM interface:
If external EEPROM 93C46 or 93C66 exists, any WRITE programming instructions after EWEN instruction be
executed can be updated effectively on EEPROM content and NINJA F/FX (ADM6992F/FX) internal mapping
register on the same time.
If no external EEPROM exists, EECS/EECK/EEDI must be kept tri-state at least 100ms after hardware reset. Any
WRITE programming instructions after EWEN instruction be executed can be updated effectively on NINJA F/FX
(ADM6992F/FX) internal mapping register. Please notice that NINJA F/FX (ADM6992F/FX) can only identify
93C66-programming instructions if no external EEPROM.
Data Sheet
29
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
4
Registers Description
This chapter describes descriptions of EEPROM Registers and Serial Management Registers.
4.1
EEPROM Registers
Table 13
EEPROM Register Map
Register
Bit 15-8
Bit 7-0
Default Value
00H
Signature
4154H
01H
Port 0 Configuration
104FH
02H
Port 1 Configuration
104FH
03H
Miscellaneous Configuration 0
0600H
04H
Miscellaneous Configuration 1
0000
05H
Miscellaneous Configuration 2
0014H
06H
Buffer Management Configuration 0
0198H
07H
Buffer Management Configuration 1
0258H
08H
Buffer Management Configuration 2
0008H
09H
Bandwidth Control Configuration 0
0000H
0AH
Bandwidth Control Configuration 1
0000H
0BH
Bandwidth Control Configuration 2
0000H
0CH
Bandwidth Control Configuration 3
0000H
0DH
PHY Miscellaneous Configuration
1A74H
0EH
Reserved MAC Address Filtering Configuration
0014
0FH
Filter Control Register 1
Filter Control Register 0
0000H
10H
Filter Control Register 3
Filter Control Register 2
0000H
11H
Filter Control Register 5
Filter Control Register 4
0000H
12H
Filter Control Register 7
Filter Control Register 6
0000H
13H
Filter Control Register 9
Filter Control Register 8
0000H
14H
Filter Control Register 11
Filter Control Register 10
0000H
15H
Filter Control Register 13
Filter Control Register 12
0000H
16H
Filter Control Register 15
Filter Control Register 14
0000H
17H
Filter Type Register 0
0000H
18H
Filter Type Register 1
0000H
19H
Filter Register 0
0000H
1AH
Filter Register 1
0000H
1BH
Filter Register 2
0000H
1CH
Filter Register 3
0000H
1DH
Filter Register 4
0000H
1EH
Filter Register 5
0000H
1FH
Filter Register 6
0000H
20H
Filter Register 7
0000H
21H
Filter Register 8
0000H
22H
Filter Register 9
0000H
Data Sheet
30
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Table 13
Register
EEPROM Register Map (cont’d)
Bit 15-8
Bit 7-0
Default Value
23H
Filter Register 10
0000H
24H
Filter Register 11
0000H
25H
Filter Register 12
0000H
26H
Filter Register 13
0000H
27H
Filter Register 14
0000H
28H
Filter Register 15
0000H
29H
PVID and PCID MASK of Port 0
00001
2AH
PVID and PCID MASK of Port 0
0000H
2BH
PVID and PCID MASK of Port 1
00001
2CH
PVID and PCID MASK of Port 1
D000H
2DH
Tag Rule 0
F000H
2EH
Tag Rule 0
00FFH
2FH
Tag Rule 1
F000H
30H
Tag Rule 1
00FFH
31H
Tag Rule 2
F000H
32H
Tag Rule 2
00FFH
33H
Tag Rule 3
F000H
34H
Tag Rule 2
00FFH
35H
OAM Configuration Register 1
0380H
36H
OAM Configuration Register 2
FEFFH
Vender Code[15:0]
0000H
37H
38H
Model Number[7:0]
Vender Code[23:16]
0000H
39H
Model Number[23:8]
0000H
3AH
Forwarding Configuration 1
6000H
3BH
Forwarding Configuration 2
0000H
3CH
Default Value Control Register
0000H
Data Sheet
31
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
4.2
EEPROM Register Descriptions
Table 14
Registers Address Space
Module
Base Address
End Address
EEPROM
00H
3CH
Table 15
Note
Registers Overview
Register Short Name
Register Long Name
Offset Address
Page Number
SR
Signature Register
00H
34
PCR_0
Port Configuration Register 0
01H
35
PCR_1
Port Configuration Register 1
02H
36
MC_0
Miscellaneous Configuration 0
03H
37
MCR_1
Miscellaneous Configuration Register 1
04H
37
MCR_2
Miscellaneous Configuration Register 2
05H
39
BMC_0
Buffer Management Configuration 0
06H
40
BMC_1
Buffer Management Configuration 1
07H
40
BMC_2
Buffer Management Configuration 2
08H
41
IBW_CCR_0
Ingress Bandwidth Control Configuration 0
09H
41
EBW_CCR_1
Egress Bandwidth Control Configuration 1
0AH
42
IBW_CCR_2
Ingress Bandwidth Control Configuration 2
0BH
42
EBW_CCR_3
Egress Bandwidth Control Configuration 3
0CH
42
PHY_MC
PHY Miscellaneous Configuration
0DH
43
MAC_AFC
MAC Address Filtering Configuration
0EH
44
PCFC_1_0
Packet Filter Control Register 1 and 0
0FH
45
PCFC_3_2
Packet Filter Control Registers 3 and 2
10H
45
PCFC_5_4
Packet Filter Control Registers 5 and 4
11H
45
PCFC_7_6
Packet Filter Control Registers 7 and 6
12H
45
PCFC_9_8
Packet Filter Control Registers 9 and 8
13H
45
PCFC_11_10
Packet Filter Control Registers 11 and 10
14H
45
PCFC_13_12
Packet Filter Control Registers 13 and 12
15H
45
PCFC_15_14
Packet Filter Control Registers 15 and 14
16H
45
TFTR_0
Filter Type Register 0
17H
46
TFTR_1
Filter Type Register 1
18H
46
FR_0
Filter Register 0
19H
47
FR_1
Filter Register 1
1AH
47
FR_2
Filter Register 2
1BH
47
FR_3
Filter Register 3
1CH
47
FR_4
Filter Register 4
1DH
47
FR_5
Filter Register 5
1EH
47
FR_6
Filter Register 6
1FH
47
FR_7
Filter Register 7
20H
47
FR_8
Filter Register 8
21H
47
Data Sheet
32
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Table 15
Registers Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Page Number
FR_9
Filter Register 9
22H
47
FR_10
Filter Register 10
23H
47
FR_11
Filter Register 11
24H
47
FR_12
Filter Register 12
25H
47
FR_13
Filter Register 13
26H
47
FR_14
Filter Register 14
27H
47
FR_15
Filter Register 15
28H
47
PB_ID_0_0
Port Base VLAN ID and Mask 0 of Port 0
29H
48
PB_ID_1_0
Port Base VLAN ID and Mask 1 of Port 0
2AH
48
PB_ID_0_1
Port Base VLAN ID and Mask 0 of Port 1
2BH
49
PB_ID_1_1
Port Base VLAN ID and Mask 1 of Port 1
2CH
49
TPR_0_0
Tag Port Rule 0 Register 0
2DH
50
TPR_1_0
Tag Port Rule 1 Register 0
2EH
50
TPR_0_1
Tag Port Rule 0 Register 1
2FH
50
TPR_1_1
Tag Port Rule 1 Register 1
30H
51
TPR_0_2
Tag Port Rule 0 Register 2
31H
50
TPR_1_2
Tag Port Rule 1 Register 2
32H
51
TPR_0_3
Tag Port Rule 0 Register 3
33H
50
TPR_1x
Tag Port Rule 1 x
34H
51
OAM_C_1
OAM Configuration Register 1
35H
51
OAM_CR_2
OAM Configuration Register 2
36H
53
MCR_3
Miscellaneous Configuration Register 3
37H
53
MCR_4
Miscellaneous Configuration 4
38H
54
MCR_5
Miscellaneous Configuration Register 5
39H
54
FC_1
Forwarding Configuration 1
3AH
55
FC_2
Forwarding Configuration 2
3BH
55
DV_CR
Default Value Control Register
3CH
56
The register is addressed wordwise.
Table 16
Mode
Register Access Types
Symbol Description HW
Description SW
read/write
rw
Register is used as input for the HW
Register is readable and writable by SW
read
r
Value written by software is ignored by
Register is written by HW (register
between input and output -> one cycle hardware; that is, software may write any
value to this field without affecting hardware
delay)
behavior (= Target for development.)
Read only
ro
Register is set by HW (register between SW can only read this register
input and output -> one cycle delay)
Read virtual
rv
Physically, there is no new register, the SW can only read this register
input of the signal is connected directly
to the address multiplexer.
Data Sheet
33
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Table 16
Register Access Types (cont’d)
Mode
Symbol Description HW
Latch high,
self clearing
lhsc
Latches high signal at high level, clear SW can read the register
on read
Latch low,
self clearing
llsc
Latches high signal at low-level, clear
on read
SW can read the register
Latch high,
mask clearing
lhmk
Latches high signal at high level,
register cleared with written mask
SW can read the register, with write mask
the register can be cleared (1 clears)
Latch low,
mask clearing
llmk
Latches high signal at low-level,
register cleared on read
SW can read the register, with write mask
the register can be cleared (1 clears)
Interrupt high,
self clearing
ihsc
Differentiates the input signal (low>high) register cleared on read
SW can read the register
Interrupt low,
self clearing
ilsc
Differentiates the input signal (high>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
ihmk
Differentiates the input signal (highSW can read the register, with write mask
>low) register cleared with written mask the register can be cleared
Interrupt low,
mask clearing
ilmk
Differentiates the input signal (low>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Interrupt enable ien
register
Enables the interrupt source for
interrupt generation
SW can read and write this register
latch_on_reset
lor
rw register, value is latched after first
clock cycle after reset
Register is readable and writable by SW
Read/write
self clearing
rwsc
Register is used as input for the hw, the Writing to the register generates a strobe
register will be cleared due to a HW
signal for the HW (1 pdi clock cycle)
mechanism.
Register is readable and writable by SW.
Table 17
Description SW
Registers Clock DomainsRegisters Clock Domains
Clock Short Name
4.2.1
Description
EEPROM Register Format
Signature Register
SR
Signature Register
Offset
00H
Reset Value
4154H
6LJQDWXUH
UR
Data Sheet
34
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Field
Bits
Type
Description
Signature
15:0
ro
Signature
4154H
SIG, Default (AT)
Port Configuration Register 0
PCR_0
Port Configuration Register 0
/%&
3$&
UZ
UZ
537 237&
UZ
Offset
01H
0$&
UZ
Reset Value
104FH
$13' $1
UZ
UZ
UZ
$1$
';
63
$1(
)&
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
LBC
15
rw
Loop-back Control
0B
N, Normal Operation (Default)
1B
LP, Local Loop-back for Port1/Port0
PAC
14
rw
Packet Authorization Control
0B
ALL, All packet (Default)
1B
PPP, PPPOE only
RPT
13
rw
Receive Packet TAG Recognition Control
0B
REC, Recognize VLAN TAG automatically (Default)
DIS, Disable
1B
OPTC
12
rw
Output Packet Tagging Control
0B
TAG, TAG/UNTAG packets if needed
1B
BP, Bypass TX packets same as RX (Default)
MAC
11:7
rw
MAC Learning Table Entry Limitation
0B
DIS, Disable Total MAC Limitation (Default)
1B
MAX, Maximum allowable total MAC
ANPD
6
rw
Auto-Negotiation Parallel Detect Follow IEEE802.3
0B
B, Both
H, Half only (Default)
1B
AN
5
rw
Auto-Negotiation Advertise Single Capability
0B
E, Expand (Default)
1B
S, Single
ANA
4
rw
Auto-Negotiation Advertisement
0B
FS, Follow speed and duplex setting to negotiate with link partner.
(Default)
1B
4W, Always 4 way Auto-negotiation
DX
3
rw
Duplex
0B
HD, Half Duplex
1B
FD, Full Duplex (Default)
Data Sheet
35
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Field
Bits
Type
Description
SP
2
rw
Speed
10M, 10M
0B
1B
100M, 100M (Default)
ANE
1
rw
Auto negotiation Enable
0B
D, Disable Auto-negotiation
1B
E, Enable Auto-negotiation. (Default)
FC
0
rw
802.3x Flow Control Command Ability
0B
D, Disable 802.3x Flow control command ability
1B
E, Enable 802.3x Flow control command ability (Default)
Port Configuration Register 1
PCR_1
Port Configuration Register 1
/%&
3$&
UZ
UZ
537 237&
UZ
Offset
02H
0$&
UZ
Reset Value
104FH
$13' $1
UZ
UZ
UZ
$1$
';
63
$1(
)&
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
LBC
15
rw
Loop-back Control
0B
N, Normal Operation (Default)
LP, Local Loop-back for Port1/Port0
1B
PAC
14
rw
Packet Authorization Control
0B
ALL, All packet (Default)
1B
PPP, PPPOE only
RPT
13
rw
Receive Packet TAG Recognition Control
0B
REC, Recognize VLAN TAG automatically (Default)
1B
DIS, Disable
OPTC
12
rw
Output Packet Tagging Control
0B
TAG, TAG/UNTAG packets if needed
BP, Bypass TX packets same as RX (Default)
1B
MAC
11:7
rw
MAC Learning Table Entry Limitation
0B
DIS, Disable Total MAC Limitation (Default)
1B
MAX, Maximum allowable total MAC
ANPD
6
rw
Auto-Negotiation Parallel Detect Follow IEEE802.3
0B
B, Both
1B
H, Half only (Default)
AN
5
rw
Auto-Negotiation Advertise Single Capability
0B
E, Expand (Default)
1B
S, Single
Data Sheet
36
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Field
Bits
Type
Description
ANA
4
rw
Auto-Negotiation Advertisement
0B
FS, Follow speed and duplex setting to negotiate with link partner.
(Default)
1B
4W, Always 4 way Auto-negotiation
DX
3
rw
Duplex
0B
HD, Half Duplex
1B
FD, Full Duplex (Default)
SP
2
rw
Speed
0B
10M, 10M
1B
100M, 100M (Default)
ANE
1
rw
Auto negotiation Enable
0B
D, Disable Auto-negotiation
1B
E, Enable Auto-negotiation. (Default)
FC
0
rw
802.3x Flow Control Command Ability
0B
D, Disable 802.3x Flow control command ability
1B
E, Enable 802.3x Flow control command ability (Default)
Miscellaneous Configuration 0
MC_0
Miscellaneous Configuration 0
Offset
03H
(&5& &56
UZ
Reset Value
0600H
036
UZ
UZ
Field
Bits
Type
Description
ECRC
15
rw
Enable CRC Check
0B
E, Enable (Default)
D, Disable
1B
CRS
14
rw
CRS (carrier sense) check disable
Checking of the length of CRS
0B
ED, Enable (Default)
1B
DD, Disable
MPS
13:0
rw
Maximum Packet Size
Maximum allowable frame size in bytes
9216D
MAX, Max. bytes number
1536D
DEF, Default value
Miscellaneous Configuration Register 1
Data Sheet
37
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
MCR_1
Miscellaneous Configuration Register 1
Offset
04H
/('B /('B
()0B
67
21 0$& 3)5& 5HV 9/$1 3
UZ
UZ
UZ
UZ
UR
UZ
UZ
Reset Value
0000H
3/
'%2
'3
$'
5HV
UZ
UZ
UZ
UZ
UR
Field
Bits
Type
Description
LED_ST
15
rw
LED Status Definition when UTP link down
0B
TBD, always put off LEDs of UTP port when UTP link down
(Default)
1B
TBD, LEDs of UTP port show DIPSW setting when auto-negotiation
disable and link down
LED_ON
14
rw
Turn on all LED
at the same time during LED self test
0B
TBD, Disable (Default)
1B
TBD, Enable
MAC
13
rw
MAC address table hashing algorithm Control
0B
DM, MAC address lookup table use direct mode to generate hash
key (Default)
1B
CRC, MAC address lookup table use CRC to generate hash key
PFRC
12
rw
Pause Frame Recognition Control
when auto-negotiation disable
0B
STOP, Stop transmitting frame if PAUSE frame received. (Default)
1B
NOS, Don’t stop transmitting frame if PAUSE frame received when
flow control capability is disabled.
Res
11
ro
Reserved
0B
DEF, Default
VLAN
10
rw
Replace VLAN ID 0 and 1 by PVID
0B
D, Disable (Default)
1B
R, Replace
EFM_P0
9
rw
Emulated Force Mode for Port0
0B
D, Disable (Default)
1B
TBD,
PL
8
rw
Preamble Leveling
0B
7B, 7 bytes (Default)
1B
6B, 6 bytes
DBO
7
rw
Disable Back-Off
0B
E, Enable (Default)
1B
D, Disable
DP
6
rw
Discard Packet after 16th Collision
0B
E, Disable (Default)
1B
D, Enable
Data Sheet
38
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Field
Bits
Type
Description
AD
5
rw
Aging Disable
E, Enable aging (Default)
0B
1B
D, Disable aging
Res
4:0
ro
Reserved
Miscellaneous Configuration Register2
MCR_2
Miscellaneous Configuration Register 2
3'
$*
UZ
UZ
Offset
05H
Reset Value
0014H
/37' 3B0 ;29( )&', 5(&+ 5(& $1',
5HV
,6
',
1
6
$/)
6
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UR
)735
)3&
&XW
UZ
UZ
UZ
873B 873B
/(' /LQN
UZ
Field
Bits
Type
Description
PD
15
rw
Polarity definition
Change for hardware pin INT_N
0B
LA, INT_N Low Active (Default)
1B
HA, INT_N High Active
AG
14
rw
Aging
0B
N, Normal (Default)
1B
F, Fast
LPTDIS
13
rw
Polarity definition change for hardware pin LPTDIS
0B
DIP, Disable Inverse Polarity of LPTDIS (Default)
1B
IP, Inverse Polarity of LPTDIS
P0_MDI
12
rw
Polarity definition change for hardware pin P0_MDI
0B
DIP, Disable Inverse Polarity of P0_MDI (Default)
1B
IP, Inverse Polarity of P0_MDI
XOVEN
11
rw
Polarity definition change for hardware pin XOVEN
0B
DIP, Disable Inverse Polarity of XOVEN (Default)
1B
IP, Inverse Polarity of XOVEN
FCDIS
10
rw
Polarity definition change for hardware pin P0_FCDIS and
P1_FCDIS
0B
DIP, Disable Inverse Polarity (Default)
1B
IP, Inverse Polarity
RECHALF
9
rw
Polarity definition change for hardware pin P0_RECHALF and
P1_RECHALF
0B
DIP, Disable Inverse Polarity (Default)
1B
IP, Inverse Polarity
REC10
8
rw
Polarity definition change for hardware pin P0_REC10 and
P1_REC10
0B
DIP, Disable Inverse Polarity (Default)
1B
IP, Inverse Polarity
Data Sheet
39
UZ
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Field
Bits
Type
Description
ANDIS
7
rw
Polarity definition change for hardware pin P0_ANDIS and
P1_ANDIS
0B
DIP, Disable Inverse Polarity (Default)
1B
IP, Inverse Polarity
Res
6
ro
Reserved
0B
DEF, Default
FTPR
5:4
rw
FTPR_MODE
00B OAM, OAM
01B FEFI, FEFI(Default)
1xB IDS, Disable
FPC
3
rw
Fault Propagation Control
0B
EP, Enable Fault Propagation in converter mode (Default)
1B
DP, Disable Fault Propagation
Cut
2
rw
Cut-Through Forwarding Control in converter mode
0B
ES, Enable 100M snooping in converter mode
1B
DS, Disable snooping (Default)
UTP_LED
1
rw
UTP led control during Loop Back Test
0B
OFF, Put off LEDs of UTP port during loopback test . (Default)
1B
NOT, Don.t put off LEDs of UTP port during loopback test.
UTP_Link
0
rw
UTP link control during Loop Back Test
0B
LD, Link Disable during Loop Back Test(Default)
1B
LE, Link Enable during Loop Back Test
Buffer Management Configuration 0
BMC_0
Buffer Management Configuration 0
Offset
06H
Reset Value
0198H
5HV
UR
Field
Bits
Type
Description
Res
15:0
ro
Reserved
0198H
DEF, Default
Buffer Management Configuration 1
BMC_1
Buffer Management Configuration 1
Data Sheet
Offset
07H
40
Reset Value
0258H
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
5HV
UR
Field
Bits
Type
Description
Res
15:0
ro
Reserved
0258H
DEF, Default
Buffer Management Configuration 2
BMC_2
Buffer Management Configuration 2
Offset
08H
Reset Value
0008H
5HV
UR
Field
Bits
Type
Description
Res
15:0
ro
Reserved
0008H
DEF, Default
Ingress Bandwidth Control Configuration 0
IBW_CCR_0
Ingress Bandwidth Control Configuration 0
Offset
09H
,%&B
3
,%&7B3
UZ
UZ
Reset Value
0000H
Field
Bits
Type
Description
IBC_P0
15
rw
Port 0 Ingress Bandwidth Control
0B
D, Disable (Default)
1B
E, Enable
IBCT_P0
14:0
rw
Port0 Ingress Bandwidth Control Threshold
Step size: 4 Kbytes
0000H
DEF, Default
Data Sheet
41
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Egress Bandwidth Control Configuration 1
EBW_CCR_1
Egress Bandwidth Control Configuration 1
Offset
0AH
(%&B
3
(%&7B3
UZ
UZ
Reset Value
0000H
Field
Bits
Type
Description
EBC_P0
15
rw
Port 0 Egress Bandwidth Control
0B
D, Disable (Default)
1B
E, Enable
EBCT_P0
14:0
rw
Port 0 Egress Bandwidth Control Threshold
Step size: 4 Kbytes
0000H
Z, Default
Ingress Bandwidth Control Configuration 2
IBW_CCR_2
Ingress Bandwidth Control Configuration 2
Offset
0BH
,%&B
3
,%&7B3
UZ
UZ
Reset Value
0000H
Field
Bits
Type
Description
IBC_P1
15
rw
Port 1 Ingress Bandwidth Control
0B
D, Disable (Default)
1B
E, Enable
IBCT_P1
14:0
rw
Port 1 Ingress Bandwidth Control Threshold
Step size: 4 Kbytes
0000H
Z, Default
Egress Bandwidth Control Configuration 3
EBW_CCR_3
Egress Bandwidth Control Configuration 3
Data Sheet
Offset
0CH
42
Reset Value
0000H
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
(%&B
3
(%&7B3
UZ
UZ
Field
Bits
Type
Description
EBC_P1
15
rw
Port 1 Egress Bandwidth Control
0B
D, Disable (Default)
E, Enable
1B
EBCT_P1
14:0
rw
Port 1 Egress Bandwidth Control Threshold
Step size: 4 Kbytes
0000H
Z, Default
PHY Miscellaneous Configuration
PHY_MC
PHY Miscellaneous Configuration
Offset
0DH
Reset Value
1A74H
5HV
UR
Field
Bits
Type
Description
Res
15:0
ro
Reserved
1A74H
CONF, Default
Data Sheet
43
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Reserved MAC Address Filtering Configuration
MAC_AFC
MAC Address Filtering Configuration
Offset
0EH
Reset Value
0014H
0)0
78)0
5HV
&5&
5HV
3)0B
3)0B
3)0B
3)0B
UZ
UZ
UR
UR
UR
UZ
UR
UZ
UZ
Field
Bits
Type
Description
MFM
15:14
rw
Match Frame Mode
00B SAM, CRC is correct and the same with CRC of last requested
transmitted user frame (Default)
01B COR, CRC is correct
10B DIF, CRC is incorrect or different with CRC of last requested
transmitted user frame
11B INC, CRC is incorrect
TUFM
13:12
rw
Transmit user frame mode
00B SF, Single frame (Default)
01B CMF, Continuous transmit until match frame found or match timer
expired
1xB CT, Continuous transmit
Res
11
ro
Reserved
0B
DEF, Default
CRC
10
ro
Disable OAM CRC check
0B
E, Enable (Default)
1B
D, Disable
Res
9:8
ro
Reserved
00B DEF, Default
PFM_10
7:6
rw
Packet Filtering Mode for Received DA
= 01 80 C2 00 00 10 ~ 01 80 C2 00 00 FF
0B
DEF, Default
PFM_02
5:4
ro
Packet Filtering Mode for Received DA
= 01 80 C2 00 00 02 ~ 01 80 C2 00 00 0F
1B
DEF, Default
PFM_01
3:2
rw
Packet Filtering Mode for Received DA
= 01 80 C2 00 00 01 and OPCODE != PAUSE
01B DEF, Default (Fixed)
PFM_00
1:0
rw
Packet Filtering Mode for Received DA
= 01 80 C2 00 00 00
00B DEF, Default
Data Sheet
44
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Packet Filter Control Registers 1 and 0
PCFC_1_0
Packet Filter Control Register 1 and 0
5HV
$3B $3B
5
5
UR
UZ
Offset
0FH
23&B$
5HV
UR
UR
UR
Reset Value
0000H
$3B $3B
5
5
UZ
23&B
UZ
UZ
Field
Bits
Type
Description
Res
15
ro
Reserved
AP1_R1
14
rw
Apply to Port 1 Rx 1
0B
DNA, Do not apply
1B
APL, Apply
AP0_R1
13
ro
Apply to Port 0 Rx 1
0B
DNA, Do not apply
1B
APL, Apply
OPC_1A
12:8
ro
OP Code for Filter
Defined in Register 1AH (1CH, 1EH, 20H, 22H, 24H, 26H, 28H)
Res
7
ro
Reserved
AP1_R1
6
rw
Apply to Port 1 Rx 1
0B
DNA, Do not apply
1B
APL, Apply
AP1_R1
5
rw
Apply to Port 0 Rx 1
0B
DNA, Do not apply
1B
APL, Apply
OPC_19
4:0
rw
OP Code for Filter
which defined in Register 19H (1BH, 1DH, 1FH, 21H, 23H, 25H, 27H)
Other Packet Filter Control Registers have the same structure and characteristics as Packet Filter Control
Registers 1 and 0; the offset addresses are listed in Table 18.
Table 18
Other Packet Filter Control Regsiters
Register Short Name
Register Long Name
Offset Address
PCFC_3_2
Packet Filter Control Registers 3 and 2
10H
PCFC_5_4
Packet Filter Control Registers 5 and 4
11H
PCFC_7_6
Packet Filter Control Registers 7 and 6
12H
PCFC_9_8
Packet Filter Control Registers 9 and 8
13H
PCFC_11_10
Packet Filter Control Registers 11 and 10
14H
PCFC_13_12
Packet Filter Control Registers 13 and 12
15H
PCFC_15_14
Packet Filter Control Registers 15 and 14
16H
Data Sheet
45
Page Number
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Filter Type Register 0
TFTR_0
Filter Type Register 0
Offset
17H
Reset Value
0000H
7)BB
7)BB
7)BB
7)BB
7)BB
7)BB
7)BB
7)BB
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
TF_7_15
15:14
rw
Type of Filter 7
TF_6_14
13:12
rw
Type of Filter 6
TF_5_13
11:10
rw
Type of Filter 5
TF_4_12
9:8
rw
Type of Filter 4
TF_3_11
7:6
rw
Type of Filter 3
TF_2_10
5:4
rw
Type of Filter 2
TF_1_9
3:2
rw
Type of Filter 1
TF_0_8
1:0
rw
Type of Filter 0
Filter Type Register 1
TFTR_1
Filter Type Register 1
Offset
18H
Reset Value
0000H
7)BB
7)BB
7)BB
7)BB
7)BB
7)BB
7)BB
7)BB
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
TF_7_15
15:14
rw
Type of Filter 15
TF_6_14
13:12
rw
Type of Filter 14
TF_5_13
11:10
rw
Type of Filter 13
TF_4_12
9:8
rw
Type of Filter 12
TF_3_11
7:6
rw
Type of Filter 11
TF_2_10
5:4
rw
Type of Filter 10
TF_1_9
3:2
rw
Type of Filter 9
TF_0_8
1:0
rw
Type of Filter 8
Data Sheet
46
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Filter Register 0
FR_0
Filter Register 0
Offset
19H
Reset Value
0000H
)LOWHU
UZ
Field
Bits
Type
Description
Filter
15:0
rw
Filter
Other Filter Registers have the same structure and characteristics as Filter Register 0; the offset addresses are
listed in Table 19.
Table 19
Other Filter Regsiters
Register Short Name
Register Long Name
Offset Address
FR_1
Filter Register 1
1AH
FR_2
Filter Register 2
1BH
FR_3
Filter Register 3
1CH
FR_4
Filter Register 4
1DH
FR_5
Filter Register 5
1EH
FR_6
Filter Register 6
1FH
FR_7
Filter Register 7
20H
FR_8
Filter Register 8
21H
FR_9
Filter Register 9
22H
FR_10
Filter Register 10
23H
FR_11
Filter Register 11
24H
FR_12
Filter Register 12
25H
FR_13
Filter Register 13
26H
FR_14
Filter Register 14
27H
FR_15
Filter Register 15
28H
Data Sheet
47
Page Number
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Port Base VLAN ID and Mask 0 of Port 0
PB_ID_0_0
Port Base VLAN ID and Mask 0 of Port 0
'35,
'&),
39,'
UZ
UZ
UZ
Offset
29H
Reset Value
0001H
5HV
Field
Bits
Type
Description
DPRI
15:13
rw
DPRI
Default Priority
DCFI
12
rw
DCFI
Default CFI
PVID
11:10
rw
PVID
Port base VLAN ID
01B DEF, Default
Port Base VLAN ID and Mask 0 of Port 1
PB_ID_1_0
Port Base VLAN ID and Mask 1 of Port 0
Offset
2AH
Reset Value
0000H
39,'
UZ
Field
Bits
Type
Description
PVID
15:0
rw
PVID Mask
Data Sheet
48
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Port Base VLAN ID and Mask 0 of Port 1
PB_ID_0_1
Port Base VLAN ID and Mask 0 of Port 1
'35,
'&),
39,'
UZ
UZ
UZ
Offset
2BH
Reset Value
0001H
5HV
Field
Bits
Type
Description
DPRI
15:13
rw
DPRI
Default Priority
DCFI
12
rw
DCFI
Default CFI
PVID
11:10
rw
PVID
Port base VLAN ID
01B DEF, Default
Port Base VLAN ID and Mask 1 of Port 1
PB_ID_1_1
Port Base VLAN ID and Mask 1 of Port 1
Offset
2CH
Reset Value
0000H
39,'
UZ
Field
Bits
Type
Description
PVID
15:0
rw
PVID Mask
Data Sheet
49
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Tag Port Rule 0 Register 0
TPR_0_0
Tag Port Rule 0 Register 0
Offset
2DH
Reset Value
F000H
5XOHB0DVN
5XOH
UZ
UZ
Field
Bits
Type
Description
Rule_Mask
15:12
rw
Rule Mask
FH D, Default
Rule
11:0
rw
Rule
Other Tag Port Rule 0 Registers have the same structure and characteristics as Tag Port Rule 0 Register 0; the
offset addresses are listed in Table 20.
Table 20
Other Tag Port Rule 0 Registers
Register Short Name
Register Long Name
Offset Address
TPR_0_1
Tag Port Rule 0 Register 1
2FH
TPR_0_2
Tag Port Rule 0 Register 2
31H
TPR_0_3
Tag Port Rule 0 Register 3
33H
Page Number
Tag Port Rule 1 Register 0
TPR_1_0
Tag Port Rule 1 Register 0
Offset
2EH
5HV
Field
Bits
Port
EX
R_Mask
Data Sheet
Reset Value
00FFH
3RUW
(;
5B0DVN
UZ
UZ
UZ
Type
Description
11:9
rw
Port to apply the rule
8
rw
Exclude Rule
7:0
rw
Rule Mask[11:4]
50
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Other Tag Port Rule 1 Registers have the same structure and characteristics as Tag Port Rule 1 Register 0; the
offset addresses are listed in Table 21.
Table 21
Other Tag Port Rule 1 Regsiters
Register Short Name
Register Long Name
Offset Address
TPR_1_1
Tag Port Rule 1 Register 1
30H
TPR_1_2
Tag Port Rule 1 Register 2
32H
Page Number
Tag Port Rule 1 x
TPR_1x
Tag Port Rule 1 x
Offset
34H
Reset Value
00FFH
/%70
7LPHU
3RUW
(5
5XOHB0DVN
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
LBTM
15
rw
Loop Back Test Mode
0B
TBD, depends on current speed configuration to test 10M or 100M
PHY (Default)
1B
TBD, Always test 100M PHY
Timer
14:12
rw
Timer
Timer to qualify power failure recovery status (second)
000B~111B, 0~8 seconds
000B
, 0 seconds (Default)
Port
11:9
rw
Port to apply the rule
ER
8
rw
Exclude Rule
Rule_Mask
7:0
rw
Rule Mask[11:4]
OAM Configuration Register 1
OAM_C_1
OAM Configuration Register 1
Offset
35H
76B'HI
76B&
3507
UZ
UZ
UZ
Data Sheet
Reset Value
0380H
'& 5&62 5&6) 8B/8 8B/' 7;) 61)& 0&
UZ
51
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Field
Bits
Type
Description
TS_Def
15:12
rw
TS-1000 OAM C field Bit[4:7] Definition for Remote Control
0000B
Z, Default
TS_C
11
rw
TS-1000 OAM C field Bit[1] Check
0B
CD, Check direction of OAM frame (Default)
1B
NC, Do not check direction of OAM frame
PRMT
10:8
rw
NINJA C (ADM6992C) Power Recovery Mask Timer when Power-OnInitial
Timer for Mask OAM after power up and Port 1 link up (second)
000B~111B, 0~8 seconds
011B
, 3 seconds (Default)
DC
7
rw
NINJA C (ADM6992C) Power Detection Control
0B
Z, Should be set
1B
TBD,
RCSO
6
rw
NINJA C (ADM6992C) OAM Remote Control Stop OAM Enable
0B
E, Enable Remote Control OAM (Default)
1B
D, Disable Remote Control OAM
RCSF
5
rw
NINJA C (ADM6992C) OAM Remote Control Start Function Enable
0B
D, Disable Remote Control (Default)
1B
E, Enable Remote Control
U_LU
4
rw
TS-1000 OAM S field Bit[7:10]
Definition when UTP link up
0B
SHOW, S7-S8 and S9 of OAM frame show PHY status if PHY link
up (Default)
1B
NOT, S7-S8 and S9 of OAM frame don’t show PHY status if PHY
link up
U_LD
3
rw
TS-1000 OAM S field Bit[7:10]
Definition when auto-negotiation enable and UTP link down
0B
DIS, Disable idiot setting. NINJA C (ADM6992C) will send DIPSW
setting to CO when UTP port auto-negotiation enable and link down
(Default)
1B
EIS, Enable idiot setting. NINJA C (ADM6992C) will always send
10MH to CO when UTP port auto-negotiation enable and link down
TXF
2
rw
Transmit MC_FAILURE when load EEPROM fail
0B
TBD, Assert MC_FAILURE when load EEPROM fail (Default)
1B
TBD, Don’t assert MC_FAILURE when load EEPOM fail
SNFC
1
rw
NTT TS-1000 Status Notification Frame Control
0B
TBD, Transmit one OAM frame if state change or state notification
request frame is received. (Default)
1B
TBD, Transmit three OAM frames if state change or state
notification request frame is received.
MC
0
rw
NTT TS-1000 MC Mode Control
0B
TBD, CPE mode (Default)
1B
TBD, CO mode
Data Sheet
52
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
OAM Configuration Register 2
NINJA C (ADM6992C) OAM C field Bit[8:15] definition for Remote Control
OAM_CR_2
OAM Configuration Register 2
Offset
36H
Reset Value
FEFFH
5&B()
5&B6)
UZ
UZ
Field
Bits
Type
Description
RC_EF
15:8
rw
Remote Control End Function
OAM C field Bit[8:15] definition
FEH
EF, Default
RC_SF
7:0
rw
Remote Control Start Function
OAM C field Bit[8:15] definition
FFH
SF, Default
Miscellaneous Configuration Register 3
Vender ID
MCR_3
Miscellaneous Configuration Register 3
Offset
37H
Reset Value
0000H
9HQGHUB,'
UZ
Field
Bits
Type
Description
Vender_ID
15:0
rw
NTT TS-1000 OAM M field Bit[15:0] definition
Vender ID Bits
Data Sheet
53
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Miscellaneous Configuration Register 4
MCR_4
Miscellaneous Configuration 4
Offset
38H
Reset Value
0000H
01BB
9,'BB
UZ
UZ
Field
Bits
Type
Description
MN_7_0
15:8
rw
NTT TS-1000 OAM M field Bit[31:24] definition
Model Number Bit [7:0]
VID_23_16
7:0
rw
NTT TS-1000 OAM M field Bit[23:16] definition
Vender ID Bit [23:16]
Miscellaneous Configuration Register 5
MCR_5
Miscellaneous Configuration Register 5
Offset
39H
Reset Value
0000H
01BB
UZ
Field
Bits
Type
Description
MN_23_8
15:0
rw
NTT TS-1000 OAM M field Bit[47:32] definition
Model Number Bits [23:8]
Data Sheet
54
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Forwarding Configuration 1
FC_1
Forwarding Configuration 1
Offset
3AH
Reset Value
6000H
5HV
)0B&
5HV
)&
UR
UZ
UR
UZ
Field
Bits
Type
Description
Res
15:4
ro
Reserved
600H
D, Default
FM_C
3:2
rw
Forwarding Mode Control
00B SF, Store & Forward (Default)
01B MCT, Modify Cut-Through
10B R, Reserved
11B MII, MII Cut-Through
Res
1
ro
Reserved
0B
, Default
FC
0
rw
Forwarding Mode auto-change Control
0B
FIX, Fix Forwarding Mode (Default)
1B
A, Automatically Change Forwarding Mode
Forwarding Configuration 2
FC_2
Forwarding Configuration 2
Offset
3BH
Reset Value
0000H
5HV
UR
Field
Bits
Type
Description
Res
15:0
ro
Reserved
0000H
Z, Default
Data Sheet
55
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Default Value Control Register
DV_CR
Default Value Control Register
38B0 36B' 36B& 30B7 ,3*
UZ
UZ
UZ
UZ
UZ
Offset
3CH
,3B' ,3B)
UZ
UZ
Reset Value
0000H
%3
(2
'/
UZ
UZ
UZ
); );B
UZ
UZ
/('B /('B /('B
',6
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
PU_M
15
rw
Power up mask mode
0B
TBD, by timer defined in EEPROM register 35H Bit[10:8] (Default)
1B
TBD, by LED self test
PS_D
14
rw
Power status detect mode
0B
TBD, mode 0 (Default)
1B
TBD, mode 1
PS_C
13
rw
Power status change mask timer
0B
TBD, the same with power up mask timer which defined in
EEPROM register 35H Bit[10:8] (Default)
1B
TBD, EEPROM register 34H Bit [14:12]
PM_T
12
rw
Power mask timer time base before first OAM was sent
0B
TBD, 1 sec (Default)
1B
TBD, 0.5 sec
IPG
11
rw
Place IPG
0B
TBD, Place IPG before and after OAM frame and loop back test
frame (Default)
1B
TBD, Place IPG/2 before and after OAM frame and loop back test
frame
IP_D
10
rw
Inverse Polarity of A_PD_DETECT
0B
TBD, Disable inverse the polarity (Default)
1B
TBD, Inverse the polarity
IP_F
9
rw
Inverse Polarity of MC_FAILURE
0B
TBD, Disable inverse the polarity (Default)
1B
TBD, Inverse the polarity
BP
8
rw
Polarity definition change for power-on-setting pin
BYPASS_PAUSE
0B
TBD, Disable inverse the default value (Default)
1B
TBD, Inverse the default value
EO
7
rw
Polarity definition change for power-on-setting pin EN_OAM
0B
TBD, Disable inverse the default value (Default)
1B
TBD, Inverse the default value
DL
6
rw
Polarity definition change for power-on-setting pin DIS_LEARN
0B
TBD, Disable inverse the default value of DIS_LEARN (Default)
1B
TBD, Inverse the default value of DIS_LEARN
Data Sheet
56
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Field
Bits
Type
Description
FX1
5
rw
Polarity definition change for power-on-setting pin FXMODE[1]
0B
TBD, Disable inverse the default value (Default)
1B
TBD, Inverse the default value
FX_0
4
rw
Polarity definition change for power-on-setting pin FXMODE[0]
0B
TBD, Disable inverse the default value (Default)
1B
TBD, Inverse the default value
LED_2
3
rw
Polarity definition change for power-on-setting pin LEDMODE[2]
0B
TBD, Disable inverse the default value (Default)
1B
TBD, Inverse the default value
LED_1
2
rw
Polarity definition change for power-on-setting pin LEDMODE[1]
0B
TBD, Disable inverse the default value (Default)
1B
TBD, Inverse the default value
LED_0
1
rw
Polarity definition change for power-on-setting pin LEDMODE[0]
0B
TBD, Disable inverse the default value (Default)
1B
TBD, Inverse the default value
DIS
0
rw
Polarity definition change for power-on-setting pin DISBP_N
0B
TBD, Disable inverse the default value (Default)
1B
TBD, Inverse the default value
4.3
Serial Management Registers
Table 22
Serial Management Register Map
Register
Bit 31-0
Default Value
00H
Chip Identify
0002 1090H
01H
Over Flow Flag
0000 0000H
02H
P0 Receive packets
0000 0000H
03H
P0 Receive byte count
0000 0000H
04H
P0 Transmit packets
0000 0000H
05H
P0 Transmit byte count
0000 0000H
06H
P0 error count
0000 0000H
07H
P0 collision count
0000 0000H
08H
P1 Receive packets
0000 0000H
09H
P1 Receive byte count
0000 0000H
0AH
P1 Transmit packets
0000 0000H
0BH
P1 Transmit byte count
0000 0000H
0CH
P1 error count
0000 0000H
0DH
P1 collision count
0000 0000H
0EH
Per Port Counter Reset
0000 0000H
0FH
Hardware Settings
Pin
10H
Interrupt Register
0000 0000H
11H
Interrupt mask Register
0000 0000H
12H
Port Status
Real Time Status
13H
EEPROM Register File Access Control
0000 4154H
Data Sheet
57
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Table 22
Serial Management Register Map (cont’d)
Register
Bit 31-0
Default Value
14H
OAM Control Register
0000 0000H
15H
Source Address of Loop Back Test User Frame 0
0000 0000H
16H
Source Address of Loop Back Test User Frame 1
0000 0000H
17H
Transmit OAM Frame Register 0
0000 0000H
18H
Transmit OAM Frame Register 1
0000 0000H
19H
Transmit OAM Frame Register 2
0000 0000H
1AH
Received OAM Frame Register 0
0000 0000H
1BH
Received OAM Frame Register 1
0000 0000H
1CH
Received OAM Frame Register 2
0000 0000H
1DH
OAM Frame Status Register
0000 0000H
Note: Any write activity to counter register will reset the counter and the overflow flag of this counter.
Data Sheet
58
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
4.4
Serial Management Register Descriptions
Table 23
Registers Address SpaceRegisters Address Space
Module
Base Address
End Address
Serial
00H
1DH
Table 24
Note
Registers Overview
Register Short Name
Register Long Name
Offset Address
Page Number
Chip_ID
Chip Identifier
00H
60
OFR
Overflow Flag Register
01H
61
PCNR_0
Port 0 Counter Register
02H
62
P0RBC
P0 Receive byte count
03H
62
P0TP
P0 Transmit packets
04H
62
P0TBC
P0 Transmit byte count
05H
62
P0EC
P0 Error count
06H
62
P0CC
P0 Collision count
07H
62
P1RP
P1 Receive packets
08H
62
P1RBC
P1 Receive byte count
09H
62
P1TP
P1 Transmit packets
0AH
62
P1TBC
P1 Transmit byte count
0BH
62
P1EC
P1 Error count
0CH
62
P1CC
P1 Collision count
0DH
62
PCRR
Port Counter Reset Register
0EH
62
HW_SSR
Hardware Setting Status Register
0FH
64
INT
Interrupt Register
10H
65
INT_M
Interrupt Mask Register
11H
66
PSR
Port Status Register
12H
68
EE_RFAC
EEPROM Register File Access Control
13H
69
OAM_CR
OAM Control Register
14H
70
SA_F_0
Source Address of Loop Back Test User Frame 0 15H
71
SA_F_1
Source Address of Loop Back Test User Frame 1 16H
72
TFR_0
Transmit OAM Frame Register 0
17H
72
TFR_1
Transmit OAM Frame Register 1
18H
72
TFR_2
Transmit OAM Frame Register 2
19H
73
RFR_0
Received OAM Frame Register 0
1AH
74
RFR_1
Received OAM Frame Register 1
1BH
74
RFR_2
Received OAM Frame Register 0
1CH
75
OAM_FSR
OAM Frame Status Register
1DH
75
The register is addressed wordwise.
Data Sheet
59
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Table 25
Register Access Types
Mode
Symbol Description HW
Description SW
read/write
rw
Register is used as input for the HW
Register is read and writable by SW
read
r
Register is written by HW (register
Value written by software is ignored by
between input and output -> one cycle hardware; that is, software may write any
delay)
value to this field without affecting hardware
behavior (= Target for development.)
Read only
ro
Register is set by HW (register between SW can only read this register
input and output -> one cycle delay)
Read virtual
rv
Physically, there is no new register, the SW can only read this register
input of the signal is connected directly
to the address multiplexer.
Latch high,
self clearing
lhsc
Latches high signal at high level, clear SW can read the register
on read
Latch low,
self clearing
llsc
Latches high signal at low-level, clear
on read
SW can read the register
Latch high,
mask clearing
lhmk
Latches high signal at high level,
register cleared with written mask
SW can read the register, with write mask
the register can be cleared (1 clears)
Latch low,
mask clearing
llmk
Latches high signal at low-level,
register cleared on read
SW can read the register, with write mask
the register can be cleared (1 clears)
Interrupt high,
self clearing
ihsc
Differentiates the input signal (low>high) register cleared on read
SW can read the register
Interrupt low,
self clearing
ilsc
Differentiates the input signal (high>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
ihmk
Differentiates the input signal (highSW can read the register, with write mask
>low) register cleared with written mask the register can be cleared
Interrupt low,
mask clearing
ilmk
Differentiates the input signal (low>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Interrupt enable ien
register
Enables the interrupt source for
interrupt generation
SW can read and write this register
latch_on_reset
lor
rw register, value is latched after first
clock cycle after reset
Register is readable and writable by SW
Read/write
self clearing
rwsc
Register is used as input for the hw, the Writing to the register generates a strobe
register will be cleared due to a HW
signal for the HW (1 pdi clock cycle)
mechanism.
Register is readable and writable by SW.
Table 26
Registers Clock DomainsRegisters Clock Domains
Clock Short Name
4.4.1
Description
Serail Management Register Format
Chip Identifier
Data Sheet
60
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Chip_ID
Chip Identifier
Offset
00H
Reset Value
0002 1090H
3B&RGH
5B&RGH
UR
UR
Field
Bits
Type
Description
P_Code
31:4
ro
Project Code
R_Code
3:0
ro
Revision Code
Overflow Flag Register
OFR
Overflow Flag Register
Offset
01H
Reset Value
0000 0000H
3 3 3 3 3 3 3 3 3 3 3 3
&& (& 7& 73 5& 53 && (& 7& 73 5& 53
5HV
OKVFOKVFOKVFOKVFOKVFOKVFOKVFOKVFOKVFOKVFOKVFOKVF
Field
Bits
Type
Description
P1CC
11
lhsc
P1 collision count
1B
TBD, Overflow
P1EC
10
lhsc
P1 error count overflow
1B
TBD, Overflow
P1TC
9
lhsc
P1 transmit byte count overflow
1B
TBD, Overflow
P1TP
8
lhsc
P1 transmit packets overflow
1B
TBD, Overflow
P1RC
7
lhsc
P1 Receive byte count overflow
1B
TBD, Overflow
P1RP
6
lhsc
P1 Receive packets overflow
1B
TBD, Overflow
P0CC
5
lhsc
P0 collision count overflow
1B
TBD, Overflow
P0EC
4
lhsc
P0 error count overflow
1B
TBD, Overflow
P0TC
3
lhsc
P0 Transmit byte count overflow
1B
TBD, Overflow
Data Sheet
61
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Field
Bits
Type
Description
P0TP
2
lhsc
P0 Transmit packets overflow
1B
TBD, Overflow
P0RC
1
lhsc
P0 Receive byte count overflow
1B
TBD, Overflow
P0RP
0
lhsc
P0 Receive packets overflow
1B
TBD, Overflow
Port 0 Counter Register
PCNR_0
Port 0 Counter Register
Offset
02H
Reset Value
0000 0000H
&RXQWHU
UZ
Field
Bits
Type
Description
Counter
31:0
rw
Counter
Other Counter Registers have the same structure and characteristics as Port 0 Counter Register; the names and
offset addresses are listed in Table 27.
Table 27
Other Counter Registers
Register Short Name
Register Long Name
Offset Address
P0RBC
P0 Receive byte count
03H
P0TP
P0 Transmit packets
04H
P0TBC
P0 Transmit byte count
05H
P0EC
P0 Error count
06H
P0CC
P0 Collision count
07H
P1RP
P1 Receive packets
08H
P1RBC
P1 Receive byte count
09H
P1TP
P1 Transmit packets
0AH
P1TBC
P1 Transmit byte count
0BH
P1EC
P1 Error count
0CH
P1CC
P1 Collision count
0DH
Page Number
Port Counter Reset Register
Data Sheet
62
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
PCRR
Port Counter Reset Register
Offset
0EH
Reset Value
0000 0000H
53 53
5HV
UZ UZ
Field
Bits
Type
Description
RP1
1
rw
Reset All Counter of Port 1
1B
RP1, Reset
RP0
0
rw
Reset All Counter of Port 0
1B
RP0, Reset
Data Sheet
63
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Hardware Setting Status Register
HW_SSR
Hardware Setting Status Register
Offset
0FH
Reset Value
pinH
5HV
%2 %2
' %
,'
'%
3
/0
)0
'$
/ (( %3 '/ 3 ($ ')
UR UR
UR
UR
UR
UR
UR UR UR UR UR UR
UR
$1$
6
'+
UR
UR
UR
Field
Bits
Type
Description
BOD
24
ro
Bonding option : Disoam
BOB
23
ro
Bonding option : Bond128
ID
22:20
ro
Chip ID[2:0]
DBP
19
ro
Disable Back Pressure
LM
18:16
ro
Led Mode[2:0]
FM
15:14
ro
Fiber Mode[1:0]
DAL
13
ro
Disable MAC address learning
EE
12
ro
Enable OAM engine
BP
11
ro
Bypass Reserved MAC address Filtering
DL
10
ro
Disable Link Pass Through
P0
9
ro
P0 MDI/MDIX
EA
8
ro
Enable Auto-Crossover
DF
7:6
ro
Disable Flow Control[1:0]
ANA
5:4
ro
Recommend Auto-Negotiation Ability for TP Port[1:0]
S
3:2
ro
Recommend Speed 10 for TP Port[1:0]
DH
1:0
ro
Recommend Duplex Half for TP/FX Port[1:0]
Data Sheet
64
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Interrupt Register
INT
Interrupt Register
Offset
10H
Reset Value
0000 0000H
)0 07 0) 58 52 89 .9
3 3 3 3 3 3 3 3
& ' ) ) ) 2 2 &2 ) ' 6 / ) ' 6 /
5HV
OKVFOKVFOKVFOKVFOKVFOKVFOKVFOKVFOKVFOKVFOKVFOKVFOKVFOKVFOKVFOKVF
Field
Bits
Type
Description
FMC
15
lhsc
Forwarding Mode Change
MTD
14
lhsc
Match Timer Done
MFF
13
lhsc
Match Frame Found
RUF
12
lhsc
Request User Frame transmitted.
ROF
11
lhsc
Request OAM Frame transmitted.
UVO
10
lhsc
Unknown Valid OAM Frame received
KVO
9
lhsc
Known Valid OAM Frame received
CO
8
lhsc
Counter Overflow(
0B
TBD, Normal
1B
TBD, Any counter defined in register 0x02~0x0e overflow
P1F
7
lhsc
Port 1 Flow Control Ability Change
0B
N, Normal
SC, Status change
1B
P1D
6
lhsc
Port 1 Duplex Change(
0B
N, Normal
1B
SC, Status change
P1S
5
lhsc
Port 1 Speed Change(
0B
N, Normal
1B
SC, Status change
P1L
4
lhsc
Port 1 Link Status Change
0B
N, Normal
SC, Status change
1B
P0F
3
lhsc
Port 0 Flow Control Ability Change
0B
N, Normal
1B
SC, Status change)
P0D
2
lhsc
Port 0 Duplex Change
0B
N, Normal
1B
SC, Status change
P0S
1
lhsc
Port 0 Speed Change
0B
N, Normal
1B
SC, Status change
Data Sheet
65
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Field
Bits
Type
Description
P0L
0
lhsc
Port 0 Link Status Change
0B
N, Normal
1B
SC, Status change
Interrupt Mask Register
INT_M
Interrupt Mask Register
Offset
11H
Reset Value
0000 0000H
)0 07 0) 58 52 89 .9
3 3 3 3 3 3 3 3
& ' &) ) ) 2 2 &2 ) ' 6 / ) ' 6 /
5HV
UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ
Field
Bits
Type
Description
FMC
15
rw
Forwarding Mode Change
0B
D, Disable
1B
E, Enable
MTD
14
rw
Match Timer Done
0B
D, Disable
1B
E, Enable
MFCF
13
rw
Match Frame Found
0B
D, Disable
E, Enable
1B
RUF
12
rw
Request User Frame transmitted
0B
D, Disable
1B
E, Enable
ROF
11
rw
Request OAM Frame transmitted
0B
D, Disable
1B
E, Enable
UVO
10
rw
Unknown Valid OAM Frame received
0B
D, Disable
E, Enable
1B
KVO
9
rw
Known Valid OAM Frame received
0B
D, Disable
1B
E, Enable
CO
8
rw
Counter Overflow
0B
D, Disable
1B
E, Enable
P1F
7
rw
Port 1 Flow Control Ability Change
0B
D, Disable
1B
E, Enable
Data Sheet
66
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Field
Bits
Type
Description
P1D
6
rw
Port 1 Duplex Change
0B
D, Disable
1B
E, Enable
P1S
5
rw
Port 1 Speed Change
0B
D, Disable
1B
E, Enable
P1L
4
rw
Port 1 Link Status Change
0B
D, Disable
1B
E, Enable
P0F
3
rw
Port 0 Flow Control Ability Change
0B
D, Disable
1B
E, Enable
P0D
2
rw
Port 0 Duplex Change
0B
D, Disable
1B
E, Enable
P0S
1
rw
Port 0 Speed Change
0B
D, Disable
1B
E, Enable
P0L
0
rw
Port 0 Link Status Change
0B
D, Disable
1B
E, Enable
Data Sheet
67
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Port Status Register
PSR
Port Status Register
Offset
12H
Reset Value
Real Time StatusH
5HV
/
%5
.
/
%5 %) %) )& ';
/6 )& ';
/6
. 6 6 6 6 UR
UR
UR
UR UR UR UR UR UR UR UR UR UR UR
Field
Bits
Type
Description
L1
15:14
ro
CBBRK_LENGTH of P1
00B L1, 0~60m
01B L2, 60~90m
10B L3, 90~130m
11B L4, 130~170m
BRK1
13
ro
CBBRK of P1
0B
N, Normal
1B
CB, Cable Broken
L0
12:11
ro
CBBRK_LENGTH of P0
00B L1, 0~60m
01B L2, 60~90m
10B L3, 90~130m
11B L4, 130~170m
BRK0
10
ro
CBBRK of P0
0B
N, Normal
1B
CB, Cable Broken
BFS1
9
ro
Buffer Full Status of Port 1
0B
N, Normal
1B
BF, Buffer Full
BFS0
8
ro
Buffer Full Status of Port 0
0B
N, Normal
BF, Buffer Full
1B
FC1
7
ro
Flow Control of Port 1
0B
D, Disable
1B
E, Enable
DX1
6
ro
Duplex of Port 1
0B
HD, Half Duplex
1B
FD, Full Duplex
S1
5
ro
Speed of Port 1
0B
10M, 10M
1B
100M, 100M
LS1
4
ro
Link Status of Port 1
0B
LD, Link Down
1B
LU, Link Up
Data Sheet
68
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Field
Bits
Type
Description
FC0
3
ro
Flow Control of Port 0
0B
D, Disable
1B
E, Enable
DX0
2
ro
Duplex of Port 0
0B
HD, Half Duplex
1B
FD, Full Duplex
S0
1
ro
Speed of Port 0
0B
10M, 10M
1B
100M, 100M
LS0
0
ro
Link Status of Port 0
0B
LD, Link Down
1B
LU, Link Up
EEPROM Register File Access Control
EE_RFAC
EEPROM Register File Access Control
Offset
13H
Reset Value
0000 4154H
&0'
5HV
$''
'$7$
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
CMD
31:29
rw
Command
000B
R, Read
001B
W, Write
> 001B
Res, Reserved
Res
28:22
rw
Reserved
0000000B Res, Reserved
ADD
21:16
rw
Address
00H to 3FH
DATA
15:0
rw
Data
Data Sheet
69
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
OAM Control Register
OAM_CR
OAM Control Register
Offset
14H
Reset Value
0000 0000H
5HV
)& )&
. 8 /% 7&
/%B+&
($ ($ (.
7& %7 0 & 2
UZ UZ UZ UZ
UZ
UZ UZ UZ UZ UZ
Field
Bits
Type
Description
FCK
12
rw
OAM FIFO Control for NTT TS-1000 frame
0B
SK, Store known OAM frame to FIFO (Default)
1B
N, Do not store
FCU
11
rw
OAM FIFO Control for unknown frame
0B
SU, Store unknown OAM frame to FIFO (Default)
1B
N, Do not store
LB
10
rw
Loop Back Test User Frame Transmit Control
0B
N, Normal (Default)
1B
REQ, Request to transmit an user frame which the SA is defined in
SMI register 15H and 16H. After the request user frame is
transmitted, this bit is cleared.
TC
9
rw
OAM frame Transmit control
0B
N, Normal (Default)
1B
REQ, Request to transmit an OAM frame which is defined in SMI
register 17H, 18H and 19H. After the request OAM frame is
transmitted, this bit is cleared.
LB_HC
8:5
rw
Loop Back Test User Frame Handling Control
0000B
D, Disable (Default)
NNNNB N, Find the first valid received Ethernet frame with its CRC. It
is the same with the most recently transmitted Ethernet frame
during NNNN*10ms After the frame is found or the timer count
done, the register will be cleared. And the search result will be
stored to Register 1DH Bit [1:0].
TC
4
rw
Discard all Ethernet frame from FX control
0B
N, Normal (Default)
1B
DE, Discard all Ethernet frame received from Port1
BT
3
rw
Block the traffic from TP to FX control
0B
N, Normal (Default)
1B
BT, Block the traffic from Port0 to Port1
EAM
2
rw
Enable Auto M field
NTT TS-1000 OAM Vendor ID/Model Number by embedded OAM engine
0B
E, Enable (Default)
1B
D, Disable
Data Sheet
70
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Field
Bits
Type
Description
EAC
1
rw
Enable Auto CRC
NTT TS-1000 OAM CRC by embedded OAM engin
0B
E, Enable (Default)
1B
D, Disable
EKO
0
rw
Enable Known OAM Frame Handling
NTT TS-1000 OAM Frame by embedded OAM engine
0B
E, Enable(Default)
1B
D, Disable
Source Address of Loop Back Test User Frame 0
SA_F_0
Source Address of Loop Back Test User
Frame 0
Offset
15H
Reset Value
0000 0000H
$GGUHVV
UZ
Field
Bits
Type
Description
Address
31:0
rw
Source Address[31:0]
Data Sheet
71
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Source Address of Loop Back Test User Frame 1
SA_F_1
Source Address of Loop Back Test User
Frame 1
Offset
16H
Reset Value
0000 0000H
5HV
%\WHB&RXQW
6RXUFHB$GG
UZ
UZ
Field
Bits
Type
Description
Byte_Count
26:16
rw
Total Byte Count of payload
Valid Ethernet frame : 46 byte ~ 1500 byte
Source_Add
15:0
rw
Source Address SA[47:32]
Transmit OAM Frame Register 0
TFR_0
Transmit OAM Frame Register 0
Offset
17H
Reset Value
0000 0000H
6B)LHOG
&B)LHOG
UZ
UZ
Field
Bits
Type
Description
S_Field
31:16
rw
S Field of OAM Frame
C_Field
15:0
rw
C Field of OAM Frame
Transmit OAM Frame Register 1
TFR_1
Transmit OAM Frame Register 1
Offset
18H
Reset Value
0000 0000H
0B)LHOG
UZ
Data Sheet
72
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Field
Bits
Type
Description
M_Field
31:0
rw
M Field Bit [31:0] of OAM Frame
Transmit OAM Frame Register 2
TFR_2
Transmit OAM Frame Register 2
Offset
19H
Reset Value
0000 0000H
5HV
&5&B)LHOG
0B)LHOG
UZ
UZ
Field
Bits
Type
Description
CRC_Field
23:16
rw
CRC Field of OAM Frame
M_Field
15:0
rw
M Field Bit [47:32] of OAM Frame
Data Sheet
73
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Received OAM Frame Register 0
RFR_0
Received OAM Frame Register 0
Offset
1AH
Reset Value
0000 0000H
6B)LHOG
&B)LHOG
UZ
UZ
Field
Bits
Type
Description
S_Field
31:16
rw
S Field of Received OAM Frame
C_Field
15:0
rw
C Field of Received OAM Fram
Received OAM Frame Register 1
RFR_1
Received OAM Frame Register 1
Offset
1BH
Reset Value
0000 0000H
5HV
0B)LHOG
UZ
Field
Bits
Type
Description
M_Field
31:16
rw
M Field Bit [31:0] of Received OAM Frame
Data Sheet
74
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Received OAM Frame Register 2
RFR_2
Received OAM Frame Register 0
Offset
1CH
Reset Value
0000 0000H
5HV
&5&B)LHOG
0B)LHOG
UZ
UZ
Field
Bits
Type
Description
CRC_Field
23:16
rw
CRC Field of Received OAM Frame
M_Field
15:0
rw
M Field Bit [47:32] of Received OAM Frame
OAM Frame Status Register
OAM_FSR
OAM Frame Status Register
Offset
1DH
Reset Value
0000 0000H
5HV
&5
&
),)2
7(
58 52
; )5 ) ) 8) .)
UZ
UZ
UZ UZ UZ UZ UZ UZ
Field
Bits
Type
Description
CRC
10
rw
Bad CRC OAM Received
0B
NB, No bad CRC OAM received
1B
B, Bad CRC OAM received
FIFO
9:6
rw
Embedded OAM FIFO Utilization
0000B
E, FIFO empty
1000B
25, 25%
1100B
50, 50%
1110B
75, 75%
1111B
F, FIFO full
TEX
5
rw
Status of Loop Back Test Timer
0B
NOT, Timer does not expire before a matched frame is found
1B
YES, Timer expires before a matched frame is found
FR
4
rw
Status of Loop Back Test User Frame
0B
NF, Matched frame is not found
1B
F, Matched frame is found
RUF
3
rw
Request User Frame transmitted
ROF
2
rw
Request OAM Frame transmitted
Data Sheet
75
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Registers Description
Field
Bits
Type
Description
UF
1
rw
Unknown Valid OAM Frame received
KF
0
rw
Known Valid OAM Frame received
Data Sheet
76
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Electrical Specification
5
Electrical Specification
DC and AC.
5.1
DC Characterization
Table 28
Electrical Absolute Maximum Rating
Parameter
Symbol
Values
Min.
Power Supply
Input Voltage
Output Voltage
Storage Temperature
Power Dissipation
ESD Rating
Table 29
VCC
VIN
Vout
TSTG
PD
ESD
Typ.
Unit
Note / Test Condition
Max.
-0.3
3.6
V
-0.3
VCC + 0.3 V
-0.3
VCC + 0.3 V
-55
155
°C
990
mW
2
KV
Recommended Operating Conditions
Parameter
Symbol
Power Supply1)
Vcc
Vcore
Vin
Tj
Core Power Supply
2)
Input Voltage
Junction Operating
Temperature
Values
Unit
Min.
Typ.
Max.
3.135
3.3
3.465
1.71
1.8
1.89
0
-
Vcc
V
0
25
115
°C
Note / Test Condition
V
1) VCC3O. VCCBIAS
2) VCCIK. VCCA2. VCCPLL
Table 30
DC Electrical Characteristics for 3.3 V Operation1)
Parameter
Symbol
Values
Min.
VIL
Input High Voltage
VIH
Output Low Volt a ge
VOL
Output High Voltage
VOH
Input Pull_up/down Resistance RI
Typ.
Input Low Voltage
2.0
0.4
50
Note / Test Condition
V
TTL
V
TTL
V
TTL
V
TTL
KΩ
VIL = 0 V or VIH = Vcc
Max.
0.8
2.4
Unit
1) Under VCC = 3.0 V~ 3.6 V, Tj = °C ~ 115 °C
5.2
AC Characterization
Power on Reset Timing, EEPROM Interface Timing, and SMI Timing.
Data Sheet
77
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Electrical Specification
Power on Reset Timing
Figure 5
Power on Reset Timing
Table 31
Power on Reset Tming
Parameter
Symbol
Values
Unit
Note / Test Condition
100
ms
TTL
100
ns
TTL
Unit
Note / Test Condition
Min.
RST Low Period
Start of Idle Pulse Width
tRST
tCONF
Typ.
Max.
EEPROM Interface Timing
Figure 6
EEPROM Interface Timing
Table 32
EEPROM Interface Timing
Parameter
Symbol
Values
Min.
EESK Period
EESK Low Period
EESK High Period
EEDI to EESK Rising Setup
Time
Data Sheet
tESK
tESKL
tESKH
tERDS
Typ.
Max.
5120
ns
2550
2570
ns
2550
2570
ns
10
ns
78
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Electrical Specification
Table 32
EEPROM Interface Timing (cont’d)
Parameter
Symbol
Values
Min.
EEDI to EESK Rising Hold
Time
tERDH
Typ.
Unit
Note / Test Condition
Max.
10
ns
EESK Falling to EEDO Output tEWDD
Delay Time
20
ns
SMI Timing
Figure 7
SMI Timing
Table 33
SMI Timing
Parameter
Symbol
Values
Min.
tCK
SDC Low Period
tCKL
SDC High Period
tCKH
SDIO to SDC rising setup time tSDS
SDC Period
Typ.
Unit
Note / Test Condition
Max.
20
ns
10
ns
10
ns
4
ns
2
ns
on read/write cycle
SDIO to SDC rising hold time
on read/write cycle
Data Sheet
tSDH
79
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Packaging
6
Packaging
128 PQFP Packaging for NINJA F/FX (ADM6992F/FX)
Figure 8
Data Sheet
128 pin QFP Outside Dimension
80
Rev. 1.02, 2005-11-25
NINJA F/FX
ADM6992F/FX
Packaging
Table 34
Dimensions for 128 PQFP Outside Dimension
Symbol
Millimeter (mm)
Inch
Min.
Typ.
Max.
Min.
Typ.
Max.
A
–
–
3.40
–
–
0.134
A1
0.25
–
0.15
0.001
–
–
A2
2.50
2.72
2.90
0.098
0.107
0.114
D
23.20 BSC.
0.913 BSC.
D1
20.00 BSC
0.787 BSC.
E
17.20 BSC
0.677 BSC.
E1
14.00 BSC
0.551 BSC.
R2
0.13
–
0.30
0.005
–
0.012
R1
0.13
–
–
0.005
–
–
Θ
0°
–
7°
0°
–
7°
Θ1
0°
–
–
0°
–
–
Alloy 42 L/F
Θ2,Θ3
7° REF
7° REF
Copper L/F
Θ2,Θ3
15° REF
15° REF
c
0.11
0.15
0.23
0.004
0.006
0.009
L
0.73
0.88
1.03
0.029
0.035
0.041
L1
1.60 Ref.
0.063 Ref.
S
0.20
–
–
b
0.17
0.20
0.27
0.008
–
–
0.007
0.008
0.011
128L
e
0.50 BSC.
0.020 BSC.
D2
18.50
0.728
E2
12.50
0.492
Tolerance of Form and Position
aaa
0.20
0.008
bbb
0.20
0.008
ccc
0.08
0.003
ddd
0.08
0.003
Note:
1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions
D1 and E1 do include mold mismatch and are determined at datum plane. -H2. Dimensions b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm. Total in
excess of the b dimension at maximum material condition. Dambar can not be located on the lower radius or
the lead foot.
Data Sheet
81
Rev. 1.02, 2005-11-25
www.infineon.com
Published by Infineon Technologies AG