ISSI IS61C12816-20T 128k x 16 high-speed cmos static ram Datasheet

ISSI
®
IS61C12816
128K x 16 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access time: 12, 15, and 20 ns
• CMOS low power operation
— 450 mW (typical) operating
— 250 µW (typical) standby
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial temperature available
• Available in 44-pin SOJ package and
44-pin TSOP(II)
DECEMBER 2000
DESCRIPTION
The ISSI IS61C12816 is a high-speed, 2,097,152-bit static
RAM organized as 131,072 words by 16 bits. It is fabricated
using ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design techniques, yields access times as fast as 12 ns with low power
consumption.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.A
data byte allows Upper Byte (UB) and Lower Byte (LB) access.
The IS61C12816 is packaged in the JEDEC standard 44-pin
400-mil SOJ and 44-pin TSOP(II).
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
1
ISSI
IS61C12816
PIN CONFIGURATIONS
44-Pin TSOP(II)
44-Pin SOJ
A15
1
44
A0
A14
2
43
A1
A13
3
42
A2
A12
4
41
OE
A11
5
40
UB
CE
6
39
LB
I/O0
7
38
I/O15
I/O1
8
37
I/O14
I/O2
9
36
I/O13
I/O3
10
35
I/O12
Vcc
11
34
GND
GND
12
33
Vcc
I/O4
13
32
I/O11
I/O5
14
31
I/O10
I/O6
15
30
I/O9
I/O7
16
29
I/O8
WE
17
28
NC
A10
18
27
A3
A9
19
26
A4
A8
20
25
A5
A7
21
24
A6
A16
22
23
NC
®
A15
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
A16
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
PIN DESCRIPTIONS
A0-A16
Address Inputs
LB
Lower-byte Control (I/O0-I/O7)
I/O0-I/O15
Data Inputs/Outputs
UB
Upper-byte Control (I/O8-I/O15)
CE
Chip Enable Input
NC
No Connection
OE
Output Enable Input
Vcc
Power
WE
Write Enable Input
GND
Ground
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
Write
2
WE
CE
OE
LB
UB
X
H
X
H
H
H
L
L
L
H
L
L
L
L
L
L
L
L
X
H
X
L
L
L
X
X
X
X
X
H
L
H
L
L
H
L
X
X
H
H
L
L
H
L
L
I/O PIN
I/O0-I/O7
I/O8-I/O15
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
Vcc Current
ISB1, ISB2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
ISSI
IS61C12816
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TSTG
PT
IOUT
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–65 to +150
1.5
20
Unit
V
°C
W
mA
®
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the
device at these or any other conditions above
those indicated in the operational sections of
this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
1
2
OPERATING RANGE
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
Speed
-12
-15, -20
-12
-15, -20
–40°C to +85°C
3
VCC
5V ± 5%
5V ± 10%
5V ± 5%
5V ± 10%
4
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
5
Min.
Max.
Unit
VCC = Min., IOH = –4.0 mA
2.4
—
V
VCC = Min., IOL = 8.0 mA
—
0.4
V
Input HIGH Voltage
2.2
VCC + 0.5
V
VIL
Input LOW Voltage(1)
–0.5
0.8
V
ILI
Input Leakage
GND - VIN - VCC
–2
2
µA
ILO
Output Leakage
GND - VOUT - VCC, Outputs Disabled
–2
2
µA
6
7
Notes:
1. VIL (min.) = –3.0V for pulse width less than 10 ns.
8
9
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-12
Min. Max.
-15
Min. Max.
-20
Min. Max.
Symbol
Parameter
Test Conditions
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max.,
IOUT = 0 mA, f = fMAX
Com.
Ind.
280
—
—
300
260
—
—
290
235
—
mA
255
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE • VIH , f = 0
Com.
Ind.
—
—
50
55
—
—
50
55
—
—
50
55
mA
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
CE • VCC – 0.2V,
VIN • VCC – 0.2V, or
VIN - 0.2V, f = 0
Com.
Ind.
—
—
10
15
—
—
10
15
—
—
10
15
mA
ISB2
Unit
10
11
12
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
3
ISSI
IS61C12816
®
CAPACITANCE(1)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
-12
Min. Max.
Parameter
-15
Min. Max.
-20
Min. Max.
Unit
tRC
tAA
tOHA
tACE
tDOE
tHZOE(2)
tLZOE(2)
tHZCE(2
tLZCE(2)
tBA
tHZB
Read Cycle Time
12
—
15
—
20
—
ns
Address Access Time
—
12
—
15
—
20
ns
Output Hold Time
3
—
3
—
4
—
ns
CE Access Time
—
12
—
15
—
20
ns
OE Access Time
—
6
—
7
—
9
ns
OE to High-Z Output
—
6
0
6
0
8
ns
OE to Low-Z Output
0
—
0
—
0
—
ns
CE to High-Z Output
0
6
0
6
0
8
ns
CE to Low-Z Output
3
—
3
—
3
—
ns
LB, UB Access Time
—
6
—
7
—
9
ns
LB, UB to High-Z Output
0
6
0
6
0
8
ns
tLZB
LB, UB to Low-Z Output
0
—
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1
4
255 Ω
5 pF
Including
jig and
scope
255 Ω
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
ISSI
IS61C12816
®
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
1
tRC
ADDRESS
2
tAA
tOHA
tOHA
DOUT
3
DATA VALID
PREVIOUS DATA VALID
4
READ CYCLE NO. 2(1,3)
5
tRC
ADDRESS
tAA
tOHA
6
OE
tHZOE
tDOE
7
tLZOE
CE
tACE
tHZCE
tLZCE
8
LB, UB
tBA
DOUT
HIGH-Z
tHZB
tLZB
DATA VALID
9
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
5
ISSI
IS61C12816
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
Parameter
-12
Min. Max.
-15
Min. Max.
-20
Min. Max.
Unit
tWC
Write Cycle Time
12
—
15
—
20
—
ns
tSCE
CE to Write End
9
—
10
—
12
—
ns
tAW
Address Setup Time
to Write End
9
—
10
—
12
—
ns
tHA
Address Hold from Write End
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
0
—
ns
tPWB
LB, UB Valid to End of Write
9
—
10
—
12
—
ns
tPWE
WE Pulse Width
9
—
10
—
12
—
ns
tSD
Data Setup to Write End
6
—
7
—
9
—
ns
Data Hold from Write End
0
—
0
—
0
—
ns
WE LOW to High-Z Output
—
6
—
7
—
9
ns
tLZWE(2) WE HIGH to Low-Z Output
3
—
3
—
3
—
ns
tHD
tHZWE
(2)
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input
pulse levels of 0 to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not
100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All
signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write.
The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that
terminates the write.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
ISSI
IS61C12816
®
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
1
tWC
2
ADDRESS
tHA
tSCE
3
CE
tPWB
LB, UB
4
tAW
tPWE
5
WE
tSA
6
WRITE(1)
tSD
tHD
7
DIN
tHZWE
DOUT
HIGH-Z
tLZWE
UNDEFINED
HIGH-Z
8
UNDEFINED
9
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
7
ISSI
IS61C12816
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part No.
Package
12
12
IS61C12816-12T
IS61C12816-12K
Plastic TSOP(II)
400-mil Plastic SOJ
15
15
IS61C12816-15T
IS61C12816-15K
Plastic TSOP(II)
400-mil Plastic SOJ
20
20
IS61C12816-20T
IS61C12816-20K
Plastic TSOP(II)
400-mil Plastic SOJ
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
12
12
IS61C12816-12TI
IS61C12816-12KI
Plastic TSOP(II)
400-mil Plastic SOJ
15
15
IS61C12816-15TI
IS61C12816-15KI
Plastic TSOP(II)
400-mil Plastic SOJ
20
20
IS61C12816-20TI
IS61C12816-20KI
Plastic TSOP(II)
400-mil Plastic SOJ
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
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