ISSI IS62LV256-70TI 32k x 8 low voltage static ram Datasheet

ISSI
®
IS62LV256
32K x 8 LOW VOLTAGE STATIC RAM
DECEMBER 2002
FEATURES
DESCRIPTION
• Access time: 45, 70 ns
• Low active power: 70 mW
• Low standby power
— 45 µW CMOS standby
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
The ISSI IS62LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using ISSI's
high-performance CMOS double-metal technology.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation is reduced to
10 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE) input and an active LOW Output Enable
(OE) input. The active LOW Write Enable (WE) controls both
writing and reading of the memory.
The IS62LV256 is pin compatible with other 32K x 8 SRAMs
in 300-mil SOJ, 330-mil plastic SOP, and TSOP (Type I Normal
and Reverse Bent) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
DECODER
256 X 1024
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
CE
OE
CONTROL
CIRCUIT
WE
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. K
12/11/02
1
ISSI
IS62LV256
®
PIN CONFIGURATION
28-Pin TSOP (Type I) (Normal Bent)
28-Pin SOJ and SOP
A14
1
28
VCC
A12
2
27
WE
A7
3
26
A13
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE
A2
8
21
A10
A1
9
20
CE
A0
10
19
I/O7
I/O0
11
18
I/O6
I/O1
12
17
I/O5
I/O2
13
16
I/O4
GND
14
15
I/O3
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
28-Pin TSOP (Type I) (Reverse Bent)
PIN DESCRIPTIONS
A0-A14
Address Inputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
Vcc
Power
GND
Ground
A3
A4
A5
A6
A7
A12
A14
VCC
WE
A13
A8
A9
A11
OE
7
6
5
4
3
2
1
28
27
26
25
24
23
22
8
9
10
11
12
13
14
15
16
17
18
19
20
21
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
2
WE
CE
OE
I/O Operation
Vcc Current
X
H
X
High-Z
ISB1, ISB2
H
H
L
L
L
L
H
L
X
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. K
12/11/02
ISSI
IS62LV256
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
TSTG
PT
IOUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +4.6
–55 to +125
–65 to +150
0.5
20
Unit
V
°C
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ± 5%
3.3V ± 5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = –1.0 mA
2.4
—
V
VOL
Output LOW Voltage
VCC = Min., IOL = 2.1 mA
—
0.4
V
VIH
Input HIGH Voltage
2.2
VCC + 0.3
V
–0.3
0.8
V
(1)
VIL
Input LOW Voltage
ILI
Input Leakage
GND ≤ VIN ≤ VCC
Com.
Ind.
–2
–5
2
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
Com.
Ind.
–2
–5
2
5
µA
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. K
12/11/02
3
ISSI
IS62LV256
®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-45 ns
Min.
Max.
-70 ns
Min.
Max.
Symbol
Parameter
Test Conditions
Unit
ICC1
Vcc Operating
Supply Current
VCC = Max., CE = VIL
IOUT = 0 mA, f = 0
Com.
Ind.
—
—
20
30
—
—
20
30
mA
ICC2
Vcc Dynamic Operating
Supply Current
VCC = Max., CE = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
35
45
—
—
30
40
mA
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
—
—
2
5
—
—
2
5
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
CE ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Com.
Ind.
—
—
90
200
—
—
90
200
µA
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
5
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc =3.3V.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. K
12/11/02
ISSI
IS62LV256
®
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
5 ns
1.5V
See Figures 1a and 1b
1213 Ω
1213 Ω
3.3V
3.3V
OUTPUT
OUTPUT
100 pF
Including
jig and
scope
1378 Ω
1378 Ω
5 pF
Including
jig and
scope
Figures 1b
Figures 1a
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-45 ns
Symbol
Parameter
-70 ns
Min.
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
45
—
70
—
ns
tAA
Address Access Time
—
45
—
70
ns
tOHA
Output Hold Time
2
—
2
—
ns
tACE
CE Access Time
—
45
—
70
ns
tDOE
OE Access Time
—
25
—
35
ns
tLZOE(2)
OE to Low-Z Output
0
—
0
—
ns
(2)
tHZOE
OE to High-Z Output
0
20
0
25
ns
(2)
tLZCE
CE to Low-Z Output
3
—
3
—
ns
tHZCE(2)
CE to High-Z Output
0
20
0
25
ns
tPU(3)
CE to Power-Up
0
—
0
—
ns
tPD
CE to Power-Down
—
30
—
50
ns
(3)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
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Rev. K
12/11/02
5
ISSI
IS62LV256
®
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
tRC
ADDRESS
tAA
tOHA
tOHA
DOUT
DATA VALID
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
tOHA
OE
tDOE
tLZOE
CE
tACE
tLZCE
DOUT
tHZCE
HIGH-Z
HIGH-Z
DATA VALID
tPU
SUPPLY
CURRENT
tHZOE
tPD
50%
ICC
50%
ISB
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. K
12/11/02
ISSI
IS62LV256
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2,3) (Over Operating Range)
Symbol
Parameter
-45 ns
Min.
Max.
-70 ns
Min.
Max.
Unit
tWC
Write Cycle Time
45
—
70
—
ns
tSCE
CE to Write End
35
—
60
—
ns
tAW
Address Setup Time to Write End
25
—
60
—
ns
tHA
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
tPWE
WE Pulse Width
25
—
55
—
ns
tSD
Data Setup to Write End
20
—
30
—
ns
tHD
Data Hold from Write End
0
—
0
—
ns
tSA
(4)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
4. Tested with OE HIGH.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. K
12/11/02
7
ISSI
IS62LV256
®
AC WAVEFORMS
WE Controlled)(1,2)
WRITE CYCLE NO. 1 (WE
tWC
ADDRESS
tHA
tSCE
CE
tAW
tPWE
WE
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA-IN VALID
CE Controlled)(1,2)
WRITE CYCLE NO. 2 (CE
tWC
ADDRESS
tSA
tHA
tSCE
CE
tAW
tPWE
WE
tHZWE
DOUT
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
tHD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
2. I/O will assume the High-Z state if OE • VIH.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. K
12/11/02
ISSI
IS62LV256
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
45
45
45
Order Part No.
IS62LV256-45J
IS62LV256-45U
IS62LV256-45T
Package
300-MIL PLASTIC SOJ
330-MIL SOP
TSOP (TYPE I NORMAL BENT)
70
70
70
IS62LV256-70U
IS62LV256-70T
IS62LV256-70RT
330-MIL SOP
TSOP (TYPE I NORMAL BENT)
TSOP (TYPE I REVERSE BENT)
Industrial Range: –40°C to +85°C
Speed (ns)
45
45
45
Order Part No.
IS62LV256-45JI
IS62LV256-45UI
IS62LV256-45TI
Package
300-MIL PLASTIC SOJ
330-mil SOP
TSOP (TYPE I NORMAL BENT)
70
70
70
IS62LV256-70UI
IS62LV256-70TI
IS62LV256-70RTI
330-mil SOP
TSOP (TYPE I NORMAL BENT)
TSOP (TYPE I REVERSE BENT)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. K
12/11/02
9
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