[ /Title (CD74 HC4016 ) /Subject (HighSpeed CMOS Logic Quad Bilat- CD74HC4016 Data sheet acquired from Harris Semiconductor SCHS199C High-Speed CMOS Logic Quad Bilateral Switch February 1998 - Revised August 2004 Features Description • Wide Analog-Input-Voltage Range . . . . . . . . . 0V to 10V The CD74HC4016 contains four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits. • Low “ON” Resistance - 45Ω (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC = 4.5V - 35Ω (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC = 6V - 30Ω (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . .1fcVCC = 9V Each switch has two input/output terminals (nY, nZ) and an active high enable input (nE). Current through the switch will not cause additional VCC current provided the analog voltage is maintained between VCC and GND. • Fast Switching and Propagation Delay Times • Low “OFF” Leakage Current • Built-In “Break-Before-Make” Switching Ordering Information • Suitable for Sample and Hold Applications • Wide Operating Temperature Range . . . -55oC to 125oC PART NUMBER • HC Types - 2V to 10V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V TEMP. RANGE (oC) PACKAGE CD74HC4016E -55 to 125 14 Ld PDIP CD74HC4016M -55 to 125 14 Ld SOIC CD74HC4016MT -55 to 125 14 Ld SOIC CD74HC4016M96 -55 to 125 14 Ld SOIC CD74HC4016PW -55 to 125 14 Ld TSSOP CD74HC4016PWR -55 to 125 14 Ld TSSOP NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD74HC4016 (PDIP, SOIC, TSSOP) TOP VIEW 1Y 1 14 VCC 1Z 2 13 1E 2Z 3 12 4E 2Y 4 11 4Y 2E 5 10 4Z 3E 6 9 3Z GND 7 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2004, Texas Instruments Incorporated 1 CD74HC4016 Functional Diagram 13 1 1E 2 5 4 2E 3 6 8 3E 9 12 11 4E 10 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z VCC = 14 GND = 7 TRUTH TABLE INPUT nE SWITCH L OFF H ON H = High Level Voltage L = Low Level Voltage Logic Diagram nY VCC nZ nE GND 2 CD74HC4016 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86 PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . 96 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 10V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) 9V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implie NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications 25oC TEST CONDITIONS PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) VIS (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS VIH - - 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V 4.5 - 45 180 - 225 - 270 Ω 6 - 35 160 - 200 - 240 Ω 9 - 30 135 - 170 - 205 Ω 4.5 - 85 320 - 400 - 480 Ω 6 - 55 240 - 300 - 360 Ω 9 - 35 170 - 215 - 255 Ω HC TYPES High Level Input Voltage Low Level Input Voltage “ON” Resistance IO = 1mA VIL RON Maximum “ON” Resistance Between Any Two Switches ∆RON Switch Off Leakage Current IIZ Logic Input Leakage Current II - VIH or VIL - VCC or GND VIL or VIH VCC or GND 4.5 - 10 - - - - - Ω 6 - 8.5 - - - - - Ω En = GND VCC or GND 6 - - ±0.1 - ±1 - ±1 µA 10 - - ±0.1 - ±1 - ±1 µA VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA 3 CD74HC4016 DC Electrical Specifications (Continued) 25oC TEST CONDITIONS PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) VIS (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS ICC VCC or GND VCC or GND 6 - - 2 - 20 - 40 µA 10 - - 16 - 160 - 320 µA Quiescent Device Current IO = 0mA Switching Specifications Input tr, tf = 6ns PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - 60 - 75 - 90 ns 4.5 - - 12 - 15 - 18 ns CL = 15pF 5 - 4 - - - - - ns CL = 50pF 6 - - 10 - 13 - 15 ns 9 - - 8 - 10 - 12 ns 2 - - 190 - 240 - 285 ns 4.5 - - 38 - 48 - 57 ns CL = 15pF 5 - 16 - - - - - ns CL = 50pF 6 - - 32 - 41 - 48 ns 9 - - 28 - 35 - 42 ns 2 - - 145 - 180 - 220 ns 4.5 - - 29 - 36 - 44 ns CL = 15pF 5 - 12 - - - - - ns CL = 50pF 6 - - 25 - 31 - 38 ns 9 - - 22 - 28 - 33 ns HC TYPES Propagation Delay, Switch In to Switch Out Propagation Delay, Switch Turn-On En to Out Propagation Delay, Switch Turn-Off En to Out tPZH, tPZL tPHZ, tPLZ Input Capacitance Power Dissipation Capacitance (Notes 2, 3) CL = 50pF CL = 50pF CI - - - - 10 - 10 - 10 pF CPD - 5 - 12 - - - - - pF NOTES: 2. CPD is used to determine the dynamic power consumption, per package. 3. PD = CPD VCC2 fi + Σ (CL + CS) VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, CS = switch capacitance, VCC = supply voltage. Analog Channel Specifications TA = 25oC PARAMETER TEST CONDITIONS VCC (V) CD74HC4016 UNITS Switch Frequency Response Bandwidth at -3dB Figure 3 Figure 6, Notes 4, 5 4.5 >200 MHz Crosstalk Between Any Two Switches, Figure 4 Figure 5, Notes 5, 6 4.5 TBE dB Total Harmonic Distortion 1kHz, VIS = 4VP-P Figure 7 4, 5 0.078 % 1kHz, VIS = 8VP-P Figure 7 9 0.018 % 4 CD74HC4016 Analog Channel Specifications TA = 25oC (Continued) PARAMETER TEST CONDITIONS Control to Switch Feedthrough Noise VCC (V) CD74HC4016 UNITS 4.5 TBE mV 9 TBE mV 4.5 -62 dB - 5 pF Figure 8 Switch “OFF” Signal Feedthrough, Figure 4 Figure 9, Notes 5, 6 Switch Input Capacitance, CS NOTES: 4. Adjust input level for 0dBm at output, f = 1MHz. 5. VIS is centered at VCC/2. 6. Adjust input for 0dBm at VIS. Typical Performance Curves 110 60 “ON” RESISTANCE, RON (Ω) “ON” RESISTANCE, RON (Ω) 100 90 VCC = 4.5V 80 70 60 50 VCC = 6V 40 30 20 50 45 VCC = 9V 40 35 30 25 20 15 10 5 10 0 0 0 1 2 3 4 4.5 INPUT SIGNAL VOLTAGE, VIS (V) 5 0 6 1 2 3 4 5 6 7 8 9 INPUT SIGNAL VOLTAGE, VIS (V) FIGURE 1. TYPICAL “ON” RESISTANCE vs INPUT SIGNAL VOLTAGE FIGURE 2. TYPICAL “ON” RESISTANCE vs INPUT SIGNAL VOLTAGE CROSSTALK, dB SWITCH OFF SIGNAL FEEDTHROUGH, dB 0 CHANNEL ON BANDWIDTH, dB 0 -1 CL = 10pF -2 VCC = 4.5V RL = 50Ω TA = 25oC PIN 4 TO 3 -3 CL = 10pF VCC = 9V RL = 50Ω TA = 25oC PIN 4 TO 3 -4 10K 100K 1M 10M FREQUENCY (f), Hz -40 -60 FIGURE 3. SWITCH FREQUENCY RESPONSE CL = 10pF VCC = 9V RL = 50Ω TA = 25oC PIN 4 TO 3 -80 -100 10K 100M CL = 10pF VCC = 4.5V RL = 50Ω TA = 25oC PIN 4 TO 3 -20 100K 1M 10M FREQUENCY (f), Hz 100M FIGURE 4. SWITCH-OFF SIGNAL FEEDTHROUGH AND CROSSTALK vs FREQUENCY 5 CD74HC4016 Analog Test Circuits VIS 0.1µF VCC VCC R SWITCH ON VIS VOS2 SWITCH ON VOS1 R R R VCC/2 C C dB METER VCC/2 VCC/2 fIS = 1MHz SINEWAVE R = 50Ω C = 10pF FIGURE 5. CROSSTALK BETWEEN TWO SWITCHES TEST CIRCUIT VCC VCC 0.1µF VIS SINE WAVE 10µF VIS VOS SWITCH ON 50Ω VIS VI = VIH SWITCH ON VOS 10kΩ 10pF dB METER VCC/2 50pF DISTORTION METER VCC/2 fIS = 1kHz TO 10kHz FIGURE 6. FREQUENCY RESPONSE TEST CIRCUIT E VCC 600Ω VCC/2 FIGURE 7. TOTAL HARMONIC DISTORTION TEST CIRCUIT SWITCH ALTERNATING ON AND OFF tr, tf ≤ 6ns fCONT = 1MHz 50% DUTY CYCLE VCC VP-P VOS 0.1µF 600Ω SCOPE VCC/2 FIGURE 8. CONTROL-TO-SWITCH FEEDTHROUGH NOISE TEST CIRCUIT VOS R R VCC/2 VCC/2 50pF fIS ≥ 1MHz SINEWAVE R = 50Ω C = 10pF SWITCH ON VIS VOS VC = VIL C dB METER FIGURE 9. SWITCH OFF SIGNAL FEEDTHROUGH Test Circuits and Waveforms 6ns tr = 6ns tf = 6ns VCC (HC) 3V (HCT) 90% 50% 10% INPUT 50% tTLH INVERTING OUTPUT 10% 50% 10% tPHZ OUTPUT HIGH TO OFF tPLH OUTPUTS ENABLED FIGURE 10. HC/HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPZH 90% 50% OUTPUTS DISABLED FIGURE 11. SWITCH TURN-ON AND TURN-OFF PROPAGATION DELAY TIMES 6 GND tPZL tPLZ OUTPUT LOW TO OFF 90% 50% 10% VCC (HC) 3V (HCT) 90% GND tTHL tPHL 6ns OUTPUT DISABLE OUTPUTS ENABLED PACKAGE OPTION ADDENDUM www.ti.com 20-Aug-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp CD74HC4016E ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC4016EE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC4016M96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4016M96E4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4016M96G4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4016MT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4016MTE4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4016MTG4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4016PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4016PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4016PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 20-Aug-2011 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC4016M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC4016MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4016M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HC4016MT SOIC D 14 250 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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