MOTOROLA MCM44E64 1mb r4000 secondary cache fast static ram module set Datasheet

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SEMICONDUCTOR TECHNICAL DATA
MCM4464 Series
1MB R4000 Secondary Cache
Fast Static RAM Module Set
Four MCM4464 modules comprise a full 1 MB of secondary cache for the
R4000 processor. Each module contains nine MCM6709J fast static RAMs for
a cache data size of 64K x 36. The tag portion, dependent on word line size,
contains either two MCM6709J or one MCM6706J fast static RAMs. All input signals, except A0 and WE are buffered using 74FBT2827 drivers with series 25 Ω
resistors.
The MCM6709J and MCM6706J are fabricated using high–performance silicon–gate BiCMOS technology. Static design eliminates the need for internal
clocks or timing strobes.
All 1MB R4000 supported secondary cache options are available.
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 10% Power Supply
All Inputs and Outputs are TTL Compatible
Three State Outputs
Fast Module Access Time: 12/15/17 ns
Zero Wait–State Operation
Unified or Split Seconday Cache Modules are Available (See Ordering
Information for Details)
Word Line Sizes of 4, 8, 16, and 32 are Available (See Ordering
Information for Details)
The Pin Compatible MCM44256 Series is also Available to Support a Full
4MB R4000 Secondary Cache.
Decoupling Capacitors are Used for Each Fast Static RAM and Buffer,
Along with Bulk Capacitance for Maximum Noise Immunity
High Quality Multi–Layer FR4 PWB with Separate Power and Ground
Planes
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
WE . . . . . . . . . . . . . . . . . . . . . . . Write Enable
DCS . . . . . . . . . . . . . . . . . . . . . . Data Enable
TCS . . . . . . . . . . . . . . . . . . . . . . . Tag Enable
OE . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ35 . . . . . . . . . Data Input / Output
TDQ0 – TDQ7 . . . TAG Data Input / Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
For proper operation of the device, VSS must
be connected to ground.
PIN ASSIGNMENT
80 LEAD SIMM — TOP VIEW
1
VCC
DQ1
2
4
3
VSS
DQ0
DQ3
6
5
DQ2
7
DQ4
9
DQ6
12
11
DQ7
DQ10
14
13
DQ9
DQ12
16
DQ14
18
15
17
DQ11
DQ13
DQ15
20
19
DQ17
22
21
VSS
DQ16
DQ19
24
23
DQ18
25
DQ20
27
DQ22
VCC
DQ5
8
VSS
DQ8
10
DQ21
26
VSS
DQ23
28
30
29
DQ25
32
31
DQ24
33
DQ26
DQ28
39
VSS
DQ31
41
DQ33
43
DQ35
45
WE
47
A1
DQ27
34
DQ29
36
35
DQ30
38
37
DQ32
40
DQ34
42
VSS
44
A0
46
A2
48
A4
50
49
A3
A6
52
51
A5
VCC
OE
54
53
55
VSS
DCS
A8
58
57
A7
59
A9
61
A11
63
A12
65
A14
67
NC
69
TCS
71
73
VSS
TDQ2
75
TDQ4
77
TDQ6
A10
VSS
A13
56
60
62
64
A15
66*
NC
68*
TDQ0
70
TDQ1
72
TDQ3
74
TDQ5
76
TDQ7
78
79
VCC
VSS 80
NOTE: Pin assignment is for unified cache. For
split cache option, Pin 68 becomes
Address MSB (A15) and Pin 66 is NC.
REV 1
8/94
 Motorola, Inc. 1994
MOTOROLA
FAST SRAM
MCM4464 SERIES
1
BLOCK DIAGRAM
64K x 36 CACHE
TCS
DCS
OE
A1
A2
A3 – A15
A0
DQ0 – DQ35
WE
TDQ0 – TDQ7
MCM6709J
E
G
A1
A2
A3 – A15
A0
DQ0 – DQ3
W
74FBT2827
DRIVER
36
8
TAG OPTIONS:
MCM6709J
A0
A1
A2
A3 – A15
E
W
G
DQ0 – DQ7
4 WORD
LINE SIZE
64K x 8
TAG
MCM6706J
A0
A1
A2 – A14
E
W
G
DQ0 – DQ7
8 WORD
LINE SIZE
32K x 8
TAG
(A0 NOT USED)
MCM6706J
A0
A1
A2 – A14
E
W
G
DQ0 – DQ7
16 WORD
LINE SIZE
16K x 8
TAG
(A0, A1 NOT USED)
MCM6706J
A0
A1
A2 – A14
E
W
G
DQ0 – DQ7
MCM4464 SERIES
2
32 WORD
LINE SIZE
8K x 8
TAG
(A0, A1, A2 NOT USED)
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating
Symbol
Value
Unit
VCC
– 0.5 to 7.0
V
Voltage Relative to VSS
Vin, Vout
– 0.5 to VCC + 0.5
V
Output Current (per I/O)
Iout
± 30
mA
Power Dissipation
PD
10
W
Temperature Under Bias
Tbias
– 10 to + 85
°C
Operating Temperature
TA
0 to + 70
°C
Tstg
– 25 to +125
°C
Power Supply Voltage
Storage Temperature
This devices on this module contain circuitry
to protect the inputs against damage due to
high static voltages or electric fields; however,
it is advised that normal precautions be taken
to avoid application of any voltage higher than
maximum rated voltages to these high–impedance circuits.
These BiCMOS memory circuits have been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The module is in a test
socket or mounted on a printed circuit board
and transverse air flow of at leat 500 linear feet
per minute is maintained.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage (Operating Voltage Range)
VCC
4.5
5.0
5.5
V
Input High Voltage
VIH
2.2
2.0
—
—
VCC + 0.3 V*
VCC + 0.3 V*
– 0.5**
—
0.8
(DQ0 – 35, TDQ0 – 7, WE, A0)
(A1 – A15, OE, DCS, TCS)
Input Low Voltage
VIL
V
V
* VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns)
** VIL (min) = – 3.0 V ac (pulse width ≤ 20 ns)
DC CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Ilkg(I)


± 10
µA
Output Leakage Current (G, xCS = VIH, Vout = 0 to VCC)
Ilkg(O)


± 10
µA
AC Supply Current (G, xCS = VIL, Iout = 0 mA)
ICCA


1850
mA
Output Low Voltage (IOL = + 8 mA)
VOL


0.4
V
OUtput High Voltage (IOH = – 4.0 mA)
VOH
2.4


V
Symbol
Typ
Max
Unit
Cin
Cin


110
10
pF
pF
Cout

10
pF
Note: Good decoupling of the local power supply should always be used.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance
Input/Output Capacitance
MOTOROLA FAST SRAM
(A0, WE)
(A1 – A15, OE, DCS, TCS)
MCM4464 SERIES
3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1A
READ CYCLE (See Notes 1 and 2)
–12
Parameter
–15
–17
Symbol
Min
Max
Min
Max
Min
Max
Unit
Address Access Time
tAVQV
—
12
—
15
—
17
ns
A0 Access Time
tA0QV
—
10
—
12
—
14
ns
Data/Tag Enable Access Time
tELQV
—
12
—
15
—
17
ns
Output Enable Access Time
tGLQV
—
9
—
10
—
11
ns
Output Hold from Address Change
tAXQX
4
—
4
—
4
—
ns
Output Hold from A0 Change
Notes
tA0XQX
4
—
4
—
4
—
ns
Data/Tag Enable Low to Output Active
tELQX
2
—
2
—
2
—
ns
3, 4
Data/Tag Enable High to Output High–Z
tEHQZ
1
9
1
10
1
11
ns
3, 4
Output Enable Low to Output Active
tGLQX
1
—
1
—
1
—
ns
3, 4
Output Enable High to Output High–Z
tGHQZ
1
9
NOTES:
1. WE is high for read cycle.
2. Enable timings are the same for both DCS and TCS.
3. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
4. This parameter is sampled and not 100% tested.
1
10
1
11
ns
3, 4
TIMING LIMITS
AC TEST LOADS
+5 V
480 Ω
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
OUTPUT
255 Ω
5 pF
VL = 1.5 V
Figure 1A
MCM4464 SERIES
4
Figure 1B
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never provides data later than that time.
MOTOROLA FAST SRAM
READ CYCLE 1 (See Note)
A1 – A15
tAVQV
A0
tA0VQV
tA0XQX
tAXQX
Q (DATA OUT)
PREVIOUS DATA VALID
DATA VALID
NOTE: Module is continuously selected (DCS or TCS = VIL, OE = VIL).
READ CYCLE 2 (See Note)
A1 – A15
tAVQV
A0
tA0VQV
tELQV
DCS/TCS
(DATA/TAG ENABLE)
tEHQZ
tELQX
OE (OUTPUT ENABLE)
tGLQV
tGHQZ
tGLQX
Q (DATA OUT)
DATA VALID
NOTE: Address valid prior to or coincident with DCS or TCS going low.
MOTOROLA FAST SRAM
MCM4464 SERIES
5
WRITE CYCLE 1 (WE Controlled, See Notes 1 and 2)
–12
Parameter
Address Setup Time
–15
–17
Symbol
Min
Max
Min
Max
Min
Max
Unit
tAVWL
5
—
5
—
5
—
ns
Notes
A0 Setup Time
tA0VWL
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVWH
12
—
15
—
17
—
ns
A0 Valid to End of Write
tA0VWH
10
—
12
—
14
—
ns
Write Pulse Width
tWLWH
tWLEH
7
—
10
—
12
—
ns
Data Valid to End of Write
tDVWH
6
—
7
—
8
—
ns
Data Hold Time
tWHDX
0
—
0
—
0
—
ns
Write Low to Data High–Z
tWLQZ
0
4
0
5
0
6
ns
3, 4
Write High to Output Active
tWHQX
3
—
3
—
3
—
ns
3, 4
Write Recovery Time
tWHAX
0
—
0
—
0
—
ns
Write Recovery Time – A0
tWHA0X
0
—
NOTES:
1. A write occurs during the overlap of DCS or TCS low and WE low.
2. Enable timings are the same for both DCS and TCS.
3. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
4. This parameter is sampled and not 100% tested.
0
—
0
—
ns
WRITE CYCLE 1
A1 – A15
tAVWH
tWHAX
A0
tA0VWH
tWHA0X
DCS/TCS
(DATA/TAG ENABLE)
tWLEH
tWLWH
WE (WRITE ENABLE)
tA0VWL
tAVWL
D (DATA IN)
tDVWH
tWHDX
DATA VALID
tWLQZ
Q (DATA OUT)
HIGH–Z
HIGH–Z
tWHQX
MCM4464 SERIES
6
MOTOROLA FAST SRAM
WRITE CYCLE 2 (DCS or TCS Controlled, See Notes 1 and 2)
–12
Parameter
Address Setup Time
–15
–17
Symbol
Min
Max
Min
Max
Min
Max
Unit
tAVEL
0
—
0
—
0
—
ns
A0 Setup Time
tA0VEL
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVEH
12
—
15
—
17
—
ns
A0 Valid to End of Write
tA0VEH
10
—
12
—
14
—
ns
Data/Tag Enable to End of Write
tELEH,
tELWH
12
—
15
—
17
—
ns
Data Valid to End of Write
tDVEH
6
—
7
—
8
—
ns
Data Hold Time
tEHDX
5
—
5
—
5
—
ns
Write Recovery Time
tEHAX
5
—
5
—
5
—
ns
Write Recovery Time – A0
tEHA0X
5
—
5
—
5
—
ns
Notes
NOTES:
1. A write occurs during the overlap of DCS or TCS low and WE low.
2. Enable timings are the same for both DCS and TCS.
WRITE CYCLE 2
A1 – A15
tAVEH
A0
tA0VEH
tELEH
DCS/TCS
(DATA/TAG ENABLE)
tEHAX
tA0VEL
tAVEL
tELWH
tEHA0X
WE (WRITE ENABLE)
tDVEH
D (DATA IN)
Q (DATA OUT)
MOTOROLA FAST SRAM
tEHDX
DATA VALID
HIGH–Z
MCM4464 SERIES
7
ORDERING INFORMATION
(Order by Full Part Number)
MCM
44X64
XX
XX
Motorola Memory Prefix
Speed (12 = 12 ns, 15 = 15 ns, 17 = 17 ns)
Part Number
Package (SG = Gold Pad SIMM)
Part Number
Unified/Split
Word Line Size
TAG Depth
MCM44A64
MCM44B64
MCM44C64
MCM44D64
Unified
Unified
Unified
Unified
4
8
16
32
64K
32K
16K
8K
MCM44E64
MCM44F64
MCM44G64
MCM44H64
Split
Split
Spllit
Split
4
8
16
32
64K
32K
16K
8K
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
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against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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MCM4464 SERIES
8
◊
CODELINE TO BE PLACED HERE
*MCM4464/D*
MCM4464/D
MOTOROLA FAST
SRAM
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