TI BQ4010LYMA-70N 8 k x 8 nonvolatile sram (5 v, 3.3 v) Datasheet

bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
8 k × 8 NONVOLATILE SRAM (5 V, 3.3 V)
FEATURES
•
•
•
•
•
•
•
GENERAL DESCRIPTION
Data Retention for at least 10 Years Without
Power
Automatic Write-Protection During
Power-up/Power-down Cycles
Conventional SRAM Operation, Including
Unlimited Write Cycles
Internal Isolation of Battery before Power
Application
5-V or 3.3-V Operation
Industry Standard 28-Pin DIP Pinout or
34-Pin LIFETIME LITHIUM™ SMD Pinout
Snap-on, Replaceable Lithium Battery
for SMD Device
(Device Number: bq401BATCAP)
The CMOS bq4010/Y/LY is a nonvolatile 65,536-bit
static RAM organized as 8,192 words by 8 bits. The
integral control circuitry and lithium energy source
provide reliable nonvolatility coupled with the
unlimited write cycles of standard SRAM.
The control circuitry constantly monitors the single
supply for an out-of-tolerance condition. When VCC
falls out of tolerance, the SRAM is unconditionally
write-protected to prevent an inadvertent write
operation.
At this time the integral energy source is switched on
to sustain the memory until after VCC returns valid.
The bq4010/Y/LY uses extremely low standby
current CMOS SRAMs, coupled with small lithium
coin cells to provide nonvolatility without long
write-cycle times and the write-cycle limitations
associated with EEPROM.
The bq4010/Y/LY requires no external circuitry and is
compatible with the industry-standard 64-Mb SRAM
pinout.
PIN CONNECTIONS
34−Pin
Lifetime Lithium Module
(TOP VIEW)
28−Pin DIP Module
(TOP VIEW)
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
NC/BW
NC
NC
NC/RST
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
NC
NC
NC
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2007, Texas Instruments Incorporated
bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
DEVICE INFORMATION
Table 1. TERMINAL FUNCTIONS
TERMINAL
DIP-28
LLM-34
VCC = 3.3 V
LLM-34
VCC = 5 V
I/O
A0
10
18
18
I
A1
9
19
19
I
A2
8
20
20
I
A3
7
21
21
I
A4
6
22
22
I
A5
5
23
23
I
A6
4
24
24
I
A7
3
25
25
I
A8
25
26
26
I
A9
24
27
27
I
A10
21
28
28
I
A11
23
29
29
I
A12
2
30
30
I
BW
-
1
-
O
Battery warning output (open drain)
CE
20
8
8
I
Chip-enable input
DQ0
11
16
16
I/O
DQ1
12
15
15
I/O
DQ2
13
14
14
I/O
DQ3
15
13
13
I/O
DQ4
16
12
12
I/O
DQ5
17
11
11
I/O
DQ6
18
10
10
I/O
DQ7
19
9
9
I/O
1
-
1
-
2
2
-
3
3
4
NAME
NC
2
-
-
26
-
-
-
31
31
-
32
32
-
33
33
34
34
DESCRIPTION
Address inputs
Data input/output
-
No connect
OE
22
7
7
I
Output enable input
RST
-
4
-
O
Power-up reset to system CPU output (open
drain)
VCC
28
5
5
I
Supply voltage input
VSS
14
17
17
-
Ground
WE
27
6
6
I
Write enable input
Submit Documentation Feedback
bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
FUNCTIONAL DESCRIPTION
When power is valid, the bq4010/Y/LY operates as a standard CMOS SRAM. During power-down and power-up
cycles, the bq4010/Y/LY acts as a nonvolatile memory, automatically protecting and preserving the memory
contents.
Power-down/power-up control circuitry constantly monitors the VCC supply for a power-fail-detect threshold VPFD.
The bq4010 monitors for VPFD = 4.62 V typical for use in 5-V systems with 5% supply tolerance. The bq4010Y
monitors for VPFD = 4.37 V typical for use in 5-V systems with 10% supply tolerance. The bq4010LY monitors for
VPFD = 2.90 V (typ) for use in 3.3-V systems.
When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All outputs become
high impedance, and all inputs are treated as don't care. If a valid access is in process at the time of power-fail
detection, the memory cycle continues to completion. If the memory cycle fails to terminate within time tWPT,
write-protection takes place.
As VCC falls past VPFD and approaches VSO, the control circuitry switches to the internal lithium backup supply,
which provides data retention until valid VCC is applied.
When VCC returns to a level above the internal backup cell voltage, the supply is switched back to VCC. After VCC
ramps above the VPFD threshold, write-protection continues for a time tCER (120 ms maximum in 5-V system,
85 ms maximum in 3.3-V system) to allow for processor stabilization. Normal memory operation may resume
after this time.
The internal coin cells used by the bq4010/Y/LY have an extremely long shelf life and provide data retention for
more than 10 years in the absence of system power.
As shipped from TI, the integral lithium cells of the MT-type module are electrically isolated from the memory.
(Self-discharge in this condition is approximately 0.5% per year.) Following the first application of VCC, this
isolation is broken, and the lithium backup provides data retention on subsequent power-downs. The LIFETIME
LITHIUM package option is shipped as two devices, which must be ordered separately.
Submit Documentation Feedback
3
bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
BLOCK DIAGRAM
LIFETIME LITHIUM
bq4010Y/LY
EBZ PACKAGE
DIP MODULE
bq4010/Y/LY
MA PACKAGE
OE
A0 - A12
8k×8
SRAM
Block
WE
DQ0 - DQ7
Power
CE
OE
A0 - A12
8k×8
SRAM
Block
WE
Power
CECON
Power-Fail
Control
+
DQ0 - DQ7
VCC
CE
CECON
Power-Fail
Control
Lithium
Cell
+
VCC
Lithium
Cell
bq401BATCAP
UDG-06075
4
Submit Documentation Feedback
bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of the datasheet, or see
the TI website at www.ti.com.
SELECTION GUIDE
DEVICE NUMBER
MAXIMUM
ACCESS
TIME (ns)
bq4010MA-70
NEGATIVE SUPPLY
TOLERANCE
(%)
NOMINAL INPUT
VOLTAGE
VCC (V)
TEMPERATURE
(°C)
MODULE
70
bq4010MA-85
85
bq4010MA-150
150
bq4010MA-200
200
bq4010YMA-70
70
bq4010YMA-85
85
bq4010YMA-150
150
bq4010YMA-200
200
bq4010YMA-70N
70
bq4010YMA-85N
85
bq4010YMA-150N
150
-5
0 to 70
DIP
5
-10
-40 to 85
bq4010YEBZ-70N
bq4010LYMA-70N
70
DIP
3.3
bq4010LYEBZ-70N
Lifetime Lithium
Lifetime Lithium
PART NUMBERING
PRODUCT
LINE
bq40
MEMORY
DENSITY
INPUT
VOLTAGE
(V)
NEGATIVE
SUPPLY
TOLERANCE
PACKAGE
SPEED
(ns)
TEMPERATURE
(°C)
10
L
Y
MA
70
N
10 = 8 k × 8
Blank = 5
Blank = 5%
MA = DIP
70
Blank = Commercial
11 = 32 k × 8
L= 3.3
Y = 10%
EBZ = SMD
85
( 0 to 70)
13 = 128 k × 8
100
14 = 256 k × 8
120
N = Industrial
15 = 512 k × 8
150
(-40 to 85)
16 = 1024 k × 8
200
17 = 2048 k × 8
Submit Documentation Feedback
5
bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
ABSOLUTE MAXIMUM RATINGS (1)
PARAMETER
VCC
CONDITION
VALUE
bq4010Y
–0.3 to 7.0
bq4010
–0.3 to 7.0
bq4010LY
–0.3 to 6.0
bq4010Y
–0.3 to 7.0
DC voltage applied on VCC relative to VSS
DC voltage applied on any pin excluding
VVT≤ VCC +0.3 V
VCC relative to VSS
VT
bq4010
bq4010LY
TOPR
Operating temperature
TSTG
Storage temperature
TBIAS
Temperature under bias
TSOLDER
Soldering temperature
(1)
UNIT
V
–0.3 to 7.0
V
–0.3 to (VCC + 0.3)
Commercial
0 to 70
Industrial
–40 to 85
Commercial
–10 to 70
Industrial
–40 to 85
Commercial
–10 to 70
Industrial
–40 to 85
For 10 seconds
°C
260
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the
Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended
periods of time may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (TA = TOPR)
MIN
TYP (1)
MAX
bq4010Y
4.50
5.00
5.50
bq4010
4.75
5.00
5.50
bq4010LY
3.00
3.30
3.60
0
0
0
VCC
Supply voltage
VSS
Supply voltage
VIL
Low-level input voltage
–0.3
0.8
VIH
High-level Input voltage
2.2
VCC + 0.3
(1)
UNIT
V
Typical values indicate operation at TA = 25°C.
CAPACITANCE (TA = 25°C, f = 1 MHz, VCC = 5.0 V or VCC = 3.3 V)
PARAMETER (1)
TEST CONDITIONS
CI/O
Input/output capacitance
Output voltage = 0 V
CIN
Input capacitance
Input voltage = 0 V
(1)
MIN
TYP
MAX
8
10
UNIT
pF
Ensured by design. Not production tested.
DC ELECTRICAL CHARACTERISTICS
TA = TOPR, VCC(min)≤ VCC≤ VCC(max)
PARAMETER
TEST CONDITIONS
TYP (1)
MAX
ILI
Input leakage current
VIN = VSS to VCC
±1
ILO
Output leakage current
CE = VIH or OE = VIH or WE = VIL
±1
VOH
Output high voltage
IOH = –1.0 mA
VOL
Output low voltage
IOL = 2.1 mA
ISB1
Standby supply current
CE = VIH
Standby supply current
CE≥ VCC– 0.2 V, 0V ≤ VIN≤ 0.2 V,
or VIN≥ VCC– 0.2
ISB2
bq4010
ICC
Operating supply current
bq4010Y
bq4010LY
(1)
6
MIN
Minimum cycle, duty = 100%,
CE = VIL, II/O = 0 mA
Typical values indicate operation at TA = 25°C, VCC = 5.0 V or VCC = 3.3 V.
Submit Documentation Feedback
2.4
0.4
UNIT
µA
V
1
2
µA
0.1
1
mA
35
30
mA
bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
DC ELECTRICAL CHARACTERISTICS (continued)
TA = TOPR, VCC(min)≤ VCC≤ VCC(max)
PARAMETER
VPFD
Power-fail-detect voltage
TEST CONDITIONS
MIN
TYP (1)
MAX
bq4010
4.55
4.62
4.75
bq4010Y
4.30
4.37
4.50
bq4010LY
2.85
2.90
2.95
bq4010
VSO
Supply switch-over voltage
UNIT
3
bq4010Y
3
bq4010LY
2.9
V
TRUTH TABLE
MODE
CE
WE
OE
I/O OPERATION
POWER
Not selected
H
X
X
High-Z
Standby
Output disable
L
H
H
High-Z
Active
Read
L
H
L
DOUT
Active
Write
L
L
H
DIN
Active
Submit Documentation Feedback
7
bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
AC TEST CONDITIONS
TEST CONDITIOINS
PARAMETER
Input pulse levels
Input rise and fall times
Input and output timing reference levels
5V
3.3 V
0 V to 3.0 V
0 V to VCC
5 ns
5 ns
1.5 V (unless otherwise specified)
50 %
See Figure 1 and Figure 2
See Figure 3 and Figure 4
Output load (including scope and jig)
+5V
+5V
1.9 kW
DOUT
1.9 kW
DOUT
1 kW
100 pF
1 kW
Figure 1. 5-V Output Load A
Figure 2. 5-V Output Load A
+ 3.3 V
+ 3.3 V
1.2 kW
DOUT
1.2 kW
DOUT
1.4 kW
30 pF
Figure 3. 3.3-V Output Load B
8
5 pF
Submit Documentation Feedback
1.4 kW
5 pF
Figure 4. 3.3-V Output Load B
bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
Table 2. READ CYCLE (TA = TOPR, VCC(min)≤ VCC≤ VCC(max))
PARAMETER
TEST CONDITIONS
-70
MIN
-85
MAX
70
MIN
-150
MAX
-200
MAX
MIN
tRC
Read cycle time
tAA
Address access time
tACE
Chip enable access time
tOE
Output enable to output valid
tCLZ
Chip enable to output in low Z
5
5
5
5
tOLZ
Output enable to output in low Z
0
0
0
0
tCHZ
Chip disable to output in high Z
tOHZ
Output disable to output in high Z
tOH
Output hold from address change
Output load A
Output load B
Output load A
85
MIN
150
MAX
200
70
85
150
200
70
85
150
200
35
45
70
90
ns
0
25
0
25
0
25
0
25
0
25
0
25
0
25
0
25
10
10
UNIT
10
10
tRC
Address
tAA
tOH
DOUT
Previous Data Valid
(1)
WE is held high for a read cycle.
(2)
Device is continuously selected: CE = OE = VIL.
Data Valid
Figure 5. Read Cycle No. 1 (Address Access) (1)(2)
tRC
CE
tACE
tCHZ
tCLZ
DOUT
High−Z
High−Z
(1)
WE is held high for a read cycle.
(2)
Device is continuously selected: CE = OE = VIL.
(3)
Address is valid prior to or coincident with CE transition low.
Figure 6. Read Cycle No. 2 (CE Access) (1)(2)(3)
Submit Documentation Feedback
9
bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
tRC
Address
tAA
OE
tOHZ
tOE
tOLZ
DOUT
Data Valid
High−Z
High−Z
(1)
WE is held high for a read cycle.
(2)
Device is continuously selected: CE = VIL.
Figure 7. Read Cycle No. 3 (OE Access)
10
Submit Documentation Feedback
(1)(2)
bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
Table 3. WRITE CYCLE (TA = TOPR, VCC(min)≤ VCC≤ VCC(max))
PARAMETER
-70
TEST CONDITIONS
MIN
-85
MAX
MIN
-150
MAX
MIN
-200
MAX
MIN
tWC
Write cycle time
70
85
150
200
tCW
Chip enable to end of write
See
(1)
65
75
100
150
tAW
Address valid to end of write
See
(1)
65
75
90
150
tAS
Address setup time
Measured from address valid to
beginning of write. (2)
0
0
0
0
tWP
Write pulse width
Measured from beginning of write to
end of write. (1)
55
65
90
130
tWR1
Write recovery time (write cycle 1)
Measured from WE going high to end
of write cycle. (3)
5
5
5
5
tWR2
Write recovery time (write cycle 2)
Measured from CE going high to end
of write cycle.(3)
15
15
15
15
tDW
Data valid to end of write
Measured to first low-to- high transition
of either CE or WE.
30
35
50
70
tDH1
Data hold time (write cycle 1)
Measured from WE going high to end
of write cycle. (4)
0
0
0
0
tDH2
Data hold time (write cycle 2)
Measured from CE going high to end
of write cycle.(4)
0
0
0
0
tWZ
Write enbled to output in high Z
I/O pins are in output state. (5)
0
tOW
Output active from end of write
(5)
5
(1)
(2)
(3)
(4)
(5)
I/O pins are in output state.
25
0
30
0
5
5
50
0
MAX
UNIT
ns
70
5
A write ends at the earlier transition of CE going high and WE going high.
A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition of CE going low and WE going low.
Either tWR1 or tWR2 must be met.
Either tDH1 or tDH2 must be met.
If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high-impedance state.
tWC
Address
tAW
tWR1
tCW
CE
tAS
tWP
WE
tDW
tDH1
Data−In Valid
DIN
tWZ
DOUT
tOW
Data Undefined (1)
High−Z
(1)
CE or WE must be high during address transition.
(2)
Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not
be applied.
(3)
If OE is high, the I/O pins remain in a state of high impedance.
Figure 8. Write Cycle No. 1 (WE-Controlled)
Submit Documentation Feedback
(1)(2)(3)
11
bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
tWC
Address
tAW
tAS
tWR2
tCW
CE
tWP
WE
tDW
DIN
tDH2
Data−in Valid
tWZ
DOUT
Data Undefined (1)
High−Z
(1)
CE or WE must be high during address transition.
(2)
Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not
be applied.
(3)
If OE is high, the I/O pins remain in a state of high impedance.
(4)
Either tWR1 or tWR2 must be met.
(5)
Either tDH1 or tDH2 must be met.
Figure 9. Write Cycle No. 2 (CE-Controlled)
12
Submit Documentation Feedback
(1)(2)(3)(4)(5)
bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
Table 4. 5-V POWER-DOWN/POWER-UP (TA = TOPR)
PARAMETER
tPF
VCC slew, 4.75 to 4.25 V
tFS
VCC slew, 4.25 to VSO
tPU
VCC slew, VSO to VPFD (max.)
tCER
tWPT
(1)
(2)
µs
µs
0
µs
40
TA =
Write-protect time
Delay after VCC slews down past VPFD before SRAM
is writeprotected.
UNIT
10
25°C (2)
Data-retention time in absence of VCC
MAX
300
Time during which SRAM is write-protected after
VCC passes VPFD on power-up.
Chip enable recovery time
tDR
MIN TYP (1)
TEST CONDITIONS
80
120
10
40
ms
years
100
150
µs
Typical values indicate operation at TA = 25°C, VCC = 5V.
Batteries are disconnected from circuit until after VCC is applied for the first time. tDR is the accumulated time in absence of power
beginning when power is first applied to the device.
tPF
VCC
4.75 V
VPFD
VPFD
4.25 V
VSO
VSO
tFS
tDR
tPU
tCER
tWPT
CE
Figure 10. 5-V Power-Down/Power-Up Timing
Submit Documentation Feedback
13
bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
Table 5. 3.3-V POWER-DOWN/POWER-UP (TA = TOPR)
PARAMETER
MIN TYP (1)
TEST CONDITIONS
tF
VCC slew, 3 V to 0 V
300
tR
VCC slew, VSO to VPFD (max)
100
tCER
Chip enable recovery time
Time during which SRAM is write-protected after
VCC passes VPFD on power-up.
10
tDR
Data-retention time in absence of VCC
TA = 25°C (2)
10
(1)
(2)
MAX
µs
85
ms
years
Typical values indicate operation at TA = 25°C, VCC = 3.3 V.
Batteries are disconnected from circuit until after VCC is applied for the first time. Data retention time (tDR) is the accumulated time in
absence of power beginning when power is first applied to the device.
VCC
3.0 V
VPFD(max)
VPFD
VSO
VSO
tR
tDR
tCER
tF
CE
Figure 11. 3.3-V Power-Down/Power-Up Timing
CAUTION:
Negative undershoots below the absolute maximum rating of -0.3 V in
battery-backup mode may affect data integrity.
14
UNIT
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ4010LYMA-70N
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4010MA-150
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4010MA-200
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4010MA-70
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4010MA-85
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4010YMA-150
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4010YMA-150N
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4010YMA-200
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4010YMA-70
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4010YMA-70N
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4010YMA-85
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4010YMA-85N
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2007
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDI061 – MAY 2001
MA (R-PDIP-T**)
PLASTIC DUAL-IN-LINE
28 PINS SHOWN
Millimeters
Inches
D
Dimension
Min.
Max.
Min.
Max.
A
0.365
0.375
9.27
A1
0.015
–
0.38
9.53
–
B
0.017
0.023
0.43
0.58
C
0.008
0.013
0.20
0.33
D/12 PIN
0.710
0.740
18.03
18.80
D/28 PIN
1.470
1.500
37.34
38.10
D/32 PIN
1.670
1.700
42.42
43.18
D/40 PIN
2.070
2.100
52.58
53.34
E
0.710
0.740
18.03
18.80
e
G
0.590
0.630
14.99
16.00
0.090
0.110
2.29
2.79
L
0.120
0.150
3.05
3.81
S/12 PIN
0.105
0.130
2.67
3.30
S
0.075
0.110
1.91
2.79
E
A
L
A1
C
B
e
S
G
4201975/A 03/01
NOTES: A. All linear dimensions are in inches (mm).
B. This drawing is subject to change without notice.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
•
1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Low Power
Wireless
www.ti.com/lpw
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
Similar pages