AZM AZ100LVEL16VTL+ Ecl/pecl oscillator gain stage & buffer with selectable enable Datasheet

AZ100LVEL16VT
ARIZONA MICROTEK, INC.
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
FEATURES
•
•
•
•
•
•
•
High Bandwidth for ≥1GHz
Similar Operation as
AZ100LVEL16VR except in
Disabled Condition: QHG is High
Operating Range of 3.0V to 5.5V
Minimizes External Components
Selectable Enable Polarity and
Threshold (CMOS/TTL or PECL)
Available in a 3x3 mm or 2x2 mm
MLP Package
S-Parameter (.s2p) and IBIS Model
Files Available on Arizona Microtek
Website
PACKAGE AVAILABILITY
PACKAGE
MARKING
NOTES
MLP 8 (2x2x0.75)
AZ100LVEL16VTNA
P9
<Date Code>
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL16VTNA+
P9+
<Date Code>
1,2
MLP 8 (2x2x0.75)
AZ100LVEL16VTNB
P8
<Date Code>
1,2,4
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL16VTNB+
P8+
<Date Code>
1,2
MLP 8 (2x2x0.75)
AZ100LVEL16VTNC
P2
<Date Code>
1,2,5
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL16VTNC+
P2+
<Date Code>
1,2
MLP 8 (2x2x0.75)
AZ100LVEL16VTND
P3
<Date Code>
1,2
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL16VTND+
P3+
<Date Code>
1,2
MLP 16 (3x3)
AZ100LVEL16VTL
MLP 16 (3x3) RoHS
Compliant / Lead (Pb)
Free
DIE
1
DESCRIPTION
PART NUMBER
2
3
4
5
6
AZ100LVEL16VTL+
AZ100LVEL16VTXP
AZM
16T
<Date Code>
AZM+
16T
<Date Code>
N/A
1,2,3
1,2
1,2
6
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
Date code format: “Y” or “YY” for year followed by “WW” for week.
Parts marked TNA for date codes prior to 4WW (prior to 2004).
Parts marked TNB for date codes prior to 4WW (prior to 2004).
Parts marked TNC for date codes prior to 4WW (prior to 2004).
Waffle Pack
The AZ100LVEL16VT is a specialized oscillator gain stage with high gain output buffer including an enable.
The QHG/Q̄HG outputs have a voltage gain several times greater than the Q/Q̄ outputs.
MLP 16, 3x3 mm Package (VTL) or DIE (VTX)
The AZ100LVEL16VTL and AZ100LVEL16VTX provide a selectable enable input (EN) that allows
continuous oscillator operation. See truth table for the Enable function. If Enable pull-up is desired in the
CMOS/TTL mode, an external ≤20 kΩ resistor connecting EN to VCC will override the on-chip pull-down resistor.
When disabled, the QHG output is forced high and the Q̄HG output is forced low. The AZ100LVEL16VTL/VTX also
provides a VBB and 470 Ω internal bias resistors from D to VBB and D̄ to VBB. The VBB pin can support 1.5 mA
sink/source current. Bypassing VBB to ground with a 0.01 μF capacitor is recommended.
The outputs Q and Q̄ each have a selectable on-chip pull-down current source. See truth table below for current
source functions. External resistors may also be used to increase pull-down current to a maximum total of 25 mA.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
AZ100LVEL16VT
Outputs QHG and Q̄HG each have an optional on-chip pull-down current source of 10 mA. When pad/pin VEEP is
left open (NC), the output current sources are disabled and the QHG /Q̄HG operate as standard PECL/ECL. When VEEP
is connected to VEE, the current sources are activated. The QHG /Q̄HG pull-down current can be decreased, by using a
resistor to connect VEEP to VEE. (See graph on page 5.)
MLP 8, 2x2 mm Package, VTNA, VTNB, VTNC & VTND Versions
All MLP 8, 2x2mm versions of the AZ100LVEL16VT provide an enable input that allows continuous oscillator
operation. VTNA and VTNB utilize an enable (EN
¯¯ ) that operates in the PECL/ECL mode. When the EN
¯¯ input is
LOW, the Q̄ and QHG/Q̄HG outputs follow the data inputs. When EN
¯¯ is HIGH, the QHG output is forced high and the
Q̄HG output is forced low. VTNC and VTND utilize an enable (EN) that operates in the CMOS/TTL mode. When the
EN input is HIGH, the Q̄ and QHG/Q̄HG outputs follow the data inputs. When EN is LOW, the QHG output is forced
high and the Q̄HG output is forced low.
For VTNA and VTND, both D and D̄ inputs are brought out and tied to the VBB pin through 470 Ω internal bias
resistors. In VTNB and VTNC, the D̄ input is internally tied directly to the VBB pin and the D input is tied to the VBB
pin through a 470 Ω internal bias resistor. Bypassing VBB to ground with a 0.01 μF capacitor is recommended.
All MLP 8, 2x2mm versions (VTNA, VTNB, VTNC & VTND) have the Q, QHG, and Q̄HG current sources
disabled, while the Q̄ output operates with a 4 mA current source to VEE.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
ENABLE TRUTH TABLE
MLP 16 (VTL) or DIE (VTX)
4mA EA.
Q
EN-SEL
EN
Q/Q̄ QHG
NC
PECL Low, VEE or NC
Data Data
NC
PECL High or VCC
Data High
VEE*
Data High
CMOS Low or VEE
VEE*
CMOS High or VCC
Data Data
Data High
VEE*
NC, no external pull-up
Data Data
VEE*
NC, with ≤20kΩ to VCC
*Connections to VCC or VEE must be less than 1Ω.
Q̄HG
Data
Low
Low
Data
Low
Data
D/D̄
Q/Q̄
QHG/Q̄HG
VBB
EN-SEL
EN/EN
¯¯
CS-SEL
VEEP
VEE
VCC
QHG
D
470 Ω
VBB
470 Ω
QHG
10mA EA.
EN
VEEP
VEE
EN-SEL
MLP 16 (VTL) or DIE (VTX)
FUNCTION
Data Inputs
Data Outputs
Data Outputs w/High Gain
Reference Voltage Output
Selects Enable Logic
Enable Input
Selects Q and Q̄ Current Source Magnitude
Optional QHG and Q̄HG Current Sources
Negative Supply
Positive Supply
April 2007 * REV - 9
CS-SEL
D
CMOS / TTL
THRESHOLD
PIN DESCRIPTION
PIN
Q
www.azmicrotek.com
2
CURRENT SOURCE TRUTH TABLE
MLP 16 (VTL) or DIE (VTX)
CS-SEL
Q
Q̄
NC
4mA typ.
4mA typ.
VEE*
8mA typ.
8mA typ.
VCC*
0
4mA typ.
*Connections to VCC or VEE must be less than 1Ω.
AZ100LVEL16VT
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
VCC
VI
VEE
VI
IOUT
TA
TSTG
Characteristic
PECL Power Supply (VEE = 0V)
PECL Input Voltage
(VEE = 0V)
ECL Power Supply
(VCC = 0V)
ECL Input Voltage
(VCC = 0V)
Output Current QHG/Q̄HG --- Continuous
--- Surge
Q/Q̄ --- Continuous
Output Current
--- Surge
Operating Temperature Range
Storage Temperature Range
Rating
0 to +8.0
0 to +6.0
-8.0 to 0
-6.0 to 0
50
100
25
50
-40 to +85
-65 to +150
Unit
Vdc
Vdc
Vdc
Vdc
mA
°C
°C
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)
Symbol
VOH
VOH
VOL
VIH
VIL
VBB
IIL
IIH
IEE
1.
2.
3.
4.
-40°C
Characteristic
2
Min
-1045
-1085
-1925
0°C
Max
-835
-880
-1555
Min
-995
-1025
-1900
25°C
Max
-835
-880
-1620
Min
-995
-1025
-1900
85°C
Max
-835
-880
-1620
Output HIGH Voltage
Output HIGH Voltage4
Output LOW Voltage2,4
Input HIGH Voltage
-880
-880
-1165
-880
D/D̄, EN/EN
¯¯ (PECL)
-1165
-1165
VCC
VCC
VEE+2000
VCC
EN (CMOS/TTL) VEE+2000
VEE+2000
Input LOW Voltage
-1475
-1810
-1475
-1810
-1475
D/D̄, EN/EN
¯¯ (PECL)
-1810
VEE + 800
VEE
VEE + 800
VEE
VEE + 800
EN (CMOS/TTL)
VEE
Reference Voltage
-1390
-1250
-1390
-1250
-1390
-1250
Input LOW Current EN3
0.5
0.5
0.5
Input HIGH Current EN3
150
150
150
Power Supply Current1
48
48
48
Specified with VEEP and CS-SEL open for VTL and VTX. Subtract 4mA for VTNA, VTNB, VTNC & VTND.
Specified with VEEP and CS-SEL connected to VEE for VTL and VTX only.
Specified with EN-SEL open for VTL and VTX only.
Specified with QHG/Q̄HG connected with 50 Ω to VCC –2V for VTNA, VTNB, VTNC & VTND.
Unit
Min
-995
-1025
-1900
Max
-835
-880
-1620
-1165
VEE+2000
-880
VCC
mV
-1810
VEE
-1390
0.5
-1475
VEE + 800
-1250
mV
150
54
mV
mV
mV
mV
μA
μA
mA
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)
Symbol
VOH
VOH
VOL
VIH
VIL
VBB
IIL
IIH
IEE
1.
2.
3.
4.
5.
-40°C
Characteristic
1,3
Min
2255
2215
1375
0°C
Max
2465
2420
1745
Min
2305
2275
1400
25°C
Max
2465
2420
1655
Min
2305
2275
1480
85°C
Max
2465
2420
1680
Output HIGH Voltage
Output HIGH Voltage1,5
Output LOW Voltage1,3,5
Input HIGH Voltage
2135
2420
2135
2420
2135
2420
D/D̄, EN/EN
¯¯ (PECL)1
EN (CMOS/TTL)
2000
VCC
2000
VCC
2000
VCC
Input LOW Voltage
1490
1825
1490
1825
1490
1825
D/D̄, EN/EN
¯¯ (PECL)1
EN (CMOS/TTL)
GND
800
GND
800
GND
800
Reference Voltage1
1910
2050
1910
2050
1910
2050
Input LOW Current EN4
0.5
0.5
0.5
Input HIGH Current EN4
150
150
150
Power Supply Current2
48
48
48
For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.
Specified with VEEP and CS-SEL open for VTL and VTX. Subtract 4mA for VTNA, VTNB, VTNC & VTND.
Specified with VEEP and CS-SEL connected to VEE for VTL and VTX only.
Specified with EN-SEL open for VTL and VTX only.
Specified with QHG/Q̄HG connected with 50 Ω to VCC –2V for VTNA, VTNB, VTNC & VTND.
April 2007 * REV - 9
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3
Unit
Min
2305
2275
1400
Max
2465
2420
1680
2135
2000
2420
VCC
mV
1490
GND
1910
0.5
1825
800
2050
mV
150
54
mV
mV
mV
mV
μA
μA
mA
AZ100LVEL16VT
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)
Symbol
VOH
VOH
VOL
VIH
VIL
VBB
IIL
IIH
IEE
1.
2.
3.
4.
5.
-40°C
Characteristic
Min
3955
3915
3075
1,3
0°C
Max
4165
4120
3445
Min
4005
3975
3100
25°C
Max
4165
4120
3338
Min
4005
3975
3100
85°C
Max
4165
4120
3338
Output HIGH Voltage
Output HIGH Voltage1,5
Output LOW Voltage1,3,5
Input HIGH Voltage
3835
4120
3835
4120
3835
4120
D/D̄, EN/EN
¯¯ (PECL)1
EN (CMOS/TTL)
2000
VCC
2000
VCC
2000
VCC
Input LOW Voltage
3190
3525
3190
3525
3190
3525
D/D̄, EN/EN
¯¯ (PECL)1
EN (CMOS/TTL)
GND
800
GND
800
GND
800
1
Reference Voltage
3610
3750
3610
3750
3610
3750
Input LOW Current EN4
0.5
0.5
0.5
Input HIGH Current EN4
150
150
150
Power Supply Current2
48
48
48
For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
Specified with VEEP and CS-SEL open for VTL and VTX. Subtract 4mA for VTNA, VTNB, VTNC & VTND.
Specified with VEEP and CS-SEL connected to VEE for VTL and VTX only.
Specified with EN-SEL open for VTL and VTX only.
Specified with QHG/Q̄HG connected with 50 Ω to VCC –2V for VTNA, VTNB, VTNC & VTND.
Unit
Min
4005
3975
3100
Max
4165
4120
3338
3835
2000
4120
VCC
mV
3190
GND
3610
0.5
3525
800
3750
mV
150
54
mV
mV
mV
mV
μA
μA
mA
AC Characteristics (VEE = -3.0V to -5.5V; VCC = GND or VEE = GND; VCC = +3.0V to +5.5V)
Symbol
Characteristic
Min
-40°C
Typ
Max
Min
0°C
Typ
Max
Min
25°C
Typ
EN
(VTL, VTX) ;
EN
EN
(VTL, VTX, VTNC, VTND)
(VTNA, VTNB)
Q
Q
Q HG
Q HG
TIMING DIAGRAM
April 2007 * REV - 9
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4
(PECL)
(CMOS)
Min
85°C
Typ
Max
Propagation Delay
tPLH / tPHL
400
400
400
430
(SE)
D to Q/Q̄ Outputs1
550
550
550
630
D to QHG/Q̄HG Outputs1 (SE)
tSKEW
Duty Cycle Skew2
(SE)
5
20
5
20
5
20
5
20
80
80
80
80
Minimum Input Swing3 DIFF
VPP
SE
160
160
160
160
Output Rise/Fall Times1
100
260
100
260
100
260
100
260
tr / t f
(20% - 80%)
1.
For VTL and VTX, output specified with VEEP and CS-SEL connected to VEE with an AC coupled 50Ω load. For VTNA, VTNB, VTNC &
VTND, AC coupled 50Ω on Q̄ to VCC –2V and DC coupled 50Ω to VCC –2V on QHG/Q̄HG.
2.
Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
3.
VPP is the minimum peak-to-peak input swing for which AC parameters guaranteed. The device has a voltage gain of ≈ 20 to Q/Q̄ outputs and a
voltage gain of ≈ 100 to QHG/Q̄HG outputs.
D
Max
Unit
ps
ps
mV
ps
AZ100LVEL16VT
AZ100LVEL16VTL
MLP 16
3x3 mm
Q
Q
NC
VCC
16
15
14
13
NC
1
12 CS-SEL
D
2
11
D
3
10 QHG
VBB
4
9
5
6
7
8
EN
NC
VEE
VEEP
QHG
EN-SEL
TOP VIEW
Bottom Center Pad may be left open or tied to VEE
ADJUSTABLE HIGH GAIN OUTPUT CURRENT
HIGH GAIN OUTPUT CURRENTS (mA)
12
10
8
6
4
2
0
0
20
40
60
80
100
120
140
VEEP TO VEE RESISTOR VALUE (OHMS)
April 2007 * REV - 9
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5
160
180
200
0
1.1
-15
1
-30
0.9
-45
0.8
-60
0.7
-75
0.6
Phase
1.2
S11 MAG 8mA
S11 MAG 4mA
S11 PHASE 8mA
S11 PHASE 4mA
Phase
Magnitude
AZ100LVEL16VT
S12 MAG 8mA
S12 MAG 4mA
S12 PHASE 8mA
S12 PHASE 4mA
-90
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
S11, D to Q̄
(50 Ω external AC, 4 & 8mA internal DC Load on Q̄)
195
0.04
170
0.03
145
Magnitude
0.05
0.02
120
0.01
95
0
70
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
S12, D to Q̄
(50 Ω external AC, 4 & 8mA internal DC Load on Q̄)
April 2007 * REV - 9
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6
45
195
40
165
35
135
30
105
25
75
20
45
15
15
10
-15
5
-45
0
S21 MAG 8mA
Phase
Magnitude
AZ100LVEL16VT
S21 MAG 4mA
S21 PHASE 8mA
S21 PHASE 4mA
-75
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
S21, D to Q̄
(50 Ω external AC, 4 & 8mA internal DC Load on Q̄)
225
0.8
200
0.7
175
Phase
Magnitude
0.9
0.6
150
0.5
125
0.4
100
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
Frequency (MHz)
S22, D to Q̄
(50 Ω external AC, 4 & 8mA internal DC Load on Q̄)
April 2007 * REV - 9
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7
1350
S22 MAG 8mA
S22 MAG 4mA
S22 PHASE 8mA
S22 PHASE 4mA
AZ100LVEL16VT
LOGIC DIAGRAMS AND PINOUTS FOR 2x2mm PACKAGE
4mA
MLP 8, 2x2mm
Q
V EE
D
Q HG
D
470 Ω
Q HG
470 Ω
D
1
D
2
8
Q
7
VCC
6
QHG
5
QHG
VEE
V BB
VBB 3
EN
EN
MLP 8, 2x2mm
AZ100LVEL16VTNA
4
TOP VIEW
4mA
Q
VEE
¯¯¯
EN operation follows PECL functionality.
D
QHG
See Timing
470Ω Diagram above.
QHG
VBB
EN
MLP 8, 2x2mm
Bottom
Pad is the VEE 8return.
AZ100LVEL16VTNB
D 1Center
Q
VBB
2
7
VCC
EN
3
6
QHG
5
QHG
VEE
MLP 8, 2x2mm
AZ100LVEL16VTNB
¯¯¯
EN operation follows PECL functionality.
See Timing Diagram above.
April 2007 * REV - 9
AZ100LVEL16VTNA
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8
4
TOP VIEW
Bottom Center Pad may be left open
or tied to VEE. Pin 4 is the VEE return.
AZ100LVEL16VT
LOGIC DIAGRAMS AND PINOUTS FOR 2x2mm PACKAGE
MLP 8, 2x2mm
4mA
Q
V EE
D
Q HG
470 Ω
Q HG
V BB
EN
D
1
AZ100LVEL16VTNC 8
VBB
2
7
VCC
EN
3
6
QHG
5
QHG
VEE
CMOS / TTL
THRESHOLD
4
MLP 8, 2x2mm
AZ100LVEL16VTNC
EN operation follows CMOS/TTL
functionality. See Timing Diagram above.
Bottom Center Pad may be left open
or tied to VEE. Pin 4 is the VEE return.
MLP 8, 2x2mm
4mA
Q
V EE
D
Q HG
D
Q HG
470
470
EN
1
D
2
EN
MLP 8, 2x2mm
AZ100LVEL16VTND
EN operation follows CMOS/TTL
functionality. See Timing Diagram above.
April 2007 * REV - 9
D
AZ100LVEL16VTND
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9
8
Q
7
VCC
6
QHG
5
QHG
VEE
VBB 3
V BB
CMOS / TTL
THRESHOLD
TOP VIEW
Q
4
TOP VIEW
Bottom Center Pad is the VEE return.
AZ100LVEL16VT
DIE PAD COORDINATES
AZ100LVEL16VT DIE:
LV16VT
A
B
L
M
J
DIE SIZE: 950u X 950u
DIE THICKNESS: 14 MILS
C
D
K
BOND PAD: 85u X 85u
E
F
I
H
G
PAD CENTER COORDINATES
NAME
A
B
C
D
E
F
G
H
I
J
K
L
M
April 2007 * REV - 9
PAD DESIGNATION
D
D̄
VBB
EN
VEE
VEEP
EN-SEL
Q̄HG
QHG
CS-SEL
VCC
Q
Q̄
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10
X(Microns)
-342.5
-342.5
-342.5
-342.5
-33.5
126.5
312.5
312.5
312.5
312.5
302.5
142.5
-140.5
Y(Microns)
312.5
144.5
-87.0
-255.0
-312.5
-312.5
-248.5
-98.5
51.5
201.5
342.5
342.5
342.5
AZ100LVEL16VT
PACKAGE DIAGRAM
MLP 8 2x2mm
Pin 1 Dot
By Marking
2.000±0.050
MLP 8
(2x2mm)
2.000±0.050
TOP VIEW
Pin 1 Identification
R0.100 TYP
0.350±0.050
0.250±0.050
0.500 bsc
8
1
7
6
2 1.200±0.050
exp. pad
3
5
4
0.600±0.050
exp. pad
BOTTOM VIEW
0.750±0.050
0.000-0.050
1
2
SIDE VIEW
Note: All dimensions are in mm
April 2007 * REV - 9
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11
3 4
0.203±0.025
1.750
Ref.
AZ100LVEL16VT
PACKAGE DIAGRAM
MLP 16 3X3mm
A
D
D
2
2.
INDEX AREA
(D/2 x E/2)
D2
D2/2
B
E2/2
E2
E
2
3x
E
e
2
e
2x
1
aaa C
2x
aaa C
TOP VIEW
bbb M C A B
5.
16 x b
L
3.
3x e
BOTTOM VIEW
ccc C
A3
A
4.
0.08 C
A1
SIDE
VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING
CONFORM TO ASME T14-1994.
2. THE TERMINAL #1 AND PAD
NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012.
3. DIMENSION b APPLIES TO METALLIZED
PAD AND IS MEASURED BETWEEN 0.25
AND 0.30 mm FROM PAD TIP.
4. COPLANARITY APPLIES TO THE
EXPOSED PADS AS WELL AS THE
TERMINALS.
5. INSIDE CORNERS OF METALLIZED PAD
MAY BE SQUARE OR ROUNDED
April 2007 * REV - 9
www.azmicrotek.com
12
C
SEATING
PLANE
MILLIMETERS
DIM
A
A1
A3
b
D
D2
E
E2
e
L
aaa
bbb
ccc
MIN
MAX
0.80
1.00
0.05
0.00
0.25 REF
0.18
0.30
3.10
2.90
1.95
0.25
3.10
2.90
1.95
0.25
0.50 BSC
0.30
0.50
0.25
0.10
0.10
AZ100LVEL16VT
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc.
makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona
Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license
rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
April 2007 * REV - 9
www.azmicrotek.com
13
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