Cypress CY2SSTV8575AC Differential clock buffer/driver Datasheet

TV8575
CY2SSTV8575
Differential Clock Buffer/Driver
Features
Operating frequency: 60 MHz to 170 MHz
Supports 266-MHz DDR SDRAM
5 differential outputs from 1 differential input
Spread Spectrum compatible
Low jitter (cycle-to-cycle): < 75
Very low skew: < 100 ps
Power Management Control input
High-impedance outputs when input clock < 20 MHz
2.5V operation
32-pin TQFP JEDEC MS-026 C
The CY2SSTV8575 is a high-performance, low-skew, low jitter
zero-delay buffer designed to distribute differential clocks in
high-speed applications. The CY2SSTV8575 generates five
differential pair clock outputs from one differential pair clock
input. In addition, the CY2SSTV8575 features differential
feedback clock outputs and inputs. This allows the
CY2SSTV8575 to be used as a zero-delay buffer.
When used as a zero-delay buffer in nested clock trees, the
CY2SSTV8575 locks onto the input reference and translates
with near zero delay to low-skew outputs.
Y2
Y2#
27
28
Y3
Y3#
Y4
Y4#
30
31
18
19
Y3
Y3#
FBOUT
FBOUT#
VDDQ
Y4
21
22
Y4#
VSS
PLL
Cypress Semiconductor Corporation
Document #: 38-07458 Rev. **
VSS
FBOUT#
FBOUT
VDDQ
TQFP-32
JEDEC MS-026 C
Y2
VSS
VDDQ
Y1
Y1#
VSS
AVSS
1 2 3 4 5 6 7 8
Y0#
Y0
FBIN
FBI
#
N
5
6
CY2SSTV8575
Y2#
•
3901 North First Street
•
San Jose
•
AVDD
CLK
CLK#
FBIN
24 23 22 21 20 19 18 17
VSS
VDDQ
9 10 11 12 13 14 15 16
15
16
VDDQ
8
Y0
Y0#
Y1
Y1#
VDDQ
AVDD
Test and
Powerdown
Logic
VDDQ
CK
CK#
OE
23
VSS
OE
2
1
12
11
FBIN#
Pin Configuration
Block Diagram
32 31 30 29 28 27 26 25
•
•
•
•
•
•
•
•
•
•
Description
CA 95134 • 408-943-2600
Revised October 30, 2002
CY2SSTV8575
Pin Description
Pin
Name
I/O
Type
Description
5,6
CLK, CLK#
I
LV Differential Input
Differential Clock Input
21
FBIN#
I
Differential Input
Feedback Clock Input. Connect to FBOUT# for accessing the
PLL.
22
FBIN
I
2,12,15,27,30
Y(0:4)
O
1,11,16,28,31
Y(0:4)#
O
18
FBOUT
O
19
FBOUT#
O
Feedback Clock Output. Connect to FBIN# for normal
operation. A bypass delay capacitor at this output will control
Input Reference/Output Clocks phase relationships.
23
OE
I
Output Enable Input. When OE is set HIGH, all Q and Q#
outputs are enabled and switch at the same frequency as CLK.
When set LOW, all Q and Q# outputs are disabled (Hi-Z) and
the PLL is powered down.
3,4,7,13,20,26,
29
VDDQ
2.5V Nominal
2.5V Power Supply for Output Clock Buffers
8
AVDD
2.5V Nominal
2.5V Power Supply for PLL. When AVDD is at GND, PLL is
bypassed and CLK is buffered directly to the device outputs.
During disable (OE = 0), the PLL is powered down.
10,14,17,24,25,
32
VSS
0.0V Ground
Common Ground
9
AVSS
0.0V Analog Ground
Analog Ground
Feedback Clock Input. Connect to FBOUT for accessing the
PLL.
Differential Outputs
Clock + Outputs
Clock – Outputs
Differential Outputs
Feedback Clock Output. Connect to FBIN for normal
operation. A bypass delay capacitor at this output will control
Input Reference/Output Clocks phase relationships.
Table 1. Function Table
INPUTS
OUTPUTS
PLL
AVDD
OE
CLK
CLK#
Y
Y#
FBOUT
FBOUT#
GND
H
L
H
L
H
L
H
BYPASSED/OFF
GND
H
H
L
H
L
H
L
BYPASSED/OFF
X
L
L
H
Z
Z
Z
Z
Off
X
L
H
L
Z
Z
Z
Z
OFF
2.5V
H
L
H
L
H
L
H
On
2.5V
H
H
L
H
L
H
L
On
2.5V
H
< 20 MHz
< 20 MHz
Hi-Z
Hi-Z
Hi-Z
HI-Z
Off
Document #: 38-07458 Rev. **
Page 2 of 8
CY2SSTV8575
Power Management Functions
Output enable/disable control of the CY2SSTV8575 allows the
user to implement power management schemes into the design. Outputs are three-stated/disabled when OE is asserted
low, see Table 1. The enabling and disabling of outputs is done
in such a manner to eliminate the possibility of the partial “runt”
clocks.
Zero Delay Buffer
When used as a zero delay buffer the CY2SSTV8575 will likely
be in a nested clock tree application. For these applications
the CY2SSTV8575 offers a differential clock input pair as a
PLL reference. The CY2SSTV8575 can lock onto the reference and translate with near zero delay to low-skew outputs.
For normal operation, the external feedback input, FBIN, is
connected to the feedback output, FBOUT. By connecting the
feedback output to the feedback input the propagation delay
through the device is eliminated. The PLL works to align the
output edge with tine input reference edge thus producing a
near zero delay. The reference frequency affects the static
phase offset of the PLL and thus the relative delay between
the inputs and outputs.
When AVDD is strapped LOW, the PLL is turned off and bypassed for test purposes.
= 2.5"
= 0.6" (Split to Terminator)
DDR _SDRAM
represents a capacitive
load
CLK
PLL
DDR SDRAM
120 Ohm
CLK#
VTR
Yx
120 Ohm
Yx#
VCP
FBIN
120 Ohm
DDR SDRAM
FBIN#
FBOUT
FBOUT#
0.3"
Figure 1. Clock Structure 1[1]
Note:
1. Output load capacitance for 2 DDR-SDRAM loads: 5 pF < CL < 8 pF.
Document #: 38-07458 Rev. **
Page 3 of 8
CY2SSTV8575
= 2.5"
= 0.6" (Split to Terminator)
DDR-SDRAM represents
a capacitive load
CLK
DDR-SDRAM
DDR-SDRAM
Stack
PLL
120 Ohm
DDR-SDRAM
CLK#
VTR
Yx
Yx#
120 Ohm
VCP
FBIN
120 Ohm
DDR-SDRAM
FBIN#
DDR-SDRAM
Stack
FBOUT
FBOUT#
DDR-SDRAM
0.3"
Figure 2. Clock Structure 2[2]
VDD
VDD
V DD/2
14 pF
OUT
VT R
60 O hm
R T = 120 O hm
OUT#
60 O hm
VCP
R eceiver
14 pF
V DD /2
Figure 3. Differential Signal Using Direct Termination Resistor
Governing Agencies
The following agencies provide specifications that apply to the CY2SSTV8575. The agency name and relevant specification is
listed below;
Agency Name
Specification
JEDEC
MS - 026-C
Note:
2. Output load capacitance for 4 DDR-SDRAM loads: 10 pF < CL < 16 pF.
Document #: 38-07458 Rev. **
Page 4 of 8
CY2SSTV8575
Absolute Maximum Ratings
proper operation, Vin and Vout should be constrained to the
range:
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For
VSS < (Vin or Vout) < VDD (VDDQ Voltage)
Parameter
Description
Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDDQ).
Conditions
Min.
Max.
Unit
Vdd
Supply Voltage
Non Functional
–0.3
3.5
VDC
VDD
Operating Voltage
Functional
2.38
2.63
VDC
Vin
Input Voltage
Relative to VSS
–0.3
2.63
VDC
Vout
Output Voltage
Relative to VSS
–0.3
2.63
VDC
Ts
Temperature, Storage
Non Functional
–65
150
°C
Ta
Temperature, Operating Ambient
Functional
0
+85
°C
ØJc
Dissipation, Junction to Case
Functional
–
18
°C/W
ØJa
Dissipation, Junction to Ambient
Functional
–
48
°C/W
ESDh
ESD Protection (Human Body Model)
–
2K
Volts
FIT
Failure in Time
–
10
ppm
Manufacturing test
DC Parameters (AVDD = VDDO = 2.5 ±5%, Temperature = 0°C to +85°C)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
–
–
0.75
V
1.75
–
–
V
–
–
0.6
V
Input Voltage,
Low[3]
VIH
Input Voltage,
High[3]
VOL
Output Voltage, Low
VDDQ = 2.375V, IOL = 12 mA
VOH
Output Voltage, High
VDDQ = 2.375V, IOH = –12 mA
1.7
–
–
V
IOL
Output Low Current
VDDQ = 2.375V, VOUT = 1.2V
26
35
–
mA
IOH
Output High Current
VDDQ = 2.375V, VOUT = 1V
28
–32
–
mA
ALL VDDQ, FO = 170 MHz
–
235
300
mA.
OE = 0 or CLK/CLK# < 20 MHz
–
–
100
µA.
–
–
4
pF
VIL
Current[4]
IDDQ
Dynamic Supply
IPDS
Power Down Current
Cin
Input pin capacitance
OE
Notes:
3. Unused inputs must be held high or low to prevent them from floating.
4. All outputs switching loaded with 16pF in 60Ω environment. See Figure 3.
Document #: 38-07458 Rev. **
Page 5 of 8
CY2SSTV8575
AC Input Parameters (AVDD = VDDQ = 2.5 ±5%, TA = 0°C to +85°C)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fin
Input Frequency
1.25
60
–
170
MHz
DTYC
Input Duty Cycle
AVDD, VDD = 2.5V±0.2V
40
–
60
%
Min.
Typ.
Max.
Unit
AC Output Parameters (AVDD= VDDQ = 2.5 ±5%, Temperature = 0°C to +85°C)[5,6]
Parameter
Description
Conditions
FOR
Output frequency range
AVDD, VDD = 2.5V±0.2V
60
–
170
MHz
tLOCK
Maximum PLL Lock Time
AVDD, VDD = 2.5V±0.2V
–
–
100
µS
60 MHz to 100 MHz
49.5
50
50.5
%
101 MHz to 170 MHz
49
–
51
%
20% to 80% of VOD
1
–
2
V/ns
20% to 80% of VOD
1
–
2
V/ns
All outputs equally loaded
–
–
100
ps
DTYC
[7]
Duty Cycle
TR
Rise Time
TF
Fall Time
Skew[9]
tSKEW
Any Output to Any Output
TPLH
Propagation Delay (Low to High)
CLK to Y
1.5
3.5
6
ns
TPHL
Propagation Delay (High to Low)
CLK to Y
1.5
3.5
6
ns
Output Disable
Time[8]
All outputs
–
3
–
ns
TOENB
Output Enable
Time[8]
All outputs
–
3
–
ns
TJIT(CC)
Cycle to Cycle Jitter
–100
–
–100
ps
TPHASE
Phase Error
–150
–
150
ps
TODIS
All outputs @ 66 MHz
TJIT(PHASE) Phase Error Jitter
All outputs @ 66 MHz
–50
–
50
ps
Notes:
5. Parameters are guaranteed by design and characterization. Not 100% tested in production.
6. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 50 kHz with a down
spread of –0.5%.
7. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWH/tC,
where the cycle time (tC) decreases as the frequency goes up.
8. Refers to transition of non-inverting output.
9. All differential input and output terminals are terminated with 120Ω/16 pF as shown in Figure 2.
Document #: 38-07458 Rev. **
Page 6 of 8
CY2SSTV8575
Ordering Information
Part Number
Package Type
Product Flow
CY2SSTV8575AC
32-pin TQFP
Commercial, 0° to 85°C
CY2SSTV8575ACT
32-pin TQFP -Tape & Reel
Commercial, 0° to 85°C
Package Drawing and Dimension
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51-85063-*B
All product and company names mentioned in this document may be the trademarks of their respective owners.
Document #: 38-07458 Rev. **
Page 7 of 8
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2SSTV8575
Document History Page
Document Title: CY2SSTV8575 Differential Clock Buffer/Driver
Document #: 38-07458
Rev.
ECN No.
Issue
Date
Orig. of
Change
**
120711
10/31/02
RGL
Document #: 38-07458 Rev. **
Description of Change
New Data Sheet
Page 8 of 8
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