Freescale MC145423DW Universal digital loop transceiver (udlt-3) Datasheet

Freescale Semiconductor, Inc.
MC145423
Errata
Universal Digital Loop Transceiver (UDLT-3)
Freescale Semiconductor, Inc...
Pin Selectable Master/Slave
Limited Distance Modem
This errata applies only to the following:
• Preproduction silicon marked “XCSAMPLE”.
• When setup to operate in UDLT1 mode triangle wave output.
Do to differences in device geometries and process, the LO1 and LO2 output impedance of the MC145423 is
higher during non-burst time than the MC145422 and MC145426 devices it replaces. To compensate for this
difference, the line interface requires a slight modification to optimize transmission performance.
The following partial schematic highlights these differences by placing the modifications inside dashed boxes.
These changes are:
• R19 changes from 110 Ω to 75 Ω.
• R21 changes from 110 Ω to 75 Ω.
• R23 is an added component with a value of 1400 Ω.
For all other device configurations, the original interface as found in the datasheet (page 25, BASIC DIGITAL
TELSET) can be used.
VDD
75 Ω
D1
R19
D2
LO1
1400 Ω
R23
VDD
75 Ω
D3
110 Ω
R21
D4
R22
See Note
LO2
1 µF
VDD
See Note
To
Battery
To
Twisted
Pair
LI
VDD
VREF
NOTE: Battery feed limiting resistors;
value up to user discretion.
For More Information On This Product,
Go to: www.freescale.com
Order Number: MC145423/D
Rev. 0, 8/24/00
MC145423
Product Preview
Universal Digital Loop
Transceiver (UDLT-3)
DW SUFFIX
SOIC
CASE 751F
Pin Selectable Master/Slave
Limited Distance Modem
The MC145423 is a CMOS integrated circuit designed to be one
of the major building blocks in digital subscriber voice/data
telephone systems and remote data acquisition and control systems.
The UDLT-3 incorporates into one device, all the functionality of
the MC145421 (ISDN UDLT-2 master), MC145425 (ISDN UDLT-2
slave), MC145422 (UDLT-1 master), and MC145426 (UDLT-1
slave).
Since these modes/functions are pin selectable, the MC145423
can be used in telephone switch line cards, as well as remote digital
telsets or data terminals.
• VDD = 4.5 V to 5.5 V
• 28-Pin SOIC and TSSOP Packages
• Protocol Independent
• Pin Controlled Power-Down
• LI Sensitivity Control in Master Mode
• 2.048 MHz Output in Slave Mode
UDLT-2 Features
• Synchronous Full Duplex 160 kbps Voice and Data
Communications in a 2B+2D Format for ISDN Compatibility
• Provides CCITT Basic Access Data Transfer Rate (2B+D) for
ISDNs on a Single Twisted Pair Up to 1 km on 26 AWG or
Larger Cable
UDLT-1 Features
• Pin Controlled Loopback
• Automatic Power-Up/Down (Slave)
• Full Duplex Synchronous 64 kbps Voice/Data Channel and Two
8 kbps Signaling Data Channels Over One 26 AWG Wire Pair Up
to 2 km
DT SUFFIX
TSSOP
CASE 1168
ORDERING INFORMATION
MC145423DW
MC145423DT
SOIC Package
TSSOP Package
MC145423
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
PIN ASSIGNMENT
VSS
Vref
LI
LB
VD
SDI1
SDI2
FRAME 10/20
SDCLK/8kHz
SDO1
SDO2
SE/(Mu/A)
PD
MOD TRI/SQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
MASTER/SLAVE
LO1
LO2
Rx
RE2/BCLK
RE1/CLKOUT
LI SENS/2.048 MHz
TDC-RDC/XTALout
CCI/XTALin
MSI/TONE
EN1-TE1
EN2-TE2/SIE/B1B2
Tx
28-PIN SOIC/TSSOP PACKAGES
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145423
BLOCK DIAGRAM
LO2
MODULATOR
SDCLK/8kHz
LO1
B1
B2
D1
D2
SDI2
D2 BUFFER
SE
LATCH
REGISTER
LOGIC
D1 BUFFER
SDI1
B2 BUFFER
RE2/
BCLK
B1 BUFFER
OSC
LB
SE
LATCH
MSI/TONE
RE1/
CLKOUT
SE/
(Mu/A)
CLKOUT
BCLK
Mu/A
EN2-TE2
MOD TRI/SQ
SEQUENCE
AND
CONTROL
FRAME 10/20
MASTER/
SLAVE
LI SENS/
2.048 MHz
PD
SE
LATCH
EN1-TE1
SE
LATCH
VD
BCLK
TDC/RDC
VD
CONTROL
D2 BUFFER
SDO2
D2
LI
Vref
DEMODULATOR
Freescale Semiconductor, Inc...
Rx
CCI/XTALIn
(TDC-RDC)/
XTALout
REGISTER
LOGIC
D1
D1 BUFFER
SDO1
B2
B2 BUFFER
B1
Tx
B1 BUFFER
EN2-TE2/
SIE
EN1-TE1
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145423
ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to VSS)
Rating
Symbol
Value
Unit
VDD – VSS
–0.5 to 6
V
Voltage, Any Pin to VSS
V
–0.5 to VDD + 0.5
V
DC Current, Any Pin (Excluding
VDD, VSS)
I
±10
mA
TA
–40 to 85
°C
Tstg
–85 to 150
°C
DC Supply Voltage
Operating Temperature
Freescale Semiconductor, Inc...
Storage Temperature
This device contains circuitry to protect
the inputs against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taken
to avoid applications of any voltage higher
than maximum rated voltages to this highimpedance circuit. For proper operation, it
is recommended that Vin and Vout be
constrained to the range VSS ≤ (Vin or Vout)
≤ VDD. Reliability of operation is enhanced
if unused inputs are tied to an appropriate
logic level (e.g., either VSS or VDD).
RECOMMENDED OPERATING CONDITIONS (TA = –40° to 85°C)
Parameter
DC Supply Voltage
Power Dissipation (PD = VDD)
VDD = 5 V
Power Dissipation (PD = VSS)
VDD = 5 V
Frame Rate
CCI CLK Frequency (MSI = 8 kHz)
UDLT-1 (CCI = 256 x MSI)
UDLT-2
Pins
Min
Typ
Max
Unit
VDD
VDD
4.5
—
5.5
V
—
—
80
mW
VDD
MSI
—
—
80
mW
7.9
8.0
8.1
kHz
—
—
2.048
8.192
—
8.29
—
—
0.25
64
128
—
—
4100
4100
16
—
4100
—
—
—
—
256
512
CCI
Frame Rate Slip*
Data Clock Rate (Master Mode)
UDLT-1
UDLT-2
TDC-RDC
SDCLK (UDLT-2 Only)
Modulation Baud Rate
UDLT-1
UDLT-2
MHz
%
kHz
LO1, LO2
kHz
kHz
* The slave’s crystal frequency divided by 512 (UDLT-1) or 1024 (UDLT-2), must equal the master’s MSI frequency ±0.25% for optimum
operation.
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145423
DIGITAL CHARACTERISTICS (VDD = 5 V ±10%, TA = –40° to 85°C, Unless Otherwise Stated)
Parameter
Input High Level
Input Low Level
Max
Unit
VDD x 0.7
—
—
V
V
µA
Input Current (Digital Pins)
—
VDD x 0.3
±1.0
Input Current LI
—
±100
µA
Input Capacitance
—
7.5
pF
Output High Current (Excluding Tx and PD)
VOH = VDD – 0.5 V
–1.6
—
mA
Output Current Low (Excluding Tx and PD)
VOL = 0.4V
1.6
—
mA
VOH = 2.5 V
VOH = VDD – 0.5 V
VOL = 0.4 V
VOL = 0.8 V
VOH = 2.5 V
VOH = VDD – 0.5 V
–3.4
–2.5
—
—
mA
2.5
3.5
—
—
mA
–90
–10
—
—
µA
VOL = 0.8 V
VOL = 0.4 V
100
60
—
—
µA
—
±10.0
µA
–450
—
µA
450
—
µA
Min
Max
Unit
4.5
6.0
Vp-p
Tx Output High Current
Freescale Semiconductor, Inc...
Min
Tx Output Low Current
PD Output High Current — Slave Mode*
PD Output Low Current — Slave Mode*
Tx, SDO1, SDO2, and VD Three-State Current
XTAL Output High Current
VOH = VDD – 0.5 V
VOL = 0.4 V
XTAL Output Low Current
* To overdrive PD from a low level to 3.5 V, or a high level to 1.5 V requires a minimum of ±800 µA drive capability.
ANALOG CHARACTERISTICS (VDD = 5 V ±10%, TA = –40° to 85°C)
Parameter
Modulation Differential Amplitude (RL = 440 Ω)
LO1 to LO2
Modulation Differential Offset
0
40
mV
Vref Voltage, Typically 9/20 x (VDD – VSS)
PCM Tone Level
2.0
2.5
V
–22
–18
dBm
Demodulator Input Amplitude*
0.05
2.5
Vpeak
50
300
kΩ
Demodulator Input Impedance (LI to Vref)
* The input level into the demodulator to reliably demodulate incoming bursts. Input referenced to Vref.
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145423
MASTER SWITCHING CHARACTERISTICS (VDD = 5 V ±10%, TA = –40° to 85°C, CL = 50 pF)
Figure
No.
Parameter
Symbol
Min
Max
Unit
tr
tf
—
2
µs
—
2
µs
90
—
tw2(H,L)
tPLH,
tPHL
45
55
—
—
50
50
tsu3
th5
20
—
ns
50
—
ns
30
—
ns
Rx to TDC-RDC Hold Time
tsu5
th1
30
—
ns
SDI1, SDI2 to MSI Setup Time
tsu2
30
—
ns
SDI1, SDI2 to MSI Hold Time
th2
30
—
ns
tP1LH
—
50
ns
TE Rising Edge to First Tx Data Bit Valid
tsu6
—
50
ns
TDC-RDC Rising Edge to Tx Data Bits 2 – 8 Valid
tsu7
tdly
—
50
ns
—
70
ns
SDCLK Rising Edge to SDO1, SDO2 Bit Valid
(UDLT-2 Only)
tsu8
—
135
ns
SDI1, SDI2 Data Setup (Data Valid Before SDCLK
Falling Edge) (UDLT-2 Only)
tsu9
50
—
ns
SDI1, SDI2 Data Hold (Data Valid After SDCLK
Falling Edge) (UDLT-2 Only)
th3
20
—
ns
tsu10
50
—
ns
th4
20
—
ns
Input Rise Time: All Digital Inputs
Input Fall Time: All Digital Inputs
Pulse Width:
TDC, RDC, RE1, RE2, MSI, SDCLK (UDLT-2)
CCI Duty Cycle
Propagation Delay:
MSI to SDO1, SDO2, VD (PD = VDD)
TDC to Tx
Freescale Semiconductor, Inc...
MSI, TE1, TE2, RE1, RE2 to TDC-RDC Setup Time
TDC-RDC to MSI, TE1, TE2, RE1, RE2, Hold Time
Rx to TDC-RDC Setup Time
MSI Rising Edge to First SDCLK Falling Edge
(UDLT-2 Only)
TE1,TE2 Falling Edge to Tx High Impedance
PD, LB Setup (PD, LB Valid Before MSI Rising Edge)
PD, LB Hold (PD, LB Valid After MSI Rising Edge)
tp
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
ns
%
ns
Freescale Semiconductor, Inc.
MC145423
SLAVE SWITCHING CHARACTERISTICS (VDD = 5 V ±10%, TA = –40° to 85°C, CL = 50 pF)
Figure
No.
Freescale Semiconductor, Inc...
Parameter
Symbol
Min
Max
Unit
Input Rise Time: All Digital Inputs
tr
—
2
µs
Input Fall Time: All Digital Inputs
tf
—
2
µs
Clock Output Pulse Width: BCLK
tw(H,L)
3.66
4.15
µs
Crystal Frequency
fx1
4.086
4.1
MHz
Propagation Delay Times:
EN1, EN2, TE1 Rising to BCLK (TONE = VDD)
EN1, EN2, TE1 Rising to BCLK (TONE = VSS)
BCLK to EN1, EN2, TE1 Falling
RE1 Rising to BCLK (UDLT-1)
RE1 Falling to BCLK (TONE = VDD) (UDLT-1)
RE1 Falling to BCLK (TONE = VSS) (UDLT-1)
BCLK to Tx
TE1,TE2 to SDO1, SDO2
tp1
tp1
tp2
tp3
tp4
tp4
tp5
tp6
–50
300
—
—
–50
300
—
—
175
400
20
20
50
400
50
50
Rx to BCLK Setup Time
tsu5
30
—
ns
Rx to BCLK Hold Time
th1
30
—
ns
SDI1, SDI2 to TE Setup Time
tsu6
30
—
ns
SDI1, SDI2 to TE Hold Time
th2
30
—
ns
EN1, EN2 Rising Edge to DCLK Rising Edge (UDLT-2)
tPHL
—
±30
ns
EN1, EN2 Rising Edge to First Tx Data Bit Valid
tdly1
—
30
ns
BCLK Rising Edge to Tx Data Bits 2 – 8 Valid
tsu7
—
–40
ns
DCLK Pulse Width High (UDLT-2)
tw(H)
31
31.5
µs
DCLK Pulse Width Low (UDLT-2)
tw(L)
31
31.5
µs
DCLK Rising Edge to SDO1, SDO2 (UDLT-2)
tdly2
—
30
ns
SDI1, SDI2 Setup (SDI1, SDI2 Valid Before DCLK
Falling Edge) (UDLT-2)
tsu9
10
—
ns
SDI1, SDI2 Hold (SDI1, SDI2 Valid After DCLK
Falling Edge) (UDLT-2)
th3
—
30
ns
tdly3
—
30
ns
Symbol
Min
Max
Unit
th
10
—
ns
tdly1
tdly2
—
40
ns
30
—
ns
tsu
25
—
ns
ns
EN1, TE1 Rising Edge to VD Valid
SE PIN TIMING
Figure
No.
Parameter
LB, PD Hold
(LB, PD Valid After SE Falling Edge)
SDO1, SDO2, VD High Impedance After SE Falling Edge
SDO1, SDO2, VD Valid After SE Rising Edge
LB, PD Setup
(LB, PD Valid Before SE Rising Edge)
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
VD
SDO1,
SDO2
SDI1,
SDI2
Rx
Tx
RE1
TE1
BCLK
th2
tdly3
tp6
tsu6
B11
tp1
B12
B13
tp5
B15
DON’T CARE
B14
B16
B17
tp2
B18
VALID
B11
B12
B13
tsu5
HIGH IMPEDANCE
tp3
tw(L)
B14
tw(H)
Freescale Semiconductor, Inc...
th1
B15
B16
B17
B18
tp4
MC145423
Freescale Semiconductor, Inc.
Figure 1. UDLT-1 Slave Timing Nonsynchronous
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
VD
SDO1,
SDO2
SDI1,
SDI2
B11
Rx
th2
tdly3
tp6
tsu6
B11
tp1
Tx
RE1
TE1
BCLK
B12
B12
B13
tsu5
B13
tp5
B14
B14
th1
B15
B15
B16
B16
B17
B17
tp2
B18
B18
VALID
HIGH IMPEDANCE
tp3
tw(L)
DON’T CARE
tw(H)
Freescale Semiconductor, Inc...
tp4
Freescale Semiconductor, Inc.
Figure 2. UDLT-1 Slave Timing Synchronous
MC145423
Figure 3. UDLT-2 Slave Timing
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
VD
SDI1,
SDI2
SDO1,
SDO2
SDCLK
B11
Rx
tdly3
tPHL
B11
tp1
Tx
EN2
EN1
BCLK
B12
B12
tsu9
th1
B13
tsu5
B13
tp5
B1
B14
B14
B1
B15
B15
th3
B16
B16
B17
B17
tp2
tdly1
tp1
B18
B18
VALID
tdly2
B21
B21
tw(H)
B22
B22
tw(H)
tsu7
B23
B23
B24
B24
B2
B2
tw(L)
Freescale Semiconductor, Inc...
B25
B25
B26
B26
tw(L)
B27
B27
B28
B28
B1
B11
B11
MC145423
Freescale Semiconductor, Inc.
Figure 4. UDLT-1 Master Timing
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
VD
SDI1,
SDI2
tsu2
SDO1,
SDO2
Rx
RE1
Tx
TE1
CCI,
TDC/
RDC
MSI
VALID
tPLH/tPHL
th2
B11
tPLH/tPHL
DON’T CARE
th5
tPLH/tPHL
tsu3
tp
tsu3
B12
th5
B13
B11
tsu5
B14
tp
tsu3
B12
B15
VALID
B17
B14
DON’T CARE
VALID
B13
th1
B16
B15
B18
tw2
B16
tw2
Freescale Semiconductor, Inc...
B17
B18
HIGH IMPEDANCE
VALID
DON’T CARE
th5
Freescale Semiconductor, Inc.
MC145423
Figure 5. UDLT-2 Master Timing
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
PD/LB
VD
SDI1,
SDI2
SDO1,
SDO2
SDCLK
Rx
RE1/
RE2
Tx
TE1/TE2
TDC/RDC
MSI
VALID
B1
tP1LH
th5
tsu10
th4
tPLH/tPHL
DON’T CARE
tPLH
dly3 /tPHL
th5
tp
tsu9
B11
B1
tsu6
th5
B1
th3
B12
tsu3
tsu5
B13
B11
tp
B14
th5
DON’T CARE
tsu8
VALID
B13
B16
DON’T CARE
B12
th1
B15
B14
B17
tw2
tsu7
B15
B18
tw2
B16
tdly
tw2
B2
B2
Freescale Semiconductor, Inc...
B17
B18
tw2
DON’T CARE
MC145423
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
SE
th
LB, PD
tsu
PREVIOUS STATE
INTERNALLY LATCHED
SDO1, SDO2, VD
tdly1
Freescale Semiconductor, Inc...
Figure 6. SE Pin Timing
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
tdly2
MC145423
Freescale Semiconductor, Inc.
MC145423
SOIC PACKAGE PINOUT COMPARISON
UDLT-3 PINOUT VERSUS MC145421DW/22DW/25DW/26DW
(UDLT-1/UDLT-2 MASTER/SLAVE) PINOUT
Freescale Semiconductor, Inc...
UDLT-3
MC145423
UDLT-1 Master
MC145422
UDLT-1 Slave
MC145426
UDLT-2 Master
MC145421
UDLT-2 Slave
MC145425
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
1
VSS
1
VSS
1
VSS
1
VSS
1
VSS
2
Vref
2
Vref
2
Vref
2
Vref
2
Vref
3
LI
3
LI
3
LI
3
LI
3
LI
4
LB
5
LB
5
LB
4
LB
4
LB
5
VD
6
VD
6
VD
5
VD
5
VD
6
SDI1
7
SI1
7
SI1
6
D1I
6
DI1
7
SDI2
9
SI2
9
SI2
7
D2I
7
DI2
8
FRAME 10/20
Logic 0
Logic 0
9
SDCLK/8kHz
High Impedance
SDCLK
10
SDO1
8
SO1
8
11
SDO2
10
SO2
12
SE/(Mu/A)
11
13
PD
12
14
MOD TRI/SQ
15
Tx
16
Tx
16
EN2-TE2/SIE/
B1B2
14
SIE
17
EN1-TE1
15
TE1
14
18
MSI/TONE
13
MSI
19
CCI/XTALin
17
20
TDC-RDC/
XTALout
18
21
LI SENS/
2.048 MHz
22
RE1/CLKOUT
23
RE2/BCLK
24
Rx
19
25
LO2
26
LO1
27
MASTER/
SLAVE
28
VDD
Logic 1
8
DCLK
8
DCLK
SO1
9
D1O
9
D1O
10
SO2
10
D2O
10
D2O
SE
11
Mu/A
11
SE
11
(Mu/A)
PD
12
PD
12
PD
12
PD
Logic 0
Logic 0
15
Logic 1
Tx
13
Tx
14
TE2
14
EN2
TE1
15
TE1
15
EN1
13
(Tone) TE
16
MSI
16
TONE
CCI
16
(XTALin) X1
17
CCI
17
(XTALin) CCI
TDC/RDC
17
(XTALout) X2
18
TDC/RDC
18
(XTALout) XTL
RE1
Tx
Logic 1
13
B1B2
Logic 0
Logic 0
LI SENS
20
Logic 1
2.048 MHz Out
Logic 0
LI SENS
2.048 MHz Out
20
RE1
19
RE1
19
CLKOUT
18
(BCLK) CLK
20
RE2
20
BCLK
Rx
19
Rx
21
Rx
21
Rx
22
LO2
22
LO2
22
LO2
22
LO2
23
LO1
23
LO1
23
LO1
23
LO1
High Impedance
Logic 0
24
VDD
Logic 1
24
VDD
Logic 0
24
VDD
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
Logic 1
24
VDD
Freescale Semiconductor, Inc.
MC145423
MC145423 UDLT-3 PIN STATES FOR UDLT-1 SLAVE MODE
UDLT-1 Slave Mode
Powered-Up
Freescale Semiconductor, Inc...
MC145423
UDLT-1 Slave Mode Powered-Down
TONE = 0, Off
No Valid
Burst Rec’d
TONE = 1, On
Valid
Burst Rec’d
No Valid
Burst Rec’d
Valid
Burst Rec’d
Pin
No.
Pin
Name
In/out
1
VSS
Power
2
Vref
Analog
Ref
AGND
VDD/2
AGND
VDD/2
AGND
VDD/2
AGND
VDD/2
AGND
VDD/2
AGND
VDD/2
3
LI
Input
Analog In
Analog In
Analog In
Analog In
Analog In
Analog In
4
LB
Input
1
0
Don’t Care
Don’t Care
Don’t Care
Don’t Care
5
VD
Output
Digital Out
Digital Out
VD = 0
VD = 1
VD = 0
VD = 1
6
SDI1
Input
8 kbps
Data In
8 kbps
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
7
SDI2
Input
8 kbps
Data In
8 kbps
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
8
FRAME
10/20
Input
0
0
0
0
0
0
9
SDCLK/
8kHz
Output
SDCLK/8kHz
SDCLK/8kHz
High-Z,
Not Used
High-Z,
Not Used
High-Z,
Not Used
High-Z,
Not Used
10
SDO1
Output
8 kbps
Data Out
8 kbps
Data Out
Data Not
Changed
8 kbps
Data Out
Data Not
Changed
8 kbps
Data Out
11
SDO2
Output
8 kbps
Data Out
8 kbps
Data Out
Data Not
Changed
8 kbps
Data Out
Data Not
Changed
8 kbps
Data Out
12
SE/(Mu/A)
Input
1= Mu,
0=A
1= Mu,
0=A
1= Mu,
0=A
1= Mu,
0=A
1= Mu,
0=A
1= Mu,
0=A
13
PD
I/O
1
1
0
0
0
0
14
MOD
TRI/SQ
Input
0
0
0
0
0
0
15
Tx
Output
64 kbps
Data Out
64 kbps
Data Out
High
Impedance
64 kbps
Data Out
64 kbps
PCM Tone
64 kbps
PCM Tone
16
EN2-TE2/
SIE/B1B2
Input
1/0 B1B2
1/0 B1B2
1/0 B1B2
1/0 B1B2
1/0 B1B2
1/0 B1B2
17
EN1-TE1
Output
EN1 = 8 kHz
EN1 = 8 kHz
EN1 = 0
EN1 = 8 kHz
EN1 = 8 kHz
EN1 = 8 kHz
18
MSI/
TONE
Input
1/0 TONE
1/0 TONE
TONE = 0
TONE = 0
TONE = 1
TONE = 1
19
CCI/
XTALin
Input
XTALin
4.096 MHz
XTALin
4.096 MHz
XTALin
4.096 MHz
XTALin
4.096 MHz
XTALin
4.096 MHz
XTALin
4.096 MHz
20
TDC-RDC/
XTALout
Output
XTALout
4.096 MHz
XTALout
4.096 MHz
XTALout
4.096 MHz
XTALout
4.096 MHz
XTALout
4.096 MHz
XTALout
4.096 MHz
21
LI SENS/
2.048 MHz
Output
2.048 MHz
2.048 MHz
2.048 MHz
2.048 MHz
2.048 MHz
2.048 MHz
22
RE1/
CLKOUT
Output
RE1 = 8 kHz
RE1 = 8 kHz
RE1 = 1
RE1 = 8 kHz
RE1 = 8 kHz
RE1 = 8 kHz
Normal
LB Low
Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145423
MC145423 UDLT-3 PIN STATES FOR UDLT-1 SLAVE MODE (continued)
MC145423
Freescale Semiconductor, Inc...
UDLT-1 Slave Mode Powered-Down
UDLT-1 Slave Mode
Powered-Up
TONE = 0, Off
TONE = 1, On
No Valid
Burst Rec’d
Valid
Burst Rec’d
No Valid
Burst Rec’d
Valid
Burst Rec’d
BCLK = 0
BCLK =
128 kHz
BCLK =
128 kHz
BCLK =
128 kHz
BCLK =
128 kHz
64 kbps
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Output
Modulator
Out
Modulator
Out
LO2 = LO1
LO2 = LO1
LO2 = LO1
LO2 = LO1
LO1
Output
Modulator
Out
Modulator
Out
LO1 = LO2
LO1 = LO2
LO1 = LO2
LO1 = LO2
27
MASTER/
SLAVE
Input
1
1
1
1
1
1
28
VDD
Power
+V
+V
+V
+V
+V
+V
Pin
No.
Pin
Name
23
In/out
Normal
LB Low
RE2/
BCLK
Output
BCLK =
128 kHz
24
Rx
Input
25
LO2
26
MC145423 UDLT-3 PIN STATES FOR UDLT-1 MASTER MODE
UDLT-1 Master Mode
Powered-Up
MC145423
UDLT-1 Master Mode
Powered-Down
Pin
No.
Pin
Name
In/out
Normal
LB Low
SE Low
Normal
SE Low
1
VSS
Power
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
2
Vref
Analog
Ref
AGND VDD/2
AGND VDD/2
AGND VDD/2
AGND VDD/2
AGND VDD/2
3
LI
Input
Analog In
Don’t Care
Analog In
Analog In
Analog In
4
LB
Input
1
0
State Latched
Don’t Care
Don’t Care
5
VD
Output
Digital out
Digital out
High Impedance
Digital out
High Impedance
6
SDI1
Input
8 kbps Data In
8 kbps Data In
State Latched
8 kbps Data In
State Latched
7
SDI2
Input
8 kbps Data In
8 kbps Data In
State Latched
8 kbps Data In
State Latched
8
FRAME 10/20
Input
0
0
0
0
0
9
SDCLK
10
SDO1
Output
8 kbps Data Out 8 kbps Data Out High Impedance 8 kbps Data Out High Impedance
11
SDO2
Output
8 kbps Data Out 8 kbps Data Out High Impedance 8 kbps Data Out High Impedance
12
SE/(Mu/A)
Input
1
1
0
1
0
13
PD
Input
1
1
State Latched
0
State Latched
14
MOD
TRI/SQ
Input
0
0
0
0
0
15
Tx
Output
64 kbps
Data Out
64 kbps
Data Out
64 kbps
Data Out
64 kbps
Data Out
64 kbps
Data Out
16
EN2-TE2/
SIE/B1B2
Input
SIE Digital In
SIE Digital In
SIE Digital In
SIE Digital In
SIE Digital In
Don’t Care High Impedance High Impedance High Impedance High Impedance High Impedance
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145423
MC145423 UDLT-3 PIN STATES FOR UDLT-1 MASTER MODE (continued)
UDLT-1 Master Mode
Powered-Up
Freescale Semiconductor, Inc...
MC145423
UDLT-1 Master Mode
Powered-Down
Pin
No.
Pin
Name
In/out
Normal
LB Low
SE Low
Normal
SE Low
17
EN1-TE1
Input
TE1 8 kHz
TE1 8 kHz
TE1 8 kHz
TE1 8 kHs
TE1 8 kHz
18
MSI/TONE
Input
MSI 8 kHz
MSI 8 kHz
MSI 8 kHz
MSI 8 kHz
MSI 8 kHz
19
CCI/
XTALin
Input
CCI 2.048 MHz
CCI 2.048 MHz
CCI 2.048 MHz
CCI 2.048 MHz
CCI 2.048 MHz
20
TDC-RDC/
XTALout
Input
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
21
LI SENS/
2.048 MHz
Input
Digital In
LI Sensitivity
Digital In
LI Sensitivity
Digital In
LI Sensitivity
Digital In
LI Sensitivity
Digital In
LI Sensitivity
22
RE1/
CLKOUT
Input
RE1 8 kHz
RE1 8 kHz
RE1 8 kHz
RE1 8 kHz
RE1 8 kHz
23
RE2/
BCLK
24
Rx
Input
64 kbps Data In
64 kbps Data In
64 kbps Data In
Don’t Care
Don’t Care
25
LO2
Output
Modulator Out
LO2 = LO1
No Effect
LO2 = LO1
LO2 = LO1
26
LO1
Output
Modulator Out
LO1 = LO2
No Effect
LO1 = LO2
LO1 = LO2
27
MASTER/
SLAVE
Input
0
0
0
0
0
28
VDD
Power
+V
+V
+V
+V
+V
Don’t Care High Impedance High Impedance High Impedance High Impedance High Impedance
MC145423 UDLT-3 PIN STATES FOR UDLT-2 SLAVE MODE
UDLT-2 Slave Mode
Powered-Up
MC145423
UDLT-2 Slave Mode
Powered-Down
TONE = 0, Off
No Valid
Burst Rec’d
TONE = 1, On
Valid
Burst Rec’d
No Valid
Burst Rec’d
Valid
Burst Rec’d
Pin
No.
Pin
Name
In/out
1
VSS
Power
2
Vref
Analog
Ref
AGND
VDD/2
AGND
VDD/2
AGND
VDD/2
AGND
VDD/2
AGND
VDD/2
AGND
VDD/2
3
LI
Input
Analog In
Analog In
Analog In
Analog In
Analog In
Analog In
4
LB
Input
1
0
Don’t Care
Don’t Care
Don’t Care
Don’t Care
5
VD
Output
Digital Out
Digital Out
VD = 0
VD = 1
VD = 0
VD = 1
6
SDI1
Input
16 kbps
Data In
16 kbps
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
7
SDI2
Input
16 kbps
Data In
16 kbps
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
8
FRAME
10/20
Input
1
1
1
1
1
1
9
SDCLK
Output
16 kHz
16 kHz
16 kHz
16 kHz
16 kHz
16 kHz
Normal
LB Low
Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145423
MC145423 UDLT-3 PIN STATES FOR UDLT-2 SLAVE MODE (continued)
UDLT-2 Slave Mode
Powered-Up
MC145423
Freescale Semiconductor, Inc...
UDLT-2 Slave Mode
Powered-Down
TONE = 0, Off
TONE = 1, On
Pin
No.
Pin
Name
In/out
Normal
LB Low
No Valid
Burst Rec’d
Valid
Burst Rec’d
No Valid
Burst Rec’d
Valid
Burst Rec’d
10
SDO1
Output
16 kbps
Data Out
16 kbps
Data Out
Data Not
Changed
16 kbps
Data Out
Data Not
Changed
16 kbps
Data Out
11
SDO2
Output
16 kbps
Data Out
16 kbps
Data Out
Data Not
Changed
16 kbps
Data Out
Data Not
Changed
16 kbps
Data Out
12
SE/
(Mu/A)
Input
1/0
Mu/A
1/0
Mu/A
1/0
Mu/A
1/0
Mu/A
1/0
Mu/A
1/0
Mu/A
13
PD
I/O
1
1
0
0
0
0
14
MOD
TRI/SQ
Input
1
1
1
1
1
1
15
Tx
Output
128 kbps
Data Out*
128 kbps
Data Out*
High
Impedance
64 kbps
Data Out
500 Hz
Tone Out
500 Hz
Tone Out
16
EN2-TE2/
SIE/B1B2
Output
EN2 8 kHz
EN2 8 kHz
EN2 = 0
EN2 = 0
EN2 8 kHz
EN2 8 kHz
17
EN1-TE1
Output
EN1 8 kHz
EN1 8 kHz
EN1 = 0
EN1 = 0
EN1 8 kHz
EN1 8 kHz
18
MSI/
TONE
Input
1/0 Tone
1/0 Tone
0 No Tone
0 No Tone
1 No Tone
1 Tone
19
CCI/
XTALin
Input
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
20
TDC-RDC/
XTALout
Output
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
21
LI SENS/
2.048 MHz
Output
2.048 MHz
2.048 MHz
2.048 MHz
2.048 MHz
2.048 MHz
2.048 MHz
22
RE1/
CLKOUT
Output
RE1 8 kHz
RE1 8 kHz
RE1 0
RE1 0
RE1 8 kHz
RE1 8 kHz
23
RE2/
BCLK
Output
BCLK
128 kHz
BCLK = 0
BCLK
128 kHz
BCLK
128 kHz
BCLK
128 kHz
BCLK
128 kHz
24
Rx
Input
128 kbps
Data In
Don’t Care
Don’t Care
Don’t Care
128 kbps
Data In
128 kbps
Data In
25
LO2
Output
Modulator
Out
Modulator
Out
LO2 = LO1
LO2 = LO1
LO2 = LO1
LO2 = LO1
26
LO1
Output
Modulator
Out
Modulator
Out
LO2 = LO1
LO2 = LO1
LO1 = LO2
LO1 = LO2
27
MASTER/
SLAVE
Input
1
1
1
1
1
1
28
VDD
Power
+V
+V
+V
+V
+V
+V
* Tx is high impedance when TE1 and TE2 are both low, simultaneously.
Tx is undefined when TE1 and TE2 are both high, simultaneously.
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145423
MC145423 UDLT-3 PIN STATES FOR UDLT-2 MASTER MODE
Freescale Semiconductor, Inc...
MC145423
UDLT-2 Master Powered-Up
UDLT-2 Master Powered-Down
Pin
No.
Pin
Name
In/out
Normal
LB Low
SE Low
Normal
SE Low
1
VSS
Power
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
2
Vref
Analog Ref
AGND VDD/2
AGND VDD/2
AGND VDD/2
AGND VDD/2
AGND VDD/2
3
LI
Input
Analog In
Don’t Care
Analog In
Analog In
Analog In
4
LB
Input
1
0
State Latched
Don’t Care
Don’t Care
5
VD
Output
Digital Out
Digital Out
High Impedance
Digital Out
High Impedance
6
SDI1
Input
16 kbps Data In
16 kbps Data In
State Latched
16 kbps Data In
State Latched
7
SDI2
Input
16 kbps Data In
16 kbps Data In
State Latched
16 kbps Data In
State Latched
8
FRAME 10/
20
Input
1
1
1
1
1
9
SDCLK
Input
16 kHz
16 kHz
16 kHz
16 kHz
16 kHz
10
SDO1
Output
16 kbps Data
Out
16 kbps Data
Out
High Impedance
16 kbps Data
Out
High Impedance
11
SDO2
Output
16 kbps Data
Out
16 kbps Data
Out
High Impedance
16 kbps Data
Out
High Impedance
12
SE/(Mu/A)
Input
1
1
0
1
0
13
PD
Input
1
1
State Latched
0
State Latched
14
MOD TRI/SQ
Input
1
1
1
1
1
15
Tx
Output
128 kbps*
Data Out
128 kbps*
Data Out
128 kbps*
Data Out
128 kbps*
Data Out
128 kbps*
Data Out
16
EN2-TE2/
SIE/B1B2
Input
TE2 8 kHz
TE2 8 kHz
TE2 8 kHz
TE2 8 kHz
TE2 8 kHz
17
EN1-TE1
Input
TE1 8 kHz
TE1 8 kHz
TE1 8 kHz
TE1 8 kHz
TE1 8 kHz
18
MSI/TONE
Input
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
19
CCI/XTALin
Input
CCI
4.096 MHz
CCI
4.096 MHz
CCI
4.096 MHz
CCI
4.096 MHz
CCI
4.096 MHz
20
TDC-RDC/
XTALout
Input
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
21
LI SENS/
2.048 MHz
Input
Digital In
Sensitivity
Digital In
Sensitivity
Digital In
Sensitivity
Digital In
Sensitivity
Digital In
Sensitivity
22
RE1/
CLKOUT
Input
RE1 8 kHz
RE1 8 kHz
RE1 8 kHz
RE1 8 kHz
RE1 8 kHz
23
RE2/BCLK
Input
RE2 8 kHz
RE2 8 kHz
RE2 8 kHz
RE2 8 kHz
RE2 8 kHz
24
Rx
Input
Don’t Care
Don’t Care
25
LO2
Output
Modulator Out
LO2 = LO1
No Effect
LO2 = LO1
LO2 = LO1
26
LO1
Output
Modulator Out
LO1 = LO2
No Effect
LO1 = LO2
LO1 = LO2
27
MASTER/
SLAVE
Input
0
0
0
0
0
28
VDD
Power
+V
+V
+V
+V
+V
128 kbps Data In 128 kbps Data In 128 kbps Data In
* Tx is high impedance when TE1 and TE2 are both low, simultaneously.
Tx is undefined when TE1 and TE2 are both high, simultaneously.
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145423
PIN DESCRIPTIONS
VSS
Negative Supply (Pin 1)
This is the most negative power pin, and should be
tied to system ground (0 V).
Freescale Semiconductor, Inc...
Vref
Voltage Reference Output (Pin 2)
This is the output from the internal reference supply
(mid-supply) and should be bypassed to both VSS and
VDD with 0.1 µF capacitors. This pin usually serves
as an analog ground reference for transformer
coupling of the device’s incoming bursts from the line.
No external load should be placed on this pin.
LI
Line Input (Pin 3)
This pin is the input to the demodulator for the
incoming bursts. This input has an internal 240 kΩ
resistor tied to the Vref pin, so an external capacitor or
line transformer may be used to couple the input signal
to the device with no dc offset.
LB
Loopback Low Input (Pin 4)
Master Mode: A low on this pin ties the internal
modulator output to the internal demodulator input,
which loops the entire burst for testing purposes.
During the loopback operation, the LI input is ignored,
and the LO1 and LO2 outputs are driven to equal
voltages. The state of the LB pin is internally latched if
the SE pin is held low. This feature is only active when
the PD input is high.
Slave Mode: When this pin is low and PD is high,
the incoming B channels from the master are burst
back to the master, instead of the Rx B channel input
data. The SDI1 and SDI2 functions operate normally
in this mode, and the BCLK (pin 23) is held low.
Additionally, for both the UDLT-1 and UDLT-2 mode,
when the TONE (pin 18) and loopback functions are
active simultaneously, the loopback function overrides
the TONE function.
VD
Valid Data Output (Pin 5)
A high level on this pin indicates that a valid line
transmission has been demodulated. A valid line
transmission burst is determined by proper
synchronization and the absence of detected bit errors.
VD is a CMOS output and is high impedance when SE
is low.
Master Mode: VD changes state on the rising
edge of MSI, when PD is high. When PD is low, VD
changes state at the end of demodulation of a
transmission burst and does not change again until
three MSI rising edges have occurred, at which time it
goes low, or until the next demodulation of a burst.
Slave Mode: If no transmissions from the master
have been received within the last 250 µs, as
determined by an internal oscillator, VD will go low.
SDI1 and SDI2
D Channel Signaling Data Bit Inputs 1 and 2
(Pins 6 and 7)
Master Mode (UDLT-1): These inputs are the
8 kbps serial data inputs in UDLT-1 mode. Data on
these pins is loaded on the rising edge of MSI for
transmission to the slave. The state of these pins is
latched if SE is held low.
Slave Mode (UDLT-1): These inputs are the
8 kbps serial data inputs in UDLT-1 mode. Data on
these pins is loaded on the rising edge of TE1 for
transmission to the master. If no transmissions from
the master are being received and PD is high, data on
these pins will be loaded into the part on an internal
signal. Therefore, data on these pins should be steady
until synchronous communication with the master has
been established, as indicated by the high on VD.
Master Mode (UDLT-2): These inputs are the
16 kbps serial data inputs in UDLT-2 mode. Two bits
should be clocked into each of these inputs between
the rising edges of the MSI frame reference clock. The
first bit of each D channel is clocked into an
intermediate buffer on the first falling edge of the
SDCLK following the rising edge of MSI. The second
bit of each D channel is clocked in on the next
negative transition of the SDCLK. If further SDCLK
negative edges occur, new information is serially
clocked into the buffer replacing the previous data,
one bit at a time. Buffered D channel bits are burst to
the slave on the next rising edge of the MSI frame
reference clock. The state of these pins is latched if SE
is held low.
Slave Mode (UDLT-2): These inputs are the
16 kbps serial data inputs in UDLT-2 mode. The D
channel data bits are clocked in serially on the
negative edge of the 16 kbps SDCLK output pin.
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
FRAME 10/20
(Pin 8)
The UDLT series of transceivers are designed to
operate using a ping-pong transmission scheme with
an 8 kHz burst rate. Each frame the master device
“pings” a burst of data to the slave, which responds
with a “pong” burst of data. This pin selects whether
this 8 kHz frame will have a 10-bit data burst for
UDLT-1 compatibility or a 20-bit data burst for
UDLT-2 compatibility.
A logic low (0 V) selects the UDLT-1 (MC145422/
MC145426) mode. This sets the device to operate with
one 64 kbps voice/data channel and two 8 kbps
signaling channels. A logic high (VDD) on this pin
selects the UDLT-2 (MC145421/MC145425) mode.
This sets the device to operate with two 64 kbps
channels and two 16 kbps channels (2B+2D).
SDCLK
D Channel Signaling Data Clock Input (Pin 9)
Master Mode (UDLT-2): This is the transmit and
receive data clock input for both D channels. See
SDO1 and SDO2 pin descriptions for more
information.
Master Mode (UDLT-1): High impedance.
Slave Mode (UDLT-2): This is the transmit and
receive data clock output for both D channels. It starts
on demodulation of a burst from the master device.
This signal is rising-edge aligned with the EN1 and
BCLK signals. After the demodulation of a burst, the
SDCLK line completes two cycles and then remains
low until the next burst from the master is
demodulated. In this manner, synchronization with the
master is established and any clock slip between
master and slave is absorbed each frame.
Slave Mode (UDLT-1): This pin outputs 8 kHz
equivalent to TE1.
SDO1 and SDO2
D Channel Signaling Data Outputs 1 and 2
(Pins 10 and 11)
Master Mode (UDLT-2): These serial outputs
provide the 16 kbps D channel signaling information
from the incoming burst. Two data bits should be
clocked out of each of these two outputs between the
rising edges of the MSI frame reference clock. The
rising edge of MSI produces the first bit of each
D channel on its respective pin. Circuitry then
searches for a negative D channel clock edge. This
MC145423
tells the D channel data shift register to produce the
second D channel bit on the next rising edge of the
SDCLK. Further rising edges of the SDCLK
recirculate the D channel output buffer information.
Master Mode (UDLT-1): These outputs are
received signaling bits from the slave UDLT and
change state on the rising edge of MSI, if PD is high;
or at the end of demodulation, if PD is low.
Slave Mode (UDLT-2): These two pins are the
outputs for the 16 kbps D channels. These pins are
updated on the rising edges of the slave SDCLK
output pin.
Slave Mode (UDLT-1): These outputs are
received signaling bits from the master UDLT and
change state on the rising edge of TE1.
SE/(Mu/A)
Signaling Enable Input or Tone Format Input
(Pin 12)
Master Mode (SE): A low on this pin causes the
state of LB, PD, SDI1, and SDI2 to be stored.
Additionally, output pins VD, SDO1, and SDO2 will
be high impedance. This allows the device to be
bussed with other UDLTs using a common control bus.
A high on this pin returns the device to normal
operation.
Slave Mode (Mu/A): This pin allows the user to
select the PCM code format for the pacifier tone. A
high on this pin selects Mu-Law. A low on this pin
selects A-Law. The state of this pin determines the
PCM code sequence for the 500 Hz square wave tone
generated when the TONE pin input is high.
PD
Power Down Low (Pin 13)
Master Mode: When this pin is held low, the
device powers down, except for the circuitry necessary
to demodulate an incoming burst and to output VD
and the B and D channel data bits. When this pin is
brought high, the device waits for three positive MSI
edges or until the end of an incoming transmission
from the slave and then begins transmitting every MSI
period to the slave UDLT on the next rising edge of
MSI.
Slave Mode: This is a bidirectional pin with a
weak output driver that can be externally overdriven.
When this pin is floating and a burst from the master is
demodulated, the weak output drivers will try to force
PD high. The drivers will try to force PD low, if
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
MC145423
Freescale Semiconductor, Inc.
250 µs have elapsed without a burst from the master
being successfully demodulated. This allows the slave
device to self power-up and power-down in demand
powered loop systems. When held low, the device
powers down and the only active circuitry, is that
which is necessary for the demodulation of data. When
held high, the device is powered up and transmits
normally in response to received bursts from the
master.
Freescale Semiconductor, Inc...
MOD TRI/SQ
Modulation Select (Pin 14)
A logic low (0 V) on this pin selects the MDPSK
modulation which has a slew controlled voltage output
for reduced EMI/RFI. This output looks like a triangle
waveform that is modulated with different angles for
the peaks. A logic high (VDD) on this pin, selects
square wave output for maximum power to the line.
Tx
Transmit Data Output (Pin 15)
Master Mode (UDLT-1): This pin is high
impedance when TE1 is low. When TE1 is high, this
pin presents new 8-bit B channel data on rising edges
of TDC-RDC.
Slave Mode (UDLT-1): B channel data is output
on this pin on the rising edge of BCLK, while TE1 is
high. This pin is high impedance when TE1 is low.
Master Mode (UDLT-2): This pin is high
impedance when both TE1 and TE2 are low. This pin
serves as an output for B channel information received
from the slave device. The B channel data is under
control of TE1 and TE2 and TDC-RDC.
Slave Mode (UDLT-2): This pin is an output for
the B channel data received from the master.
B channel 1 data is output on the first eight cycles of
the BCLK output when EN1 is high. B channel 2 data
is output on the next eight cycles of the BCLK, when
EN2 is high. B channel data bits are clocked out on the
rising edge of the BCLK output pin.
EN2-TE2/SIE/B1B2
B Channel 2 Enable Output or
Signal Insert Enable (Pin 16)
Master Mode (SIE UDLT-1): In this mode, this
pin functions as SIE. When held high, this pin causes
signal bit 2, as received from the slave, to be inserted
into the LSB of the outgoing PCM word at the Tx pin.
The SDI2 pin will be ignored, and in its place, the LSB
of the incoming word at the Rx pin will be transmitted
to the slave. The PCM word to the slave will have LSB
forced low in this mode. In this manner, signal bit 2 to/
from the slave UDLT is inserted into the PCM words
the master sends and receives from the backplane, for
routing through the PABX for simultaneous voice/data
communication. The state of this pin is internally
latched if the SE pin is brought and held low.
Slave Mode (UDLT-1): In this mode, this pin is
an input and selects the timeslot used for transferring
the receive data word. When this pin is low, the device
uses the RE1 pin timing the same as the MC145426
UDLT-1 slave. When this pin is a logic 1, the receive
word is latched in during the TE1 timeslot,
simultaneously with the transmit word transfer. The
RE1 pin timing is not affected by this selection.
Master Mode (EN2-TE2 UDLT-2): In this mode,
this pin functions as EN2-TE2. This pin, along with
TE1 pin-17 control the output of data for their
respective B-channel on the Tx output pin. When both
TE1 and TE2 are low, the Tx pin is high impedance.
The rising edge of the respective enable produces the
first bit of the selected B-channel data on the Tx pin.
Internal circuitry then scans for the next negative
transition of the TDC-RDC clock. Following this
event, the next seven bits of the selected B-channel
data are output on the next seven rising edges of the
TDC-RDC data clock. When TE1 and TE2 are high
simultaneously, data on the Tx pin is undefined. TE1
and TE2 should be approximately leading-edge
aligned with the TDC-RDC data clock. To keep the Tx
pin out of the high impedance state, these enable lines
should be high while the respective B channel data is
being output.
Slave Mode (EN2-TE2 UDLT-2): Functioning as
EN2-TE2, this pin is an output and serves as an 8 kHz
enable signal for the input and output of the B channel
2 data. While EN2 is high, B channel 2 data is clocked
out on the Tx pin on the eight rising edges of the
BCLK. During this same time, B channel 2 input data
is clocked in on the Rx pin, on the eight falling edges
of the BCLK.
EN1-TE1
B Channel 1 Enable Output (Pin 17)
This pin is the logical inverse of EN2-TE2, and
serves to control B channel 1 data. See the above pin
description for more information. EN1 serves as the
slave device’s 8 kHz frame reference signal. The VD
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
MC145423
pin is also updated on the rising edge of the EN1
signal.
desired. XTALout should be left open if an external
signal is used on this input.
MSI/TONE
Master Sync Input or Tone Enable Input
(Pin 18)
TDC-RDC/Xtalout
Transmit and Receive Data Clock or Crystal
Output (Pin 20)
Master Mode (MSI): This pin is the master 8 kHz
frame reference input. The rising edge of MSI loads
B and D channel data, which had been input during the
previous frame, into the modulator section of the
device, and initiates the outbound burst onto the
twisted pair cable. The rising edge of MSI also
initiates the buffering of the B and D channel data
demodulated during the previous frame. MSI should
be approximately leading edge aligned with the TDCRDC data clock input signal.
Slave Mode (TONE): A high on this pin causes a
500 Hz square wave PCM tone to be inserted in place
of the demodulated data. This feature allows the
designer to provide audio feedback for telset keyboard
depressions.
Master Mode (TDC-RDC): This input is the
transmit and receive data clock for the B channel data.
Output data changes state on the rising edge of this
signal, and input data is read on the falling edges of
this signal. TDC-RDC should be roughly leading edge
aligned with MSI.
Slave Mode (XTALout): This pin is the crystal
out pin. It is capable of driving one external CMOS
input and 15 pF of additional capacitance. See pin
description for XTALin (pin 19).
CCI/XTALin
Convert Clock Input or Crystal Input (Pin 19)
Master Mode (CCI UDLT-1): A 2.048 MHz
clock signal should be applied to this pin. This signal
is used for internal sequencing and control. This signal
should be frequency and phase coherent with MSI for
optimum performance.
Slave Mode (XTALin UDLT-1): A 4.096 MHz
crystal is tied between this pin and XTALout (pin 20).
A 10 MΩ resistor across this pin and XTALout and
25 pF capacitors from this pin and XTALout to VSS
are required for stability and to ensure start-up. This
pin may be driven from an external source. XTALout
should be left open if an external signal is used on this
input.
Master Mode (CCI UDLT-2): An 8.192 MHz
clock should be supplied to this input. The 8.192 MHz
input should be 50% duty cycle. This signal may free
run with respect to all other clocks without
performance degradation.
Slave Mode (XTALin UDLT-2): Normally, an
8.192 MHz crystal is tied between this pin and the
XTALout (pin 20). A 10 MΩ resistor between
XTALin and XTALout and 25 pF capacitors from
XTALin and XTALout to VSS are required to ensure
stability and start-up. XTALin may also be driven with
an external 8.192 MHz signal if a crystal is not
LI SENS/2.048 MHz
Line Input Sensitivity or 2.048 MHz Output
(Pin 21)
Master Mode: By applying a logic 1 on this pin,
the sensitivity of LI is reduced by 15 dB. This reduces
the effects of crosstalk, and false detects that would be
picked up and demodulated when the LI pin is
connected to an open loop.
Slave Mode: This pin outputs a 2.048 MHz signal
for use with a PCM codec-filter. All other device
clocks are generated from the rising edge of this clock.
The 8 kHz enables are derived by dividing this
2.048 MHz clock by a nominal ratio of 256. Phase
synchronization to the master UDLT’s burst is
achieved by dividing this clock by the ratios of either
255, 256, or 257.
RE1/CLKOUT
Receive Data Enable 1 Input or Clock Output
(Pin 22)
Master Mode (RE1 UDLT-1): A rising edge on
this pin will enable data on the Rx pin to be loaded
into the receive data register on the next eight falling
edges of the TDC-RDC data clock. RE1 and TDCRDC should be approximately leading edge aligned.
Slave Mode (RE1 UDLT-1): This B series
CMOS output is the inverse of TE1 (see TE1 pin
description).
Master Mode (RE1 UDLT-2): This input along
with RE2 (pin 23) control the input of B channel data
on the Rx pin. The rising edge of the respective enable
signal causes the device to load the selected receive
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
MC145423
Freescale Semiconductor, Inc.
data buffer with data from the Rx pin on the next eight
falling edges of the TDC-RDC clock. The RE1 and
RE2 enables should be roughly leading edge aligned
with the TDC-RDC data clock. These enables are
rising edge sensitive and need not be high for the
entire B channel input period.
Slave Mode (CLKOUT UDLT-2): This pin
serves as a buffered output of the crystal frequency
divided by two.
Freescale Semiconductor, Inc...
RE2/BCLK
Receive Data Enable Input 2 or B Channel
Data Clock Output (Pin 23)
Master Mode (UDLT-1): This pin is high
impedance.
Master Mode (RE2 UDLT-2): See pin
description for RE1 (pin 22).
Slave Mode (BCLK UDLT-1 and UDLT-2):
This output provides the data clock for the telset
codec-filter. This clock signal is 128 kHz and begins
operating upon the successful demodulation of a burst
from the master. At this time, EN1-TE1 goes high and
BCLK starts toggling. BCLK remains active for
16 periods, at the end of which time it remains low
until another burst is received from the master. In this
manner, synchronization between the master and slave
is established and any clock slippage is absorbed each
frame. If TONE (pin 18) is brought high, then EN1TE1/RE1 are generated from an internal oscillator
until TONE is brought low, or an incoming burst from
the master is received. BCLK is disabled when LB is
held low.
which is simultaneous with the transfer of the transmit
word. See the pin descriptions for EN2-TE2/SIE/
B1B2 and EN1-TE2 for more information.
Master Mode (UDLT-2): B channel data is input
on this pin and controlled by the RE1, RE2, and TDCRDC pins.
Slave Mode (UDLT-2): This pin is an input for
the B channel data. B channel 1 data is clocked in on
the first eight falling edges of the BCLK output
following the rising edge of the EN1 output. B channel
2 data is clocked in on the next eight falling edges of
the BCLK following the rising edge of the EN2
output.
LO2
Line Drive Output (Pin 25)
The LO2 pin, along with LO1 (pin 26) form a pushpull output, to drive the twisted pair transmission line.
The UDLT-1 drives the twisted pair with a 10-bit,
256 kHz modified DPSK (MDPSK) burst, or a square
wave (set by pin 14 MOD TRI/SQ) burst, each 125 µs.
The UDLT-2 drives the twisted pair with a 20-bit
512 kHz modulated burst. When these pins are idle
and set for square wave modulation, they rest at the
positive power supply voltage. When these pins are
idle and set for MDPSK, they rest at Vref. For power
supply voltages less than 4.5 V, squarewave
modulation must be used.
LO1
Line Driver Output (Pin 26)
See the pin description for LO2 (pin 25).
Rx
Receive Data Input (Pin 24)
MASTER/SLAVE
Master/Slave Mode (Pin 27)
Master Mode (UDLT-1): The 8-bit B channel
data is clocked into the device on this pin, on the
falling edges of TDC-RDC, under the control of RE1.
Slave Mode (UDLT-1): The 8-bit B channel data
from the telset PCM codec-filter is input on this pin on
the eight falling edges of BCLK after RE1 goes high,
when EN2-TE2/SIE/B1B2, pin 16 is low. When EN2TE2/SIE/B1B2, pin16 is high, the receive data word is
latched in during the high period of EN1-TE1, pin 17
A logic low (0 V) on this pin selects master and a
logic high (VDD) selects slave.
VDD
Positive Supply (Pin 28)
This is the most positive power supply pin.
Acceptable operating voltages are from 4.5 V to 5.5 V.
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
1.0 µF
1.0 µF
68 µF
ROW &
COL
KEYPAD
MIC
1 kΩ
1 kΩ
5V
REC
VSS
VDD
1 kΩ
PULSE TONE
DIALER
100 kΩ
OCSout
OSCin
MS
OH/T
TSO
MO
OP
DTMF OUT
420 pF
75 kΩ
3.58 MHz
0.1 µF
VSS
TI+
TI–
TG
MCLK
VAG
VAG-REF
MC145484
FST
BCLKT
BCLKR
DT
FSR
DR
PO+
PO–
PD
RO–
PI
VDD
Mu/A
1 kΩ
5V
0.01 µF
10 kΩ
10 V
20 pF
4.7 µF
10 V
20 pF
SPEAKER
4.096 MHz
TDC-RDC/XTALout
10 MΩ
MSI/TONE
2.048 MHz
CCI/XTALin
SDCLK
SDO1
SDO2
EN2-TE2 (I/O)/SIE
SDI2
Rx
RE1/CLKout
RE2/BCLK
Tx
EN1-TE1 (I/O)
270 Ω
5V
1.8 kΩ
4.7 µF
5V
FRAME 10/20
VSS
SE/(Mu/A)
SDI1
MOD TRI/SQ
MASTER/SLAVE
LO1
LO2
VD
LB
LI
Vref
PD
VDD
LM317
MC145423
UDLT-3
SLAVE
MODE
BASIC DIGITAL TELSET
Freescale Semiconductor, Inc...
78M05
5V
110 Ω
110 Ω
5V
5V
4.7 kΩ
50 µF
110 Ω
N=2
110 Ω
N=4
4.7 kΩ
33 V
2W
20 Ω
N = 0.5
N = 0.5
RING
TIP
Freescale Semiconductor, Inc.
MC145423
MC145423
Freescale Semiconductor, Inc.
MULTICHANNEL DIGITAL LINE CARD
POWER
SUPPLY
VDD
LO1
Vref
TIP
LO2
LI
SDI1
SDI2
Freescale Semiconductor, Inc...
SDO1
MSI/TONE
Tx
Rx
TDC/RDC/XTALout
SDO2
EN2-TE2(I/O)/SIE
SE/(Mu/A)
MASTER/SLAVE
LB
VD
TO
BACKPLANE
CCI/XTALin
UDLT-3 PD
MASTER RE1/CLKOUT
MODE EN1-TE1 (I/O)
SDCLK
RE2/BCLK
LI SENS/2.048 MHz
8 kHz FRAME SYNC
TRANSMIT DATA BUS
RECEIVE DATA BUS
2.048 MHz DATA CLOCK
MOD SELECT
FRAME 10/20
VSS
RING
TO
BACKPLANE
POWER
SUPPLY
TIP
VDD
LO1
Vref
LO2
LI
MSI/TONE
Tx
Rx
TDC/RDC/XTALout
CCI/XTALin
UDLT-3 PD
MASTER RE1/CLKOUT
MODE EN1-TE1 (I/O)
SDO1
EN2-TE2(I/O)/SIE
SDO2
SDI1
SDI2
SDCLK
RE2/BCLK
LI SENS/2.048 MHz
LB
VD
SE/(Mu/A)
MASTER/SLAVE
MOD SELECT
FRAME 10/20
VSS
RING
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
TIMING
AND
CONTROL
Freescale Semiconductor, Inc.
MC145423
PACKAGE DIMENSIONS
DW SUFFIX
SOIC PACKAGE
CASE 751F-05
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSIONS.
4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
15
0.25
E
H
M
B
M
28
1
14
A
PIN 1 IDENT
L
0.10
A1
Freescale Semiconductor, Inc...
B
e
C
B
C
0.025
M
C A
S
B
SEATING
PLANE
θ
DIM
A
A1
B
C
D
E
e
H
L
θ
S
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
MILLIMETERS
MIN
MAX
2.35
2.65
0.13
0.29
0.35
0.49
0.23
0.32
17.80
18.05
7.40
7.60
1.27 BSC
10.05
10.55
0.41
0.90
0°
8°
Freescale Semiconductor, Inc.
MC145423
DT SUFFIX
TSSOP PACKAGE
CASE 1168-01
B
D
A
A
b1
C
28
15
c
c1
E/2
E
(b)
E1
SECTION A-A
Freescale Semiconductor, Inc...
1
PIN 1
INDEX
14
2X
e/2
26X
0.2
A
B
2X 14 TIPS
e
C
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION D DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION IS
0.15 PER SIDE.
4. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR MOLD PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25 PER
SIDE.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSIONS. DAMBAR PROTRUSION SHALL NOT
CAUSE THE LEAD WIDTH TO EXCEED 0.38.
END
VIEW
VIEW A
TOP VIEW
0.05
(D)
0.2
28X
A
SEATING PLANE
A
28X b
0.1 M
SIDE VIEW
A
A
B
(θ 1°)
C
GAGE
PLANE
A1
θ°
0.25
L
VIEW A
A2
DIM
A
A1
A2
b
b1
c
c1
D
e
E
E1
L
θ
θ1
For More
Information On This Product,
TELECOMMUNICATIONS
Go to: www.freescale.com
MILLIMETERS
MIN
MAX
--1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.19
0.25
0.09
0.20
0.09
0.16
9.60
9.80
0.65 BSC
6.40 BSC
4.30
4.50
0.50
0.70
0°
8°
14° REF
MC145423
Home Page:
www.freescale.com
email:
[email protected]
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
(800) 521-6274
480-768-2130
[email protected]
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
[email protected]
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064, Japan
0120 191014
+81 2666 8080
[email protected]
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate,
Tai Po, N.T., Hong Kong
+800 2666 8080
[email protected]
For Literature Requests Only:
Freescale Semiconductor
Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
(800) 441-2447
303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor
@hibbertgroup.com
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
MC145423/D
Similar pages