Renesas M62338P 8-bit 3ch i2c bus d/a converter with buffer amplifier Datasheet

M62333P/FP, M62338P/FP
8-bit 3ch I2C BUS D/A Converter with Buffer Amplifiers
REJ03D0865-0300
Rev.3.00
Jun 15, 2007
Description
The M62333/M62338 is an integrated circuit semiconductor of CMOS structure with 3 channels of built in D/A
converters with output buffer operational amplifiers.
The input is 2-wires serial method is used for the transfer format of digital data to allow connection with a
microcomputer with minimum wiring.
The output buffer operational amplifier employs AB class output circuit with sync and source drive capacity of 1.0 mA
or more, and it operates in the whole voltage range from VCC to ground.
The M62333 and the M62338 differ only in their slave address.
Features
• Digital data transfer format: I2C BUS serial data method
• Output buffer operational amplifier: It operates in the whole voltage range from VCC to ground.
• High output current drive capacity: ±1.0 mA over
Application
Conversion from digital data to analog control data for home-use and industrial equipment.
Signal gain control or automatic adjustment of Display-monitor or CTV.
Block Diagram
VCC
SCL
SDA
GND
8
7
6
5
I2C BUS transceiver
Power on
reset
Channel
decoder
8
8-bit latch
8-bit latch
8-bit latch
8-bit upper
segment R-2R
8-bit upper
segment R-2R
8-bit upper
segment R-2R
+ −
+ −
+ −
1
2
3
AO1
AO2
AO3
REJ03D0865-0300 Rev.3.00 Jun 15, 2007
Page 1 of 9
M62333P/FP, M62338P/FP
Pin Arrangement
M62333P/FP
M62338P
M62338FP
AO1
1
8
VCC
AO1
1
8
VCC
AO2
2
7
SCL
AO2
2
7
SCL
AO3
3
6
SDA
AO3
3
6
SDA
NC
4
5
GND
NC
4
5
GND
(Top view)
(Top view)
NC: No connection
NC: No connection
Outline: PRDP0008AA-A (8P4) [P]
Outline: PRSP0008DA-A (8P2S-A)
PRSP0008DE-C [FP] (recommend)
PRSP0008DA-A (8P2S-A) [FP] (not recommend for new design)
Pin Description
Pin No.
6
Pin Name
SDA
Function
Serial data input terminal
7
1
SCL
AO1
Serial clock input terminal
8-bit resolution D/A converter output terminal
2
3
AO2
AO3
8
5
VCC
GND
Power supply terminal
GND terminal
REJ03D0865-0300 Rev.3.00 Jun 15, 2007
Page 2 of 9
M62333P/FP, M62338P/FP
Absolute Maximum Ratings
Ratings
Unit
Supply voltage
Input voltage
Item
VCC
Vin
Symbol
–0.3 to 7.0
–0.3 to VCC + 0.3
V
V
Output voltage
Power dissipation
VO
Pd
–0.3 to VCC + 0.3
417 (P) / 272 (FP)
V
mW
Operating temperature
Storage temperature
Topr
Tstg
–20 to 85
–55 to 125
°C
°C
Electrical Characteristics
(VCC = +5 V ± 10%, GND = 0 V, Ta = –20 to 85°C unless otherwise noted)
Limits
Item
Symbol
Typ
5.0
Max
5.5
Unit
Supply voltage
VCC
Min
2.7
Supply current
ICC
0
0.9
2.7
mA
0
0.6
1.8
mA
V
Input leak current
Input low voltage
IILK
VIL
–10
—
—
—
10
0.2 VCC
µA
V
Input high voltage
Buffer amplifier output
voltage range
VIH
VAO
0.8 VCC
0.1
—
—
—
VCC – 0.1
V
V
Buffer amplifier output
drive range
IAO
0.2
–1.0
—
—
VCC – 0.2
1.0
V
mA
Differential nonlinearity
SDL
–1.0
—
1.0
LSB
Nonlinearity
Zero code error
SL
SZERO
–1.5
–2.0
—
—
1.5
2.0
LSB
LSB
Full scale error
Output capacitate load
SFULL
CO
–2.0
—
—
—
2.0
0.1
LSB
µF
Buffer amplifier output
impedance
RO
—
5.0
—
Ω
REJ03D0865-0300 Rev.3.00 Jun 15, 2007
Page 3 of 9
Test Conditions
CLK = 500 kHz operation, IAO = 0 µA
Data: 6Ah (at maximum current)
SDA = SCL = GND, IAO = 0 µA
VIN = 0 to VCC
IAO = ±100 µA
IAO = ±500 µA
Upper side saturation voltage = 0.3 V
Lower side saturation voltage = 0.2 V
VCC = 5.12 V (20 mV/LSB)
without load (IAO = 0)
M62333P/FP, M62338P/FP
I2C BUS Line Characteristics
Min
Max
Unit
SCL clock frequency
Time the bus must be free before a new transmission can start
Item
tSCL
tBUF
0
4.7
100
—
kHz
µs
Hold time START condition
(After this period, the first clock pulse is generated)
Low period of the clock
tHD:STA
4.0
—
µs
tLOW
4.7
—
µs
High period of the clock
Set-up time for START condition
(Only relevant for a repeated START condition)
tHIGH
tSU:STA
4.0
4.7
—
—
µs
µs
Hold time DATA
Set-up time DATA
tHD:DAT
tSU:DAT
0
250
—
—
µs
ns
Rise time of both SDA and SCL lines
Fall time of both SDA and SCL lines
tR
tF
—
—
1000
300
ns
ns
Set-up time for STOP condition
tSU:STO
4.0
—
µs
Note:
Symbol
Transmitter must internally provide at least a hold time to bridge the undefined region (300 ns Max) of the falling
edge of SCL.
Timing Chart
tR, tF
tBUF
VIH
SDA
VIL
tHD:STA
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
VIH
SCL
VIL
tLOW
tHIGH
Start
REJ03D0865-0300 Rev.3.00 Jun 15, 2007
Page 4 of 9
Start
Stop
Start
M62333P/FP, M62338P/FP
I2C BUS Format
STA
Note:
Slave address
W
A
Sub address
A
DAC data
A
STP
STA: start condition, A: affirmation bit, W: write (SDA = Low), STP: stop condition
• Slave address
M62333
M62338
First
1
Last
0
0
1
1
1
First
1
Last
1
0
0
1
1
1
0
• Sub address
First
X
Last
X
X
X
X
X
S1
Don't care
S0
Channel select data
S1
S0
0
0
Channel
select data
0
1
D7
0
ch3 selection
1
1
Don’t care
Last
LSB
D6
D5
D4
D3
D1
D2
D0
First
MSB
Last
LSB
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
:
1
1
0
0
0
0
:
1
1
0
0
0
0
:
1
1
0
0
0
0
:
1
1
0
0
0
0
:
1
1
0
0
0
0
:
1
1
0
0
1
1
:
1
1
0
1
0
1
:
0
1
REJ03D0865-0300 Rev.3.00 Jun 15, 2007
Page 5 of 9
ch1 selection
ch2 selection
1
• DAC data
First
MSB
Channel Selection
DAC output
VCC / 256 × 1
VCC / 256 × 2
VCC / 256 × 3
VCC / 256 × 4
:
VCC / 256 × 255
VCC
M62333P/FP, M62338P/FP
Timing Chart (Model)
<Start condition to slave address bit>
1
SDA
2
3
4
5
6
7
W
A
2
3
4
5
6
7
8
A
SCL
D/A
output
Start condition
<Sub address bit>
1
SDA
SCL
D/A
output
<DAC data bit to stop condition>
SDA
1
2
3
4
5
6
7
8
A
SCL
D/A
output
Stop
condition
• Start condition
With SCL at High, SDA line goes from High to Low
• Stop condition
With SCL at High, SDA line goes from Low to High
(Under normal circumstances, SDA is changed when SCL is Low)
• Acknowledge bit
The receiving IC has to pull down SDA line whenever receive slave data.
(The transmitting IC releases the SDA line just then transmit 8-bit data.)
Digital Data Formats
STA
Slave address
Sub address 2
A
W
DAC data 2
REJ03D0865-0300 Rev.3.00 Jun 15, 2007
Page 6 of 9
Sub address 1
A
A
A
Sub address n
DAC data 1
A
DAC data n
A
…………
A
STP
M62333P/FP, M62338P/FP
Precaution for Use
• Supply voltage terminal (VCC) is also used for D/A converter upper reference voltage setting. If ripple or spike is
input this terminal, accuracy of D/A conversion is down. So, when use this device, please connect capacitor among
VCC to GND for stable D/A conversion.
• This IC’s output amplifier has an advantage to capacitive load. So it’s no problem at device action when connect
capacitor (0.1 µF Max) among output to GND for every noise eliminate.
• Purchase of Renesas’s I2C components conveys a license under the Philips I2C Patent Rights to use these
components an I2C system, provided that the system conforms to I2C Standard Specification as defined by Philips.
Application Example
1 AO1
Analog output
terminals
VCC 8
5V
2 AO2
5V
3 AO3
SCL 7
SDA 6
4
REJ03D0865-0300 Rev.3.00 Jun 15, 2007
Page 7 of 9
+
10 µF
GND 5
MCU
M62333P/FP, M62338P/FP
Package Dimensions
RENESAS Code
PRDP0008AA-A
5
1
4
MASS[Typ.]
0.5g
c
*1
E
8
Previous Code
8P4
e1
JEITA Package Code
P-DIP8-6.3x8.84-2.54
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
*2
D
e1
D
E
A
A1
A2
bp
b2
b3
c
L
A1
A
A2
Reference
Symbol
SEATING PLANE
*3 b
3
*3 b
2
bp
e
e
L
JEITA Package Code
P-SOP8-4.4x4.85-1.27
RENESAS Code
PRSP0008DE-C
*1
Previous Code
—
Min Nom Max
7.32 7.62 7.92
8.7 8.9 9.1
6.15 6.3 6.45
4.5
0.51
3.3
0.4 0.5 0.6
0.9 1.0 1.3
1.4 1.5 1.8
0.22 0.27 0.34
15°
0°
2.29 2.54 2.79
3.0
MASS[Typ.]
0.1g
F
D
8
Dimension in Millimeters
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
5
c
*2
E
HE
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
Z
Reference
Symbol
4
1
e
*3
bp
x
M
A
A2
L1
A1
θ
L
y
Detail F
REJ03D0865-0300 Rev.3.00 Jun 15, 2007
Page 8 of 9
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Dimension in Millimeters
Min Nom Max
4.65 4.85 5.05
4.2
4.4 4.6
1.85
0.00 0.1 0.20
2.03
0.34 0.4 0.46
0.15 0.20 0.25
0°
8°
5.7 6.2 6.5
1.12 1.27 1.42
0.12
0.10
0.75
0.25 0.45 0.65
0.90
M62333P/FP, M62338P/FP
JEITA Package Code
P-SOP8-4.4x5-1.27
RENESAS Code
PRSP0008DA-A
MASS[Typ.]
0.07g
E
5
*1
HE
8
Previous Code
8P2S-A
F
1
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
4
Index mark
c
A2
*2
A1
D
L
A
Reference
Symbol
*3
e
bp
y
D
E
A2
A1
A
bp
c
Detail F
HE
e
y
L
REJ03D0865-0300 Rev.3.00 Jun 15, 2007
Page 9 of 9
Dimension in Millimeters
Min Nom Max
4.8 5.0 5.2
4.2 4.4 4.6
1.5
0.05
1.9
0.35 0.4 0.5
0.13 0.15 0.2
0°
10°
5.9 6.2 6.5
1.12 1.27 1.42
0.1
0.2 0.4 0.6
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