PROCESS CP555 Central Small Signal Transistor TM Semiconductor Corp. PNP - Saturated Switch Transistor Chip PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 15 X 10 MILS Die Thickness 8 MILS Base Bonding Pad Area 3.6 X 2.4 MILS Emitter Bonding Pad Area 3.6 X 2.4 MILS Top Side Metalization Al - 20,000Å Back Side Metalization Au - 15,000Å GEOMETRY GROSS DIE PER 4 INCH WAFER 75,330 PRINCIPAL DEVICE TYPES CMPT3640 CMPT4209 2N4209 BACKSIDE COLLECTOR 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R2 (1-August 2002) Central TM Semiconductor Corp. 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com PROCESS CP555 Typical Electrical Characteristics R2 (1-August 2002)