Holtek HT1620 Ram mapping 32x4 lcd controller for i/o c Datasheet

HT1620
RAM Mapping 32´4 LCD Controller for I/O mC
Features
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Logic operating voltage: 2.4V~3.3V
LCD voltage: 3.6V~4.9V
Low operating current <3mA at 3V
External 32.768kHz crystal oscillator
Selection of 1/2 or 1/3 bias, and selection of
1/2 or 1/3 or 1/4 duty LCD applications
Internal time base frequency sources
Two selectable buzzer frequencies
(2kHz/4kHz)
Built-in capacitor type bias charge pump
Time base or WDT overflow output
·
·
·
·
·
·
·
·
·
8 kinds of time base/WDT clock source
32´4 LCD driver
Built-in 32´4-bit display RAM
3-wire serial interface
Internal LCD driving frequency source
Software configuration feature
R/W address auto increment
Data mode and command mode
instructions
Three data accessing modes
General Description
for the interface between the host controller
and the HT1620. The HT1620 consumes low
operating current owing to adopting capacitor
type bias charge pump. The HT162X series
have many kinds of products that match various applications.
The HT1620 is a 128 pattern (32´4), memory
mapping, and multi-function LCD driver. The
S/W configuration feature of the HT1620
makes it suitable for multiple LCD applications including LCD modules and display subsystems. Only three or four lines are required
Selection Table
HT162X
HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270
COM
4
4
8
8
8
8
16
16
16
SEG
32
32
32
32
48
64
48
64
64
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Built-in Osc.
Crystal Osc.
Ö
Ö
Ö
1
Ö
July 26, 1999
HT1620
Block Diagram
D is p la y R A M
O S C O
O S C I
C S
R D
W R
C o n
a n
T im
C ir c
tro l
d
in g
u it
C O M 0
L C D D r iv e r /
B ia s C ir c u it
C O M 3
S E G 0
D A T A
V D D
S E G 3 1
V S S
C C 1
C C 2
V O 1 5 N
V E E
B Z
B Z
T o n e F re q u e n c y
G e n e ra to r
W a tc h d o g T im e r
&
T im e B a s e G e n e r a to r
IR Q
Notes: CS: Chip selection
BZ, BZ: Tone outputs
WR, RD, DATA: Serial interface
COM0~COM3, SEG0~SEG31: LCD outputs
IRQ: Time base or WDT overflow output
VO15N: Half voltage circuit output pin
VEE: Double voltage circuit output pin
CC1/CC2: External capacitor pin, for double voltage and half voltage circuit use
2
July 26, 1999
HT1620
Pin Assignment
C S
R D
W R
D A T A
V S S
O S C O
O S C I
V D D
IR Q
B Z
B Z
C C 1
N C
6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2
1
5 1
2
5 0
N C
3
4 9
4
N C
4 8
5
4 7
6
4 6
7
4 5
8
4 4
N C
C
V O 1
V
C O
C O
C O
C O
S E
S E
S E
S E
S E
S E
S E
S E
S E
N C
C 2
5 N
E E
M 0
M 1
M 2
M 3
G 0
G 1
G 2
G 3
G 4
G 5
G 6
G 7
G 8
N C
9
4 3
H T 1 6 2 0
6 4 Q F P
1 0
1 1
4 2
4 1
1 2
4 0
1 3
3 9
1 4
3 8
1 5
3 7
1 6
3 6
1 7
3 5
1 8
1 9
3 4
2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
3 3
N C
N C
N C
N C
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
N C
G 3 1
G 3 0
G 2 9
G 2 8
G 2 7
G 2 6
G 2 5
G 2 4
G 2 3
G 2 2
G 2 1
G 2 0
N C
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
N C
G 1 9
G 1 8
G 1 7
G 1 6
G 1 5
G 1 4
G 1 3
G 1 2
G 1 1
G 1 0
G 9
3
July 26, 1999
HT1620
Pad Assignment
C C 1
B Z
B Z
IR Q
V D D
O S C I
O S C O
V S S
D A T A
W R
R D
C S
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
1
C C 2
V O 1 5 N
2
V E E
3
C O M 0
4
C O M 1
5
6
C O M 2
C O M 3
7
S E G 0
8
S E G 1
9
S E G 2
S E G 3
3 9
S E G 3 1
3 8
S E G 3 0
1 0
3 7
S E G 2 9
1 1
3 6
S E G 2 8
S E G 4
1 2
3 5
S E G 2 7
S E G 5
1 3
3 4
S E G 2 6
3 3
S E G 2 5
3 2
S E G 2 4
(0 ,0 )
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
S E G 6
S E G 7
S E G 8
S E G 9
S E G 1 0
S E G 1 1
S E G 1 2
S E G 1 3
S E G 1 4
S E G 1 5
S E G 1 6
S E G 1 7
S E G 1 8
S E G 1 9
Chip size: 142 ´ 141 (mil)
3 1
S E G 2 3
3 0
S E G 2 2
2 9
S E G 2 1
2 8
S E G 2 0
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
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July 26, 1999
HT1620
Pad Coordinates
Unit: mil
Pad No.
X
Y
Pad No.
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
-61.58
-61.83
-61.83
-61.83
-61.83
-61.83
-61.83
-61.83
-61.83
-61.83
-61.83
-61.83
-61.83
-60.90
-54.27
-47.64
-41.01
-34.38
-27.75
-21.12
-14.49
-7.86
-1.23
5.40
12.03
18.66
63.62
50.83
43.73
37.10
30.47
23.84
17.21
10.58
3.95
-2.68
-9.31
-15.94
-22.57
-64.26
-64.26
-64.26
-64.26
-64.26
-64.26
-64.26
-64.26
-64.26
-64.26
-64.26
-64.26
-64.26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
25.29
66.98
66.98
66.98
66.98
66.98
66.98
66.98
66.98
66.98
66.98
66.98
66.98
65.71
59.08
52.45
40.59
29.75
22.95
16.32
9.56
-2.21
-21.80
-39.52
-49.60
-64.26
-62.65
-56.01
-49.38
-42.76
-36.13
-29.50
-22.86
-16.24
-9.60
-2.97
3.65
10.28
64.39
64.39
64.39
64.39
64.39
64.39
64.39
64.39
64.30
64.39
64.39
63.62
5
July 26, 1999
HT1620
Pad Description
Pad No.
Pad Name
I/O
Description
2
VO15N
O
Half voltage circuit output pin
3
VEE
¾
Double voltage circuit output pin
4~7
COM0~COM3
O
LCD common outputs
8~39
SEG0~SEG31
O
LCD segment outputs
I
Chip selection input with pull-high resistor
When the CS is logic high, the data and command, read from or
written to the HT1620 are disabled. The serial interface circuit is
also reset. But if the CS is at logic low level and is input to the CS
pad, the data and command transmission between the host controller and the HT1620 are all enabled.
40
CS
41
RD
I
READ clock input with pull-high resistor
Data in the RAM of the HT1620 are clocked out on the falling
edge of the RD signal. The clocked out data will appear on the
DATA line. The host controller can use the next raising edge to
latch the clocked out data.
42
WR
I
WRITE clock input with pull-high resistor
Data on the DATA line are latched into the HT1620 on the rising
edge of the WR signal.
43
DATA
I/O
Serial data input/output with pull-high resistor
44
VSS
¾
Negative power supply, Ground
45
OSCO
O
46
OSCI
I
The OSCI and OSCO pads are connected to a 32.768kHz crystal
in order to generate a system clock.
47
VDD
¾
Positive power supply
48
IRQ
O
Time base or WDT overflow flag, NMOS open drain output
49, 50
BZ, BZ
O
2kHz or 4kHz tone frequency output pair (tri-state output buffer)
51, 1
CC1, CC2
I
External capacitor pin, for double voltage and half voltage circuit
use
Absolute Maximum Ratings
o
o
Supply Voltage..............................-0.3V to 3.6V
Storage Temperature.................-50 C to 125 C
Input Voltage .................VSS-0.3V to VDD+0.3V
Operating Temperature...............-25 C to 75 C
o
o
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
6
July 26, 1999
HT1620
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
¾
Min.
Typ.
Max.
Unit
2.4
¾
3.3
V
VDD
Operating Voltage
¾
IDD
Operating Current
3V
No load*
¾
2
3
mA
ISTB
Standby Current
3V
No load*
¾
¾
1
mA
VIL
Input Low Voltage
3V
DATA, WR, CS, RD
¾
¾
0.6
V
VIH
Input High Voltage
3V
DATA, WR, CS, RD
2.4
¾
3.0
V
IOL1
DATA, BZ, BZ, IRQ
3V
VOL=0.3V
0.8
1.6
¾
mA
IOH1
DATA, BZ, BZ
3V
VOH=2.7V
-0.6
-1.2
¾
mA
IOL2
LCD Common Sink
Current
3V
VOL=0.3V
80
150
¾
mA
IOH2
LCD Common Source
Current
3V
VOH=2.7V
-70
-120
¾
mA
IOL3
LCD Segment Sink
Current
3V
VOL=0.3V
70
140
¾
mA
IOH3
LCD Segment Source
Current
3V
VOH=2.7V
-30
-60
¾
mA
RPH
Pull-high Resister
3V
DATA, WR, CS, RD
40
80
150
kW
* No load: LCD OFF, Buzzer OFF, CS=WR=RD=High
A.C. Characteristics
Symbol
fSYS
Parameter
Ta=25°C
Test Conditions
VDD
System Clock
3V
LCD Frame Frequency
¾
LCD Frame Frequency 1/2 Duty
¾
LCD Frame Frequency 1/3 Duty
¾
LCD Frame Frequency 1/4 Duty
¾
tCOM
LCD Common Period
¾
fCLK
Serial Data Clock
3V
fTONE
Tone Frequency
¾
fLCD
7
Conditions
Crystal 32kHz
Min.
Typ. Max. Unit
¾
32
¾
kHz
¾
64
¾
Hz
¾
64
¾
Hz
¾
56
¾
Hz
¾
64
¾
Hz
n: Number of COM
¾
n/fLCD
¾
s
Write mode
¾
¾
150
kHz
Read mode
¾
¾
75
kHz
¾
¾
2 or 4
¾
kHz
Crystal 32kHz
July 26, 1999
HT1620
Symbol
Test Conditions
Parameter
tCS
Serial Interface Reset Pulse
Width
(Figure 3)
¾
tCLK
WR, RD Input Pulse Width
(Figure 1)
3V
tr, tf
Rise/Fall Time Serial Data Clock
Width
(Figure 1)
3V
tsu
Setup Time for DATA to WR, RD
Clock Width
(Figure 2)
th
Min.
Conditions
VDD
CS
Typ. Max. Unit
¾
250
¾
ns
Write mode
3.34
¾
¾
Read mode
6.67
¾
¾
¾
¾
120
¾
ns
3V
¾
¾
120
¾
ns
Hold Time for DATA to WR, RD
Clock Width
(Figure 2)
3V
¾
¾
120
¾
ns
tsu1
Setup Time for CS to WR,RD
Clock Width
(Figure 3)
3V
¾
¾
100
¾
ns
th1
Hold Time for CS to WR, RD Clock
Width
(Figure 3)
3V
¾
¾
100
¾
ns
ms
V A L ID D A T A
D B
tf
W R , R D
C lo c k
tr
9 0 %
5 0 %
1 0 %
tC
V
G N D
tC
L K
ts
D D
W R , R D
C lo c k
L K
Figure 1
W R , R D
C lo c k
S
V
th
u 1
5 0 %
F IR S T
C lo c k
5 0 %
V
D D
G N D
G N D
1
V
L A S T
C lo c k
th
u
D D
5 0 %
ts
D D
G N D
Figure 2
tC
C S
V
5 0 %
D D
G N D
Figure 3
8
July 26, 1999
HT1620
Functional Description
Display memory - RAM structure
Buzzer tone output
The static display RAM is organized into 32´4
bits and stores the display data. The contents of
the RAM are directly mapped to the contents of
the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MOD
IFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns.
A simple tone generator is implemented in the
HT1620. The tone generator can output a pair
of differential driving signals on the BZ and BZ
which are used to generate a single tone.
C O M 3
C O M 2
C O M 1
0
S E G 1
1
S E G 2
2
S E G 3
3
S E G 3 1
3 1
3
D
2
D
The HT1620 is a 128 (32´4) pattern LCD driver.
It can be configured as 1/2 or 1/3 bias and 2 or 3
or 4 commons of LCD driver by the S/W configuration. This feature makes the HT1620 suitable
for multiple LCD applications. The LCD driving
clock is derived from the system clock. The value
of the driving clock is always 256Hz even when it
is at a 32.768kHz crystal oscillator frequency. The
LCD corresponding commands are summarized
in the table.
C O M 0
S E G 0
D
LCD driver
1
D
0
A d d r e s s 6 b its
(A 5 , A 4 , ..., A 0 )
The bold form of 1 0 0, namely 1 0 0, indicates
the command mode ID. If successive commands
have been issued, the command mode ID will be
omitted, except for the first command. The LCD
OFF command turns the LCD display off by disabling the LCD bias generator. The LCD ON
command, on the other hand, turns the LCD
display on by enabling the LCD bias generator.
The BIAS and COM are the LCD panel related
commands. With the use of the LCD related
commands, the HT1620 can be compatible with
most types of LCD panels.
A d d r
D a ta
D a ta 4 b its
(D 3 , D 2 , D 1 , D 0 )
RAM mapping
Time base and watchdog timer - WDT
The time base generator and WDT share the
same divided (/256) counter. TIMER DIS/EN/CLR,
WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT
time-out occurs, the IRQ pin will stay at a logic
low level until the CLR WDT or the IRQ DIS
command is issued.
T im e B a s e
T IM E R
/2 5 6
C lo c k S o u r c e
V D D
C L R
T im e r
W D T
/4
Q
D
C K
C L R
IR Q
E N /D IS
W D T E N /D IS
IR Q
E N /D IS
R
W D T
Timer and WDT configurations
9
July 26, 1999
HT1620
Name
Command Code
Function
LCD OFF
10000000010X
Turn off LCD outputs
LCD ON
10000000011X
Turn on LCD outputs
1000010abXcX
c=0: 1/2 bias option
c=1: 1/3 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
BIAS and COM
Command format
Interfacing
The HT1620 can be configured by the S/W setting. There are two mode commands to configure
the HT1620 resources and to transfer the LCD
display data. The configuration mode of the
HT1620 is called command mode, and its command mode ID is 1 0 0. The command mode consists of a system configuration command, a
system frequency selection command, an LCD
configuration command, a tone frequency selection command, a timer/WDT setting command,
and an operating command. The data mode, on
the other hand, includes READ, WRITE, and
READ-MODIFY-WRITE operations. The following are the data mode IDs and the command
mode ID:
Only four lines are required to interface with
the HT1620. The CS line is used to initialize the
serial interface circuit and to terminate the communication between the host controller and the
HT1620. If the CS pin is set to 1, the data and
command issued between the host controller and
the HT1620 are first disabled and then initialized. Before issuing a mode command or mode
switching, a high level pulse is required to initialize the serial interface of the HT1620. The DATA
line is the serial data input/output line. Data to
be read or written or commands to be written
have to be passed through the DATA line. The RD
line is the READ clock input. Data in the RAM
are clocked out on the falling edge of the RD signal, and the clocked out data will then appear on
the DATA line. It is recommended that the host
controller read in correct data during the interval
between the rising edge and the next falling edge
of the RD signal. The WR line is the WRITE clock
input. The data, address, and command on the
DATA line are all clocked into the HT1620 on the
rising edge of the WR signal. There is an optional
IRQ line to be used as an interface between the
host controller and the HT1620. The IRQ pin can
be selected as a timer output or a WDT overflow
flag output by the S/W setting. The host controller can perform the time base or the WDT function by connecting with the IRQ pin of the
HT1620.
Operation
Mode
ID
READ
Data
110
WRITE
Data
101
READ-MODIFY-WRITE
Data
101
COMMAND
Command 1 0 0
The mode command should be issued before the
data or command is transferred. If successive
commands have been issued, the command
mode ID, 1 0 0, can be omitted. While the system is operating in the non-successive command or the non-successive address data mode,
the CS pin should be set to ²1² and the previous
operation mode will be reset also. Once the CS
pin returns to ²0², a new operation mode ID
should be issued first.
10
July 26, 1999
HT1620
Timing Diagrams
READ mode (command code: 1 1 0)
C S
W R
R D
D A T A
1
0
1
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s 1 (M A 1 )
D 0 D 1 D 2 D 3
D a ta (M A 1 )
1
0
1
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s 2 (M A 2 )
D 0 D 1 D 2 D 3
D a ta (M A 2 )
READ mode (successive address reading)
C S
W R
R D
1
D A T A
1
0
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s (M A )
D 0 D 1 D 2 D 3
D a ta (M A )
D 0 D 1 D 2 D 3
D a ta (M A + 1 )
D 0 D 1 D 2 D 3
D a ta (M A + 2 )
D 0 D 1 D 2 D 3
D a ta (M A + 3 )
D 0
WRITE mode (command code: 1 0 1)
C S
W R
D A T A
1
0
1
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s 1 (M A 1 )
D 0 D 1 D 2 D 3
D a ta (M A 1 )
11
1
0
1
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s 2 (M A 2 )
D 0 D 1 D 2 D 3
D a ta (M A 2 )
July 26, 1999
HT1620
WRITE mode (successive address writing)
C S
W R
1
D A T A
1
0
A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0
M e m o ry A d d re s s (M A ) D a ta (M A )
D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 )
Note: It is recommended that the host controller should read with the data from the DATA line
between the raising edge of the RD line and the falling edge of the next RD line.
READ-MODIFY-WRITE mode (command code: 1 0 1)
C S
W R
R D
D A T A
1
1
0
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s 1 (M A 1 )
D 0 D 1 D 2 D 3
D a ta (M A 1 )
D 0 D 1 D 2 D 3
D a ta (M A 1 )
1
0
1
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s 2 (M A 2 )
D 0 D 1 D 2 D 3
D a ta (M A 2 )
READ-MODIFY-WRITE mode (successive address accessing)
C S
W R
R D
D A T A
1
0
1
A 5 A 4 A 3 A 2 A 1 A 0
M e m o ry A d d re s s (M A )
D 0 D 1 D 2 D 3
D a ta (M A )
D 0 D 1 D 2 D 3
D a ta (M A )
12
D 0 D 1 D 2 D 3
D a ta (M A + 1 )
D 0 D 1 D 2 D 3
D a ta (M A + 1 )
D 0 D 1 D 2 D 3
D a ta (M A + 2 )
D 0
July 26, 1999
HT1620
Command mode (command code: 1 0 0)
C S
W R
D A T A
1
0
0
C 8
C 7 C 6
C 5 C 4 C 3 C 2 C 1
C o m m a n d 1
C 0
C 8
C o m m a n d ...
C 7 C 6
C 5 C 4 C 3 C 2 C 1
C o m m a n d i
C 0
C o m m a n d
o r
D a ta M o d e
Mode (data and command mode)
C S
W R
D A T A
C o m m a n d
o r
D a ta M o d e
A d d re s s a n d D a ta
C o m m a n d
o r
D a ta M o d e
A d d re s s a n d D a ta
C o m m a n d
o r
D a ta M o d e
A d d re s s a n d D a ta
R D
13
July 26, 1999
HT1620
Application Circuits
V D D
0 .1 m F
C C 1
C C 2
V D D
0 .1 m F
3 M W
V O 1 5 N
0 .1 m F
V E E
C S
*
O S C I
R D
W R
D A T A
m C
*
H T 1 6 2 0
O S C O
C ry s ta l
3 2 7 6 8 H z
O s c illa to r
B Z
R
P ie z o
IR Q
C O M 0 ~ C O M 3
S E G 0 ~ S E G 3 1
B Z
1 /2 o r 1 /3 B ia s ; 1 /2 , 1 /3 o r 1 /4 D u ty
L C D P a n e l
* Notes: The connection of the IRQ and RD pin is selectable depending on the requirement of the mC.
VDD=2.4V~3.3V, VEE=-1/2 VDD, VLCD (LCD voltage)=VDD-VEE=3/2 VDD=3.6V~4.9V.
Adjust R (external pull-high resistance) to fit user¢s time base clock.
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July 26, 1999
HT1620
Command Summary
Name
ID
Command Code
D/C
Function
Def.
READ
1 1 0 A5A4A3A2A1A0D0D1D2D3
D
Read data from the RAM
WRITE
1 0 1 A5A4A3A2A1A0D0D1D2D3
D
Write data to the RAM
READ
MODIFY
WRITE
1 0 1 A5A4A3A2A1A0D0D D2D3
D
Read and write to the RAM
SYS DIS
1 0 0 0000-0000-X
C
Turn off both system oscillator
and LCD bias generator
SYS EN
1 0 0 0000-0001-X
C
Turn on system oscillator
LCD OFF
1 0 0 0000-0001-X
C
Turn off LCD bias generator
LCD ON
1 0 0 0000-0011-X
C
Turn on LCD bias generator
TIMER DIS 1 0 0 0000-0100-X
C
Disable time base output
Yes
WDT DIS
1 0 0 0000-0101-X
C
Disable WDT time-out flag
output
Yes
TIMER EN
1 0 0 0000-0010-X
C
Enable time base output
WDT EN
1 0 0 0000-0111-X
C
Enable WDT time-out flag
output
TONE OFF
1 0 0 0000-1000-X
C
Turn off tone outputs
CLR TIMER 1 0 0 0000-1101-X
C
Clear the contents of the time base
generator
CLR WDT
C
Clear the contents of the WDT
stage
C
LCD 1/2 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
BIAS 1/2
1 0 0 0000-111X-X
1 0 0 0010-abX0-X
BIAS 1/3
1 0 0 0010-abX1-X
C
LCD 1/3 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
TONE 4K
1 0 0 010X-XXXX-X
C
Tone frequency, 4kHz
TONE 2K
1 0 0 0110-XXXX-X
C
Tone frequency, 2kHz
IRQ DIS
1 0 0 100X-0XXX-X
C
Disable IRQ output
IRQ EN
1 0 0 100X-1XXX-X
C
Enable IRQ output
15
Yes
Yes
Yes
Yes
July 26, 1999
HT1620
Name
ID
Command Code
D/C
Function
Def.
F1
1 0 0 101X-0000-X
C
Time base clock output: 1Hz
The WDT time-out flag after: 4s
F2
1 0 0 101X-0001-X
C
Time base clock output: 2Hz
The WDT time-out flag after: 2s
F4
1 0 0 101X-0010-X
C
Time base clock output: 4Hz
The WDT time-out flag after: 1s
F8
1 0 0 101X-0011-X
C
Time base clock output: 8Hz
The WDT time-out flag after: 1/2 s
F16
1 0 0 101X-0100-X
C
Time base clock output: 16Hz
The WDT time-out flag after: 1/4 s
F32
1 0 0 101X-0101-X
C
Time base clock output: 32Hz
The WDT time-out flag after: 1/8 s
F64
1 0 0 101X-0110-X
C
Time base clock output: 64Hz
The WDT time-out flag after: 1/16 s
F128
1 0 0 101X-0111-X
C
Time base clock output: 128Hz
The WDT time-out flag after:1/32 s
TEST
1 0 0 1110-0000-X
C
Test mode, user don¢t use.
NORMAL
1 0 0 1110-0011-X
C
Normal mode
Yes
Yes
,
Notes: X : Don t care
A5~A0 : RAM addresses
D3~D0 : RAM data
D/C : Data/command mode
Def. : Power on reset default
All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the
command mode ID. If successive commands have been issued, the command mode ID except for the
first command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from a 32.768kHz crystal oscillator. Calculation of the frequency is based on
the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1620 after power on reset, for power on reset may fail, which in turn leads to malfunctioning of the HT1620.
16
July 26, 1999
HT1620
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Microelectronics Enterprises Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Copyright Ó 1999 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
17
July 26, 1999
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