Cypress CY62137FV30 2-mbit (128 k x 16) static ram automatic power down when deselected Datasheet

CY62137FV30 MoBL®
2-Mbit (128 K × 16) Static RAM
2-Mbit (128 K × 16) Static RAM
Features
■
Very high speed: 45 ns
■
Temperature ranges
❐ Industrial: –40 °C to +85 °C
■
Wide voltage range: 2.20 V–3.60 V
■
Pin
compatible
with
CY62137CV/CV25/CV30/CV33,
CY62137V, and CY62137EV30
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 5 A (Industrial)
■
Ultra low active power
❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Byte power down feature
■
Available in Pb free 48-ball very fine-pitch ball grid array
(VFBGA) and 44-pin thin small outline package (TSOP) II
package
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input and output pins (I/O0 through I/O15) are placed
in a high impedance state in the following conditions when the
device is deselected (CE HIGH), the outputs are disabled (OE
HIGH), both the Byte High Enable and the Byte Low Enable are
disabled (BHE, BLE HIGH), or during an active write operation
(CE LOW and WE LOW).
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A16).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW, while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
Functional Description
The CY62137FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
128K x 16
RAM Array
Cypress Semiconductor Corporation
Document Number: 001-07141 Rev. *J
•
A16
A15
A14
A13
A11
A12
CE
BHE
BLE
198 Champion Court
I/O8–I/O15
BHE
WE
CE
OE
BLE
COLUMN DECODER
POWER DOWN
CIRCUIT
I/O0–I/O7
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 16, 2011
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CY62137FV30 MoBL®
Contents
Product Portfolio .............................................................. 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Document Number: 001-07141 Rev. *J
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Page 2 of 16
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CY62137FV30 MoBL®
Product Portfolio
Power Dissipation
Product
VCC Range (V)
Range
CY62137FV30LL Industrial
Speed
(ns)
Min
Typ [1]
Max
2.2 V
3.0 V
3.6 V
45
Operating ICC (mA)
f = 1MHz
f = fmax
Standby ISB2 (A)
Typ [1]
Max
Typ [1]
Max
Typ [1]
Max
1.6
2.5
13
18
1
5
Pin Configuration
Figure 1. 48-Ball VFBGA Pinout [2, 3]
Figure 2. 44-Pin TSOP II [2]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS I/O11
NC
A7
VCC
D
VCC
NC
A16
I/O4
VSS
E
I/O14 I/O13 A14
A15
I/O5
I/O6
F
I/O12
I/O3
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, H6 and H3 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb and 64 Mb respectively.
Document Number: 001-07141 Rev. *J
Page 3 of 16
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CY62137FV30 MoBL®
DC input voltage [5] ........................................–0.3 V to 3.9 V
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Supply voltage to ground
potential .........................................................–0.3 V to 3.9 V
DC voltage applied to outputs
in High Z state [4, 5] ........................................–0.3 V to 3.9 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage ......................................... > 2001 V
(MIL–STD–883, method 3015)
Latch up current ..................................................... > 200 mA
Operating Range
Device
CY62137FV30LL
Ambient
VCC[6]
Temperature
Industrial –40 °C to +85 °C 2.2 V to 3.6 V
Range
Electrical Characteristics
Over the Operating Range
Parameter
Description
VOH
Output high voltage
VOL
Output low voltage
VIH
Input high voltage
VIL
Input low voltage
IIX
IOZ
ICC
Input leakage current
Output leakage current
VCC operating supply
current
ISB1[8]
Automatic power-down
current – CMOS inputs
ISB2 [8]
Automatic power-down
current – CMOS inputs
Test Conditions
2.2 < VCC < 2.7
IOH = –0.1 mA
IOH = –1.0 mA
2.7 < VCC < 3.6
2.2 < VCC < 2.7
IOL = 0.1 mA
IOL = 2.1 mA
2.7 < VCC < 3.6
2.2 < VCC < 2.7
2.7 < VCC < 3.6
2.2 < VCC < 2.7
2.7 < VCC < 3.6
GND < VI < VCC
GND < VO < VCC, Output disabled
f = fmax = 1/tRC
VCC = VCC(max)
IOUT = 0 mA
f = 1 MHz
CMOS levels
CE > VCC –0.2 V, or
(BHE and BLE) > VCC–0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE and WE), VCC = VCC(max)
CE > VCC – 0.2 V or
(BHE and BLE) > VCC–0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
Min
2.0
2.4
–
–
1.8
2.2
–0.3
–0.3
–1
–1
–
–
45 ns (Industrial)
Typ [7]
Max
–
–
–
–
–
0.4
–
0.4
–
VCC + 0.3
–
VCC + 0.3
–
0.6
–
0.8
–
+1
–
+1
13
18
1.6
2.5
Unit
V
V
V
V
V
V
V
V
A
A
mA
–
1
5
A
–
1
5
A
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max)=VCC + 0.75 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
Document Number: 001-07141 Rev. *J
Page 4 of 16
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CY62137FV30 MoBL®
Capacitance
Parameter [9]
Description
Input capacitance
CIN
Output capacitance
COUT
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
10
10
Unit
pF
pF
Thermal Resistance
Parameter [9]
Description
JA
Thermal resistance
(Junction to ambient)
JC
Thermal resistance
(Junction to case)
Test Conditions
48-ball VFBGA 44-pin TSOP II Unit
Still air, soldered on a 3 × 4.5 inch, two
layer printed circuit board
75
77
C/W
10
13
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
VCC
Output
10%
Including
JIG and
Scope
90%
GND
Rise Time = 1 V / ns
R2
30 pF
Parameters
R1
R2
RTH
VTH
All Input Pulses
VCC
90%
10%
Fall Time = 1 V / ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
V
2.5 V (2.2 V to 2.7 V)
16667
15385
8000
1.20
3.0 V (2.7 V to 3.6 V)
1103
1554
645
1.75
Unit



V
Notes
9. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-07141 Rev. *J
Page 5 of 16
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CY62137FV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
Conditions
VCC for data retention
[11]
Data retention current
tCDR [12]
Chip deselect to data
retention time
tR [13]
Operation recovery time
VCC = 1.5 V, CE > VCC – 0.2 V, or
(BHE and BLE) > VCC –0.2 V
VIN > VCC – 0.2 V or VIN < 0.2 V
Industrial
CY62137FV30LL-45
Min
Typ [10]
Max
Unit
1.5
–
–
V
–
–
4
A
0
–
–
ns
45
–
–
ns
Data Retention Waveform
Figure 4. Data Retention Waveform [14]
VCC
CE or
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.5 V
VCC(min)
tR
BHE.BLE
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document Number: 001-07141 Rev. *J
Page 6 of 16
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CY62137FV30 MoBL®
Switching Characteristics
Parameter [15, 16]
Description
45 ns (Industrial)
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
5
–
ns
[17]
tLZOE
OE LOW to low Z
tHZOE
OE HIGH to high Z [17, 18]
–
18
ns
tLZCE
CE LOW to low Z [17]
10
–
ns
tHZCE
CE HIGH to high Z [17, 18]
–
18
ns
tPU
CE LOW to power up
0
–
ns
tPD
CE HIGH to power down
–
45
ns
tDBE
BLE/BHE LOW to data valid
–
45
ns
tLZBE
BLE/BHE LOW to low Z [17, 19]
5
–
ns
–
18
ns
tHZBE
Write Cycle
BLE/BHE HIGH to high Z
[17, 18]
[20]
tWC
Write cycle time
45
–
ns
tSCE
CE LOW to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tBW
BLE/BHE LOW to write end
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to high Z [17, 18]
–
18
ns
10
–
ns
tLZWE
WE HIGH to low Z
[17]
Notes
15. Test conditions for all parameters, other than tristate parameters, assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 5.
16. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further
clarification.
17. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
19. If both byte enables are toggled together, this value is 10 ns.
20. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these
signals terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
Document Number: 001-07141 Rev. *J
Page 7 of 16
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CY62137FV30 MoBL®
Switching Waveforms
Figure 5. Read Cycle 1: Address Transition Controlled [21, 22]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle 2: OE Controlled [22, 23]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
21. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
22. WE is HIGH for read cycle.
23. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 001-07141 Rev. *J
Page 8 of 16
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CY62137FV30 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle 1: WE Controlled [24, 25, 26]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 27
tHD
DATAIN
tHZOE
Figure 8. Write Cycle 2: CE Controlled [24, 25, 26]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 27
tHZOE
Notes
24. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these
signals terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
25. Data I/O is high impedance if OE = VIH.
26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
27. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-07141 Rev. *J
Page 9 of 16
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CY62137FV30 MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle 3: WE Controlled, OE LOW [28]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA I/O
NOTE 29
tHD
DATAIN
tLZWE
tHZWE
Figure 10. Write Cycle 4: BHE/BLE Controlled, OE LOW [28]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 29
tSD
tHD
DATAIN
tLZWE
Notes
28. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
29. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-07141 Rev. *J
Page 10 of 16
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CY62137FV30 MoBL®
Truth Table
CE
X
WE
OE
BHE
BLE
[30]
[30]
High Z
Deselect or power-down
Standby (ISB)
X
Inputs or Outputs
Mode
Power
H
X
X
[30]
X
X
H
H
High Z
Deselect or power-down
Standby (ISB)
L
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
H
H
L
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
High Z
Output disabled
Active (ICC)
L
H
H
L
H
High Z
Output disabled
Active (ICC)
L
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
X
Note
30. The ‘X’ (Don’t care) state for the Chip enable (CE) and Byte enables (BHE and BLE) in the truth table refer to the logic state (either HIGH or LOW). Intermediate
voltage levels on these pins is not permitted.
Document Number: 001-07141 Rev. *J
Page 11 of 16
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CY62137FV30 MoBL®
Ordering Information
Speed
(ns)
45
Ordering Code
CY62137FV30LL-45BVI
Package
Diagram
Package Type
51-85150 48-ball VFBGA
CY62137FV30LL-45BVXI
48-ball VFBGA (Pb-free)
CY62137FV30LL-45ZSXI
51-85087 44-pin TSOP II (Pb-free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 3
7
F V30 LL - 45 XX X
I
Temperature Grade: I = Industrial
Pb-free
Package Type: XX = BV or ZS
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
Speed Grade: 45 ns
Low Power
Voltage Range: 3 V typical
Process Technology: 90 nm
Bus width = × 16
Density = 2-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-07141 Rev. *J
Page 12 of 16
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CY62137FV30 MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 x 8 x 1.0 mm) BV48/BZ48, 51-85150
51-85150 *F
Document Number: 001-07141 Rev. *J
Page 13 of 16
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CY62137FV30 MoBL®
Package Diagrams (continued)
Figure 12. 44-pin TSOP Z44-II, 51-85087
PIN 1 I.D.
11.938 (0.470)
11.735 (0.462)
10.262 (0.404)
10.058 (0.396)
1
22
Z Z Z
Z X Z
AA
44
23
BOTTOM VIEW
TOP VIEW
0.400(0.016)
0.300 (0.012)
0.800 BSC
(0.0315)
EJECTOR MARK
(OPTIONAL)
CAN BE LOCATED
ANYWHERE IN THE
BOTTOM PKG
BASE PLANE
10.262 (0.404)
10.058 (0.396)
0.10 (.004)
18.517 (0.729)
18.313 (0.721)
0.150 (0.0059)
0.050 (0.0020)
1.194 (0.047)
0.991 (0.039)
0.210 (0.0083)
0.120 (0.0047)
0°-5°
SEATING
PLANE
0.597 (0.0235)
0.406 (0.0160)
DIMENSION IN MM (INCH)
MAX
MIN.
Acronyms
Acronym
51-85087-*C
Document Conventions
Description
Units of Measure
BLE
byte low enable
BHE
byte high enable
°C
degree Celsius
CE
chip enable
MHz
Mega Hertz
CMOS
complementary metal oxide semiconductor
A
micro Amperes
I/O
input/output
s
micro seconds
OE
output enable
mA
milli Amperes
SRAM
static random access memory
mm
milli meter
TSOP
thin small outline package
ns
nano seconds
VFBGA
very fine-pitch ball grid array
%
percent
WE
write enable
pF
pico Farads

ohms
V
Volts
W
Watts
Document Number: 001-07141 Rev. *J
Symbol
Unit of Measure
Page 14 of 16
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CY62137FV30 MoBL®
Document History Page
Document Title: CY62137FV30 MoBL®, 2-Mbit (128 K × 16) Static RAM
Document Number: 001-07141
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
449438
See ECN
NXR
New datasheet
*A
464509
See ECN
NXR
Changed the ISB2(typ) value from 1.0 A to 0.5 A
Changed the ISB2(max) value from 4 A to 2.5 A
Changed the ICC(typ) value from 2 mA to 1.6 mA and ICC(max) value from
2.5 mA to 2.25 mA for f=1 MHz test condition
Changed the ICC(typ) value from 15 mA to 13 mA and ICC(max) value from
20 mA to 18 mA for f=1 MHz test condition
Changed the ICCDR(typ) value from 0.7 A to 0.5 A and ICCDR(max) value from 3 A
to 2.5 A
*B
566724
See ECN
NXR
Converted from preliminary to final
Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz
Changed the ISB2(typ) value from 0.5 A to 1 A
Changed the ISB2(max) value from 2.5 A to 5 A
Changed the ICCDR(typ) value from 0.5 A to 1 A and ICCDR(max) value from 2.5 A
to 4 A
*C
869500
See ECN
VKN
Added Automotive-A and Automotive-E information
Updated Ordering Information Table
Added footnote 13 related to tACE
*D
901800
See ECN
VKN
Added footnote 9 related to ISB2 and ICCDR
Made footnote 14 applicable to AC parameters from tACE
*E
1371124
See ECN
VKN/AESA Converted Automotive information from preliminary to final
Changed IIX min spec from –1 A to –4 A and IIX max spec from +1 A to +4 A
Changed IOZ min spec from –1 A to –4 A and IOZ max spec from +1 A to +4 A
*F
1875374
See ECN
VKN/AESA Added -45BVI part in the Ordering Information table
*G
2943752 06/03/2010
*H
3055031
*I
*J
10/12/10
VKN
Added Contents
Added footnote related to Chip enable and Byte enables in Truth Table
Updated Package Diagrams
Updated links in Sales, Solutions, and Legal Information
RAME
Added Acronyms and Units of Measure Table
Converted all table notes into footnotes.
Updated Electrical Characteristics, Switching Characteristics table, and
Data Retention Characteristics table
Updated Package Diagrams from 51-85150 *E to *F
Changed ISB1/ISB2/ICCDR test conditions to reflect byte power down feature
3123998 01/03/2011
RAME
Separated Automotive and Industrial parts from datasheet
Removed Automotive info
3285093 06/16/2011
RAME
Updated Functional Description (Removed “For best practice recommendations, refer
to the Cypress application note AN1064, SRAM System Guidelines.”).
Updated in new template.
Document Number: 001-07141 Rev. *J
Page 15 of 16
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