MOTOROLA MCM6729WJ12 256k x 4 bit fast static random access memory Datasheet

MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
256K x 4 Bit Fast Static Random
Access Memory
The MCM6729 is a 1,048,576 bit static random access memory organized as
262,144 words of 4 bits. This device is fabricated using high performance silicon–
gate BiCMOS technology. Static design eliminates the need for external clocks
or timing strobes.
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
This device meets JEDEC standards for functionality and revolutionary pinout,
and is available in a 400 mil plastic small–outline J–leaded package.
•
•
•
•
•
•
Single 5 V ± 10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
All Inputs and Outputs Are TTL Compatible
Three State Outputs
Fast Access Times: 10, 12 ns
Center Power and I/O Pins for Reduced Noise
BLOCK DIAGRAM
A
VCC
VSS
A
A
A
A
MEMORY
MATRIX
512 ROWS x 512 x 4
COLUMNS
ROW
DECODER
A
A
MCM6729
WJ PACKAGE
400 MIL SOJ
CASE 857A–02
PIN ASSIGNMENT
NC
1
32
A
A
2
31
A
A
3
30
A
A
4
29
A
A
5
28
A
E
6
27
G
DQ0
7
26
DQ3
VCC
8
25
VSS
VSS
9
24
VCC
DQ1
10
23
DQ2
W
11
22
A
A
12
21
A
A
13
20
A
A
14
19
A
A
15
18
A
NC
16
17
NC
A
A
PIN NAMES
DQ0
COLUMN I/O
COLUMN DECODER
INPUT
DATA
CONTROL
DQ3
E
A
A
A
A
A
A
A
A
A
A0 – A17 . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ3 . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . No Connection
W
G
REV 4
5/95
 Motorola, Inc. 1995
MOTOROLA
FAST SRAM
MCM6729
1
TRUTH TABLE (X = Don’t Care)
E
G
W
Mode
VCC Current
Output
Cycle
H
X
X
Not Selected
ISB1, ISB2
High–Z
—
L
H
H
Output Disabled
ICCA
High–Z
—
L
L
H
Read
ICCA
Dout
Read Cycle
L
X
L
Write
ICCA
High–Z
Write Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Symbol
Value
Unit
VCC
– 0.5 to + 7.0
V
Vin, Vout
– 0.5 to VCC + 0.5
V
Output Current
Iout
±30
mA
Power Dissipation
PD
1.2
W
Temperature Under Bias
Tbias
– 10 to + 85
°C
Operating Temperature
TA
0 to + 70
°C
Power Supply Voltage
Voltage Relative to VSS for Any Pin
Except VCC
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
Storage Temperature — Plastic
This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages to these high–impedance circuits.
This BiCMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
Supply Voltage (Operating Voltage Range)
Parameter
VCC
4.5
5.0
5.5
V
Input High Voltage
VIH
2.2
—
VCC + 0.3**
V
Input Low Voltage
VIL
– 0.5*
—
0.8
V
Symbol
Min
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Ilkg(I)
—
± 1.0
µA
Output Leakage Current (E = VIH, Vout = 0 to VCC)
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.
** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.
DC CHARACTERISTICS
Parameter
Ilkg(O)
—
± 1.0
µA
Output Low Voltage (IOL = + 8.0 mA)
VOL
—
0.4
V
Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
—
V
POWER SUPPLY CURRENTS
Parameter
Symbol
MCM6729–10
MCM6729–12
Unit
Notes
AC Active Supply Current (Iout = 0 mA) (VCC = max, f = fmax)
ICCA
165
155
mA
1, 2, 3
Active Quiescent Current (E = VIL, VCC = max, f = 0 MHz)
ICC2
90
90
mA
AC Standby Current (E = VIH, VCC = max, f = fmax)
ISB1
60
60
mA
CMOS Standby Current (VCC = max, f = 0 MHz, E ≥ VCC – 0.2 V,
Vin ≤ VSS + 0.2 V, or ≥ VCC – 0.2 V)
ISB2
20
20
mA
1, 2, 3
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data states are all zero.
MCM6729
2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Typ
Max
Unit
Address Input Capacitance
Cin
—
6
pF
Control Pin Input Capacitance
Cin
—
6
pF
Input/Output Capacitance
CI/O
—
8
pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ±10%, TA = 0 to +70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1A
READ CYCLE TIMING (See Notes 1 and 2)
Parameter
MCM6729–10
MCM6729–12
Symbol
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
10
—
12
—
ns
3
Address Access Time
tAVQV
—
10
—
12
ns
Enable Access Time
tELQV
—
10
—
12
ns
Output Enable Access Time
tGLQV
—
5
—
6
ns
Output Hold from Address Change
tAXQX
3
—
3
—
ns
Enable Low to Output Active
tELQX
3
—
3
—
ns
4,5,6
Output Enable Low to Output Active
tGLQX
0
—
0
—
ns
4,5,6
Enable High to Output High–Z
tEHQZ
0
5
0
6
ns
4,5,6
Output Enable High to Output High–Z
tGHQZ
0
5
0
6
ns
4,5,6
NOTES:
1. W is high for read cycle.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHQZ (max) < t ELQX (min), and t GHQZ (max) < tGLQX (min), both for a given device and from
device to device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = VIL, G = VIL).
8. Addresses valid prior to or coincident with E going low.
TIMING LIMITS
AC TEST LOADS
+5 V
480 Ω
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
OUTPUT
255 Ω
5p
VL = 1.5 V
Figure 1A
MOTOROLA FAST SRAM
Figure 1B
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never provides data later than that time.
MCM6729
3
READ CYCLE 1 (See Note 7)
tAVAV
A (ADDRESS)
tAXQX
Q (DATA OUT)
PREVIOUS DATA VALID
DATA VALID
tAVQV
READ CYCLE 2 (See Note 8)
tAVAV
A (ADDRESS)
tAVQV
tELQV
E (CHIP ENABLE)
tEHQZ
tELQX
G (OUTPUT ENABLE)
tGHQZ
tGLQV
tGLQX
Q (DATA OUT)
MCM6729
4
DATA VALID
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6729–10
MCM6729–12
Symbol
Min
Max
Min
Max
Unit
Notes
tAVAV
10
—
12
—
ns
3
Address Setup Time
tAVWL
0
—
0
—
ns
Address Valid to End of Write
tAVWH
9
—
10
—
ns
Address Valid to End of Write, G High
tAVWH
8
—
9
—
ns
Write Pulse Width
tWLWH,
tWLEH
9
—
10
—
ns
Write Pulse Width, G High
tWLWH,
tWLEH
8
—
9
—
ns
Data Valid to End of Write
tDVWH
5
—
6
—
ns
Data Hold Time
tWHDX
0
—
0
—
ns
Write Low to Data High–Z
tWLQZ
0
5
0
6
ns
4,5,6
Write High to Output Active
tWHQX
3
—
3
—
ns
4,5,6
Write Recovery Time
tWHAX
0
—
0
—
ns
Parameter
Write Cycle Time
NOTES:
1. A write occurs during the overlap of E low and W low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
tAVAV
A (ADDRESS)
tWHAX
tAVWH
E (CHIP ENABLE)
tWLEH
tWLWH
W (WRITE ENABLE)
tDVWH
tAVWL
D (DATA IN)
tWHDX
DATA VALID
tWLQZ
Q (DATA OUT)
HIGH–Z
HIGH–Z
tWHQX
MOTOROLA FAST SRAM
MCM6729
5
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6729–10
MCM6729–12
Symbol
Min
Max
Min
Max
Unit
Notes
tAVAV
10
—
12
—
ns
3
Address Setup Time
tAVEL
0
—
0
—
ns
Address Valid to End of Write
tAVEH
8
—
9
—
ns
Enable to End of Write
tELEH,
tELWH
8
—
9
—
ns
Data Valid to End of Write
tDVEH
5
—
6
—
ns
Data Hold Time
tEHDX
0
—
0
—
ns
Write Recovery Time
tEHAX
0
—
0
—
ns
Parameter
Write Cycle Time
4,5
NOTES:
1. A write occurs during the overlap of E low and W low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
tAVAV
A (ADDRESS)
tAVEH
tELEH
E (CHIP ENABLE)
tAVEL
tELWH
tEHAX
W (WRITE ENABLE)
tDVEH
D (DATA IN)
Q (DATA OUT)
MCM6729
6
tEHDX
DATA VALID
HIGH–Z
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
32–LEAD
400 MIL SOJ
CASE 857A–02
F 32 PL
0.17 (0.007)
T B
S
S
A
S
N
32
D 32 PL
0.17 (0.007) S
17
1
T B
A
S
S
NOTE 3
DETAIL Z
16
0.17 (0.007)
-A-
T A
S
S
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TO BE DETERMINED AT PLANE -T-.
4. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
5. DIMENSION A & B INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT THE PARTING LINE.
S
P
L
G
-BE
C
0.10 (0.004)
K
DETAIL Z
-T-
SEATING
PLANE
S RADIUS
R
0.25 (0.010)
S
T A
S
B
S
NOTE 3
DIM
A
B
C
D
E
F
G
K
L
N
P
R
S
INCHES
MIN
MAX
0.820
0.830
0.395
0.405
0.128
0.148
0.016
0.020
0.088
0.098
0.026
0.032
0.050 BSC
0.035
0.045
0.025 BSC
0.030
0.045
0.435
0.445
0.365
0.375
0.030
0.040
MILLIMETERS
MIN
MAX
20.83 21.08
10.03 10.29
3.75
3.26
0.50
0.41
2.48
2.24
0.81
0.67
1.27 BSC
1.14
0.89
0.64 BSC
1.14
0.76
11.05 11.30
9.52
9.27
1.01
0.77
ORDERING INFORMATION
(Order by Full Part Number)
MCM
6729 WJ
XX
XX
Motorola Memory Prefix
Shipping Method (R2 = Tape and Reel, Blank = Rails)
Part Number
Speed (10 = 10 ns, 12 = 12 ns)
Package (WJ = 400 mil SOJ)
Full Part Numbers — MCM6729WJ10
MCM6729WJ12
MCM6729WJ10R2
MCM6729WJ12R2
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
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against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
MCM6729
7
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Tai Po, N.T., Hong Kong.
MCM6729
8
◊
CODELINE TO BE PLACED HERE
MOTOROLA FAST
SRAM
MCM6729/D
*MCM6729/D*
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