ON MAC4DLM-001 Sensitive gate triacs silicon bidirectional thyristor Datasheet

MAC4DLM
Preferred Device
Sensitive Gate Triacs
Silicon Bidirectional Thyristors
Designed for high volume, low cost, industrial and consumer
applications such as motor control; process control; temperature, light
and speed control.
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Features
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•
•
•
•
•
•
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TRIACS
4.0 AMPERES RMS
600 VOLTS
Small Size Surface Mount DPAK Package
Passivated Die for Reliability and Uniformity
Four−Quadrant Triggering
Blocking Voltage to 600 V
On−State Current Rating of 4.0 Amperes RMS at 93°C
Low Level Triggering and Holding Characteristics
Epoxy Meets UL 94, V−0 @ 0.125 in
ESD Ratings: Human Body Model, 3B 8000 V
Machine Model, C 400 V
MT2
MT1
G
MARKING
DIAGRAMS
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Peak Repetitive Off−State Voltage (Note 1)
(TJ = −40 to 110°C, Sine Wave,
50 to 60 Hz, Gate Open)
VDRM,
VRRM
600
V
On−State RMS Current
(Full Cycle Sine Wave, 60 Hz,
TC = 93°C)
IT(RMS)
4.0
Peak Non-Repetitive Surge Current
(One Full Cycle, 60 Hz, TJ = 110°C)
Circuit Fusing Consideration
(t = 8.3 msec)
Peak Gate Power
(Pulse Width ≤ 10 sec, TC = 93°C)
1 2
3
ITSM
40
A
I2t
6.6
A2sec
W
PG(AV)
0.1
W
Peak Gate Current
(Pulse Width ≤ 10 sec, TC = 93°C)
IGM
0.2
A
Peak Gate Voltage
(Pulse Width ≤ 10 sec, TC = 93°C)
VGM
5.0
V
Operating Junction Temperature Range
TJ
−40 to
110
°C
Storage Temperature Range
Tstg
−40 to
150
°C
DPAK−3
CASE 369D
STYLE 6
YWW
AC
4DLM
1
2
3
Y
WW
= Year
= Work Week
PIN ASSIGNMENT
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the device are exceeded.
August, 2004 − Rev. 2
YWW
AC
4DLM
4
0.5
 Semiconductor Components Industries, LLC, 2004
DPAK
CASE 369C
STYLE 6
A
PGM
Average Gate Power
(t = 8.3 msec, TC = 93°C)
4
1
1
Main Terminal 1
2
Main Terminal 2
3
Gate
4
Main Terminal 2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MAC4DLM/D
MAC4DLM
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
RJC
RJA
RJA
3.5
88
80
°C/W
TL
260
°C
Unit
Thermal Resistance − Junction−to−Case
Thermal Resistance − Junction−to−Ambient
Thermal Resistance − Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering Purposes (Note 3)
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted; Electricals apply in both directions)
Symbol
Characteristic
Min
Typ
Max
−
−
−
−
0.01
2.0
−
1.3
1.6
−
−
−
−
1.8
2.1
2.4
4.2
3.0
3.0
3.0
5.0
0.5
0.5
0.5
0.5
0.62
0.57
0.65
0.74
1.3
1.3
1.3
1.3
OFF CHARACTERISTICS
Peak Repetitive Blocking Current
(VD = Rated VDRM, VRRM; Gate Open)
IDRM,
IRRM
TJ = 25°C
TJ = 110°C
mA
ON CHARACTERISTICS
Peak On−State Voltage (Note 4)
(ITM = ± 6.0 A)
VTM
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 )
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
MT2(−), G(+)
IGT
Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 )
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
MT2(−), G(+)
VGT
Gate Non−Trigger Voltage
(VD = 12 V, RL = 100 , TJ = 110°C)
MT2(+), G(+); MT2(+), G(−); MT2(−), G(−); MT2(−), G(+)
VGD
Holding Current
(VD = 12 V, Gate Open, Initiating Current = ± 200 mA)
IH
Latching Current
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
MT2(−), G(+)
IL
(VD = 12 V, IG = 5.0 mA)
(VD = 12 V, IG = 5.0 mA)
(VD = 12 V, IG = 5.0 mA)
(VD = 12 V, IG = 10 mA)
V
mA
V
V
0.1
0.4
−
−
1.5
15
−
−
−
−
1.75
5.2
2.1
2.2
10
10
10
10
Min
Typ
Max
−
3.0
−
10
−
−
mA
mA
DYNAMIC CHARACTERISTICS
Characteristic
Symbol
Rate of Change of Commutating Current
(VD = 200 V, ITM = 1.8 A, Commutating dv/dt = 1.0 V/sec,
TJ = 110°C, f = 250 Hz, CL = 5.0 fd, LL = 80 mH, RS = 56 ,
CS = 0.03 fd) With snubber see Figure 11
di/dt(c)
Critical Rate of Rise of Off−State Voltage
(VD = 0.67 X Rated VDRM, Exponential Waveform,
Gate Open, TJ = 110°C)
Unit
A/ms
dv/dt
V/s
2. These ratings are applicable when surface mounted on the minimum pad sizes recommended.
3. 1/8″ from case for 10 seconds.
4. Pulse Test: Pulse Width ≤ 2.0 msec, Duty Cycle ≤ 2%.
ORDERING INFORMATION
Device
MAC4DLM−001
MAC4DLMT4
Package Type
Package
Shipping†
DPAK−3
369D
75 Units / Rail
DPAK
369C
16 mm Tape & Reel (2.5 k / Reel)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
MAC4DLM
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current
Symbol
Parameter
VTM
VDRM
Peak Repetitive Forward Off−State Voltage
IDRM
Peak Forward Blocking Current
VRRM
Peak Repetitive Reverse Off−State Voltage
IRRM
Peak Reverse Blocking Current
VTM
Maximum On−State Voltage
IH
Holding Current
on state
IH
IRRM at VRRM
off state
IH
Quadrant 3
MainTerminal 2 −
VTM
Quadrant Definitions for a Triac
MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2
Quadrant II
(+) MT2
(−) IGT
GATE
Quadrant I
(+) IGT
GATE
MT1
MT1
REF
REF
IGT −
+ IGT
(−) MT2
(−) MT2
Quadrant III
Quadrant 1
MainTerminal 2 +
Quadrant IV
(+) IGT
GATE
(−) IGT
GATE
MT1
MT1
REF
REF
−
MT2 NEGATIVE
(Negative Half Cycle)
All polarities are referenced to MT1.
With in−phase signals (using standard AC lines) quadrants I and III are used.
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3
+ Voltage
IDRM at VDRM
P(AV) , AVERAGE POWER DISSIPATION (WATTS)
110
= 30°
105
60°
90°
100
α
α
95
120°
= CONDUCTION ANGLE
180°
dc
90
0.5
0
1.0
1.5
2.0
3.0
2.5
3.5
α
4.0
α
120°
90°
= CONDUCTION ANGLE
3.0
2.0
60°
= 30°
1.0
0
0
1.0
0.5
2.0
1.5
3.0
2.5
3.5
Figure 1. RMS Current Derating
Figure 2. On−State Power Dissipation
TYPICAL @ TJ = 25°C
MAXIMUM @ TJ = 110°C
1.0
MAXIMUM @ TJ = 25°C
0.1
0.5
1.5
1.0
2.0
2.5
3.0
3.5
4.0
1.0
0.1
ZJC(t) = RJC(t)r(t)
0.01
4.0
0.1
10
1.0
100
1000
10 K
VT, INSTANTANEOUS ON−STATE VOLTAGE (VOLTS)
t, TIME (ms)
Figure 3. On−State Characteristics
Figure 4. Transient Thermal Response
1.0
7.0
VGT, GATE TRIGGER VOLTAGE (VOLTS)
8.0
I GT, GATE TRIGGER CURRENT (mA)
5.0
IT(RMS), RMS ON−STATE CURRENT (AMPS)
10
Q4
6.0
5.0
dc
180°
IT(RMS), RMS ON−STATE CURRENT (AMPS)
100
0
6.0
4.0
r(t) , TRANSIENT RESISTANCE (NORMALIZED)
I T, INSTANTANEOUS ON−STATE CURRENT (AMPS)
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( °C)
MAC4DLM
Q3
4.0
Q2
3.0
Q1
2.0
1.0
0
−40 −25
Q4
Q1
0.8
Q2
Q3
0.6
0.4
0.2
−10
5.0
20
35
50
65
80
95
−40 −25
110
−10
5.0
20
35
50
65
80
95
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Typical Gate Trigger Current versus
Junction Temperature
Figure 6. Typical Gate Trigger Voltage versus
Junction Temperature
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4
110
MAC4DLM
12
4.0
IL, LATCHING CURRENT (mA)
IH , HOLDING CURRENT (mA)
5.0
3.0
MT2 NEGATIVE
2.0
MT2 POSITIVE
1.0
0
−40 −25
10
8.0
6.0
4.0
Q4
2.0 Q1
Q3
0
−10
5.0
20
35
50
65
80
95
−40 −25
110
20
5.0
−10
35
50
65
80
95
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Typical Holding Current versus
Junction Temperature
Figure 8. Typical Latching Current versus
Junction Temperature
40
110
10
VPK = 400 V
dv/dt(c), CRITICAL RATE OF RISE OF
COMMUTATING VOLTAGE (V/ s)
VD = 400 V
TJ = 110°C
35
30
25
100°C
TJ = 110°C
90°C
1.0
20
15
MAC4DLM
10
5.0
tw
f=
1
2 tw
(di/dt)c =
VDRM
6f ITM
1000
0.1
100
1000
10 K
0
1.0
2.0
3.0
4.0
5.0
6.0
RGK, GATE−MT1 RESISTANCE (OHMS)
di/dt(c), RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 9. Minimum Exponential Static dv/dt
versus Gate−MT1 Resistance
Figure 10. Critical Rate of Rise of
Commutating Voltage
LL
200 VRMS
ADJUST FOR
ITM, 60 Hz VAC
CHARGE
1N4007
MEASURE
I
TRIGGER
CHARGE
CONTROL
NON-POLAR
CL
TRIGGER CONTROL
STATIC dv/dt (V/ s)
Q2
RS
−
CS
MT2
1N914 51 G
ADJUST FOR +
di/dt(c)
200 V
MT1
Note: Component values are for verification of rated (di/dt)c. See AN1048 for additional information.
Figure 11. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)c
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5
MAC4DLM
PACKAGE DIMENSIONS
DPAK
CASE 369C
ISSUE O
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
4
Z
A
S
1
2
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
3
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
T
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
0.180 0.215
0.025 0.040
0.020
−−−
0.035 0.050
0.155
−−−
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
SOLDERING FOOTPRINT
6.20
0.244
3.0
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
SCALE 3:1
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6
mm inches
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.57
5.45
0.63
1.01
0.51
−−−
0.89
1.27
3.93
−−−
MAC4DLM
PACKAGE DIMENSIONS
DPAK−3
CASE 369D−01
ISSUE B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
C
B
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
3 PL
0.13 (0.005)
M
STYLE 6:
PIN 1.
2.
3.
4.
T
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7
MT1
MT2
GATE
MT2
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
MAC4DLM
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MAC4DLM/D
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