Si9124 New Product Vishay Siliconix 500-kHz Push-Pull DC-DC Converter With Integrated Secondary Synchronous Rectification Control FEATURES D D D D D D 12-V to 72-V Input Voltage Range D Compatible with ETSI 300 132-2 100 V, 100-ms Transients D Integrated Push-Pull 1-A Primary Drivers D Voltage Mode Control D Voltage Feedforward Compensation D High Voltage Pre-Regulator Operates During Start-Up D Current Sensing On OUTB Primary Device Hiccup Current Control During Shorted Load Low Input Voltage Detection Programmable Soft-Start Function Programmable Oscillator Frequency Over Temperature Protection APPLICATIONS D Network Cards D Power Supply Modules DESCRIPTION Si9124 is a dedicated push-pull controller IC ideally suited to fixed telecom dc-dc converter applications where high efficiency is required at low output voltages (e.g. <3.3 V). Designed to operate within the voltage range of 12-72 V and withstand 100 V, 100 ms transients, the IC is capable of controlling and directly driving both primary side MOSFET switches of a push-pull circuit. High conversion efficiency is achieved by use of synchronous rectifying MOSFET transistors in the secondary. Due to the very low on-resistance of the secondary MOSFETs, a significant increase in the efficiency can be achieved as compared with conventional Schottky diodes for today’s low output voltages. On-chip control of the dead time delays between the primary and secondary signals keep efficiencies high and prevents accidental destruction of the power transformer or wasted energy from self timed approaches. Such a system can achieve conversion efficiencies well in excess of 90%. FUNCTIONAL BLOCK DIAGRAM VINEXT + C - VIN1 REXT To VCC Power Transformer VIN VCC OUTA Pre-Reg VOUT CVCC EP Voltage Information SS Primary Drivers Voltage Control SoftStart CLOAD RLOAD OUTB PWM CSS CS2 Secondary Driver Current Control CS1 RS Pulse Transformer Driver Logic SEC_SYNC Si9124 Push-Pull Synchronous Controller Opto Error Amp 1.215 V Figure 1. Document Number: 72099 S-03638—Rev. B, 20-Mar-03 www.vishay.com 1 Si9124 New Product Vishay Siliconix DESCRIPTION (CONTINUED) Si9124 has advanced current monitoring circuitry to permit the user to set the maximum current in the primary circuit. Such a feature acts as protection against output shorts. Upon sensing an overload condition, the converter is shut off for a period of time and then soft-start cycle is re-initiated, achieving hiccup mode operation. Current sensing is by means of a sense resistor on the primary device. An integrated over-temperature shutdown circuit also protects the system. circuit permits direct operation from input voltage with only one series resistor during startup. The pre-regulator automatically disconnects from the input supply when the output voltage is established by means of a feedback winding from the filter inductor. Si9124 is available in TSSOP-16 pin package. In order to satisfy the stringent ambient temperature requirements, Si9124 is rated to handle the industrial temperature range of –40 to 85_C. The 100-V depletion mode MOSFET integrated pre-regulator DETAILED BLOCK DIAGRAM VIN VCC ROSC VREF Pre-Regulator + - VUVLO VCC2 Level Shift 8.8 V VINDET PGND2 OSC Ramp Error Amplifier VCC VSD + - 2.2 R 550 mV R EP Primary A Driver VFF VUV + - VREF OUTA + + - Primary B Driver PWM Comparator OUTB 1.65 V I Driver Control and Timing 4I SS VCC SEC_SYNC Gain CS2 CS1 + - Peak DET SEC_SYNC Driver Hiccup Mode Start OTP Si9124 Over Current Protection PGND GND Figure 2. www.vishay.com 2 Document Number: 72099 S-03638—Rev. B, 20-Mar-03 Si9124 New Product Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (ALL VOLTAGES REFERENCED TO GND = 0 V) VIN (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 V HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . . . . . . . . 5 mA VIN (100 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 to 150_C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 V Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125_C Power Dissipationa TSSOP-16 (TA = 25_C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 W VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 V VREF, ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V SEC_SYNC Drive Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Thermal Impedance (JA) TSSOP-16b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100_C/W Notes a. Device mounted on JEDEC compliant 1S2P (4 layer) test board. b. Derate - 10 mW/_C above 25_C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE (ALL VOLTAGES REFERENCED TO GND = 0 V) VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 to 72 V CSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 nF CVIN1 CVIN2 . . . . . . . . . . . . . . . . . . . . . . . 100 F/ESR 100 m and 0.1 F CREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 F VCC Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 to 13.2 V CBOOST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 F CVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 F CLOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 F fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 to 600 kHz Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC - 0.3 V ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 to 72 k Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC REXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 k Reference Voltage Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 mA SPECIFICATIONSa Limits Test Conditions Unless Specified - 40 to 85_C Symbol CS1 = CS2 = 0 V, fNOM = 500 kHz, VIN = 48 V VINDET = 4.8 V; 10 V VCC 13.2 V, VCC2 = VCC Minb Typc Output Voltage VREF VCC = 12 V, 25_C Load = 0 mA 3.2 3.3 Short Circuit Current ISREF VREF = 0 V Load Regulation dVr/dlr IREF = 0 to - 2.5 mA - 30 Power Supply Rejection PSRR @ 100Hz 60 Parameter Maxb Unit Reference (3.3 V) 3.4 V - 50 mA - 75 mV dB Oscillator Accuracy (1% ROSC) Max Frequency ROSC = 30 k, fNOM = 500 kHz FMAX ROSC = 24 k IBIAS VEP = 0 V - 20 20 % 600 kHz Error Amplifier Input Bias Current Gain Bandwidth Power Supply Rejection Slew Rate AV BW PSRR @ 100Hz SR - 40 - 15 A - 2.2 V/V 5 MHz 60 dB 0.5 V/s 150 mV Current Sense Amplifier Input Voltage CM Range VCM Input Amplifier Gain AVOL 17.5 dB BW 5 MHz Input Amplifier Bandwidth Input Amplifier Offset Voltage VCC Hiccup Threshold Hysteresis Document Number: 72099 S-03638—Rev. B, 20-Mar-03 VCS1 - GND, VCS2 - GND 5 VOS VTHCUP Increase CS2 Until SS Hiccups 150 Decrease CS2 Until SS Clamps - 50 mV www.vishay.com 3 Si9124 New Product Vishay Siliconix SPECIFICATIONSa Limits Test Conditions Unless Specified Parameter Symbol CS1 = CS2 = 0 V, fNOM = 500 kHz, VIN = 48 V VINDET = 4.8 V; 10 V VCC 13.2 V, VCC2 = VCC - 40 to 85_C Minb Typc Maxb 92 95 Unit PWM Operation Duty Cyclee DMAX DMIN fOSC = 500 kHz VEP = 0 V 90 15 VEP = 1.85 V % Pre-Regulator Input Voltage (Continuous) VIN IIN = 10 A 72 Input Leakage Current ILKG VIN = 72 V, VCC VREG 10 IREG1 VIN = 72 V, VINDET VSD Regulator Bias Current IREG2 VIN = 72 V, VINDET VREF Pre-Regulator Drive Capacility ISTART VCC VREG VCC P Pre-Regulator R l t T Turn Off Threshold Voltage VREG1 VINDET VREF VREG2 VINDET = 0 V VUVLO VCC Rising Undervoltage Lockoutd VUVLO Hysteresis 86 200 4.5 7.5 A mA 20 TA = 25_C V 7.4 9.1 10.4 8.5 9.1 9.7 9.2 TA = 25_C 7.15 8.6 9.8 8.1 8.6 9.3 VUVLOHYS V 0.5 Soft-Start Soft-Start Current Output Soft-Start Completion Voltage ISS1 0 VSS 2 Vbe 12 20 28 ISS2 2 Vbe VSS 4.8 V 60 100 200 VSS_COMP Normal Operation 7.35 8.1 8.85 VSD VINDET Rising 350 550 720 A V Shutdown VINDET Shutdown FN VINDET Hysteresis VINDET 200 mV VINDET Input Threshold Voltages VINDET - VIN Under Voltage VUV VINDET Hysteresis VINDET Rising 3.13 3.3 VINDET 0.3 Activating Temperature TJ Increasing 160 De-Activating Temperature TJ Decreasing 130 3.46 V Over Temperature Protection _C Converter Supply Current (VCC) Shutdown ICC1 Shutdown, VINDET = 0 V 50 140 350 Switching Disabled ICC2 VINDET VREF 1.8 2.8 3.8 Switching w/o Loadf ICC3 VINDET VREF, fNOM = 500 kHz 3.0 4.4 6.8 Switching with CLOAD ICC4 VCC = 12 V, OUTA = OUTB = 3 nF, CSEC_SYNC = 0.3 nF 15.2 IHCUP CS2 - CS1 = 200 mV, COUTA = COUTB = 3 nF CSEC_SYNC = 0.3 nF 4.3 VCC Hiccup Current www.vishay.com 4 A mA Document Number: 72099 S-03638—Rev. B, 20-Mar-03 Si9124 New Product Vishay Siliconix SPECIFICATIONSa Limits Test Conditions Unless Specified - 40 to 85_C Symbol CS1 = CS2 = 0 V, fNOM = 500 kHz, VIN = 48 V VINDET = 4.8 V; 10 V VCC 13.2 V, VCC2 = VCC Minb Output High Voltage VOH Sourcing 10 mA VCC2 0.3 Output Low Voltage VOL Sinking 10 mA Parameter Typc Maxb Unit Output A Primary Driver VCC2 Current Peak Output Source Peak Output Sink ICC5 ISOURCE 0.1 VCC2 = 12 V, PGND2 = 0 V ISINK Rise Time tr Fall Time tf PGND2 + 0.3 0.75 TA = 25_C, 25_C COUTA = 3 nF, nF VCC = 12 V, V 20 - 80% 1.55 1.1 - 1.0 - 0.75 V mA A 1.0 18 28 22 28 ns Output B Primary Driver Output High Voltage VOH Sourcing 10 mA Output Low Voltage VOL Sinking 10 mA Peak Output Source ISOURCE Peak Output Sink ISINK Rise Time tr Fall Time tf VCC 0.3 V 0.3 - 1.0 VCC = 12 V, V PGND = 0 V 0.75 TA = 25_C, 25_C COUTB = 3 nF, nF VCC = 12 V, V 20 - 80% - 0.75 A 1.0 19 28 24 28 ns Secondary_Synchronous Driver Output High Voltage VOH Sourcing 10 mA Output Low Voltage VOL Sinking 10 mA Leading Edge Delays Trailing Edge Delays Peak Output Source Peak Output Sink td1 td3 td2 td4 ISOURCE ISINK Rise Time tr Fall Time tf TA = 25_C, 25_C VCC = 12 V V, LX = 48 V, V See Figure 3 COUTA = COUTB = 3nF, 3nF CSEC_SYNC 0 3 nF SEC SYNC = 0.3 VCC 0.4 V 0.4 80 110 80 110 80 110 80 110 ns - 100 VCC = 12 V TA = 25_C, 25_C CSEC_SYNC 0 3 nF, nF VCC = 12 V, V 20 - 80% SEC SYNC = 0.3 mA 100 16 28 17 28 ns Voltage Mode Error Amplifier td1A td2B Input to A-side switch off 200 Input to B-side switch off 200 td3A td4B Input to A-side switch off 200 Input to B-side switch off 200 ns Current Mode Current Amplifier ns Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (- 40_ to 85_C). c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing and are measured at VCC = 12 V unless otherwise noted. d. VUVLO tracks VREG1 by a diode drop. e. Measured on OUTA or OUTB outputs. f. Note total supply current drawn is ICC3 plus ICC5. Document Number: 72099 S-03638—Rev. B, 20-Mar-03 www.vishay.com 5 Si9124 New Product Vishay Siliconix TIMING DIAGRAMS FOR MOS DRIVERS VCC SEC_SYNC GND VCC OUTA GND OUTB GND Time VCC 50% OUTA VCC SEC_SYNC 50% 50% GND Leading Trailing td3 td4 VCC 50% OUTB GND Leading Trailing td1 td2 Figure 3. Hiccup Time Out Soft Start Over Current Detected VOLTS SS 2 Vbe GND Time t2 t1 Figure 4. www.vishay.com 6 Soft-Start, Hiccup Mode Operation Document Number: 72099 S-03638—Rev. B, 20-Mar-03 Si9124 New Product Vishay Siliconix PIN CONFIGURATION Si9124DQ (TSSOP-16) ORDERING INFORMATION VIN 1 16 VCC2 Part Number VCC 2 15 OUTA Si9124DQ-T1 VREF 3 14 PGND2 GND 4 13 OUTB ROSC 5 12 PGND EP 6 11 SEC_SYNC VINDET 7 10 SS CS1 8 9 Si9124DQ Temperature Range Package Tape and Reel - 40 to 85_C Bulk CS2 Top View PIN DESCRIPTION Pin Number Name Function 1 VIN Input supply voltage for the start-up circuit. 2 VCC Supply voltage for internal circuitry 3 VREF 3.3-V reference, decoupled with 1-F capacitor 4 GND Analog Ground 5 ROSC External resistor connection to oscillator 6 EP 7 VINDET 8 CS1 Current limit amplifier negative input 9 CS2 Current limit amplifier positive input 10 SS Voltage control input VIN under voltage detect and shutdown function input. Shuts down or disables switching when VINDET falls below preset threshold voltages and provides the feed forward voltage. Soft-Start control - external capacitor connection 11 SEC_SYNC 12 PGND A driver power ground. 13 OUTB B gate drive signal – primary 14 PGND2 15 OUTA A gate drive signal – primary 16 VCC2 VCC2 connect to VCC Document Number: 72099 S-03638—Rev. B, 20-Mar-03 Secondary side timing signal B driver power ground www.vishay.com 7 Si9124 New Product Vishay Siliconix DETAILED FUNCTIONAL BLOCK DIAGRAM VCC VIN Pre-Regulator Reference Voltage 3.3 V VREF + - VREG VREF + - VINDET VUVLO VUV + - Voltage Feedforward Primary A Driver VSD VCC2 160_C Temp Protection 550 mV VSD OSC Oscillator + 8.6 V VREF ROSC 9.1 V 9.1 V OUTA PGND2 VUV VUVLO OTP Clock Clock Logic VCC 132 k OUTB 60 k EP + + Current Control Logic PWM Generator VREF/2 CS2 CS1 Primary B Driver Gain + - PGND 100 mV Blanking VCC 80 A 20 A SS SS Control VCC Secondary Synchronous Driver SEC_SYNC GND SS Enable Figure 5. DETAILED OPERATION Start-Up A detailed Functional Block Diagram is shown in Figure 5 with additional detail of the pre-regulator shown in Figure 6. The pre-regulator circuit acts as a linear regulator to provide VCC directly from the VINEXT supply until the VCC supply voltage between 10 V to 13.2 V can be sustained from an auxiliary winding from the secondary of the power inductor. www.vishay.com 8 When VINEXT rises above 0 V (see Figure 6), the internal pre-regulator begins charging the external capacitor on VCC. The charging current is limited to typically 40 mA by the internal DMOS device. When Vcc exceeds the UVLO voltage of 8.8 V, a soft-start cycle of the controller is initiated to provide power to the secondary. Once switching commences, the internal gate drivers for the primary side switching transistors and the drive current into the secondary synchronization driver draw additional current from the VCC capacitor and pre-regulator. Document Number: 72099 S-03638—Rev. B, 20-Mar-03 Si9124 New Product event of an over voltage condition on VCC, an internal voltage clamp turns on at 14.5 V to shunt excessive current to GND. In systems where operation is directly from a 12 V supply, VINEXT and VCC can be connected to the 12 V bus. The pre-regulator will remain on until VCC equals VREG but between VUVLO and VREG, excessive current may result in VCC falling below VUVLO and stopping soft start operation. This situation is avoided by the hysteresis between VREG and VUVLO and correct sizing of the VCC capacitor, bootstrap capacitor, the soft-start capacitor, the primary MOSFET gate driving charge, and load on the SEC_SYNC output. The value of the VCC capacitor should be chosen to be capable of maintaining soft start operation with VCC above VUVLO until the VCC current can be supplied from the external circuit (e.g. via an auxiliary winding on the secondary inductor). The soft-start circuit is designed for the dc-dc converter to start up in an orderly manner and reduce component stress. Soft start is achieved by ramping the maximum achievable duty cycle during the soft start time. The duty cycle is increased from zero to the final value at the rate set by the an external capacitor, CSS as shown in Figure 7. The hiccup time is set by an internal 20 µA current source charging CSS from 0 V to 2 Vbe, at which point switching begins. Then a 100 µA charging current is applied to CSS to charge from 2 Vbe to the final value controlling the duty cycle as it rises. In the event of UVLO, shutdown or over current, the SS pin will be held low (1 V) disabling driver switching. A longer soft-start time may be needed for highly capacitive loads and high peak-output current applications. In the event of an over current condition being detected, the soft-start pin will be pulled low and the cycle will start again performing a hiccup as shown in Figure 4. The hiccup off-time, t1, is given by: VINEXT REXT = 1.4 k Auxillary VCC VIN HVDMOS VCC t1 CSS 1.2 V 20 A CVCC 4.7 F 14.5 V Vishay Siliconix The soft-start time t2 is can be estimated as: VREF GND Figure 6. High-Voltage Pre-Regulator Circuit t2 The feedback voltage from the output of the auxiliary winding must sustain VCC above VREG to fully disconnect the pre-regulator, isolating VCC from VINEXT. VCC is then maintained above VREG for the duration of operation. In the CSS VOUT n (K 100 A) where VOUT is the output of the converter, and n is the turns ratio of the primary to each secondary winding, and K is the ratio of the resistive divider from VINEXT to VINDET (typically 10/1). VCC + Peak Detect 4I GM - I SS Control CS1 CS2 - SS Enable AV + AV 150 mV SS Blank CSS AV 100 mV Figure 7. Document Number: 72099 S-03638—Rev. B, 20-Mar-03 Current-Sense and Soft-Start Circuit Block Diagram www.vishay.com 9 Si9124 New Product Vishay Siliconix Care should be taken to control the operating time using the internal preregulator to prevent excessive power dissipation in the IC. The use of an external dropping resistor connected in series with the VIN pin to drop the voltage during start up is recommended. The value of REXT is selected to drop the input voltage to the IC under worst case conditions thereby dissipating power in the resistor, instead of the IC. If the supply output is shorted and the auxiliary winding does not provide the VCC current, then continuous soft start cycles will occur. The average power in the IC during start-up where the hiccup operation would be performed continuously is given by: Power (IC) V IN t1 ICC2 t2ICC4 I CC5 I SEC_SYNC Power REXT VID t 1 t 2 t1 ICC2 t2I CC4 ICC5 ISEC_SYNC t1 t2 where VID VINEXT VIN where ICC2 is the non-switching supply current, ICC4 and ICC5 are the supply current while switching, and ISEC_SYNC is the average current out of the SEC_SYNC pin, and t1 and t2 are defined in Figure 4. After the feedback voltage from the secondary overrides the internal pre-regulator, no current flows through REXT. An example of the feedback circuitry is shown in Figure 15. The SS pin has a predictable +1.25-mV/_C temperature coefficient and can be used to continuously monitor the junction temperature of the IC for a given power dissipation. Reference The reference voltage of Si9124 is set at 3.3 V. The reference voltage should be de-coupled externally with a 0.1 µF capacitor. The VREF voltage is 0 V in shutdown mode and has 50-mA source capability. Voltage Mode PWM Operation Under normal load conditions, the IC operates in voltage mode and generates a fixed frequency pulse-width modulated signal to the drivers. Duty cycle is controlled over a wide range to maintain the output voltage under line and load variation. Voltage feed-forward is also included to improve line regulation and transient response. In the push-pull topology requiring isolation between output and input, the reference voltage and error amplifier must be supplied externally, usually on the secondary side. The error information is usually passed to the power controller through an opto-coupling device for isolation. The error information enters the IC via pin EP and where 0 V results in the maximum duty cycle, whilst 2 V represents minimum duty cycle. The EP error signal is gained up by -2.2X via an inverting amplifier and compared against the internal ramp www.vishay.com 10 generator. The relationship between Duty Cycle and VEP is shown in the Typical Characteristic section, Duty Cycle vs. VEP at 25 _C , page 12. Voltage feed-forward is implemented by taking the attenuated VINEXT signal at VINDET to directly modulate he duty cycle. This relationship is shown in the Typical Characteristic section, Duty Cycle vs. VINDET, page 12. The response time to line transients is very short since the PWM duty cycle is charged directly without having to go through the error amplifier feedback loop. At start-up, i.e., once VCC is greater than VUVLO, switching is initiated under soft-start control which increases maximum attainable switch on-time linearly over the soft-start period. Start-up from a VINDET power down, over-temperature, or over current is also initiated under soft-start control. Push-Pull Sequence and Synchronous Rectification Timing The PWM signal generated within the IC controls the OUTA and OUTB drivers on alternate cycles. A period of inactivity always results after initiation of the soft-start cycle until the soft-start voltage reaches approximately 2 Vbe and PWM generated switching begins. The timing and coordination of the drives to the primary and secondary stages is very important and the relationships are shown in Figure 3. It is essential to avoid the situation where both of the secondary MOSFETs are on when either the OUTA or OUTB switches are active. In this situation the transformer would effectively be presented with a short across the output. To avoid this a timing signal is made available which is ahead of the primary drive outputs by 80 ns. Primary MOSFET Drivers The drive voltage for the primary MOSFETs is provided directly from the VCC and VCC2 supply. The switch gate drive signals OUTA and OUTB are shown in Figure 3. The drive currents for the primary side MOSFETs is supplied from the VCC and VCC2 supply and can influence start up conditions. Secondary Synchronization Driver The secondary side MOSFETs are driven by the SEC_SYNC output via a pulse transformer and gate driver circuits. The time relationships are shown in Figure 3. Logic circuitry on the secondary side is required to align the synchronous rectifier gate drive with the primary drive. The current supplied to the pulse transformer is drawn from VCC. Oscillator The oscillator is designed to operate at a frequencies up to 500 kHz. The 500-kHz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. The oscillator and therefore the switching frequency is programmable by a resistor on the The relationship is shown in the Typical ROSC pin. Characteristics, FOSC vs. ROSC. Document Number: 72099 S-03638—Rev. B, 20-Mar-03 Si9124 New Product Vishay Siliconix achieved by choosing an appropriate resistive tap between VINEXT and ground. Hiccup Operation Current limiting is achieved by monitoring the differential voltage between CS1 and CS2 pins which are connected across a primary sense resistor. Once the differential voltage exceeds the 150-mV trigger point, Hiccup operation is started. The soft-start voltage on the SS pin is pulled to ground and switching stops until the SS pin charges up to 2 Vbe whereupon a duty cycle limited soft start is initiated. The upper and lower switching points of the current limit have 50 mV of hysteresis. VINEXT Voltage Monitor – VINDET The Si9124 provides a means of sensing the voltage on VINEXT to control the operating mode and provides the feed-forward control voltage to the PWM controller. This is When the VINDET voltage is greater than 720 mV but less than VREF and VCC is greater than VUVLO, all internal circuitry is enabled, but switching is stopped. VINDET also provides the input to the voltage feed-forward function by adjusting the amplitude of the PWM ramp to the PWM comparator. Shutdown Mode If VINDET pin is forced below 470 mV the device will enter SHUTDOWN mode. This powers down all unnecessary functions of the controller, ensures that the primary switches are off and results in a low level current demand of 150 A from the VINEXT or VCC supplies. TYPICAL CHARACTERISTICS VSS vs. Temperature, VCC = 12 V VREG vs. Temperature, VIN = 48 V 8.20 10.0 8.15 9.5 TC = +1.25 mV/C V REG(V) V SS (V) 8.10 VINDET VREF 8.05 9.0 VINDET VREF TC = - 11 mV/C 8.5 8.00 8.0 7.95 7.90 - 50 - 25 0 25 50 75 100 125 7.5 - 50 150 - 25 0 25 Temperature (_C) 75 100 125 150 Temperature (_C) ISS1 vs. VCC vs. Temperature ISS2 vs. VCC vs. Temperature 25 140 VCC = 13 V 130 23 VCC = 12 V I SS1 (uA) I SS1 (uA) 50 21 VCC = 13 V 120 VCC = 12 V 110 19 100 VCC = 10 V VCC = 10 V 17 15 - 50 90 - 25 0 25 50 Temperature (_C) Document Number: 72099 S-03638—Rev. B, 20-Mar-03 75 100 125 80 - 50 - 25 0 25 50 75 100 125 Temperature (_C) www.vishay.com 11 Si9124 New Product Vishay Siliconix TYPICAL CHARACTERISTICS FOSC vs. ROSC @ VCC = 12 V VREF vs. Temperature, VCC = 12 V 600 3.300 3.295 500 V REF (V) FOSC (kHz) 3.290 400 3.285 3.280 300 3.275 200 20 30 40 50 60 70 3.270 - 50 80 - 25 0 ROSC (k) 25 50 75 100 Temperature (_C) IHCUP vs. SS Duty Cycle, CSS 22 = nF OUTA, OUTB Duty Cycle vs. VEP 100 14 3.6 V = VINDET 90 13 Duty Cycle (%) 80 IHCUP (mA) 12 11 10 70 60 50 40 9 4.8 V 7.2 V VCC = 12 V 30 8 VCC = 12 V ViINDET = 4.8 V OUTA = OUTB = 3 nF CSEC_SYNC = 0.3 nF 7 20 10 6 10 20 30 40 0 0.0 50 0.5 SS Duty Cycle (%) = t2 / (t1 + t2) 1.5 2.0 Duty Cycle vs. VINDET @ 25_C VEP = 1.2 V, VCC = 9.5 V OUTA, OUTB Delay vs. Temperture 100 120 VCC = 12 V 90 td1, td3 100 80 Duty Cycle % Delay (ns) 1.0 VEP (V) td2, td4 80 70 60 50 60 OUTA, OUTB 40 40 - 50 - 25 0 25 50 Temperature (_C) www.vishay.com 12 75 100 125 30 2.5 3.5 4.5 5.5 6.5 7.5 VINDET (V) Document Number: 72099 S-03638—Rev. B, 20-Mar-03 Si9124 New Product Vishay Siliconix TYPICAL CHARACTERISTICS IREG2 vs. Temperature ICC3 + ICC5 vs. Temperature 5.5 6.0 Drivers w/o CLOAD VIN = 48 V Drivers w/o CLOAD VCC = 12 V 5.5 ICC5 + ICC3 (mA) IREG2 (mA) 5.0 4.5 4.0 5.0 4.5 3.5 - 50 0 50 4.0 - 50 100 0 250 VCC = 12 V 200 VCC = 12 V 200 150 ISINK (mA) ISOURCE (mA) 100 OUTA, OUTB ISINK vs. VOL OUTA, OUTB ISOURCE vs. VOH 250 100 150 100 50 50 0 0 0 200 400 600 0 800 200 400 600 800 VOL (mV) VOH (mV) SEC_SYNC ISOURCE vs. VOH SEC_SYNC ISINK vs. VOL 35 35 30 30 VCC = 12 V VCC = 12 V 25 25 ISINK (mA) ISOURCE (mA) 50 Temperature (_C) Temperature (_C) 20 15 20 15 10 10 5 5 0 0 0 200 400 VOH (mV) Document Number: 72099 S-03638—Rev. B, 20-Mar-03 600 800 0 200 400 600 800 VOL (mV) www.vishay.com 13 Si9124 New Product Vishay Siliconix TYPICAL WAVEFORMS Figure 8. Over Current Hiccup (CS2 = 200 mV) Figure 9. Over Current Hiccup Cycle OUTA 20 V/div OUTA 20 V/div VCC = 12 V VCC = 12 V OUTB 20 V/div OUTB 20 V/div CS2 100 mV/div CS2 100 mV/div GND CSS = 22 nF SS 1 V/div CSS = 22 nF SS 1 V/div 200 s/div 200 s/div Figure 10. Pre-Regulator Start-Up Figure 11. Operating Driver Waveforms VCC = 12 V OUTA 5 V/div VINEXT SEC_SYNC 5 V/div 10 V/div VCC OUTB 5 V/div 500 ns/div 2 ms/div Figure 12. SEC_SYNC Set-Up Time (td3, td4) VCC = 12 V Figure 13. SEC_SYNC Set-Up Time (td1, td2) VCC = 12 V SEC_SYNC 5 V/div OUTA 5 V/div OUTB 5 V/div SEC_SYNC 5 V/div 100 ns/div www.vishay.com 14 100 ns/div Document Number: 72099 S-03638—Rev. B, 20-Mar-03 Si9124 New Product Vishay Siliconix LOGIC REPRESENTATIVE APPLICATION SCHEMATIC D3 U1 5 V Reg 4 C36 +5 V C37 0.1 F 0.1 F GND +5 V D1B BAT54S R33 470 D1A BAT54S +5 V TXOUT C35 R31 0.1 F 10 4 D1B BAT54S D1A BAT54S L2A +5 V PRE 3 R32 1 k CLX 2 D 1 CLR C36 10 F OUTN 11 12 13 +5 V D1B BAT54S 2 74AC00 L3B CLX Q 9 D CLR Q 8 D1A BAT54S GATEA 2 74AC32 PRE 74HC74 1 3 L2A GND 470 Q L4A L3A 5 6 74HC74 +5 V 10 R34 Q 4 6 5 R35 5 k R36 5 k GATEB 5 74AC32 +5 V L4B 74AC00 R37 1 k 3 GND 1 2 OUTP 5V GND Tab 1 VIN VOUT 3 1 VAUX VAUX 1N4001 Q5 2N3904 VOUT Figure 14. Document Number: 72099 S-03638—Rev. B, 20-Mar-03 www.vishay.com 15 C10 4.7 F 16 V 1 2 3 C29 470 pF C9 1 F 4 VCC OUTA VREF PGND2 GND OUTB ROSC PGND R1 90 k C30 200 - 800 pF R6 35 k 6 7 R5 10 k 8 EP SEC_SYNC 4 15 13 CS1 SS CS2 9, 10 30BQ040 Q5 D7 30BQ040 D6 MBR0520 Si4886DY 5, 6, 7, 8 1, 2, 3 2 k 7, 8 8:2:2 4 5, 6, 7, 8 C12 15 pF C14 22 nF 3.3 V 3,4 R12 0.01 9 C22 + 47 F 10 V 1, 2, 3 C23 + 47 F 10 V C16 R15 1 nF 3.3 Figure 15. R24 1 M C34 0.1 F 5V OUTP GATEA OUTN GATEB R19 2.2 k C28 1 nF C25 33 nF Q8B 3 VAUX GND R26 5.6 k 1 2 VIN - TX_OUT 2:1 EP7 2 2 Q7B VOUT T2 U2 MOC207 5 VOUT 4 LOGIC C21 0.047 F VIN + C32 + 10 F 6.3 V Si4886DY 2 k 6 C24 + 47 F 10 V OUT_GND Q6 R11 2 k R7 GND 1:3 1, 2, 3 3 4 4 6 6 1 R18 300 k Q7A Si3552DV 1 5 Q8A Si3552DV 5 7 Document Number: 72099 S-03638—Rev. B, 20-Mar-03 R22 33 k 7 6 U3 LM7301 3 + - 2 R25 2 k 4 C26 0.1 F C27 0.1 F 1 2 U4 LM4041C1M3 - 1.2 3 OUT_GND + C19 4.7 F 16 V C33 0.1 F R23 18.6 k New Product C11 1 nF 5 4 D5 Si4490DY 1, 2, 3 10 T3 LEP-9080 7, 8, 9 Q2 11 1, 2, 3 Q4 D4 30BQ040 Si4886DY 11, 12 4 12 D8 DAS19 4 5, 6, 7, 8 Si4490DY 1, 2, 3 14 R16 10 Q3 Q1 R10 VINDET 5, 6, 7, 8 D11 SMAJ12CA Si4886DY 5, 6, 7, 8 5 3.3 4 1, 2, 3 PUSH - PULL 5, 6 T1 1, 2 VCC2 Si9124 1 nF 5, 6, 7, 8 16 VIN + C4 15 F 100 V R14 Si9124 + C3 + C2 1 F 15 F 100 V 100 V R27 1.4 k C15 Vishay Siliconix + C1 1 F 100 V REPRESENTATIVE APPLICATION SCHEMATIC DIAGRAM www.vishay.com 16 VINEXT