Renesas HD6413007 16-bit single-chip microcomputer Datasheet

REJ09B0396-0500
The revision list can be viewed directly by clicking the title page.
The revision list summarizes the locations of revisions and
additions. Details should always be checked by referring to the
relevant text.
16
H8/3006, H8/3007
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8 Family/H8/300H Series
H8/3006
H8/3007
Rev.5.00
Revision date: Sep. 12, 2007
HD6413006
HD6413007
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev.5.00 Sep. 12, 2007 Page ii of xxviii
REJ09B0396-0500
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in
the manual.
⎯ The input pins of CMOS products are generally in the high-impedance state. In
operation with an unused pin in the open-circuit state, extra electromagnetic noise is
induced in the vicinity of LSI, an associated shoot-through current flows internally, and
malfunctions may occur due to the false recognition of the pin state as an input signal.
Unused pins should be handled as described under Handling of Unused Pins in the
manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
⎯ The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the
states of pins are not guaranteed from the moment when power is supplied until the
reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on
reset function are not guaranteed from the moment when power is supplied until the
power reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
⎯ The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has
become stable. When switching the clock signal during program execution, wait until the
target clock signal has stabilized.
⎯ When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization
of the clock signal. Moreover, when switching to a clock signal produced with an
external resonator (or by an external oscillator) while program execution is in progress,
wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number,
confirm that the change will not lead to problems.
⎯ The characteristics of MPU/MCU in the same group but having different type numbers
may differ because of the differences in internal memory capacity and layout pattern.
When changing to products of different type numbers, implement a system-evaluation
test for each of the products.
Rev.5.00 Sep. 12, 2007 Page iii of xxviii
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Rev.5.00 Sep. 12, 2007 Page iv of xxviii
REJ09B0396-0500
Preface
The H8/3006 and H8/3007 are a series of high-performance microcontrollers that integrate system
supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include RAM, 16-bit timers, 8-bit timers, a programmable
timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI),
an A/D converter, a D/A converter, I/O ports, and a DMA controller (DMAC).
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently in each area, simplifying the connection of different types of memory. Four
MCU operating modes (modes 1 to 4) are provided, offering a choice of data bus width initial
value and address space.
With these features, the H8/3006 and H8/3007 offer easy implementation of compact, highperformance systems.
This manual describes the H8/3006 and H8/3007 Group hardware. For details of the instruction
set, refer to the H8/300H Series Software Manual.
Rev.5.00 Sep. 12, 2007 Page v of xxviii
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Rev.5.00 Sep. 12, 2007 Page vi of xxviii
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Main Revisions for This Edition
Item
Page
Revision (See Manual for Details)
All
⎯
Company name and brand names amended
(Before) Hitachi, Ltd. → (After) Renesas Technology Corp.
5.4.2 Interrupt
Sequence
102
Figure amended
D15 to D0
Figure 5.7 Interrupt
Sequence
8.7.2 Register
Configuration
274
Table 8.14 Port A Pin
Functions (Modes 1 to
4)
Description and note amended
Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to
TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, bits CKS2 to
CKS0 in 8TCR2 of the 8-bit timer, bit NDER3 in NDERA, and
bit PA3DDR select the pin function as follows.
PA3/TP3/TIOCB0/TCLKD
Notes: 2. TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in
any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in
8TCR2 are as shown in (3) in the table below.
PA2/TP2/TIOCA0/TCLKC 275
Table amended
Pin
Pin Functions and Selection Method
PA2/TP2/
TIOCA0/
TCLKC
Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2
to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR0 of the 8-bit timer, bit
NDER2 in NDERA, and bit PA2DDR select the pin function as follows.
16-bit timer
channel 0
settings
(1) in table below
(2) in table below
PA2DDR
⎯
0
1
1
NDER2
⎯
⎯
0
1
TIOCA0 output
PA2
input
PA2
output
Pin function
TP2
output
TIOCA0 input*
TCLKC input*
1
2
Notes: 1. TIOCA0 input when IOA2 = 1.
2. TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of
16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR0 are as shown in
(3) in the table below.
16-bit timer
channel 0
settings
(2)
(1)
PWM0
(2)
(1)
1
⎯
0
IOA2
1
0
IOA1
0
0
1
⎯
⎯
IOA0
0
1
⎯
⎯
⎯
8-bit timer
channel 0
settings
(4)
CKS2
0
CKS1
⎯
CKS0
⎯
(3)
1
0
0
1
1
⎯
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Item
Page
Revision (See Manual for Details)
8.7.2 Register
Configuration
276
Table amended
Table 8.14 Port A Pin
Functions (Modes 1 to
4)
Pin
Pin Functions and Selection Method
PA1/TP1/
TCLKB/
TEND1
Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer,
bits CKS2 to CKS0 in 8TCR3 of the 8-bit timer, bit NDER1 in NDERA, and bit
PA1DDR select the pin function as follows.
PA1/TP1/TCLKB/TEND1
PA1DDR
0
1
NDER1
⎯
0
1
PA1 input
PA1 output
TP1 output
Pin function
1
TCLKB input*
1
TEND1 output*
2
Notes: 1. TCLKB input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0, and
TPSC0 = 1 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in
8TCR3 are as shown in (1) in the table below.
2. When an external request is specified as a DMAC activation source,
TEND1 output regardless of bits PA1DDR and NDER1.
8-bit timer
channel 3
settings
PA0/TP0/TCLKA/TEND0 277
(2)
CKS2
0
CKS1
⎯
CKS0
⎯
(1)
1
0
0
1
⎯
1
Table amended
Pin
Pin Functions and Selection Method
PA0/TP0/
TCLKA/
TEND0
Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer,
bits CKS2 to CKS0 in 8TCR1 of the 8-bit timer, bit NDER0 in NDERA, and bit
PA0DDR select the pin function as follows.
PA 0DDR
0
NDER0
⎯
Pin function
1
0
PA0 input
1
PA0 output
TP0 output
TCLKA input*
1
TEND0 output*
2
Notes: 1. TCLKA input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0 and
TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in
8TCR0 are as shown in (1) in the table below.
2. When an external request is specified as a DMAC activation source,
TEND0 output regardless of bits PA0DDR and NDER0.
8-bit timer
channel 1
settings
Rev.5.00 Sep. 12, 2007 Page viii of xxviii
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(2)
CKS2
0
CKS1
⎯
CKS0
⎯
(1)
1
0
0
1
1
⎯
Item
Page
Revision (See Manual for Details)
8.8.2 Register
Configuration
281
Description amended
The DRAM interface settings by bits DRAS2 to DRAS0 in
DRCRA, bits OIS3/2 and OS1/0 in 8TCSR3, bits CCLR1 and
CCLR0 in 8TCR3, bit CS4E in CSCR, bit NDER11 in NDERB,
and bit PB3DDR select the pin function as follows.
Port B Data Register
(PBDR):
Table 8.16 Port B Pin
Functions
PB3/TP11/TMIO3/DREQ1/
CS4
PB2/TP10/TMO2/CS5
282
Table amended
Pin
Pin Functions and Selection Method
PB2/TP10/
TMO2/CS5
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and
OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and bit PB2DDR
select the pin function as follows.
DRAM interface
settings
(1) in table below
OIS3/2 and
OS1/0
All 0
⎯
1
⎯
⎯
0
1
1
⎯
⎯
⎯
NDER10
⎯
0
1
⎯
⎯
⎯
PB2
input
PB2
output
TP10
output
CS5
output
TMO2
output
CS5
output*
0
Pin function
PB0/TP8/TMO0/CS7
Not all 0
PB2DDR
CS5E
PB1/TP9/TMIO1/DREQ0/
CS6
(2) in
table
below
Description amended
Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCLR1 and CCLR0 in
8TCR0, bit CS6E in CSCR, bit NDER9 in NDERB, and bit
PB1DDR select the pin function as follows.
283
Description amended
Bits OIS3/2 and OS1/0 in 8TCSR0, bit CS7E in CSCR, bit
NDER8 in NDERB, and bit PB0DDR select the pin function as
follows.
9.1.4 Register
Configuration
Table 9.3 16-bit timer
Registers
291
Table amended
Channel
Address*
Name
Abbreviation
R/W
Common
H'FFF64
Timer interrupt status register A
TISRA
R/(W)* H'88
1
Initial
Value
2
Rev.5.00 Sep. 12, 2007 Page ix of xxviii
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Item
Page
Revision (See Manual for Details)
9.4.6 Setting Initial
Value of 16-Bit Timer
Output
333
Figure amended
T1
φ
Figure 9.32 Example of
Timing for Setting Initial
Value of 16-Bit Timer
Output by Writing to
TOLR
Address bus
TOLR
16-bit timer output pin
10.2.3 Time Constant 357
Registers B (TCORB)
Note added
10.2.4 Timer Control
Register (8TCR)
Note added
359
TOLR address
N
N
Note: * When channel 1 and channel 3 are designated for
TCORB input capture, the CMFB flag is not set by a
channel 0 or channel 2 compare match B.
Note: When input capture B is set as the 8TCNT1 and
8TCNT3 counter clear source, 8TCNT0 and 8TCNT2
are not cleared by compare match B.
Bits 4 and 3⎯Counter
Clear 1 and 0 (CCLR1,
CCLR0):
Bits 2 to 0⎯Clock
Select 2 to 0 (CSK2 to
CSK0):
Description replaced
10.2.5 Timer
362
Control/Status Registers
(8TCSR)
Note added
Bit 7⎯Compare
Match/Input Capture
Flag B (CMFB):
Bit 6⎯Compare Match
Flag A (CMFA):
Bit 4⎯Reserved (In
8TCSR1):
T3
T2
Note: * When bit ICE is set to 1 in 8TCSR1 and 8TCSR3, the
CMFB flag is not set when 8TCNT0 = TCORB0 or
8TCNT2 = TCORB2.
Description amended
Status flag that indicates the occurrence of a TCORA compare
match
.
363
Description replaced
Bit 4⎯Input Capture
Enable (ICE) (In
8TCSR1 and 8TCSR3):
Rev.5.00 Sep. 12, 2007 Page x of xxviii
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Item
Page
Revision (See Manual for Details)
10.4.5 Operation with
Cascaded Connection
373
Description amended
…In this case, the timer operates as below. Similarly, if bits
CKS2 to CKS0 are set to (100) in either 8TCR2 or 8TCR3, the
8-bit timers of channels 2 and 3 are cascaded. …
375
Description amended
• The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter
(8TCNT3) overflows (from H'FF to H'00).
10.4.6 Input Capture
Setting
376
11.3.3 Normal TPC
Output
406
Note added
Note: When TCORB1 in channel 1 is used for input capture,
TCORB0 in channel 0 cannot be used as a compare
match register.
Similarly, when TCORB3 in channel 3 is used for input
capture, TCORB2 in channel 2 cannot be used as a
compare match register.
Description amended
4. Enable the IMFA interrupt in TISRA.
The DMAC can also be set up to transfer data to the next
data register.
Figure 11.4 Setup
Procedure for Normal
TPC Output (Example)
Figure 11.5 Normal
TPC Output Example
(Five-Phase Pulse
Output)
407
13.1 Overview
425
Description amended
• The 16-bit timer channel to be used as the output trigger
channel is set up so that GRA is an output compare register
and the counter will be cleared by compare match A. The
trigger period is set in GRA.
The IMIEA bit is set to 1 in TISRA to enable the compare
match A interrupt.
Description amended
The H8/3006 and H8/3007 have a serial communication
interface (SCI) with three independent channels. All three
channels have identical functions. The SCI can communicate in
both asynchronous and synchronous mode. It also has a
multiprocessor communication function for serial
communication among two or more processors.
13.2.3 Transmit Shift
Register (TSR)
431
13.3.4 Synchronous
Operation
478
Description amended
… If the TDRE flag is set to 1 in SSR, however, the SCI does
not load the TDR contents into TSR. The CPU cannot read or
write TSR directly.
Description amended
• The SCI synchronizes with the serial clock input or output and
performs receive operation.
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Item
Page
Revision (See Manual for Details)
14.3.4 Register
Settings
499
Description amended
With the direct convention type, the logic 1 level corresponds to
state Z and the logic 0 level to state A, and transfer is
performed in LSB-first order. In the example above, the first
character data is H'3B. The parity bit is 1, following the even
parity rule designated for smart cards.
Smart Card Mode
Register (SCMR)
Settings:
14.4 Usage Notes
511
Note on Block Transfer
Mode Support:
15.1 Overview
Description added
The smart card interface installed in the H8/3006 and H8/3007
support an IC card (smart card) interface with provision for
ISO/IEC7816-3 T=0 (character transmission). Therefore, block
transfer operations are not supported (error signal transmission,
detection, and automatic data retransmission are not
performed).
513
Description amended
When the A/D converter is not used, it can be halted
independently to conserve power. For details see section 19.6,
Module Standby Function.
The H8/3006 and H8/3007 support 70/134-state conversion as
a high-speed conversion mode. Note that it differs in this
respect from the H8/3048 Group, which supports 134/266-state
conversion.
15.2.1 A/D Data
Registers A to D
(ADDRA to ADDRD)
517
16.1.3 Pin
Configuration
536
The CPU can always read
Table 16.1 D/A
Converter Pins
20.2.2 AC
Characteristics
581
Table 20.7 Control
Signal Timing
20.3.6 Timer
Input/Output Timing
Description amended
603
A.3 Number of States 633
Required for Execution
the A/D data registers.
Table amended
Pin Name
Abbreviation
I/O
Function
Analog power
supply pin
AVCC
Input
Analog power supply and
reference voltage
Table amended
Item
Symbol
NMI, IRQ pulse width
(in recovery from software standby mode)
tNMIW
Description amended
The timings of 16-bit and 8-bit timer are shown as follows:
Notes amended
Notes: 1. Not available in the H8/3006 and H8/3007.
Table A.4 Number of
Cycles per Instruction
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2. n is the value set in register R4L or R4. The source
and destination are accessed n + 1 times each.
Item
Page
Revision (See Manual for Details)
C.3 Port 7 Block
Diagrams
724
Figure amended
Figure C.3 (b) Port 7
Block Diagram (Pins P76
and P77)
C.7 Port B Block
Diagrams
P7 n
742
Figure amended
Figure C.7 (e) Port B
Block Diagram (Pin PB6)
PB6
Figure C.7 (f) Port B
743
Block Diagram (Pin PB7)
Figure amended
RPB
Rev.5.00 Sep. 12, 2007 Page xiii of xxviii
REJ09B0396-0500
Item
Page
759
Appendix H
Comparison of H8/300H
Series Product
Specifications
Revision (See Manual for Details)
Table amended
H8/3067, H8/3062
Group
Item
9
A/D
Conversion start External trigger/8-bit
converter trigger input
timer compare match
H.1 Differences
between H8/3067 and
H8/3062 Group,
H8/3048 Group,
H8/3006 and H8/3007,
and H8/3002
Conversion
states
70/134
H8/3048
Group
H8/3006, H8/3007
H8/3002
External
trigger
External trigger/8-bit
timer compare match
External
trigger
134/266
70/134
134/266
All trademarks and registered trademarks are the property of their respective owners.
Rev.5.00 Sep. 12, 2007 Page xiv of xxviii
REJ09B0396-0500
Contents
Section 1 Overview .............................................................................................................
1.1
1.2
1.3
1
Overview........................................................................................................................... 1
Internal Block Diagram..................................................................................................... 6
Pin Description.................................................................................................................. 7
1.3.1 Pin Arrangement .................................................................................................. 7
1.3.2 Pin Functions ....................................................................................................... 9
1.3.3 Pin Assignments in Each Mode ........................................................................... 14
Section 2 CPU ...................................................................................................................... 19
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Overview...........................................................................................................................
2.1.1 Features................................................................................................................
2.1.2 Differences from H8/300 CPU.............................................................................
CPU Operating Modes ......................................................................................................
Address Space ...................................................................................................................
Register Configuration ......................................................................................................
2.4.1 Overview..............................................................................................................
2.4.2 General Registers .................................................................................................
2.4.3 Control Registers .................................................................................................
2.4.4 Initial CPU Register Values .................................................................................
Data Formats .....................................................................................................................
2.5.1 General Register Data Formats ............................................................................
2.5.2 Memory Data Formats .........................................................................................
Instruction Set ...................................................................................................................
2.6.1 Instruction Set Overview .....................................................................................
2.6.2 Instructions and Addressing Modes .....................................................................
2.6.3 Tables of Instructions Classified by Function......................................................
2.6.4 Basic Instruction Formats ....................................................................................
2.6.5 Notes on Use of Bit Manipulation Instructions....................................................
Addressing Modes and Effective Address Calculation .....................................................
2.7.1 Addressing Modes ...............................................................................................
2.7.2 Effective Address Calculation..............................................................................
Processing States...............................................................................................................
2.8.1 Overview..............................................................................................................
2.8.2 Program Execution State......................................................................................
2.8.3 Exception-Handling State ....................................................................................
2.8.4 Exception-Handling Sequences ...........................................................................
2.8.5 Bus-Released State...............................................................................................
19
19
20
21
22
23
23
24
25
26
27
27
28
30
30
31
32
41
42
44
44
46
50
50
51
51
53
54
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REJ09B0396-0500
2.9
2.8.6 Reset State ...........................................................................................................
2.8.7 Power-Down State ...............................................................................................
Basic Operational Timing .................................................................................................
2.9.1 Overview..............................................................................................................
2.9.2 On-Chip Memory Access Timing........................................................................
2.9.3 On-Chip Supporting Module Access Timing ......................................................
2.9.4 Access to External Address Space .......................................................................
54
54
55
55
55
56
57
Section 3 MCU Operating Modes .................................................................................. 59
3.1
3.2
3.3
3.4
3.5
3.6
Overview...........................................................................................................................
3.1.1 Operating Mode Selection ...................................................................................
3.1.2 Register Configuration.........................................................................................
Mode Control Register (MDCR) ......................................................................................
System Control Register (SYSCR) ...................................................................................
Operating Mode Descriptions ...........................................................................................
3.4.1 Mode 1 .................................................................................................................
3.4.2 Mode 2 .................................................................................................................
3.4.3 Mode 3 .................................................................................................................
3.4.4 Mode 4 .................................................................................................................
Pin Functions in Each Operating Mode ............................................................................
Memory Map in Each Operating Mode ............................................................................
3.6.1 Note on Reserved Areas.......................................................................................
59
59
60
60
61
63
63
63
64
64
64
65
65
Section 4 Exception Handling ......................................................................................... 69
4.1
4.2
4.3
4.4
4.5
4.6
Overview...........................................................................................................................
4.1.1 Exception Handling Types and Priority...............................................................
4.1.2 Exception Handling Operation.............................................................................
4.1.3 Exception Vector Table .......................................................................................
Reset..................................................................................................................................
4.2.1 Overview..............................................................................................................
4.2.2 Reset Sequence ....................................................................................................
4.2.3 Interrupts after Reset............................................................................................
Interrupts...........................................................................................................................
Trap Instruction.................................................................................................................
Stack Status after Exception Handling..............................................................................
Notes on Stack Usage .......................................................................................................
69
69
69
70
72
72
72
74
75
76
76
77
Section 5 Interrupt Controller .......................................................................................... 79
5.1
Overview........................................................................................................................... 79
5.1.1 Features................................................................................................................ 79
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5.2
5.3
5.4
5.5
5.1.2 Block Diagram .....................................................................................................
5.1.3 Pin Configuration.................................................................................................
5.1.4 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
5.2.1 System Control Register (SYSCR) ......................................................................
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) .............................................
5.2.3 IRQ Status Register (ISR)....................................................................................
5.2.4 IRQ Enable Register (IER) ..................................................................................
5.2.5 IRQ Sense Control Register (ISCR) ....................................................................
Interrupt Sources ...............................................................................................................
5.3.1 External Interrupts ...............................................................................................
5.3.2 Internal Interrupts.................................................................................................
5.3.3 Interrupt Vector Table..........................................................................................
Interrupt Operation............................................................................................................
5.4.1 Interrupt Handling Process...................................................................................
5.4.2 Interrupt Sequence ...............................................................................................
5.4.3 Interrupt Response Time......................................................................................
Usage Notes ......................................................................................................................
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ......................
5.5.2 Instructions that Inhibit Interrupts........................................................................
5.5.3 Interrupts during EEPMOV Instruction Execution ..............................................
80
81
81
82
82
83
89
90
91
92
92
93
93
97
97
102
103
104
104
105
105
Section 6 Bus Controller.................................................................................................... 107
6.1
6.2
Overview...........................................................................................................................
6.1.1 Features................................................................................................................
6.1.2 Block Diagram .....................................................................................................
6.1.3 Pin Configuration.................................................................................................
6.1.4 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
6.2.1 Bus Width Control Register (ABWCR)...............................................................
6.2.2 Access State Control Register (ASTCR) .............................................................
6.2.3 Wait Control Registers H and L (WCRH, WCRL)..............................................
6.2.4 Bus Release Control Register (BRCR) ................................................................
6.2.5 Bus Control Register (BCR) ................................................................................
6.2.6 Chip Select Control Register (CSCR)..................................................................
6.2.7 DRAM Control Register A (DRCRA) .................................................................
6.2.8 DRAM Control Register B (DRCRB) .................................................................
6.2.9 Refresh Timer Control/Status Register (RTMCSR) ............................................
6.2.10 Refresh Timer Counter (RTCNT)........................................................................
6.2.11 Refresh Time Constant Register (RTCOR) .........................................................
107
107
108
110
111
112
112
113
113
117
119
121
122
124
127
128
129
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6.3
Operation ..........................................................................................................................
6.3.1 Area Division.......................................................................................................
6.3.2 Bus Specifications................................................................................................
6.3.3 Memory Interfaces...............................................................................................
6.3.4 Chip Select Signals ..............................................................................................
6.4 Basic Bus Interface ...........................................................................................................
6.4.1 Overview..............................................................................................................
6.4.2 Data Size and Data Alignment.............................................................................
6.4.3 Valid Strobes........................................................................................................
6.4.4 Memory Areas .....................................................................................................
6.4.5 Basic Bus Control Signal Timing ........................................................................
6.4.6 Wait Control ........................................................................................................
6.5 DRAM Interface ...............................................................................................................
6.5.1 Overview..............................................................................................................
6.5.2 DRAM Space and RAS Output Pin Settings .......................................................
6.5.3 Address Multiplexing...........................................................................................
6.5.4 Data Bus...............................................................................................................
6.5.5 Pins Used for DRAM Interface............................................................................
6.5.6 Basic Timing........................................................................................................
6.5.7 Precharge State Control .......................................................................................
6.5.8 Wait Control ........................................................................................................
6.5.9 Byte Access Control and CAS Output Pin...........................................................
6.5.10 Burst Operation....................................................................................................
6.5.11 Refresh Control....................................................................................................
6.5.12 Examples of Use ..................................................................................................
6.5.13 Usage Notes .........................................................................................................
6.6 Interval Timer ...................................................................................................................
6.6.1 Operation .............................................................................................................
6.7 Interrupt Sources...............................................................................................................
6.8 Burst ROM Interface.........................................................................................................
6.8.1 Overview..............................................................................................................
6.8.2 Basic Timing........................................................................................................
6.8.3 Wait Control ........................................................................................................
6.9 Idle Cycle..........................................................................................................................
6.9.1 Operation .............................................................................................................
6.9.2 Pin States in Idle Cycle ........................................................................................
6.10 Bus Arbiter........................................................................................................................
6.10.1 Operation .............................................................................................................
6.11 Register and Pin Input Timing ..........................................................................................
6.11.1 Register Write Timing .........................................................................................
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130
132
133
133
134
134
134
136
136
138
145
147
147
147
148
148
149
149
151
152
153
154
160
164
168
170
170
175
176
176
176
177
178
178
181
182
182
185
185
6.11.2 BREQ Pin Input Timing ...................................................................................... 186
Section 7 DMA Controller ................................................................................................ 187
7.1
7.2
7.3
7.4
7.5
7.6
Overview...........................................................................................................................
7.1.1 Features................................................................................................................
7.1.2 Block Diagram .....................................................................................................
7.1.3 Functional Overview............................................................................................
7.1.4 Pin Configuration.................................................................................................
7.1.5 Register Configuration.........................................................................................
Register Descriptions (1) (Short Address Mode) ..............................................................
7.2.1 Memory Address Registers (MAR) .....................................................................
7.2.2 I/O Address Registers (IOAR) .............................................................................
7.2.3 Execute Transfer Count Registers (ETCR) ..........................................................
7.2.4 Data Transfer Control Registers (DTCR) ............................................................
Register Descriptions (2) (Full Address Mode) ................................................................
7.3.1 Memory Address Registers (MAR) .....................................................................
7.3.2 I/O Address Registers (IOAR) .............................................................................
7.3.3 Execute Transfer Count Registers (ETCR) ..........................................................
7.3.4 Data Transfer Control Registers (DTCR) ............................................................
Operation...........................................................................................................................
7.4.1 Overview..............................................................................................................
7.4.2 I/O Mode..............................................................................................................
7.4.3 Idle Mode.............................................................................................................
7.4.4 Repeat Mode ........................................................................................................
7.4.5 Normal Mode.......................................................................................................
7.4.6 Block Transfer Mode ...........................................................................................
7.4.7 DMAC Activation................................................................................................
7.4.8 DMAC Bus Cycle ................................................................................................
7.4.9 Multiple-Channel Operation ................................................................................
7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................
7.4.11 NMI Interrupts and DMAC..................................................................................
7.4.12 Aborting a DMAC Transfer.................................................................................
7.4.13 Exiting Full Address Mode ..................................................................................
7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode..........................
Interrupts ...........................................................................................................................
Usage Notes ......................................................................................................................
7.6.1 Note on Word Data Transfer................................................................................
7.6.2 DMAC Self-Access .............................................................................................
7.6.3 Longword Access to Memory Address Registers ................................................
7.6.4 Note on Full Address Mode Setup .......................................................................
187
187
188
188
190
190
191
192
192
193
195
198
198
198
199
201
207
207
209
211
214
218
221
226
227
233
234
235
236
237
238
238
239
239
239
240
240
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7.6.5
7.6.6
7.6.7
7.6.8
7.6.9
Note on Activating DMAC by Internal Interrupts ...............................................
NMI Interrupts and Block Transfer Mode ...........................................................
Memory and I/O Address Register Values ..........................................................
Bus Cycle when Transfer Is Aborted ...................................................................
Transfer Requests by A/D Converter...................................................................
241
242
242
243
243
Section 8 I/O Ports .............................................................................................................. 245
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Overview...........................................................................................................................
Port 4.................................................................................................................................
8.2.1 Overview..............................................................................................................
8.2.2 Register Configuration.........................................................................................
Port 6.................................................................................................................................
8.3.1 Overview..............................................................................................................
8.3.2 Register Configuration.........................................................................................
Port 7.................................................................................................................................
8.4.1 Overview..............................................................................................................
8.4.2 Register Configuration.........................................................................................
Port 8.................................................................................................................................
8.5.1 Overview..............................................................................................................
8.5.2 Register Configuration.........................................................................................
Port 9.................................................................................................................................
8.6.1 Overview..............................................................................................................
8.6.2 Register Configuration.........................................................................................
Port A................................................................................................................................
8.7.1 Overview..............................................................................................................
8.7.2 Register Configuration.........................................................................................
Port B ................................................................................................................................
8.8.1 Overview..............................................................................................................
8.8.2 Register Configuration.........................................................................................
245
248
248
249
251
251
252
255
255
255
256
256
257
261
261
262
265
265
267
277
277
278
Section 9 16-Bit Timer....................................................................................................... 285
9.1
9.2
Overview...........................................................................................................................
9.1.1 Features................................................................................................................
9.1.2 Block Diagrams ...................................................................................................
9.1.3 Pin Configuration.................................................................................................
9.1.4 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
9.2.1 Timer Start Register (TSTR) ...............................................................................
9.2.2 Timer Synchro Register (TSNC) .........................................................................
9.2.3 Timer Mode Register (TMDR) ............................................................................
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285
287
290
291
292
292
293
295
9.3
9.4
9.5
9.6
9.2.4 Timer Interrupt Status Register A (TISRA).........................................................
9.2.5 Timer Interrupt Status Register B (TISRB) .........................................................
9.2.6 Timer Interrupt Status Register C (TISRC) .........................................................
9.2.7 Timer Counters (16TCNT) ..................................................................................
9.2.8 General Registers (GRA, GRB)...........................................................................
9.2.9 Timer Control Registers (16TCR) .......................................................................
9.2.10 Timer I/O Control Register (TIOR) .....................................................................
9.2.11 Timer Output Level Setting Register C (TOLR) .................................................
CPU Interface....................................................................................................................
9.3.1 16-Bit Accessible Registers .................................................................................
9.3.2 8-Bit Accessible Registers ...................................................................................
Operation...........................................................................................................................
9.4.1 Overview..............................................................................................................
9.4.2 Basic Functions....................................................................................................
9.4.3 Synchronization ...................................................................................................
9.4.4 PWM Mode..........................................................................................................
9.4.5 Phase Counting Mode ..........................................................................................
9.4.6 Setting Initial Value of 16-Bit Timer Output .......................................................
Interrupts ...........................................................................................................................
9.5.1 Setting of Status Flags..........................................................................................
9.5.2 Timing of Clearing of Status Flags ......................................................................
9.5.3 Interrupt Sources and DMA Controller Activation..............................................
Usage Notes ......................................................................................................................
297
300
303
305
306
307
310
312
314
314
316
317
317
317
325
327
331
333
334
334
336
336
338
Section 10 8-Bit Timers ..................................................................................................... 351
10.1 Overview...........................................................................................................................
10.1.1 Features................................................................................................................
10.1.2 Block Diagram .....................................................................................................
10.1.3 Pin Configuration.................................................................................................
10.1.4 Register Configuration.........................................................................................
10.2 Register Descriptions ........................................................................................................
10.2.1 Timer Counters (8TCNT) ....................................................................................
10.2.2 Time Constant Registers A (TCORA) .................................................................
10.2.3 Time Constant Registers B (TCORB)..................................................................
10.2.4 Timer Control Register (8TCR) ...........................................................................
10.2.5 Timer Control/Status Registers (8TCSR) ............................................................
10.3 CPU Interface....................................................................................................................
10.3.1 8-Bit Registers .....................................................................................................
10.4 Operation...........................................................................................................................
10.4.1 8TCNT Count Timing..........................................................................................
351
351
352
353
354
355
355
356
357
358
361
366
366
368
368
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10.4.2 Compare Match Timing.......................................................................................
10.4.3 Input Capture Signal Timing ...............................................................................
10.4.4 Timing of Status Flag Setting ..............................................................................
10.4.5 Operation with Cascaded Connection..................................................................
10.4.6 Input Capture Setting ...........................................................................................
10.5 Interrupt ............................................................................................................................
10.5.1 Interrupt Source ...................................................................................................
10.5.2 A/D Converter Activation....................................................................................
10.6 8-Bit Timer Application Example.....................................................................................
10.7 Usage Notes ......................................................................................................................
10.7.1 Contention between 8TCNT Write and Clear......................................................
10.7.2 Contention between 8TCNT Write and Increment ..............................................
10.7.3 Contention between TCOR Write and Compare Match ......................................
10.7.4 Contention between TCOR Read and Input Capture ...........................................
10.7.5 Contention between Counter Clearing by Input Capture and
Counter Increment ...............................................................................................
10.7.6 Contention between TCOR Write and Input Capture ..........................................
10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection) ........................................................................................
10.7.8 Contention between Compare Matches A and B .................................................
10.7.9 8TCNT Operation at Internal Clock Source Switchover .....................................
369
371
372
373
375
376
376
377
377
378
378
379
380
381
382
383
384
385
385
Section 11 Programmable Timing Pattern Controller (TPC) ................................. 389
11.1 Overview...........................................................................................................................
11.1.1 Features................................................................................................................
11.1.2 Block Diagram.....................................................................................................
11.1.3 Pin Configuration.................................................................................................
11.1.4 Register Configuration.........................................................................................
11.2 Register Descriptions ........................................................................................................
11.2.1 Port A Data Direction Register (PADDR) ...........................................................
11.2.2 Port A Data Register (PADR)..............................................................................
11.2.3 Port B Data Direction Register (PBDDR) ...........................................................
11.2.4 Port B Data Register (PBDR) ..............................................................................
11.2.5 Next Data Register A (NDRA) ............................................................................
11.2.6 Next Data Register B (NDRB).............................................................................
11.2.7 Next Data Enable Register A (NDERA)..............................................................
11.2.8 Next Data Enable Register B (NDERB) ..............................................................
11.2.9 TPC Output Control Register (TPCR) .................................................................
11.2.10 TPC Output Mode Register (TPMR) ...................................................................
11.3 Operation ..........................................................................................................................
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389
390
391
392
393
393
393
394
394
395
396
398
399
400
402
404
11.3.1 Overview..............................................................................................................
11.3.2 Output Timing......................................................................................................
11.3.3 Normal TPC Output.............................................................................................
11.3.4 Non-Overlapping TPC Output .............................................................................
11.3.5 TPC Output Triggering by Input Capture ............................................................
11.4 Usage Notes ......................................................................................................................
11.4.1 Operation of TPC Output Pins .............................................................................
11.4.2 Note on Non-Overlapping Output........................................................................
404
405
406
408
410
410
410
411
Section 12 Watchdog Timer ............................................................................................. 413
12.1 Overview...........................................................................................................................
12.1.1 Features................................................................................................................
12.1.2 Block Diagram .....................................................................................................
12.1.3 Pin Configuration.................................................................................................
12.1.4 Register Configuration.........................................................................................
12.2 Register Descriptions ........................................................................................................
12.2.1 Timer Counter (TCNT)........................................................................................
12.2.2 Timer Control/Status Register (TCSR) ................................................................
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................
12.2.4 Notes on Register Access.....................................................................................
12.3 Operation...........................................................................................................................
12.3.1 Watchdog Timer Operation .................................................................................
12.3.2 Interval Timer Operation .....................................................................................
12.3.3 Timing of Setting of Overflow Flag (OVF) .........................................................
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ..................................
12.4 Interrupts ...........................................................................................................................
12.5 Usage Notes ......................................................................................................................
413
413
414
414
415
415
415
416
418
419
420
420
422
422
423
423
424
Section 13 Serial Communication Interface ................................................................ 425
13.1 Overview...........................................................................................................................
13.1.1 Features................................................................................................................
13.1.2 Block Diagram .....................................................................................................
13.1.3 Pin Configuration.................................................................................................
13.1.4 Register Configuration.........................................................................................
13.2 Register Descriptions ........................................................................................................
13.2.1 Receive Shift Register (RSR) ..............................................................................
13.2.2 Receive Data Register (RDR) ..............................................................................
13.2.3 Transmit Shift Register (TSR) .............................................................................
13.2.4 Transmit Data Register (TDR).............................................................................
13.2.5 Serial Mode Register (SMR)................................................................................
425
425
427
428
429
430
430
430
431
431
432
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13.2.6 Serial Control Register (SCR)..............................................................................
13.2.7 Serial Status Register (SSR) ................................................................................
13.2.8 Bit Rate Register (BRR) ......................................................................................
13.3 Operation ..........................................................................................................................
13.3.1 Overview..............................................................................................................
13.3.2 Operation in Asynchronous Mode .......................................................................
13.3.3 Multiprocessor Communication...........................................................................
13.3.4 Synchronous Operation........................................................................................
13.4 SCI Interrupts....................................................................................................................
13.5 Usage Notes ......................................................................................................................
13.5.1 Notes on Use of SCI ............................................................................................
436
441
446
454
454
457
466
473
481
482
482
Section 14 Smart Card Interface ..................................................................................... 487
14.1 Overview...........................................................................................................................
14.1.1 Features................................................................................................................
14.1.2 Block Diagram.....................................................................................................
14.1.3 Pin Configuration.................................................................................................
14.1.4 Register Configuration.........................................................................................
14.2 Register Descriptions ........................................................................................................
14.2.1 Smart Card Mode Register (SCMR) ....................................................................
14.2.2 Serial Status Register (SSR) ................................................................................
14.2.3 Serial Mode Register (SMR) ...............................................................................
14.2.4 Serial Control Register (SCR)..............................................................................
14.3 Operation ..........................................................................................................................
14.3.1 Overview..............................................................................................................
14.3.2 Pin Connections ...................................................................................................
14.3.3 Data Format .........................................................................................................
14.3.4 Register Settings ..................................................................................................
14.3.5 Clock....................................................................................................................
14.3.6 Transmitting and Receiving Data ........................................................................
14.4 Usage Notes ......................................................................................................................
487
487
488
488
489
490
490
492
494
494
495
495
495
496
498
499
501
509
Section 15 A/D Converter ................................................................................................. 513
15.1 Overview...........................................................................................................................
15.1.1 Features................................................................................................................
15.1.2 Block Diagram.....................................................................................................
15.1.3 Pin Configuration.................................................................................................
15.1.4 Register Configuration.........................................................................................
15.2 Register Descriptions ........................................................................................................
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................
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513
514
515
516
516
516
15.3
15.4
15.5
15.6
15.2.2 A/D Control/Status Register (ADCSR) ...............................................................
15.2.3 A/D Control Register (ADCR) ............................................................................
CPU Interface....................................................................................................................
Operation...........................................................................................................................
15.4.1 Single Mode (SCAN = 0).....................................................................................
15.4.2 Scan Mode (SCAN = 1) .......................................................................................
15.4.3 Input Sampling and A/D Conversion Time..........................................................
15.4.4 External Trigger Input Timing .............................................................................
Interrupts ...........................................................................................................................
Usage Notes ......................................................................................................................
518
520
522
523
523
525
527
528
528
529
Section 16 D/A Converter ................................................................................................. 535
16.1 Overview...........................................................................................................................
16.1.1 Features................................................................................................................
16.1.2 Block Diagram .....................................................................................................
16.1.3 Pin Configuration.................................................................................................
16.1.4 Register Configuration.........................................................................................
16.2 Register Descriptions ........................................................................................................
16.2.1 D/A Data Registers 0 and 1 (DADR0/1)..............................................................
16.2.2 D/A Control Register (DACR) ............................................................................
16.2.3 D/A Standby Control Register (DASTCR) ..........................................................
16.3 Operation...........................................................................................................................
16.4 D/A Output Control ..........................................................................................................
535
535
536
536
537
537
537
538
539
540
541
Section 17 RAM .................................................................................................................. 543
17.1 Overview...........................................................................................................................
17.1.1 Block Diagram .....................................................................................................
17.1.2 Register Configuration.........................................................................................
17.2 System Control Register (SYSCR) ...................................................................................
17.3 Operation...........................................................................................................................
543
543
544
544
545
Section 18 Clock Pulse Generator .................................................................................. 547
18.1 Overview...........................................................................................................................
18.1.1 Block Diagram .....................................................................................................
18.2 Oscillator Circuit...............................................................................................................
18.2.1 Connecting a Crystal Resonator...........................................................................
18.2.2 External Clock Input ............................................................................................
18.3 Duty Adjustment Circuit ...................................................................................................
18.4 Prescalers ..........................................................................................................................
18.5 Frequency Divider.............................................................................................................
547
547
548
548
550
552
552
552
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18.5.1 Register Configuration......................................................................................... 553
18.5.2 Division Control Register (DIVCR) .................................................................... 553
18.5.3 Usage Notes ......................................................................................................... 554
Section 19 Power-Down State ......................................................................................... 555
19.1 Overview........................................................................................................................... 555
19.2 Register Configuration...................................................................................................... 557
19.2.1 System Control Register (SYSCR) ...................................................................... 557
19.2.2 Module Standby Control Register H (MSTCRH)................................................ 559
19.2.3 Module Standby Control Register L (MSTCRL)................................................. 560
19.3 Sleep Mode ....................................................................................................................... 562
19.3.1 Transition to Sleep Mode..................................................................................... 562
19.3.2 Exit from Sleep Mode.......................................................................................... 562
19.4 Software Standby Mode.................................................................................................... 563
19.4.1 Transition to Software Standby Mode ................................................................. 563
19.4.2 Exit from Software Standby Mode ...................................................................... 563
19.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 564
19.4.4 Sample Application of Software Standby Mode.................................................. 565
19.4.5 Note...................................................................................................................... 565
19.5 Hardware Standby Mode .................................................................................................. 566
19.5.1 Transition to Hardware Standby Mode................................................................ 566
19.5.2 Exit from Hardware Standby Mode ..................................................................... 566
19.5.3 Timing for Hardware Standby Mode ................................................................... 566
19.6 Module Standby Function................................................................................................. 567
19.6.1 Module Standby Timing ...................................................................................... 567
19.6.2 Read/Write in Module Standby............................................................................ 567
19.6.3 Usage Notes ......................................................................................................... 567
19.7 System Clock Output Disabling Function......................................................................... 568
Section 20 Electrical Characteristics ............................................................................. 569
20.1 Absolute Maximum Ratings .............................................................................................
20.2 Electrical Characteristics...................................................................................................
20.2.1 DC Characteristics ...............................................................................................
20.2.2 AC Characteristics ...............................................................................................
20.2.3 A/D Conversion Characteristics...........................................................................
20.2.4 D/A Conversion Characteristics...........................................................................
20.3 Operational Timing...........................................................................................................
20.3.1 Clock Timing .......................................................................................................
20.3.2 Control Signal Timing .........................................................................................
20.3.3 Bus Timing ..........................................................................................................
Rev.5.00 Sep. 12, 2007 Page xxvi of xxviii
REJ09B0396-0500
569
570
570
580
588
590
591
591
592
593
20.3.4
20.3.5
20.3.6
20.3.7
20.3.8
DRAM Interface Bus Timing ..............................................................................
TPC and I/O Port Timing.....................................................................................
Timer Input/Output Timing .................................................................................
SCI Input/Output Timing .....................................................................................
DMAC Timing.....................................................................................................
599
602
603
604
605
Appendix A Instruction Set .............................................................................................. 607
A.1
A.2
A.3
Instruction List .................................................................................................................. 607
Operation Code Maps ....................................................................................................... 622
Number of States Required for Execution ........................................................................ 625
Appendix B Internal I/O Registers ................................................................................. 634
B.1
B.2
Addresses .......................................................................................................................... 634
Functions........................................................................................................................... 643
Appendix C I/O Port Block Diagrams........................................................................... 719
C.1
C.2
C.3
C.4
C.5
C.6
C.7
Port 4 Block Diagram .......................................................................................................
Port 6 Block Diagrams......................................................................................................
Port 7 Block Diagrams......................................................................................................
Port 8 Block Diagrams......................................................................................................
Port 9 Block Diagrams......................................................................................................
Port A Block Diagrams .....................................................................................................
Port B Block Diagrams .....................................................................................................
719
720
723
725
729
735
738
Appendix D Pin States ....................................................................................................... 744
D.1
D.2
Port States in Each Mode .................................................................................................. 744
Pin States at Reset ............................................................................................................. 750
Appendix E Timing of Transition to and Recovery from Hardware
Standby Mode ............................................................................................... 752
Appendix F List of Product Codes ................................................................................. 753
Appendix G Package Dimensions .................................................................................. 754
Appendix H Comparison of H8/300H Series Product Specifications .................. 757
H.1
H.2
Differences between H8/3067 and H8/3062 Group, H8/3048 Group, H8/3006 and
H8/3007, and H8/3002 ...................................................................................................... 757
Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B) ....... 760
Rev.5.00 Sep. 12, 2007 Page xxvii of xxviii
REJ09B0396-0500
Rev.5.00 Sep. 12, 2007 Page xxviii of xxviii
REJ09B0396-0500
1. Overview
Section 1 Overview
1.1
Overview
The H8/3006 and H8/3007 are a series of microcontrollers (MCUs) that integrate system
supporting functions together with an H8/300H CPU core having an original Renesas architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include RAM, a 16-bit timer, an 8-bit timer, a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller
(DMAC), and other facilities.
Four MCU operating modes offer a choice of bus width and address space size.
Table 1.1 summarizes the features of the H8/3006 and H8/3007.
Rev.5.00 Sep. 12, 2007 Page 1 of 764
REJ09B0396-0500
1. Overview
Table 1.1
Features
Feature
Description
CPU
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
•
Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight
32-bit registers)
High-speed operation
•
Maximum clock rate: 20 MHz
•
Add/subtract: 100 ns
• Multiply/divide: 700 ns
16-Mbyte address space
Instruction features
Memory
•
8/16/32-bit data transfer, arithmetic, and logic instructions
•
Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits)
•
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
•
Bit accumulator function
•
Bit manipulation instructions with register-indirect specification of bit positions
H8/3007
• RAM: 4 kbytes
H8/3006
•
Interrupt
controller
RAM: 2 kbytes
•
Seven external interrupt pins: NMI, IRQ0 to IRQ5
•
36 internal interrupts
•
Three selectable interrupt priority levels
Rev.5.00 Sep. 12, 2007 Page 2 of 764
REJ09B0396-0500
1. Overview
Feature
Description
Bus controller
•
Address space can be partitioned into eight areas, with independent bus
specifications in each area
•
Chip select output available for areas 0 to 7
•
8-bit access or 16-bit access selectable for each area
DMA controller
(DMAC)
•
Two-state or three-state access selectable for each area
•
Selection of two wait modes
•
Number of program wait states selectable for each area
•
Direct connection of burst ROM
•
Direct connection of up to 8-Mbyte DRAM (or DRAM interface can be used
as interval timer)
•
Bus arbitration function
Short address mode
•
Maximum four channels available
•
Selection of I/O mode, idle mode, or repeat mode
•
Can be activated by compare match/input capture A interrupts from 16-bit
timer channels 0 to 2, conversion-end interrupts from the A/D converter,
transmit-data-empty and receive-data-full interrupts from the SCI, or external
requests
Full address mode
16-bit timer,
3 channels
•
Maximum two channels available
•
Selection of normal mode or block transfer mode
•
Can be activated by compare match/input capture A interrupts from 16-bit
timer channels 0 to 2, conversion-end interrupts from the A/D converter,
external requests, or auto-request
•
Three 16-bit timer channels, capable of processing up to six pulse outputs or
six pulse inputs
•
16-bit timer counter (channels 0 to 2)
•
Two multiplexed output compare/input capture pins (channels 0 to 2)
•
Operation can be synchronized (channels 0 to 2)
•
PWM mode available (channels 0 to 2)
•
Phase counting mode available (channel 2)
•
DMAC can be activated by compare match/input capture A interrupts
(channels 0 to 2)
Rev.5.00 Sep. 12, 2007 Page 3 of 764
REJ09B0396-0500
1. Overview
Feature
Description
8-bit timer,
4 channels
•
8-bit up-counter (external event count capability)
•
Two time constant registers
•
Two channels can be connected
•
Maximum 16-bit pulse output, using 16-bit timer as time base
•
Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)
•
Non-overlap mode available
•
Output data can be transferred by DMAC
•
Internal reset signal can be generated by overflow
•
Reset signal can be output externally
•
Usable as an interval timer
•
Selection of asynchronous or synchronous mode
•
Full duplex: can transmit and receive simultaneously
•
On-chip baud-rate generator
•
Smart card interface functions added
•
Resolution: 10 bits
•
Eight channels, with selection of single or scan mode
•
Variable analog conversion voltage range
•
Sample-and-hold function
•
A/D conversion can be started by an external trigger or 8-bit timer comparematch
•
DMAC can be activated by an A/D conversion end interrupt
•
Resolution: 8 bits
•
Two channels
•
D/A outputs can be sustained in software standby mode
•
35 input/output pins
•
12 input-only pins
Programmable
timing pattern
controller (TPC)
Watchdog
timer (WDT),
1 channel
Serial
communication
interface (SCI),
3 channels
A/D converter
D/A converter
I/O ports
Rev.5.00 Sep. 12, 2007 Page 4 of 764
REJ09B0396-0500
1. Overview
Feature
Description
Operating
modes
Four MCU operating modes
Mode
Address Space Address Pins Initial Bus Width Max. Bus Width
Mode 1
1 Mbyte
A19 to A0
8 bits
16 bits
Mode 2
1 Mbyte
A19 to A0
16 bits
16 bits
Mode 3
16 Mbytes
A23 to A0
8 bits
16 bits
Mode 4
16 Mbytes
A23 to A0
16 bits
16 bits
•
Sleep mode
•
Software standby mode
•
Hardware standby mode
•
Module standby function
•
Programmable system clock frequency division
Other features
•
On-chip clock pulse generator
Product lineup
Part No.
Power-down
state
H8/3007
5 V ±10%
(5 V)
2.7 to 5.5 V
(Low voltage)
H8/3006
5 V ±10%
(5 V)
2.7 to 5.5 V
(Low voltage)
Model
Package
HD6413007F
100-pin QFP (FP-100B)
HD6413007TE
100-pin TQFP (TFP-100B)
HD6413007FP
100-pin QFP (FP-100A)
HD6413007VF
100-pin QFP (FP-100B)
HD6413007VTE
100-pin TQFP (TFP-100B)
HD6413007VFP
100-pin QFP (FP-100A)
HD6413006F
100-pin QFP (FP-100B)
HD6413006TE
100-pin TQFP (TFP-100B)
HD6413006FP
100-pin QFP (FP-100A)
HD6413006VF
100-pin QFP (FP-100B)
HD6413006VTE
100-pin TQFP (TFP-100B)
HD6413006VFP
100-pin QFP (FP-100A)
Rev.5.00 Sep. 12, 2007 Page 5 of 764
REJ09B0396-0500
1. Overview
1.2
Internal Block Diagram
Data bus
P40 /D0
P41 /D1
P42 /D2
P43 /D3
P44 /D4
P45 /D5
P46 /D6
P47 /D7
D8
D9
D10
D11
D12
D13
D14
D15
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
Figure 1.1 shows an internal block diagram.
Port 4
Address bus
MD2
Data bus (upper)
MD1
Data bus (lower)
A19
A18
MD0
A17
EXTAL
A16
A15
Clock pulse
generator
STBY
RES
RESO
A14
H8/300H CPU
A13
Address bus
XTAL
Bus controller
NMI
Interrupt controller
AS
RD
DMA controller
(DMAC)
HWR
LWR
A10
A9
A8
A6
A5
Port 6
BREQ/P61
A11
A7
φ/P67
BACK/P62
A12
A4
A3
RAM
WAIT/P60
A2
A1
A0
CS0/P84
CS3/IRQ1/P81
16-bit timer unit
RFSH/IRQ0/P80
Serial communication
interface
(SCI) × 3 channels
8-bit timer unit
Programmable
timing pattern
controller (TPC)
P95 /SCK 1 /IRQ 5
P94 /SCK 0 /IRQ 4
A/D converter
Port 9
CS2/IRQ2/P82
Port 8
ADTRG/CS1/IRQ3/P83
Watchdog timer
(WDT)
D/A converter
P93 /RxD1
P92 /RxD0
P91 /TxD 1
P90 /TxD 0
Figure 1.1 Block Diagram
Rev.5.00 Sep. 12, 2007 Page 6 of 764
REJ09B0396-0500
AN0/P70
AN1/P71
AN2/P72
AN3/P73
AN4/P74
AN5/P75
DA0/AN6/P76
DA1/AN7/P77
AVSS
AVCC
VREF
TEND0/TCLKA/TP0/PA0
TEND1/TCLKB/TP1/PA1
Port 7
TCLKC/TIOCA0/TP2/PA2
TCLKD/TIOCB0/TP3/PA3
A23/TIOCA1/TP4/PA4
A22/TIOCB1/TP5/PA5
A21/TIOCA2/TP6/PA6
A20/TIOCB2/TP7/PA7
CS7/TMO0/TP8/PB0
CS6/DREQ0/TMIO1/TP9/PB1
Port A
CS5/TMO2/TP10/PB2
CS4/DREQ1/TMIO3/TP11/PB3
UCAS/TP12/PB4
TxD2/TP14/PB6
SCK2/LCAS/TP13/PB5
RxD2/TP15/PB7
Port B
1. Overview
1.3
Pin Description
1.3.1
Pin Arrangement
MD2
MD1
MD0
LWR
HWR
RD
AS
VCC
XTAL
EXTAL
VSS
NMI
RES
STBY
P67/φ
P62 /BACK
P61 /BREQ
P60 /WAIT
VSS
A19
A18
A17
A16
A15
A14
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
The pin arrangement of the H8/3006, H8/3007 FP-100B and TFP-100B packages is shown in
figure 1.2, and that of the FP-100A package in figure 1.3.
AVCC
76
50
A13
VREF
77
49
A12
P70/AN0
78
48
A11
P71/AN1
79
47
A10
P72/AN2
80
46
A9
P73/AN3
81
45
A8
P74/AN4
82
44
VSS
P75/AN5
83
43
A7
P76/AN6/DA0
84
42
A6
P77/AN7/DA1
85
41
A5
AVSS
86
40
A4
P80/IRQ0/RFSH
87
39
A3
P81/IRQ1/CS3
88
38
A2
P82/IRQ2/CS2
89
37
A1
P83/IRQ3/CS1/ADTRG
90
36
A0
P84/CS0
91
35
VCC
VSS
92
34
D15
PA0/TP0/TCLKA/TEND0
93
33
D14
PA1/TP1/TCLKB/TEND1
94
32
D13
PA2/TP2/TIOCA0/TCLKC
95
31
D12
PA3/TP3/TIOCB0/TCLKD
96
30
D11
PA4/TP4/TIOCA1/A23
97
29
D10
PA5/TP5/TIOCB1/A22
98
28
D9
PA6/TP6/TIOCA2/A21
99
27
D8
PA7/TP7/TIOCB2/A20
100
26
D7/P47
Top view
(FP-100B, TFP-100B)
15
16
17
18
19
20
21
22
23
24
25
RxD1 /P93
IRQ4 /SCK0 /P94
IRQ5 /SCK1 /P95
D0 /P40
D1 /P41
D2 /P42
D3 /P43
VSS
D4 /P44
D5 /P45
D6 /P46
14
9
RxD2/TP15/PB7
RxD0 /P92
8
TxD2/TP14/PB6
13
7
SCK2/LCAS/TP13/PB5
TxD1 /P91
6
UCAS/TP12/PB4
12
5
CS4/DREQ1/TMIO3/TP11/PB3
TxD0 /P90
4
CS5/TMO2/TP10/PB2
11
3
CS6/DREQ0/TMIO1/TP9/PB1
10
2
RESO
VSS
1
VCC
CS7/TMO0/TP8/PB0
INDEX
Figure 1.2 Pin Arrangement (FP-100B or TFP-100B, Top View)
Rev.5.00 Sep. 12, 2007 Page 7 of 764
REJ09B0396-0500
A21/TIOCA2 /TP6 /PA6
A20/TIOCB2 /TP7 /PA7
V CC
CS7 /TMO0 /TP8 /PB0
CS6 /DREQ 0 /TMIO1 /TP9 /PB1
CS 5 /TMO 2 /TP10 /PB2
CS 4 /DREQ 1 /TMIO 3 /TP11/PB3
UCAS/TP12 /PB4
SCK 2 /LCAS/TP13 /PB5
TxD 2 /TP14 /PB6
RxD 2 /TP15 /PB 7
RESO
VSS
TxD0 /P90
TxD1 /P91
RxD 0 /P9 2
RxD 1 /P9 3
IRQ 4 /SCK 0 /P94
IRQ 5 /SCK 1 /P95
D0 /P4 0
D1 /P41
D2 /P42
D3 /P43
V SS
D4/P44
D5/P45
D6/P46
D7/P47
D8
D9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P70/AN0
VREF
AVCC
MD2
MD1
MD0
LWR
HWR
RD
AS
VCC
XTAL
EXTAL
VSS
NMI
RES
STBY
P67/φ
P62/BACK
P61/BREQ
P60/WAIT
VSS
A19
A18
A17
A16
A15
A14
A13
A12
1. Overview
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6/DA0
P77/AN7/DA1
AVSS
P80/IRQ0/RFSH
P81/IRQ1/CS3
P82/IRQ2/CS2
P83/IRQ3/CS1/ADTRG
P84/CS0
VSS
PA0/TP0/TCLKA/TEND0
PA1/TP1/TCLKB/TEND1
PA2/TP2/TIOCA0/TCLKC
PA3/TP3/TIOCB0/TCLKD
PA4/TP4/TIOCA1/A23
PA5/TP5/TIOCB1/A22
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Rev.5.00 Sep. 12, 2007 Page 8 of 764
REJ09B0396-0500
Top view
(FP-100A)
Figure 1.3 Pin Arrangement (FP-100A, Top View)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A11
A10
A9
A8
VSS
A7
A6
A5
A4
A3
A2
A1
A0
VCC
D15
D14
D13
D12
D11
D10
1. Overview
1.3.2
Pin Functions
Table 1.2 summarizes the pin functions.
Table 1.2
Pin Functions
Pin No.
Type
Symbol
FP-100B
TFP-100B FP-100A I/O
Power
VCC
1, 35, 68
3, 37, 70 Input
Power: For connection to the power supply.
Connect all VCC pins to the system power
supply.
VSS
11, 22,
44, 57,
65, 92
13, 24,
46, 59,
67, 94
Input
Ground: For connection to ground (0 V).
Connect all VSS pins to the 0-V system power
supply.
XTAL
67
69
Input
For connection to a crystal resonator.
For examples of crystal resonator and external
clock input, see section 18, Clock Pulse
Generator.
EXTAL
66
68
Input
For connection to a crystal resonator or input
of an external clock signal. For examples of
crystal resonator and external clock input, see
section 18, Clock Pulse Generator.
φ
61
63
Output System clock: Supplies the system clock to
external devices.
75 to 73
77 to 75 Input
Clock
Operating MD2 to
mode
MD0
control
Name and Function
Mode 2 to mode 0: For setting the operating
mode, as follows. Inputs at these pins must
not be changed during operation.
MD2
MD1
MD0
Operating Mode
0
0
0
⎯
0
0
1
Mode 1
0
1
0
Mode 2
0
1
1
Mode 3
1
0
0
Mode 4
1
0
1
⎯
1
1
0
⎯
1
1
1
⎯
Rev.5.00 Sep. 12, 2007 Page 9 of 764
REJ09B0396-0500
1. Overview
Pin No.
Type
Symbol
FP-100B
TFP-100B FP-100A I/O
System
control
RES
63
65
Input
RESO
10
12
Output Reset output: Outputs the reset signal
generated by the watchdog timer to external
devices
STBY
62
64
Input
Standby: When driven low, this pin forces
a transition to hardware standby mode.
BREQ
59
61
Input
Bus request: Used by an external bus master
to request the bus right
BACK
60
62
Output Bus request acknowledge: Indicates that the
bus has been granted to an external bus
master
64
66
Input
IRQ5 to
IRQ0
17, 16,
90 to 87
19, 18, Input
92 to 89
Address
bus
A23 to A0
100 to 97, 99, 100, Output Address bus: Outputs address signals
56 to 45, 1, 2,
43 to 36 58 to 47,
45 to 38
Data bus
D15 to D0
34 to 23,
21 to 18
36 to 25, Input/ Data bus: Bidirectional data bus
23 to 20 output
Bus
control
CS7 to
CS0
2 to 5,
88 to 91
4 to 7,
Output Chip select: Select signals for areas 7 to 0
90 to 93
AS
69
71
Output Address strobe: Goes low to indicate valid
address output on the address bus
RD
70
72
Output Read: Goes low to indicate reading from the
external address space
HWR
71
73
Output High write: Goes low to indicate writing to the
external address space; indicates valid data
on the upper data bus (D15 to D8).
LWR
72
74
Output Low write: Goes low to indicate writing to the
external address space; indicates valid data
on the lower data bus (D7 to D0).
WAIT
58
60
Input
Interrupts NMI
Rev.5.00 Sep. 12, 2007 Page 10 of 764
REJ09B0396-0500
Name and Function
Reset input: When driven low, this pin resets
the chip.
Nonmaskable interrupt: Requests a
nonmaskable interrupt
Interrupt request 5 to 0: Maskable interrupt
request pins
Wait: Requests insertion of wait states in bus
cycles during access to the external address
space
1. Overview
Pin No.
Type
Symbol
FP-100B
TFP-100B FP-100A I/O
DRAM
interface
RFSH
87
CS2 to
CS5
89, 88, 5, 91, 90,
4
7, 6
Output Row address strobe RAS: Row address
strobe signal for DRAM
RD
70
72
Output Write enable WE: Write enable signal for
DRAM
HWR
UCAS
71
6
73
8
Output Upper column address strobe UCAS:
Column address strobe signal for DRAM
LWR
LCAS
72
7
74
9
Output Lower column address strobe LCAS:
Column address strobe signal for DRAM
DMA
controller
(DMAC)
DREQ1,
DREQ0
5, 3
7, 5
Input
TEND1,
TEND0
94, 93
96, 95
Output Transfer end 1 and 0: These signals indicate
that the DMAC has ended a data transfer.
16-bit
timer
TCLKD to 96 to 93
TCLKA
98 to95
Input
89
Name and Function
Output Refresh: Indicates a refresh cycle
DMA request 1 and 0: DMAC activation
requests
Clock input D to A: External clock inputs
TIOCA2 to 99, 97, 95 1, 99, 97 Input/ Input capture/output compare A2 to A0:
TIOCA0
output GRA2 to GRA0 output compare or input
capture, or PWM output
TIOCB2 to 100, 98,
TIOCB0
96
2, 100,
98
Input/ Input capture/output compare B2 to B0:
output GRB2 to GRB0 output compare or input
capture, or PWM output
8-bit timer TMO0,
TMO2
2, 4
4, 6
Output Compare match output: Compare match
output pins
TMIO1,
TMIO3
3, 5
5, 7
Input/ Input capture input/compare match output:
output Input capture input or compare match output
pins
TCLKD to 96 to 93
TCLKA
98 to 95 Input
Counter external clock input: These pins
input an external clock to the counters.
Rev.5.00 Sep. 12, 2007 Page 11 of 764
REJ09B0396-0500
1. Overview
Pin No.
Type
Symbol
FP-100B
TFP-100B FP-100A I/O
Name and Function
Program- TP15 to
mable
TP0
timing
pattern
controller
(TPC)
9 to 2,
11 to 4,
100 to 93 2, 1,
100 to
95
Output TPC output 15 to 0: Pulse output
Serial
communication
interface
(SCI)
TxD2 to
TxD0
8, 13, 12
10, 15,
14
Output Transmit data (channels 0, 1, 2): SCI data
output
RxD2 to
RxD0
9, 15, 14
11, 17,
16
Input
SCK2 to
SCK0
7, 17, 16
9, 19, 18 Input/ Serial clock (channels 0, 1, 2): SCI clock
output input/output
85 to 78
87 to 80 Input
Analog 7 to 0: Analog input pins
90
92
Input
A/D conversion external trigger input:
External trigger input for starting A/D
conversion
D/A
DA1, DA0
converter
85, 84
87, 86
Output Analog output: Analog output from the
D/A converter
A/D and
AVCC
D/A
converters
76
78
Input
Power supply pin for the A/D and
D/A converters. Connect to the system power
supply when not using the A/D and
D/A converters.
AVSS
86
88
Input
Ground pin for the A/D and D/A converters.
Connect to system ground (0 V).
VREF
77
79
Input
Reference voltage input pin for the A/D and
D/A converters. Connect to the system power
supply when not using the A/D and
D/A converters.
A/D
AN7 to
converter AN0
ADTRG
Rev.5.00 Sep. 12, 2007 Page 12 of 764
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Receive data (channels 0, 1, 2): SCI data
input
1. Overview
Pin No.
FP-100B
TFP-100B FP-100A I/O
Type
Symbol
Name and Function
I/O ports
P47 to P40 26 to 23,
21 to 18
28 to 25, Input/ Port 4: Eight-bit input/output pins. The
23 to 20 output direction of each-bit pin can be selected in the
port 4 data direction register (P4DDR).
P67,
61 to 58
P62 to P60
63 to 60 Input/ Port 6: Four-bit input/output pins. The
output direction of each-bit pin can be selected in the
port 6 data direction register (P6DDR).
P77 to P70 85 to 78
87 to 80 Input
P84 to P80 91 to 87
93 to 89 Input/ Port 8: Five-bit input/output pins. The direction
output of each-bit pin can be selected in the port 8
data direction register (P8DDR).
Port 7: Eight-bit input pins
P95 to P90 17 to 12
19 to 14 Input/ Port 9: Six-bit input/output pins. The direction
output of each-bit pin can be selected in the port 9
data direction register (P9DDR).
PA7 to
PA0
100 to 93 2, 1,
100 to
95
Input/ Port A: Eight-bit input/output pins. The
output direction of each-bit pin can be selected in the
port A data direction register (PADDR).
PB7 to
PB0
9 to 2
Input/ Port B: Eight-bit input/output pins. The
output direction of each-bit pin can be selected in the
port B data direction register (PBDDR).
11 to 4
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1. Overview
1.3.3
Pin Assignments in Each Mode
Table 1.3 lists the pin assignments in each mode.
Table 1.3
Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A)
Pin No.
Pin Name
FP-100B
TFP-100B
FP-100A
Mode 1
Mode 2
Mode 3
Mode 4
1
3
VCC
VCC
VCC
VCC
2
4
PB0/TP8/TMO0/
CS7
PB0/TP8/TMO0/
CS7
PB0/TP8/TMO0/
CS7
PB0/TP8/TMO0/
CS7
3
5
PB1/TP9/TMIO1/
DREQ0/CS6
PB1/TP9/TMIO1/
DREQ0/CS6
PB1/TP9/TMIO1/
DREQ0/CS6
PB1/TP9/TMIO1/
DREQ0/CS6
4
6
PB2/TP10/TMO2/
CS5
PB2/TP10/TMO2/
CS5
PB2/TP10/TMO2/
CS5
PB2/TP10/TMO2/
CS5
5
7
PB3/TP11/TMIO3/
DREQ1/CS4
PB3/TP11/TMIO3/
DREQ1/CS4
PB3/TP11/TMIO3/
DREQ1/CS4
PB3/TP11/TMIO3/
DREQ1/CS4
6
8
PB4/TP12/UCAS
PB4/TP12/UCAS
PB4/TP12/UCAS
PB4/TP12/UCAS
7
9
PB5/TP13/LCAS/
SCK2
PB5/TP13/LCAS/
SCK2
PB5/TP13/LCAS/
SCK2
PB5/TP13/LCAS/
SCK2
8
10
PB6/TP14/TxD2
PB6/TP14/TxD2
PB6/TP14/TxD2
PB6/TP14/TxD2
9
11
PB7/TP15/RxD2
PB7/TP15/RxD2
PB7/TP15/RxD2
PB7/TP15/RxD2
10
12
RESO
RESO
RESO
RESO
11
13
VSS
VSS
VSS
VSS
12
14
P90/TxD0
P90/TxD0
P90/TxD0
P90/TxD0
13
15
P91/TxD1
P91/TxD1
P91/TxD1
P91/TxD1
14
16
P92/RxD0
P92/RxD0
P92/RxD0
P92/RxD0
15
17
P93/RxD1
P93/RxD1
P93/RxD1
P93/RxD1
16
18
P94 /IRQ4 /SCK0
P94 /IRQ4 /SCK0
P94 /IRQ4 /SCK0
P94 /IRQ4 /SCK0
17
19
P95/IRQ5 /SCK1
P95/IRQ5 /SCK1
P95/IRQ5 /SCK1
P95/IRQ5 /SCK1
20
P40/D0*
1
P40/D0*
2
P40/D0*
1
P40/D0*
2
P41/D1*
2
P41/D1*
1
P41/D1*
2
18
19
21
P41/D1*
1
20
22
P42/D2*
1
P42/D2*
2
P42/D2*
1
P42/D2*
2
21
23
P43/D3*
1
P43/D3*
2
P43/D3*
1
P43/D3*
2
22
24
VSS
23
25
P44/D4*
VSS
1
Rev.5.00 Sep. 12, 2007 Page 14 of 764
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P44/D4*
VSS
2
P44/D4*
VSS
1
P44/D4*
2
1. Overview
Pin No.
FP-100B
TFP-100B
FP-100A
Pin Name
Mode 1
Mode 2
Mode 3
P45/D5*
2
P45/D5*
1
P45/D5*
2
P46/D6*
2
P46/D6*
1
P46/D6*
2
P47/D7*
2
P47/D7*
1
P47/D7*
2
24
26
P45/D5*
1
25
27
P46/D6*
1
1
Mode 4
26
28
P47/D7*
27
29
D8
D8
D8
D8
28
30
D9
D9
D9
D9
29
31
D10
D10
D10
D10
30
32
D11
D11
D11
D11
31
33
D12
D12
D12
D12
32
34
D13
D13
D13
D13
33
35
D14
D14
D14
D14
34
36
D15
D15
D15
D15
35
37
VCC
VCC
VCC
VCC
36
38
A0
A0
A0
A0
37
39
A1
A1
A1
A1
38
40
A2
A2
A2
A2
39
41
A3
A3
A3
A3
40
42
A4
A4
A4
A4
41
43
A5
A5
A5
A5
42
44
A6
A6
A6
A6
43
45
A7
A7
A7
A7
44
46
VSS
VSS
VSS
VSS
45
47
A8
A8
A8
A8
46
48
A9
A9
A9
A9
47
49
A10
A10
A10
A10
48
50
A11
A11
A11
A11
49
51
A12
A12
A12
A12
50
52
A13
A13
A13
A13
51
53
A14
A14
A14
A14
52
54
A15
A15
A15
A15
53
55
A16
A16
A16
A16
54
56
A17
A17
A17
A17
Rev.5.00 Sep. 12, 2007 Page 15 of 764
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1. Overview
Pin No.
Pin Name
FP-100B
TFP-100B
FP-100A
Mode 1
Mode 2
Mode 3
Mode 4
55
57
A18
A18
A18
A18
56
58
A19
A19
A19
A19
57
59
VSS
VSS
VSS
VSS
58
60
P60/WAIT
P60/WAIT
P60/WAIT
P60/WAIT
59
61
P61/BREQ
P61/BREQ
P61/BREQ
P61/BREQ
60
62
P62/BACK
P62/BACK
P62/BACK
P62/BACK
61
63
P67/φ
P67/φ
P67/φ
P67/φ
62
64
STBY
STBY
STBY
STBY
63
65
RES
RES
RES
RES
64
66
NMI
NMI
NMI
NMI
65
67
VSS
VSS
VSS
VSS
66
68
EXTAL
EXTAL
EXTAL
EXTAL
67
69
XTAL
XTAL
XTAL
XTAL
68
70
VCC
VCC
VCC
VCC
69
71
AS
AS
AS
AS
70
72
RD
RD
RD
RD
71
73
HWR
HWR
HWR
HWR
72
74
LWR
LWR
LWR
LWR
73
75
MD0
MD0
MD0
MD0
74
76
MD1
MD1
MD1
MD1
75
77
MD2
MD2
MD2
MD2
76
78
AVCC
AVCC
AVCC
AVCC
77
79
VREF
VREF
VREF
VREF
78
80
P70/AN0
P70/AN0
P70/AN0
P70/AN0
79
81
P71/AN1
P71/AN1
P71/AN1
P71/AN1
80
82
P72/AN2
P72/AN2
P72/AN2
P72/AN2
81
83
P73/AN3
P73/AN3
P73/AN3
P73/AN3
82
84
P74/AN4
P74/AN4
P74/AN4
P74/AN4
83
85
P75/AN5
P75/AN5
P75/AN5
P75/AN5
84
86
P76/AN6/DA0
P76/AN6/DA0
P76/AN6/DA0
P76/AN6/DA0
85
87
P77/AN7/DA1
P77/AN7/DA1
P77/AN7/DA1
P77/AN7/DA1
Rev.5.00 Sep. 12, 2007 Page 16 of 764
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1. Overview
Pin No.
Pin Name
FP-100B
TFP-100B
FP-100A
Mode 1
Mode 2
Mode 3
Mode 4
86
88
AVSS
AVSS
AVSS
AVSS
87
89
P80/IRQ0/RFSH
P80/IRQ0/RFSH
P80/IRQ0/RFSH
P80/IRQ0/RFSH
88
90
P81/IRQ1/CS3
P81/IRQ1/CS3
P81/IRQ1/CS3
P81/IRQ1/CS3
89
91
P82/IRQ2/CS2
P82/IRQ2/CS2
P82/IRQ2/CS2
P82/IRQ2/CS2
90
92
P83/IRQ3/CS1/
ADTRG
P83/IRQ3/CS1/
ADTRG
P83/IRQ3/CS1/
ADTRG
P83/IRQ3/CS1/
ADTRG
91
93
P84/CS0
P84/CS0
P84/CS0
P84/CS0
92
94
VSS
VSS
VSS
VSS
93
95
PA0/TP0/TCLKA/ PA0/TP0/TCLKA/ PA0/TP0/TCLKA/ PA0/TP0/TCLKA/
TEND0
TEND0
TEND0
TEND0
94
96
PA1/TP1/TCLKB/ PA1/TP1/TCLKB/ PA1/TP1/TCLKB/ PA1/TP1/TCLKB/
TEND1
TEND1
TEND1
TEND1
95
97
PA2/TP2/TIOCA0/ PA2/TP2/TIOCA0/ PA2/TP2/TIOCA0/ PA2/TP2/TIOCA0/
TCLKC
TCLKC
TCLKC
TCLKC
96
98
PA3/TP3/TIOCB0/ PA3/TP3/TIOCB0/ PA3/TP3/TIOCB0/ PA3/TP3/TIOCB0/
TCLKD
TCLKD
TCLKD
TCLKD
97
99
PA4/TP4/TIOCA1
PA4/TP4/TIOCA1
PA4/TP4/TIOCA1/ PA4/TP4/TIOCA1/
A23
A23
98
100
PA5/TP5/TIOCB1
PA5/TP5/TIOCB1
PA5/TP5/TIOCB1/ PA5/TP5/TIOCB1/
A22
A22
99
1
PA6/TP6/TIOCA2
PA6/TP6/TIOCA2
PA6/TP6/TIOCA2/ PA6/TP6/TIOCA2/
A21
A21
100
2
PA7/TP7/TIOCB2
PA7/TP7/TIOCB2
A20
A20
Notes: 1. In modes 1 and 3, the P40 to P47 functions of pins P40/D0 to P47/D7 are selected after a
reset, but they can be changed by software.
2. In modes 2 and 4, the D0 to D7 functions of pins P40/D0 to P47/D7 are selected after a
reset, but they can be changed by software.
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1. Overview
Rev.5.00 Sep. 12, 2007 Page 18 of 764
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2. CPU
Section 2 CPU
2.1
Overview
The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general
registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
2.1.1
Features
The H8/300H CPU has the following features.
• Upward compatibility with H8/300 CPU
Can execute H8/300 Series object programs
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• Sixty-two basic instructions
⎯ 8/16/32-bit data transfer, arithmetic and logic instructions
⎯ Multiply and divide instructions
⎯ Powerful bit-manipulation instructions
• Eight addressing modes
⎯ Register direct [Rn]
⎯ Register indirect [@ERn]
⎯ Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]
⎯ Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
⎯ Absolute address [@aa:8, @aa:16, or @aa:24]
⎯ Immediate [#xx:8, #xx:16, or #xx:32]
⎯ Program-counter relative [@(d:8, PC) or @(d:16, PC)]
⎯ Memory indirect [@@aa:8]
• 16-Mbyte linear address space
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2. CPU
• High-speed operation
⎯ All frequently-used instructions execute in two to four states
⎯ Maximum clock frequency:
20 MHz
⎯ 8/16/32-bit register-register add/subtract: 100 ns
⎯ 8 × 8-bit register-register multiply:
700 ns
⎯ 16 ÷ 8-bit register-register divide:
700 ns
⎯ 16 × 16-bit register-register multiply:
1.1 µs
⎯ 32 ÷ 16-bit register-register divide:
1.1 µs
• Two CPU operating modes
⎯ Normal mode (not available in the H8/3006 and H8/3007)
⎯ Advanced mode
• Low-power mode
Transition to power-down state by SLEEP instruction
2.1.2
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8/300H has the following enhancements.
• More general registers
Eight 16-bit registers have been added.
• Expanded address space
⎯ Advanced mode supports a maximum 16-Mbyte address space.
⎯ Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
⎯ Data transfer, arithmetic, and logic instructions can operate on 32-bit data.
⎯ Signed multiply/divide instructions and other instructions have been added.
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2. CPU
2.2
CPU Operating Modes
The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes.
Normal mode*
Maximum 64 kbytes, program
and data areas combined
Advanced mode
Maximum 16 Mbytes, program
and data areas combined
CPU operating modes
Note: * Normal mode is not available in the H8/3006 and H8/3007.
Figure 2.1 CPU Operating Modes
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2. CPU
2.3
Address Space
Figure 2.2 shows a simple memory map for the H8/3006 and H8/3007. The H8/300H CPU can
address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes
in advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode.
The 1-Mbyte operating modes use 20-bit addressing. The upper 4 bits of effective addresses are
ignored.
H'0000
H'00000
H'000000
H'FFFF
H'FFFFF
H'FFFFFF
a. 1-Mbyte mode
Normal mode*
b. 16-Mbyte mode
Advanced mode
Note: * Normal mode is not available in the H8/3006 and H8/3007.
Figure 2.2 Memory Map
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2. CPU
2.4
Register Configuration
2.4.1
Overview
The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers:
general registers and control registers.
General Registers (ERn)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7
E7
R7H
R7L
(SP)
Control Registers (CR)
23
0
PC
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
Legend:
SP: Stack pointer
PC: Program counter
CCR: Condition code register
Interrupt mask bit
I:
User bit or interrupt mask bit
UI:
Half-carry flag
H:
User bit
U:
Negative flag
N:
Zero flag
Z:
Overflow flag
V:
Carry flag
C:
Figure 2.3 CPU Registers
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2. CPU
2.4.2
General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used without distinction between data registers and address registers. When a
general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
When the general registers are used as 32-bit registers or as address registers, they are designated
by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.
Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers
(extended registers)
E0 to E7
RH registers
R0H to R7H
ER registers
ER0 to ER7
R registers
R0 to R7
RL registers
R0L to R7L
Figure 2.4 Usage of General Registers
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REJ09B0396-0500
2. CPU
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the
stack.
Free area
SP (ER7)
Stack area
Figure 2.5 Stack
2.4.3
Control Registers
The control registers are the 24-bit program counter (PC) and the 8-bit condition code register
(CCR).
Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU
will execute. The length of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so
the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is
regarded as 0.
Condition Code Register (CCR): This 8-bit register contains internal CPU status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted
regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask
bit. For details see section 5, Interrupt Controller.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
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2. CPU
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and
XORC instructions.
Bit 3—Negative Flag (N): Stores the value of the most significant bit of data, regarded as the
sign bit.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry is generated by execution of an operation, and
cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC,
STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional
branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and
UI bits, see section 5, Interrupt Controller.
2.4.4
Initial CPU Register Values
In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit
in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular,
the initial value of the stack pointer (ER7) is also undefined. The stack pointer (ER7) must
therefore be initialized by an MOV.L instruction executed immediately after a reset.
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2. CPU
2.5
Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1,
2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as
two digits of 4-bit BCD data.
2.5.1
General Register Data Formats
Figures 2.6 and 2.7 show the data formats in general registers.
Data Type
General
Register
1-bit data
RnH
Data Format
7
0
7 6 5 4 3 2 1 0
Don't care
7
1-bit data
7
4-bit BCD data
RnH
7 6 5 4 3 2 1 0
Don't care
RnL
4 3
0
Don't care
Upper digit Lower digit
7
4-bit BCD data
Byte data
Byte data
Don't care
RnL
4 3
0
Upper digit Lower digit
7
0
MSB
LSB
Don't care
RnH
RnL
0
7
0
MSB
LSB
Don't care
Legend:
RnH: General register RH
RnL: General register RL
Figure 2.6 General Register Data Formats (1)
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2. CPU
Data Type
General
Register
Word data
Rn
Word data
Data Format
15
0
MSB
LSB
15
0
MSB
LSB
En
31
16 15
0
Longword data ERn
MSB
LSB
Legend::
ERn: General register
En:
General register E
Rn:
General register R
MSB: Most significant bit
LSB: Least significant bit
Figure 2.7 General Register Data Formats (2)
2.5.2
Memory Data Formats
Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and
longword data on memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
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2. CPU
Data Type
Address
Data Format
1-bit data
Address L
7
Byte data
Address L
MSB
Word data
Address 2M
MSB
7
0
6
5
4
Address 2N
2
1
0
LSB
Address 2M + 1
Longword data
3
LSB
MSB
Address 2N + 1
Address 2N + 2
Address 2N + 3
LSB
Figure 2.8 Memory Data Formats
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
size or longword size.
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2. CPU
2.6
Instruction Set
2.6.1
Instruction Set Overview
The H8/300H CPU has 64 types of instructions, which are classified in table 2.1.
Table 2.1
Instruction Classification
Function
Instruction
Types
1
1
2
2
Data transfer
MOV, PUSH* , POP* , MOVTPE* , MOVFPE*
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, 18
MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU
Logic operations
AND, OR, XOR, NOT
4
Shift operations
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
8
Bit manipulation
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, 14
BIXOR, BLD, BILD, BST, BIST
Branch
Bcc* , JMP, BSR, JSR, RTS
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
9
Block data transfer
EEPMOV
1
3
5
Total 64 types
Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn.
PUSH.W Rn is identical to MOV.W Rn, @–SP.
POP.L ERn is identical to MOV.L @SP+, Rn.
PUSH.L ERn is identical to MOV.L Rn, @–SP.
2. Not available in the H8/3006 and H8/3007.
3. Bcc is a generic branching instruction.
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2.6.2
Instructions and Addressing Modes
Table 2.2 indicates the instructions available in the H8/300H CPU.
Table 2.2
Instructions and Addressing Modes
Addressing Modes
Function
Instruction
#xx
Rn
@ERn
@
(d:16,
ERn)
Data
transfer
MOV
BWL
BWL
BWL
BWL
BWL
BWL
B
BWL
BWL
⎯
⎯
⎯
⎯
POP, PUSH
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
WL
MOVFPE,
MOVTPE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ADD, CMP
BWL
BWL
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SUB
WL
BWL
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ADDX, SUBX
B
B
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ADDS, SUBS
⎯
L
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
INC, DEC
⎯
BWL
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DAA, DAS
⎯
B
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
MULXU,
MULXS,
DIVXU, DIVXS
⎯
BW
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
NEG
⎯
BWL
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
EXTU, EXTS
⎯
Arithmetic
operations
@
(d:24,
ERn)
@ERn+/
@–ERn
@
aa:8
@
aa:16
@
aa:24
@
(d:8,
PC)
@
(d:16,
PC)
@@
aa:8
⎯
WL
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
AND, OR, XOR ⎯
BWL
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
BWL
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Shift instructions
⎯
BWL
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Bit manipulation
⎯
B
B
⎯
⎯
⎯
B
⎯
⎯
⎯
⎯
⎯
⎯
Branch
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Logic
operations
NOT
Bcc, BSR
⎯
⎯
JMP, JSR
⎯
⎯
RTS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
TRAPA
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
RTE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SLEEP
⎯
⎯
⎯
⎯
⎯
⎯
⎯
LDC
B
B
W
W
W
W
STC
⎯
B
W
W
W
ANDC, ORC,
XORC
B
⎯
⎯
⎯
NOP
⎯
⎯
⎯
Block data transfer
⎯
⎯
⎯
System
control
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
W
W
⎯
⎯
⎯
W
⎯
W
W
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
BW
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2. CPU
2.6.3
Tables of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation
used in these tables is defined next.
Operation Notation
Rd
General register (destination)*
Rs
General register (source)*
Rn
General register*
ERn
General register (32-bit register or address register)
(EAd)
Destination operand
(EAs)
Source operand
CCR
Condition code register
N
N (negative) flag of CCR
Z
Z (zero) flag of CCR
V
V (overflow) flag of CCR
C
C (carry) flag of CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
−
Subtraction
×
Multiplication
÷
Division
∧
AND logical
∨
OR logical
⊕
Exclusive OR logical
→
Move
¬
NOT (logical complement)
:3/:8/:16/:24
3-, 8-, 16-, or 24-bit length
Note:
*
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).
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Table 2.3
Data Transfer Instructions
Instruction Size*
Function
MOV
(EAs) → Rd, Rs → (EAd)
B/W/L
Moves data between two general registers or between a general register and
memory, or moves immediate data to a general register.
MOVFPE
B
(EAs) → Rd
Cannot be used in this LSI.
MOVTPE
B
Rs → (EAs)
Cannot be used in this LSI.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. Similarly, POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W
Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L ERn, @–SP.
Note:
*
B:
W:
L:
Size refers to the operand size.
Byte
Word
Longword
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Table 2.4
Arithmetic Operation Instructions
Instruction Size*
Function
ADD,SUB
Rd ± Rs → Rd, Rd ± #IMM → Rd
B/W/L
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Immediate byte data cannot
be subtracted from data in a general register. Use the SUBX or ADD
instruction.)
ADDX,
SUBX
B
INC,
DEC
B/W/L
ADDS,
SUBS
L
DAA,
DAS
B
MULXU
B/W
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on data in two general
registers, or on immediate data and data in a general register.
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands can
be incremented or decremented by 1 only.)
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to CCR to produce 4-bit BCD data.
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
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Instruction Size*
Function
DIVXU
Rd ÷ Rs → Rd
B/W
Performs unsigned division on data in two general registers: either 16 bits ÷ 8
bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient
and 16-bit remainder
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷ 8
bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder
CMP
B/W/L
Rd − Rs, Rd – #IMM
Compares data in a general register with data in another general register or
with immediate data, and sets CCR according to the result.
NEG
B/W/L
0 − Rd → Rd
Takes the two's complement (arithmetic complement) of data in a general
register.
EXTS
W/L
Rd (sign extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by extending the sign bit.
EXTU
W/L
Rd (zero extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by padding with zeros.
Note:
*
B:
W:
L:
Size refers to the operand size.
Byte
Word
Longword
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2. CPU
Table 2.5
Logic Operation Instructions
Instruction Size*
Function
AND
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
B/W/L
Performs a logical AND operation on a general register and another general
register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another general
register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and another
general register or immediate data.
NOT
B/W/L
¬ Rd → Rd
Takes the one's complement (logical complement) of general register
contents.
Note:
*
B:
W:
L:
Table 2.6
Size refers to the operand size.
Byte
Word
Longword
Shift Instructions
Instruction Size*
Function
SHAL,
SHAR
B/W/L
Performs an arithmetic shift on general register contents.
SHLL,
SHLR
B/W/L
ROTL,
ROTR
B/W/L
ROTXL,
ROTXR
B/W/L
Note:
Rd (shift) → Rd
Rd (shift) → Rd
Performs a logical shift on general register contents.
Rd (rotate) → Rd
Rotates general register contents.
*
B:
W:
L:
Rd (rotate) → Rd
Rotates general register contents, including the carry bit.
Size refers to the operand size.
Byte
Word
Longword
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2. CPU
Table 2.7
Bit Manipulation Instructions
Instruction Size*
Function
BSET
1 → (<bit-No.> of <EAd>)
B
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
BNOT
B
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
BTST
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit immediate
data or the lower 3 bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag. The bit number is specified by
3-bit immediate data.
BIAND
B
C ∧ [¬ (<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a general register or
memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
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2. CPU
Instruction Size*
Function
BOR
C ∨ (<bit-No.> of <EAd>) → C
B
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BIOR
B
C ∨ [¬ (<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general register or
memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BIXOR
B
C ⊕ [¬ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the carry
flag.
The bit number is specified by 3-bit immediate data.
BILD
B
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
The bit number is specified by 3-bit immediate data.
BIST
B
C → ¬ (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a general
register or memory operand.
The bit number is specified by 3-bit immediate data.
Note:
* Size refers to the operand size.
B: Byte
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2. CPU
Table 2.8
Branching Instructions
Instruction Size
Bcc
⎯
Function
Branches to a specified address if address specified condition is met. The
branching conditions are listed below.
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
Bcc (BHS)
Carry clear (high or same) C = 0
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
JMP
⎯
Branches unconditionally to a specified address
BSR
⎯
Branches to a subroutine at a specified address
JSR
⎯
Branches to a subroutine at a specified address
RTS
⎯
Returns from a subroutine
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2. CPU
Table 2.9
System Control Instructions
Instruction Size*
Function
TRAPA
⎯
Starts trap-instruction exception handling
RTE
⎯
Returns from an exception-handling routine
SLEEP
⎯
Causes a transition to the power-down state
LDC
B/W
(EAs) → CCR
Moves the source operand contents to the condition code register. The
condition code register size is one byte, but in transfer from memory, data is
read by word access.
STC
B/W
CCR → (EAd)
Transfers the CCR contents to a destination location. The condition code
register size is one byte, but in transfer to memory, data is written by word
access.
ANDC
B
CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data.
ORC
B
XORC
B
CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data.
CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate data.
NOP
⎯
PC + 2 → PC
Only increments the program counter.
Note:
* Size refers to the operand size.
B: Byte
W: Word
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2. CPU
Table 2.10 Block Transfer Instruction
Instruction
Size
Function
EEPMOV.B
⎯
if R4L ≠ 0 then
repeat @ER5+ → @ER6+, R4L − 1 → R4L
until
R4L = 0
else next;
EEPMOV.W
⎯
if R4 ≠ 0 then
repeat @ER5+ → @ER6+, R4 − 1 → R4
until
R4 = 0
else next;
Block transfer instruction. This instruction transfers the number of data bytes
specified by R4L or R4, starting from the address indicated by ER5, to the
location starting at the address indicated by ER6. At the end of the transfer,
the next instruction is executed.
2.6.4
Basic Instruction Formats
The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (OP field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first 4 bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the
first 8 bits are 0 (H'00).
Condition Field: Specifies the branching condition of Bcc instructions.
Figure 2.9 shows examples of instruction formats.
Rev.5.00 Sep. 12, 2007 Page 41 of 764
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2. CPU
Operation field only
op
NOP, RTS, etc.
Operation field and register fields
op
rn
rm
ADD.B Rn, Rm, etc.
Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm
EA (disp)
Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:8
Figure 2.9 Instruction Formats
2.6.5
Notes on Use of Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the
byte, then write the byte back. Care is required when these instructions are used to access registers
with write-only bits, or to access ports.
Step
Description
1
Read
Read one data byte at the specified address
2
Modify
Modify one bit in the data byte
3
Write
Write the modified data byte back to the specified address
Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under
the following conditions.
P47, P46:
P45 – P40:
Input pins
Output pins
The intended purpose of this BCLR instruction is to switch P40 from output to input.
Rev.5.00 Sep. 12, 2007 Page 42 of 764
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2. CPU
Before Execution of BCLR Instruction
P47
P46
P45
P44
P43
P42
P41
P40
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
DDR
0
0
1
1
1
1
1
1
Execution of BCLR Instruction
BCLR
; Execute BCLR instruction on DDR
#0, @P4DDR
After Execution of BCLR Instruction
P47
P46
P45
P44
P43
P42
P41
P40
Input/output
Output
Output
Output
Output
Output
Output
Output
Input
DDR
1
1
1
1
1
1
1
0
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR
are set to 1, making P47 and P46 output pins.
The BCLR instruction can be used to clear flags in the on-chip registers to 0. In the case of the
IRQ status register (ISR), for example, a flag must be read as a condition for clearing it, but when
using the BCLR instruction, if it is known that a flag has been set to 1 in an interrupt-handling
routine, for instance, it is not necessary to read the flag ahead of time.
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2. CPU
2.7
Addressing Modes and Effective Address Calculation
2.7.1
Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,
BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit
number in the operand.
Table 2.11 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@−ERn
5
Absolute address
@aa:8/@aa:16/@aa:24
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8, PC)/@(d:16, PC)
8
Memory indirect
@@aa:8
1 Register Direct⎯Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit
register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit
registers.
2 Register Indirect⎯@ERn: The register field of the instruction code specifies an address
register (ERn), the lower 24 bits of which contain the address of the operand.
3 Register Indirect with Displacement⎯@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit
displacement contained in the instruction code is added to the contents of an address register
(ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the
address of a memory operand. A 16-bit displacement is sign-extended when added.
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4 Register Indirect with Post-Increment or Pre-Decrement⎯@ERn+ or @–ERn:
• Register indirect with post-increment⎯@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or
longword access, the register value should be even.
• Register indirect with pre-decrement⎯@−ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result become the address of a memory
operand. The result is also stored in the address register. The value subtracted is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the resulting
register value should be even.
5 Absolute Address⎯@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute
address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long
(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all
assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A
24-bit absolute address can access the entire address space. Table 2.12 indicates the accessible
address ranges.
Table 2.12 Absolute Address Access Ranges
Absolute
Address
1-Mbyte Modes
16-Mbyte Modes
8 bits (@aa:8)
H'FFF00 to H'FFFFF
(1048320 to 1048575)
H'FFFF00 to H'FFFFFF
(16776960 to 16777215)
16 bits (@aa:16)
H'00000 to H'07FFF,
H'F8000 to H'FFFFF
(0 to 32767, 1015808 to 1048575)
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
(0 to 32767, 16744448 to 16777215)
24 bits (@aa:24)
H'00000 to H'FFFFF
(0 to 1048575)
H'000000 to H'FFFFFF
(0 to 16777215)
6 Immediate⎯#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit
(#xx:16), or 32-bit (#xx:32) immediate data as an operand.
The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data
implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate
data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data
specifying a vector address.
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7 Program-Counter Relative⎯@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is signextended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to
+32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should
be an even number.
8 Memory Indirect⎯@@aa:8: This mode can be used by the JMP and JSR instructions. The
instruction code contains an 8-bit absolute address specifying a memory operand. This memory
operand contains a branch address. The memory operand is accessed by longword access. The first
byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2.10. The
upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to
255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector area.
For further details see section 5, Interrupt Controller.
Specified by @aa:8
Reserved
Branch address
Figure 2.10 Memory-Indirect Branch Address Specification
When a word-size or longword-size memory operand is specified, or when a branch address is
specified, if the specified memory address is odd, the least significant bit is regarded as 0. The
accessed data or instruction code therefore begins at the preceding address. See section 2.5.2,
Memory Data Formats.
2.7.2
Effective Address Calculation
Table 2.13 explains how an effective address is calculated in each addressing mode. In the
1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to
generate a 20-bit effective address.
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4
3
2
r
r
r
op
r
Register indirect with pre-decrement
@–ERn
op
Register indirect with post-increment
@ERn+
Register indirect with post-increment
or pre-decrement
op
Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
op
Register indirect (@ERn)
rm rn
Register direct (Rn)
1
op
Addressing Mode and
Instruction Format
No.
31
31
1 for a byte operand,
2 for a word operand,
4 for a longword operand
1, 2, or 4
General register contents
1, 2, or 4
General register contents
disp
General register contents
General register contents
Sign extension
31
31
Effective Address Calculation
0
0
0
0
23
23
23
23
Operand is general
register contents
Effective Address
0
0
0
0
2. CPU
Table 2.13 Effective Address Calculation
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7
6
5
No.
abs
abs
abs
IMM
op
disp
Program-counter relative
@(d:8, PC) or @(d:16, PC)
op
Immediate
#xx:8, #xx:16, or #xx:32
op
@aa:24
op
@aa:16
op
Absolute address
@aa:8
Addressing Mode and
Instruction Format
disp
PC contents
Sign
extension
23
Effective Address Calculation
0
16 15
H'FFFF
8 7
23
Operand is immediate data
23
Sign
extension
23
23
Effective Address
0
0
0
0
2. CPU
Memory indirect @@aa:8
8
abs
Legend:
r, rm, rn:
op:
disp:
IMM:
abs:
abs
Register field
Operation field
Displacement
Immediate data
Absolute address
op
Advanced mode
op
Normal mode
Addressing Mode and
Instruction Format
No.
31
8 7
abs
0
H'0000
8 7
abs
0
0
15
0
Memory contents
H'0000
Memory contents
23
23
Effective Address Calculation
23
23 16 15
H'00
Effective Address
0
0
2. CPU
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2. CPU
2.8
Processing States
2.8.1
Overview
The H8/300H CPU has five processing states: the program execution state, exception-handling
state, power-down state, reset state, and bus-released state. The power-down state includes sleep
mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing
states. Figure 2.13 indicates the state transitions.
Processing states
Program execution state
The CPU executes program instructions in sequence
Exception-handling state
A transient state in which the CPU executes a hardware sequence
(saving PC and CCR, fetching a vector, etc.) in response to a reset,
interrupt, or other exception
Bus-released state
The external bus has been released in response to a bus request
signal from a bus master other than the CPU
Reset state
The CPU and all on-chip supporting modules are initialized and halted
Power-down state
Sleep mode
The CPU is halted to conserve power
Software standby mode
Hardware standby mode
Figure 2.11 Processing States
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2.8.2
Program Execution State
In this state the CPU executes program instructions in normal sequence.
2.8.3
Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception handling
the CPU references the stack pointer (ER7) and saves the program counter and condition code
register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2.14 Exception Handling Types and Priority
Priority
Type of Exception Detection Timing
Start of Exception Handling
High
Reset
Synchronized with clock
Exception handling starts immediately
when RES changes from low to high
Interrupt
End of instruction
execution or end of
exception handling*
When an interrupt is requested,
exception handling starts at the end of
the current instruction or current
exception-handling sequence
Trap instruction
When TRAPA instruction Exception handling starts when a trap
is executed
(TRAPA) instruction is executed
Low
Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
or immediately after reset exception handling.
Figure 2.12 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.
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Reset
External interrupts
Exception
sources
Interrupt
Internal interrupts (from on-chip supporting modules)
Trap instruction
Figure 2.12 Classification of Exception Sources
Bus request
End of bus release
Program execution state
End of bus
release
Bus
request
Exception
handling source
Bus-released state
End of
exception
handling
Interrupt source
Exception-handling state
NMI, IRQ 0 , IRQ 1,
or IRQ 2 interrupt
SLEEP
instruction
with SSBY = 0
Sleep mode
SLEEP instruction
with SSBY = 1
Software standby mode
RES = High
Reset state
*1
STBY = High, RES = Low
Hardware standby mode
*2
Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs
whenever RES goes low.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2.13 State Transitions
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2.8.4
Exception-Handling Sequences
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit
is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then
the CPU fetches a start address from the exception vector table and execution branches to that
address.
Figure 2.14 shows the stack after the exception-handling sequence.
SP−4
SP (ER7)
SP−3
SP+1
SP−2
SP+2
SP−1
SP+3
SP (ER7)
Stack area
Before exception
handling starts
CCR
PC
SP+4
Even
address
Pushed on stack
After exception
handling ends
Legend:
CCR: Condition code register
SP:
Stack pointer
Notes: 1. PC is the address of the first instruction executed after the return from the
exception-handling routine.
2. Registers must be saved and restored by word access or longword access,
starting at an even address.
Figure 2.14 Stack Structure after Exception Handling
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2.8.5
Bus-Released State
In this state the bus is released to a bus master other than the CPU, in response to a bus request.
The bus masters other than the CPU are the DMA controller, the DRAM interface, and an external
bus master. While the bus is released, the CPU halts except for internal operations. Interrupt
requests are not accepted. For details see section 6.10, Bus Arbiter.
2.8.6
Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The I
bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.
Reset exception handling starts when the RES signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details see section 12,
Watchdog Timer.
2.8.7
Power-Down State
In the power-down state the CPU stops operating to conserve power. There are three modes: sleep
mode, software standby mode, and hardware standby mode.
Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the
SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop
immediately after execution of the SLEEP instruction, but the contents of CPU registers are
retained.
Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all
on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long
as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.
The I/O ports also remain in their existing states.
Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input
goes low. As in software standby mode, the CPU and all clocks halt and the on-chip supporting
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.
For further information see section 19, Power-Down State.
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2. CPU
2.9
Basic Operational Timing
2.9.1
Overview
The H8/300H CPU operates according to the system clock (φ). The interval from one rise of the
system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of
two or three states. The CPU uses different methods to access on-chip memory, the on-chip
supporting modules, and the external address space. Access to the external address space can be
controlled by the bus controller.
2.9.2
On-Chip Memory Access Timing
On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and
word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin
states.
Bus cycle
T1 state
T2 state
φ
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.15 On-Chip Memory Access Cycle
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2. CPU
T1
T2
φ
Address bus
AS , RD, HWR , LWR
Address
High
High impedance
D15 to D0
Figure 2.16 Pin States during On-Chip Memory Access
2.9.3
On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the internal I/O register being accessed. Figure 2.17 shows the on-chip supporting
module access timing. Figure 2.18 indicates the pin states.
Bus cycle
T1 state
T2 state
T3 state
φ
Address bus
Read
access
Address
Internal read signal
Internal data bus
Read data
Internal write signal
Write
access
Internal data bus
Write data
Figure 2.17 Access Cycle for On-Chip Supporting Modules
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2. CPU
T1
T2
T3
φ
Address bus
AS , RD, HWR , LWR
Address
High
High impedance
D15 to D0
Figure 2.18 Pin States during Access to On-Chip Supporting Modules
2.9.4
Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in
two or three states. For details see section 6, Bus Controller.
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3. MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Overview
3.1.1
Operating Mode Selection
The H8/3006 and H8/3007 have four operating modes (modes 1 to 4) that are selected by the
mode pins (MD2 to MD0) as indicated in table 3.1. The input at these pins determines the size of
the address space and the initial bus mode.
Table 3.1
Operating Mode Selection
Description
Operating
Mode
Mode Pins
Initial Bus
1
Mode*
On-Chip
RAM
MD2
MD1
MD0
Address Space
⎯
0
0
0
Setting prohibited
Setting prohibited
Setting prohibited
Mode 1
0
0
1
1 Mbyte
8 bits
Enabled*
2
Mode 2
0
1
0
1 Mbyte
16 bits
Enabled*
2
Mode 3
0
1
1
16 Mbytes
8 bits
Enabled*
2
Mode 4
1
0
0
16 Mbytes
16 bits
Enabled*
2
⎯
1
0
1
⎯
⎯
⎯
⎯
1
1
0
⎯
⎯
⎯
⎯
1
1
1
⎯
⎯
⎯
Notes: 1. In modes 1 to 4, an 8-bit or 16-bit data bus can be selected on a per-area basis by
settings made in the area bus width control register (ABWCR). For details see
section 6, Bus Controller.
2. If the RAME bit in SYSCR is cleared to 0, these addresses become external addresses.
For the address space size there are two choices: 1 Mbyte, or 16 Mbyte.The external data bus is
either 8 or 16 bits wide depending on ABWCR settings. If 8-bit access is selected for all areas, 8bit bus mode is used. For details see section 6, Bus Controller.
Modes 1 and 2 support a maximum address space of 1 Mbyte. Modes 3 and 4 support a maximum
address space of 16 Mbytes.
The H8/3006 and H8/3007 can be used only in modes 1 to 4. The inputs at the mode pins must
select one of these four modes. The inputs at the mode pins must not be changed during operation.
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3. MCU Operating Modes
When changing the mode, the chip must be placed in the reset state before the mode pin inputs are
changed.
3.1.2
Register Configuration
The H8/3006 and H8/3007 have a mode control register (MDCR) that indicates the inputs at the
mode pins (MD2 to MD0), and a system control register (SYSCR). Table 3.2 summarizes these
registers.
Table 3.2
Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'EE011
Mode control register
MDCR
R
Undetermined
System control register
SYSCR
R/W
H'09
H'EE012
Note:
3.2
Lower 20 bits of the address in advanced mode.
*
Mode Control Register (MDCR)
MDCR is an 8-bit read-only register that indicates the current operating mode of the
H8/3006 and H8/3007.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
MDS2
MDS1
MDS0
Initial value
1
1
0
0
0
⎯*
⎯*
⎯*
Read/Write
⎯
⎯
⎯
⎯
⎯
R
R
R
Reserved bits
Mode select 2 to 0
Bits indicating the current
operating mode
Note: * Determined by pins MD 2 to MD 0 .
Bits 7 and 6⎯Reserved: These bits can not be modified and are always read as 1.
Bits 5 to 3⎯Reserved: These bits can not be modified and are always read as 0.
Bits 2 to 0⎯Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins
MD2 to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to
MDS0 are read-only bits. The mode pin (MD2 to MD0) levels are latched into these bits when
MDCR is read.
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3. MCU Operating Modes
3.3
System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3006 and H8/3007.
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
SSOE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAM enable
Enables or
disables
on-chip RAM
Software standby output
port enable
Selects the output state of
the address bus and bus
control signals in software
standby mode
NMI edge select
Selects the valid edge
of the NMI input
User bit enable
Selects whether to use the UI bit in CCR
as a user bit or an interrupt mask bit
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
Software standby
Enables transition to software standby mode
Bit 7⎯Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 19, Power-Down State.)
When software standby mode is exited by an external interrupt and a transition is made to normal
operation, this bit remains set to 1. To clear this bit, write 0.
Bit 7
SSBY
Description
0
SLEEP instruction causes transition to sleep mode
1
SLEEP instruction causes transition to software standby mode
(Initial value)
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3. MCU Operating Modes
Bits 6 to 4⎯Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the length of time
the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when
software standby mode is exited by an external interrupt.
When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the
system clock rate.
For further information about waiting time selection, see section 19.4.3, Selection of Waiting
Time for Exit from Software Standby Mode.
Bit 6
STS2
Bit 5
STS1
Bit 4
STS0
Description
0
0
0
Waiting time = 8,192 states
1
Waiting time = 16,384 states
0
Waiting time = 32,768 states
1
Waiting time = 65,536 states
0
Waiting time = 131,072 states
1
Waiting time = 262,144 states
0
Waiting time = 1,024 states
1
Illegal setting
1
1
0
1
(Initial value)
Bit 3⎯User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an interrupt mask bit.
Bit 3
UE
Description
0
UI bit in CCR is used as an interrupt mask bit
1
UI bit in CCR is used as a user bit
(Initial value)
Bit 2⎯NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 2
NMIEG
Description
0
An interrupt is requested at the falling edge of NMI
1
An interrupt is requested at the rising edge of NMI
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(Initial value)
3. MCU Operating Modes
Bit 1⎯Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (CS0 to CS7, AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as
outputs or fixed high, or placed in the high-impedance state in software standby mode.
Bit 1
SSOE
Description
0
In software standby mode, the address bus and bus control signals are all highimpedance
(Initial value)
1
In software standby mode, the address bus retains its output state and bus control
signals are fixed high
Bit 0⎯RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
3.4
Operating Mode Descriptions
3.4.1
Mode 1
(Initial value)
A maximum 1-Mbyte address space can be accessed. The initial bus mode after a reset is 8 bits,
with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the
bus mode switches to 16 bits.
3.4.2
Mode 2
A maximum 1-Mbyte address space can be accessed. The initial bus mode after a reset is 16 bits,
with 16-bit access to all areas. If all areas are designated for 8-bit access in ABWCR, the bus
mode switches to 8 bits.
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3. MCU Operating Modes
3.4.3
Mode 3
Part of port A function as address pins A23 to A20, permitting access to a maximum 16-Mbyte
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least
one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits. A23 to A21
are valid when 0 is written in bits 7 to 5 of the bus release control register (BRCR). (In this mode
A20 is always used for address output.)
3.4.4
Mode 4
Part of port A function as address pins A23 to A20, permitting access to a maximum 16-Mbyte
address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all
areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits. A23 to A21 are
valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A20 is always used for address
output.)
3.5
Pin Functions in Each Operating Mode
The pin functions of port 4 and port A vary depending on the operating mode. Table 3.3 indicates
their functions in each operating mode.
Table 3.3
Port
Pin Functions in Each Mode
Mode 1
Port 4
P47 to P40*
Port A
PA7 to PA4
Mode 2
1
D7 to D0*
Mode 3
1
PA7 to PA4
P47 to P40*
Mode 4
1
PA6 to PA4, A20*
D7 to D0*
2
1
PA6 to PA4, A20*
2
Notes: 1. Initial state. The bus mode can be switched by settings in ABWCR. These pins function
as P47 to P40 in 8-bit bus mode, and as D7 to D0 in 16-bit bus mode.
2. Initial state. A20 is always an address output pin. PA6 to PA4 are switched over to A23 to
A21 output by writing 0 in bits 7 to 5 of BRCR.
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3. MCU Operating Modes
3.6
Memory Map in Each Operating Mode
Figures 3.1 and 3.2 show a memory maps of the H8/3006 and H8/3007. The address space is
divided into eight areas.
The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.
The address locations of the on-chip RAM and internal I/O registers differ between the 1-Mbyte
modes (modes 1, 2), and the 16-Mbyte modes (modes 3, 4). The address range specifiable by the
CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs.
3.6.1
Note on Reserved Areas
The memory map of the H8/3006 and H8/3007 includes reserved areas to which read/write access
is prohibited. Note that normal operation is not guaranteed if the following reserved areas are
accessed.
The internal I/O register space of the H8/3006 and H8/3007 includes a reserved area to which
access is prohibited. For details, see Appendix B, Internal I/O Registers.
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3. MCU Operating Modes
Modes 1 and 2
(1 Mbyte)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000 External address
space
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'F8000
H'FEF1F
H'FEF20
H'FFFE9
H'FFFEA
H'FFFFF
Area 1
Area 1
Area 2
H'3FFFFF
H'400000
Area 3
Area 2
Area 4
H'5FFFFF
H'600000
Area 5
Area 6
H'7FFFFF
H'800000
Area 7
Internal I/O
registers (2)
External
address
space
External
address
space
Area 3
Area 4
H'9FFFFF
H'A00000
External address
space
On-chip RAM*
16-bit absolute
addresses
Area 0
H'1FFFFF
H'200000
Internal I/O
registers (1)
H'FFF00
H'FFF1F
H'FFF20
H'007FFF
Area 5
16-bit absolute addresses
H'EE0FF
H'0000FF
Area 0
8-bit absolute addresses
H'EE000
Vector area
H'BFFFFF
H'C00000
Area 6
H'DFFFFF
H'E00000
H'FEE000
Area 7
Internal I/O
registers (1)
H'FEE0FF
H'FF8000
External address
space
On-chip RAM*
H'FFFF00
H'FFFF1F
H'FFFF20
H'FFFFE9
H'FFFFEA
H'FFFFFF
Internal I/O
registers (2)
External
address
space
8-bit absolute addresses
H'FFEF1F
H'FFEF20
16-bit absolute addresses
H'07FFF
Memory-indirect
branch addresses
H'000FF
H'000000
16-bit absolute
addresses
Vector area
Memory-indirect
branch addresses
H'00000
Modes 3 and 4
(16 Mbytes)
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.1 H8/3007 Memory Map in Each Operating Mode
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3. MCU Operating Modes
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000 External address
space
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'F8000
H'FF71F
H'FF720
H'FFF00
H'FFF1F
H'FFF20
H'FFFE9
H'FFFEA
H'FFFFF
Area 1
Area 1
Area 2
H'3FFFFF
H'400000
Area 3
Area 2
Area 4
H'5FFFFF
H'600000
Area 5
Area 6
H'7FFFFF
H'800000
Area 7
Internal I/O
registers (1)
Internal I/O
registers (2)
External
address
space
External
address
space
Area 3
Area 4
H'9FFFFF
H'A00000
External address
space
On-chip RAM*
16-bit absolute
addresses
Area 0
H'1FFFFF
H'200000
Area 5
16-bit absolute addresses
H'EE0FF
H'007FFF
Area 0
8-bit absolute addresses
H'EE000
H'0000FF
H'BFFFFF
H'C00000
Area 6
H'DFFFFF
H'E00000
H'FEE000
Area 7
Internal I/O
registers (1)
H'FEE0FF
External address
space
H'FF8000
H'FFF71F
H'FFF720
H'FFFF00
H'FFFF1F
H'FFFF20
H'FFFFE9
H'FFFFEA
On-chip RAM*
Internal I/O
registers (2)
External
address
space
16-bit absolute addresses
H'07FFF
Vector area
8-bit absolute addresses
H'000FF
H'000000
16-bit absolute
addresses
Vector area
Memory-indirect
branch addresses
H'00000
Memory-indirect
branch addresses
Modes 3 and 4
(16 Mbytes)
Modes 1 and 2
(1 Mbyte)
H'FFFFFF
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.2 H8/3006 Memory Map in Each Operating Mode
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3. MCU Operating Modes
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4. Exception Handling
Section 4 Exception Handling
4.1
Overview
4.1.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are
accepted at all times in the program execution state.
Table 4.1
Exception Types and Priority
Priority
Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the RES pin
Interrupt
Interrupt requests are handled when execution of the current
instruction or handling of the current exception is completed
Trap instruction
(TRAPA)
Started by execution of a trap instruction (TRAPA)
Low
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows.
1. The program counter (PC) and condition code register (CCR) are pushed onto the stack.
2. The CCR interrupt mask bit is set to 1.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
Note: For a reset exception, steps 2 and 3 above are carried out.
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4. Exception Handling
4.1.3
Exception Vector Table
The exception sources are classified as shown in figure 4.1. Different vectors are assigned to
different exception sources. Table 4.2 lists the exception sources and their vector addresses.
• Reset
External interrupts: NMI, IRQ 0 to IRQ5
Exception
sources
• Interrupts
• Trap instruction
Internal interrupts: 36 interrupts from on-chip
supporting modules
Figure 4.1 Exception Sources
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4. Exception Handling
Table 4.2
Exception Vector Table
Vector Address*
1
3
Exception Source
Vector Number
Advanced Mode
Normal Mode*
Reset
0
H'0000 to H'0003
H'0000 to H'0001
Reserved for system use
1
H'0004 to H'0007
H'0002 to H'0003
2
H'0008 to H'000B
H'0004 to H'0005
3
H'000C to H'000F
H'0006 to H'0007
4
H'0010 to H'0013
H'0008 to H'0009
5
H'0014 to H'0017
H'000A to H'000B
6
H'0018 to H'001B
H'000C to H'000D
External interrupt (NMI)
7
H'001C to H'001F
H'000E to H'000F
Trap instruction (4 sources)
8
H'0020 to H'0023
H'0010 to H'0011
9
H'0024 to H'0027
H'0012 to H'0013
10
H'0028 to H'002B
H'0014 to H'0015
11
H'002C to H'002F
H'0016 to H'0017
External interrupt IRQ0
12
H'0030 to H'0033
H'0018 to H'0019
External interrupt IRQ1
13
H'0034 to H'0037
H'001A to H'001B
External interrupt IRQ2
14
H'0038 to H'003B
H'001C to H'001D
External interrupt IRQ3
15
H'003C to H'003F
H'001E to H'001F
External interrupt IRQ4
16
H'0040 to H'0043
H'0020 to H'0021
External interrupt IRQ5
17
H'0044 to H'0047
H'0022 to H'0023
Reserved for system use
18
H'0048 to H'004B
H'0024 to H'0025
19
H'004C to H'004F
H'0026 to H'0027
20
to
63
H'0050 to H'0053
to
H'00FC to H'00FF
H'0028 to H'0029
to
H'007E to H'007F
Internal interrupts*
2
Notes: 1. Lower 16 bits of the address.
2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table.
3. Normal mode is not available in the H8/3006 and H8/3007.
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4. Exception Handling
4.2
Reset
4.2.1
Overview
A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the
chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the
on-chip supporting modules. Reset exception handling begins when the RES pin changes from
low to high.
The chip can also be reset by overflow of the watchdog timer. For details see section 12,
Watchdog Timer.
4.2.2
Reset Sequence
The chip enters the reset state when the RES pin goes low.
To ensure that the chip is properly reset, hold the RES pin low for at last 20 ms at power-up. To
reset the chip during operation, hold the RES pin low for at least 10 system clock (φ) cycles. See
appendix D.2, Pin States at Reset, for the states of the pins in the reset state.
When the RES pin goes high after being held low for the necessary time, the chip starts reset
exception handling as follows.
• The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
• The contents of the reset vector address (H'0000 to H'0003) are read, and program execution
starts from the address indicated in the vector address.
Figure 4.2 shows the reset sequence in modes 1 and 3. Figure 4.3 shows the reset sequence in
modes 2 and 4.
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(2)
(4)
(3)
(6)
(5)
(8)
(7)
Internal
processing
Address of reset vector: (1) = H'000000, (3) = H'000001, (5) = H'000002, (7) = H'000003
Start address (contents of reset exception handling vector address)
Start address
First instruction of program
High
(1)
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
(1), (3), (5), (7)
(2), (4), (6), (8)
(9)
(10)
D15 to D8
HWR , LWR
RD
Address
bus
RES
φ
Vector fetch
(10)
(9)
Prefetch of
first program
instruction
4. Exception Handling
Figure 4.2 Reset Sequence (Modes 1 and 3)
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4. Exception Handling
Internal
processing
Vector fetch
Prefetch of first
program instruction
φ
RES
Address bus
(1)
(3)
(5)
RD
HWR , LWR
High
(2)
D15 to D0
(1), (3)
(2), (4)
(5)
(6)
(4)
(6)
Address of reset vector: (1) = H'000000, (3) = H'000002
Start address (contents of reset exception handling vector address)
Start address
First instruction of program
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Figure 4.3 Reset Sequence (Modes 2 and 4)
4.2.3
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR
will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. The first instruction of the program is
always executed immediately after the reset state ends. This instruction should initialize the stack
pointer (example: MOV.L #xx:32, SP).
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4. Exception Handling
4.3
Interrupts
Interrupt exception handling can be requested by seven external sources (NMI, IRQ0 to IRQ5), and
36 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources
and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT),
DRAM interface, 16-bit timer, 8-bit timer, DMA controller (DMAC), serial communication
interface (SCI), and A/D converter. Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
External interrupts
NMI (1)
IRQ 0 to IRQ 5 (6)
Internal interrupts
WDT*1 (1)
DRAM interface*2 (1)
16-bit timer (9)
8-bit timer (8)
DMAC (4)
SCI (12)
A/D converter (1)
Interrupts
Notes: Numbers in parentheses are the number of interrupt sources.
1. When the watchdog timer is used as an interval timer, it generates an interrupt
request at every counter overflow.
2. When the DRAM interface is used as an interval timer, it generates an interrupt request
at compare match.
Figure 4.4 Interrupt Sources and Number of Interrupts
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4. Exception Handling
4.4
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a
start address from a vector table entry corresponding to a vector number from 0 to 3, which is
specified in the instruction code.
4.5
Stack Status after Exception Handling
Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP−4
SP−3
SP−2
SP−1
SP (ER7) →
Stack area
SP (ER7) →
SP+1
SP+2
SP+3
SP+4
Before exception handling
CCR
PCE
PCH
PCL
Even address
After exception handling
Pushed on stack
Legend:
PCE: Bits 23 to 16 of program counter (PC)
PCH: Bits 15 to 8 of program counter (PC)
PCL: Bits 7 to 0 of program counter (PC)
CCR: Condition code register
SP: Stack pointer
Notes: 1. PC indicates the address of the first instruction that will be executed after return.
2. Registers must be saved in word or longword size at even addresses.
Figure 4.5 Stack after Completion of Exception Handling
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4. Exception Handling
4.6
Notes on Stack Usage
When accessing word data or longword data, the H8/3006 and H8/3007 regard the lowest address
bit as 0. The stack should always be accessed by word access or longword access, and the value of
the stack pointer (SP: ER7) should always be kept even.
Use the following instructions to save registers:
PUSH.W Rn
PUSH.L ERn
(MOV.W Rn, @–SP)
(MOV.L ERn, @–SP)
Use the following instructions to restore registers:
POP.W Rn
POP.L ERn
(MOV.W @SP+, Rn)
(MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what
happens when the SP value is odd.
SP
CCR
R1L
SP
H'FFFEFA
H'FFFEFB
PC
PC
H'FFFEFC
H'FFFEFD
H'FFFEFF
SP
TRAPA instruction executed
SP set to H'FFFEFF
MOV. B R1L, @-ER7
Data saved above SP
CCR contents lost
Legend:
CCR: Condition code register
PC: Program counter
R1L: General register R1L
SP: Stack pointer
Note: The diagram illustrates modes 3 and 4.
Figure 4.6 Operation when SP Value Is Odd
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4. Exception Handling
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5. Interrupt Controller
Section 5 Interrupt Controller
5.1
Overview
5.1.1
Features
The interrupt controller has the following features:
• Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three-level enable/disable state setting possible by means of the I and UI bits in the CPU's
condition code register (CCR) and the UE bit in the system control register (SYSCR)
• Seven external interrupt pins
NMI has the highest priority and is always accepted; either the rising or falling edge can be
selected. For each of IRQ0 to IRQ5, sensing of the falling edge or level sensing can be selected
independently.
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5. Interrupt Controller
5.1.2
Block Diagram
Figure 5.1 shows a block diagram of the interrupt controller.
CPU
ISCR
IER
IPRA, IPRB
NMI
input
IRQ input
section ISR
IRQ input
OVF
TME
.
.
.
.
.
.
.
TEI
TEIE
Priority
decision logic
Interrupt
request
Vector
number
.
.
.
I
UI
Interrupt controller
UE
SYSCR
Legend:
ISCR:
IER:
ISR:
IPRA:
IPRB:
SYSCR:
IRQ sense control register
IRQ enable register
IRQ status register
Interrupt priority register A
Interrupt priority register B
System control register
Figure 5.1 Interrupt Controller Block Diagram
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CCR
5. Interrupt Controller
5.1.3
Pin Configuration
Table 5.1 lists the interrupt pins.
Table 5.1
Interrupt Pins
Name
Abbreviation I/O
Nonmaskable interrupt
NMI
Input Nonmaskable interrupt, rising edge or
falling edge selectable
External interrupt request 5 to 0
IRQ5 to IRQ0
Input Maskable interrupts, falling edge or level
sensing selectable
5.1.4
Function
Register Configuration
Table 5.2 lists the registers of the interrupt controller.
Table 5.2
Interrupt Controller Registers
1
Address*
Name
Abbreviation
R/W
Initial Value
H'EE012
System control register
SYSCR
R/W
H'09
H'EE014
IRQ sense control register
ISCR
R/W
H'00
H'EE015
IRQ enable register
IER
R/W
H'00
2
H'EE016
IRQ status register
ISR
R/(W)*
H'00
H'EE018
Interrupt priority register A
IPRA
R/W
H'00
H'EE019
Interrupt priority register B
IPRB
R/W
H'00
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Only 0 can be written, to clear flags.
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5. Interrupt Controller
5.2
Register Descriptions
5.2.1
System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the
action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM.
Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register
(SYSCR).
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
SSOE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAM enable
Software standby
output port enable
Standby timer
select 2 to 0
Software standby
NMI edge select
Selects the NMI input edge
User bit enable
Selects whether to use the UI bit in
CCR as a user bit or interrupt mask bit
Bit 3⎯User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an
interrupt mask bit.
Bit 3
UE
Description
0
UI bit in CCR is used as interrupt mask bit
1
UI bit in CCR is used as user bit
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(Initial value)
5. Interrupt Controller
Bit 2⎯NMI Edge Select (NMIEG): Selects the NMI input edge.
Bit 2
NMIEG
Description
0
Interrupt is requested at falling edge of NMI input
1
Interrupt is requested at rising edge of NMI input
5.2.2
(Initial value)
Interrupt Priority Registers A and B (IPRA, IPRB)
IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.
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5. Interrupt Controller
Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which
interrupt priority levels can be set.
Bit
7
6
5
4
3
2
1
0
IPRA7
IPRA6
IPRA5
IPRA4
IPRA3
IPRA2
IPRA1
IPRA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Priority
level A0
Selects the
priority level
of 16-bit timer
channel 2
interrupt
requests
Priority level A1
Selects the priority level
of 16-bit timer channel 1
interrupt requests
Priority level A2
Selects the priority level of
16-bit timer channel 0 interrupt
requests
Priority level A3
Selects the priority level of WDT,
DRAM interface, and A/D converter
interrupt requests
Priority level A4
Selects the priority level of IRQ 4 and IRQ 5
interrupt requests
Priority level A5
Selects the priority level of IRQ 2 and IRQ 3 interrupt requests
Priority level A6
Selects the priority level of IRQ 1 interrupt requests
Priority level A7
Selects the priority level of IRQ 0 interrupt requests
IPRA is initialized to H'00 by a reset and in hardware standby mode.
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5. Interrupt Controller
Bit 7⎯Priority Level A7 (IPRA7): Selects the priority level of IRQ0 interrupt requests.
Bit 7
IPRA7
Description
0
IRQ0 interrupt requests have priority level 0 (low priority)
1
IRQ0 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 6⎯Priority Level A6 (IPRA6): Selects the priority level of IRQ1 interrupt requests.
Bit 6
IPRA6
Description
0
IRQ1 interrupt requests have priority level 0 (low priority)
1
IRQ1 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 5⎯Priority Level A5 (IPRA5): Selects the priority level of IRQ2 and IRQ3 interrupt requests.
Bit 5
IPRA5
Description
0
IRQ2 and IRQ3 interrupt requests have priority level 0 (low priority)
1
IRQ2 and IRQ3 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 4⎯Priority Level A4 (IPRA4): Selects the priority level of IRQ4 and IRQ5 interrupt requests.
Bit 4
IPRA4
Description
0
IRQ4 and IRQ5 interrupt requests have priority level 0 (low priority)
1
IRQ4 and IRQ5 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 3⎯Priority Level A3 (IPRA3): Selects the priority level of WDT, DRAM interface, and A/D
converter interrupt requests.
Bit 3
IPRA3
Description
0
WDT, DRAM interface, and A/D converter interrupt requests have priority level 0
(low priority)
(Initial value)
1
WDT, DRAM interface, and A/D converter interrupt requests have priority level 1
(high priority)
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5. Interrupt Controller
Bit 2⎯Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt
requests.
Bit 2
IPRA2
Description
0
16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (Initial value)
1
16-bit timer channel 0 interrupt requests have priority level 1 (high priority)
Bit 1⎯Priority Level A1 (IPRA1): Selects the priority level of 16-bit timer channel 1 interrupt
requests.
Bit 1
IPRA1
Description
0
16-bit timer channel 1 interrupt requests have priority level 0 (low priority) (Initial value)
1
16-bit timer channel 1 interrupt requests have priority level 1 (high priority)
Bit 0⎯Priority Level A0 (IPRA0): Selects the priority level of 16-bit timer channel 2 interrupt
requests.
Bit 0
IPRA0
Description
0
16-bit timer channel 2 interrupt requests have priority level 0 (low priority) (Initial value)
1
16-bit timer channel 2 interrupt requests have priority level 1 (high priority)
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5. Interrupt Controller
Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which
interrupt priority levels can be set.
Bit
7
6
5
4
3
2
1
0
IPRB7
IPRB6
IPRB5
⎯
IPRB3
IPRB2
IPRB1
⎯
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bit
Priority level B1
Selects the priority level
of SCI channel 2 interrupt
requests
Priority level B2
Selects the priority level of
SCI channel 1 interrupt requests
Priority level B3
Selects the priority level of SCI
channel 0 interrupt requests
Reserved bit
Priority level B5
Selects the priority level of DMAC
interrupt requests (channels 0 and 1)
Priority level B6
Selects the priority level of 8-bit timer channel 2, 3 interrupt requests
Priority level B7
Selects the priority level of 8-bit timer channel 0, 1 interrupt requests
IPRB is initialized to H'00 by a reset and in hardware standby mode.
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5. Interrupt Controller
Bit 7⎯Priority Level B7 (IPRB7): Selects the priority level of 8-bit timer channel 0, 1 interrupt
requests.
Bit 7
IPRB7
Description
0
8-bit timer channel 0, 1 interrupt requests have priority level 0 (low priority)(Initial value)
1
8-bit timer channel 0, 1 interrupt requests have priority level 1 (high priority)
Bit 6⎯Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt
requests.
Bit 6
IPRB6
Description
0
8-bit timer channel 2, 3 interrupt requests have priority level 0 (low priority)(Initial value)
1
8-bit timer channel 2, 3 interrupt requests have priority level 1 (high priority)
Bit 5⎯Priority Level B5 (IPRB5): Selects the priority level of DMAC interrupt requests
(channels 0 and 1).
Bit 5
IPRB5
Description
0
DMAC interrupt requests (channels 0 and 1) have priority level 0
(low priority)
(Initial value)
1
DMAC interrupt requests (channels 0 and 1) have priority level 1 (high priority)
Bit 4⎯Reserved: This bit can be written and read, but it does not affect interrupt priority.
Bit 3⎯Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests.
Bit 3
IPRB3
Description
0
SCI channel 0 interrupt requests have priority level 0 (low priority)
1
SCI channel 0 interrupt requests have priority level 1 (high priority)
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(Initial value)
5. Interrupt Controller
Bit 2⎯Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests.
Bit 2
IPRB2
Description
0
SCI channel 1 interrupt requests have priority level 0 (low priority)
1
SCI channel 1 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 1⎯Priority Level B1 (IPRB1): Selects the priority level of SCI channel 2 interrupt requests.
Bit 1
IPRB1
Description
0
SCI channel 2 interrupt requests have priority level 0 (low priority)
1
SCI channel 2 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 0⎯Reserved: This bit can be written and read, but it does not affect interrupt priority.
5.2.3
IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ5 interrupt
requests.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
Initial value
0
0
0
0
0
0
0
0
Read/Write
⎯
⎯
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Reserved bits
IRQ 5 to IRQ0 flags
These bits indicate IRQ 5 to IRQ 0
interrupt request status
Note: * Only 0 can be written, to clear flags.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6⎯Reserved: These bits can not be modified and are always read as 0.
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5. Interrupt Controller
Bits 5 to 0⎯IRQ5 to IRQ0 Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ5 to
IRQ0 interrupt requests.
Bits 5 to 0
IRQ5F to IRQ0F Description
0
[Clearing conditions]
1
(Initial value)
•
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
•
IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried
out.
•
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
[Setting conditions]
•
IRQnSC = 0 and IRQn input is low.
•
IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 5 to 0
5.2.4
IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that enables or disables IRQ0 to IRQ5 interrupt requests.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
IRQ 5 to IRQ0 enable
These bits enable or disable IRQ 5 to IRQ 0 interrupts
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6⎯Reserved: These bits can be written and read, but they do not enable or disable
interrupts.
Bits 5 to 0⎯IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits enable or disable
IRQ5 to IRQ0 interrupts.
Bits 5 to 0
IRQ5E to IRQ0E Description
0
IRQ5 to IRQ0 interrupts are disabled
1
IRQ5 to IRQ0 interrupts are enabled
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(Initial value)
5. Interrupt Controller
5.2.5
IRQ Sense Control Register (ISCR)
ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the
inputs at pins IRQ5 to IRQ0.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
IRQ 5 to IRQ0 sense control
These bits select level sensing or falling-edge
sensing for IRQ 5 to IRQ 0 interrupts
ISCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6⎯Reserved: These bits can be written and read, but they do not select level or
falling-edge sensing.
Bits 5 to 0⎯IRQ5 to IRQ0 Sense Control (IRQ5SC to IRQ0SC): These bits select whether
interrupts IRQ5 to IRQ0 are requested by level sensing of pins IRQ5 to IRQ0, or by falling-edge
sensing.
Bits 5 to 0
IRQ5SC to IRQ0SC Description
0
Interrupts are requested when IRQ5 to IRQ0 inputs are low
1
Interrupts are requested by falling-edge input at IRQ5 to IRQ0
(Initial value)
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5. Interrupt Controller
5.3
Interrupt Sources
The interrupt sources include external interrupts (NMI, IRQ0 to IRQ5) and 36 internal interrupts.
5.3.1
External Interrupts
There are seven external interrupts: NMI, and IRQ0 to IRQ5. Of these, NMI, IRQ0, IRQ1, and
IRQ2 can be used to exit software standby mode.
NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the I
and UI bits in CCR. The NMIEG bit in SYSCR selects whether an interrupt is requested by the
rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector
number 7.
IRQ0 to IRQ5 Interrupts: These interrupts are requested by input signals at pins IRQ0 to IRQ5.
The IRQ0 to IRQ5 interrupts have the following features.
• ISCR settings can select whether an interrupt is requested by the low level of the input at pins
IRQ0 to IRQ5, or by the falling edge.
• IER settings can enable or disable the IRQ0 to IRQ5 interrupts. Interrupt priority levels can be
assigned by four bits in IPRA (IPRA7 to IPRA4).
• The status of IRQ0 to IRQ5 interrupt requests is indicated in ISR. The ISR flags can be cleared
to 0 by software.
Figure 5.2 shows a block diagram of interrupts IRQ0 to IRQ5.
IRQnSC
IRQnE
IRQnF
Edge/level
sense circuit
S
Q
R
IRQn input
Clear signal
Note: n = 5 to 0
Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5
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IRQn interrupt
request
5. Interrupt Controller
Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF).
φ
IRQn
input pin
IRQnF
Note: n = 5 to 0
Figure 5.3 Timing of Setting of IRQnF
Interrupts IRQ0 to IRQ5 have vector numbers 12 to 17. These interrupts are detected regardless of
whether the corresponding pin is set for input or output. When using a pin for external interrupt
input, clear its DDR bit to 0 and do not use the pin for chip select output, refresh output, SCI
input/output, or A/D external trigger input.
5.3.2
Internal Interrupts
Thirty-Six internal interrupts are requested from the on-chip supporting modules.
• Each on-chip supporting module has status flags for indicating interrupt status, and enable bits
for enabling or disabling interrupts.
• Interrupt priority levels can be assigned in IPRA and IPRB.
• 16-bit timer, SCI, and A/D converter interrupt requests can activate the DMAC, in which case
no interrupt request is sent to the interrupt controller, and the I and UI bits are disregarded.
5.3.3
Interrupt Vector Table
Table 5.3 lists the interrupt sources, their vector addresses, and their default priority order. In the
default priority order, smaller vector numbers have higher priority. The priority of interrupts other
than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order
shown in table 5.3.
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5. Interrupt Controller
Table 5.3
Interrupt Sources, Vector Addresses, and Priority
Vector Address*
Interrupt Source
Origin
Vector Number
Advanced Mode
IPR
Priority
NMI
External
pins
7
H'001C to H'001F
⎯
High
12
H'0030 to H'0033
IPRA7
IRQ1
13
H'0034 to H0037
IPRA6
IRQ2
IRQ3
14
15
H'0038 to H'003B
H'003C to H'003F
IPRA5
IRQ4
IRQ5
16
17
H'0040 to H'0043
H'0044 to H'0047
IPRA4
IRQ0
Reserved
⎯
18
19
H'0048 to H'004B
H'004C to H'004F
WOVI
(interval timer)
Watchdog
timer
20
H'0050 to H'0053
CMI
(compare match)
DRAM
interface
21
H'0054 to H'0057
Reserved
⎯
22
H'0058 to H'005B
ADI (A/D end)
A/D
23
H'005E to H'005F
IMIA0
(compare match/
input capture A0)
IMIB0
(compare match/
input capture B0)
OVI0 (overflow 0)
16-bit timer
channel 0
24
H'0060 to H'0063
25
H'0064 to H'0067
26
H'0068 to H'006B
Reserved
⎯
27
H'006C to H'006F
IMIA1
(compare match/
inputcapture A1)
IMIB1
(compare match/
input capture B1)
OVI1 (overflow 1)
16-bit timer
channel 1
28
H'0070 to H'0073
29
H'0074 to H'0077
30
H'0078 to H'007B
Reserved
⎯
31
H'007C to H'007F
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IPRA3
IPRA2
IPRA1
Low
5. Interrupt Controller
Vector Address*
Interrupt Source
Origin
Vector Number
Advanced Mode
IPR
Priority
IMIA2
(compare match/
input capture A2)
IMIB2
(compare match/
input capture B2)
OVI2 (overflow 2)
16-bit timer
channel 2
32
H'0080 to H'0083
IPRA0
High
33
H'0084 to H'0087
34
H'0088 to H'008B
Reserved
⎯
35
H'008C to H'008F
CMIA0
(compare match
A0)
CMIB0
(compare match
B0)
CMIA1/CMIB1
(compare match
A1/B1)
TOVI0/TOVI1
(overflow 0/1)
8-bit timer
channel 0/1
36
H'0090 to H'0093
37
H'0094 to H'0097
38
H'0098 to H'009B
39
H'009C to H'009F
CMIA2
(compare match
A2)
CMIB2
(compare match
B2)
CMIA3/CMIB3
(compare match
A3/B3)
TOVI2/TOVI3
(overflow 2/3)
8-bit timer
channel 2/3
40
H'00A0 to H'00A3
41
H'00A4 to H'00A7
42
H'00A8 to H'00AB
43
H'00AC to H'00AF
DEND0A
DEND0B
DEND1A
DEND1B
DMAC
44
45
46
47
H'00B0 to H'00B3
H'00B4 to H'00B7
H'00B8 to H'00BB
H'00BC to H'00BF
IPRB5
Reserved
⎯
48
49
50
51
H'00C0 to H'00C3
H'00C4 to H'00C7
H'00C8 to H'00CB
H'00CC to H'00CF
⎯
IPRB7
IPRB6
Low
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5. Interrupt Controller
Vector Address*
Interrupt Source
Origin
Vector Number
Advanced Mode
IPR
Priority
ERI0
(receive error 0)
RXI0 (receive
data full 0)
TXI0 (transmit
data empty 0)
TEI0
(transmit end 0)
SCI
channel 0
52
H'00D0 to H'00D3
IPRB3
High
53
H'00D4 to H'00D7
54
H'00D8 to H'00DB
55
H'00DC to H'00DF
ERI1
(receive error 1)
RXI1 (receive
data full 1)
TXI1 (transmit
data empty 1)
TEI1 (transmit
end 1)
SCI
channel 1
56
H'00E0 to H'00E3
57
H'00E4 to H'00E7
58
H'00E8 to H'00EB
59
H'00EC to H'00EF
ERI2
(receive error 2)
RXI2 (receive
data full 2)
TXI2 (transmit
data empty 2)
TEI2 (transmit
end 2)
SCI
channel 2
60
H'00F0 to H'00F3
61
H'00F4 to H'00F7
62
H'00F8 to H'00FB
63
H'00FC to H'00FF
Note:
*
Lower 16 bits of the address.
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IPRB2
IPRB1
Low
5. Interrupt Controller
5.4
Interrupt Operation
5.4.1
Interrupt Handling Process
The H8/3006 and H8/3007 handle interrupts differently depending on the setting of the UE bit.
When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the
I and UI bits. Table 5.4 indicates how interrupts are handled for all setting combinations of the
UE, I, and UI bits.
NMI interrupts are always accepted except in the reset and hardware standby states. IRQ interrupts
and interrupts from the on-chip supporting modules have their own enable bits. Interrupt requests
are ignored when the enable bits are cleared to 0.
Table 5.4
UE, I, and UI Bit Settings and Interrupt Handling
SYSCR
CCR
UE
I
UI
Description
1
0
⎯
All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
1
⎯
No interrupts are accepted except NMI.
0
⎯
All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
1
0
NMI and interrupts with priority level 1 are accepted.
1
No interrupts are accepted except NMI.
0
UE = 1: Interrupts IRQ0 to IRQ5 and interrupts from the on-chip supporting modules can all be
masked by the I bit in the CPU's CCR. Interrupts are masked when the I bit is set to 1, and
unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority. Figure
5.4 is a flowchart showing how interrupts are accepted when UE = 1.
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5. Interrupt Controller
Program execution state
No
Interrupt requested?
Yes
Yes
NMI
No
No
Pending
Priority level 1?
Yes
IRQ 0
No
Yes
IRQ 1
IRQ 0
No
Yes
No
IRQ 1
Yes
No
Yes
TEI2
TEI2
Yes
Yes
No
I=0
Yes
Save PC and CCR
I ←1
Read vector address
Branch to interrupt
service routine
Figure 5.4 Process Up to Interrupt Acceptance when UE = 1
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5. Interrupt Controller
• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
• When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
• The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request
is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held
pending.
• When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
• In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
saved indicates the address of the first instruction that will be executed after the return from the
interrupt service routine.
• Next the I bit is set to 1 in CCR, masking all interrupts except NMI.
• The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
UE = 0: The I and UI bits in the CPU's CCR and the IPR bits enable three-level masking of
IRQ0 to IRQ5 interrupts and interrupts from the on-chip supporting modules.
• Interrupt requests with priority level 0 are masked when the I bit is set to 1, and are unmasked
when the I bit is cleared to 0.
• Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1, and
are unmasked when either the I bit or the UI bit is cleared to 0.
• For example, if the interrupt enable bits of all interrupt requests are set to 1, IPRA is set to
H'20, and IPRB is set to H'00 (giving IRQ2 and IRQ3 interrupt requests priority over other
interrupts), interrupts are masked as follows:
a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ2 > IRQ3 >IRQ0 …).
b. If I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 are unmasked.
c. If I = 1 and UI = 1, all interrupts are masked except NMI.
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5. Interrupt Controller
Figure 5.5 shows the transitions among the above states.
I←0
a. All interrupts are
unmasked
I←0
b. Only NMI, IRQ 2 , and
IRQ 3 are unmasked
I ← 1, UI ← 0
Exception handling,
or I ← 1, UI ← 1
UI ← 0
Exception handling,
or UI ← 1
c. All interrupts are
masked except NMI
Figure 5.5 Interrupt Masking State Transitions (Example)
Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.
• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
• When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
• The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request
is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set to 1 and
the UI bit is cleared to 0, only NMI and interrupts with priority level 1 are accepted; interrupt
requests with priority level 0 are held pending. If the I bit and UI bit are both set to 1, interrupt
requests are held pending.
• When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
• In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
saved indicates the address of the first instruction that will be executed after the return from the
interrupt service routine.
• The I and UI bits are set to 1 in CCR, masking all interrupts except NMI.
• The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
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5. Interrupt Controller
Program execution state
No
Interrupt requested?
Yes
Yes
NMI
No
No
Pending
Priority level 1?
Yes
IRQ 0
No
IRQ 0
Yes
IRQ 1
No
Yes
No
IRQ 1
Yes
No
Yes
TEI2
TEI2
Yes
Yes
No
No
I=0
I=0
Yes
Yes
No
UI = 0
Yes
Save PC and CCR
I ← 1, UI ← 1
Read vector address
Branch to interrupt
service routine
Figure 5.6 Process Up to Interrupt Acceptance when UE = 0
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Figure 5.7 Interrupt Sequence
(2)
(1)
(4)
High
(3)
(8)
(7)
(10)
(9)
(12)
(11)
Vector fetch
(14)
(13)
(6), (8)
PC and CCR saved to stack
(9), (11) Vector address
(10), (12) Starting address of interrupt service routine (contents of
vector address)
(13)
Starting address of interrupt service routine; (13) = (10), (12)
(14)
First instruction of interrupt service routine
(6)
(5)
Stack
Note: Mode 2, with program code and stack in external memory area accessed in two states via 16-bit bus.
Instruction prefetch address (not executed;
return address, same as PC contents)
(2), (4) Instruction code (not executed)
(3)
Instruction prefetch address (not executed)
(5)
SP − 2
(7)
SP − 4
(1)
D15 to D0
HWR , LWR
RD
Address
bus
Interrupt
request
signal
φ
Instruction Internal
prefetch
processing
Prefetch of
interrupt
Internal
service routine
processing instruction
5.4.2
Interrupt level
decision and wait
for end of instruction
Interrupt accepted
5. Interrupt Controller
Interrupt Sequence
Figure 5.7 shows the interrupt sequence in mode 2 when the program code and stack are in an
external memory area accessed in two states via a 16-bit bus.
5. Interrupt Controller
5.4.3
Interrupt Response Time
Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the
first instruction of the interrupt service routine is executed.
Table 5.5
Interrupt Response Time
External Memory
No.
On-Chip
Memory
Item
1
8-Bit Bus
2 States
3 States
Interrupt priority
decision
2*
2
Maximum number
of states until end of
current instruction
1 to 23
1 to 27
1 to 31*
3
Saving PC and CCR
to stack
4
8
12*
4
Vector fetch
4
8
5
Instruction prefetch*
2
4
3
Total
Internal processing*
2*
1
1
6
2*
1
16-Bit Bus
2 States
2*
4
1
3 States
2*
1
4
1 to 23
1 to 25*
4
4
6*
4
12*
4
4
6*
4
8
12*
4
4
6*
4
4
4
4
4
4
19 to 41
31 to 57
43 to 73
19 to 41
25 to 49
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the
interrupt service routine.
3. Internal processing after the interrupt is accepted and internal processing after vector
fetch.
4. The number of states increases if wait states are inserted in external memory access.
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5. Interrupt Controller
5.5
Usage Notes
5.5.1
Contention between Interrupt and Interrupt-Disabling Instruction
When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not
disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR,
MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant
when execution of the instruction ends the interrupt is still enabled, so its interrupt exception
handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception
handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored.
This also applies to the clearing of an interrupt flag to 0.
Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in the 16-bit timer's TISRA
register.
TISRA write cycle by CPU
IMIA exception handling
φ
Internal
address bus
TISRA address
Internal
write signal
IMIEA
IMIA
IMFA interrupt
signal
Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction
This type of contention will not occur if the interrupt is masked when the interrupt enable bit or
flag is cleared to 0.
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5. Interrupt Controller
5.5.2
Instructions that Inhibit Interrupts
The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after
determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is
currently executing one of these interrupt-inhibiting instructions, however, when the instruction is
completed the CPU always continues by executing the next instruction.
5.5.3
Interrupts during EEPMOV Instruction Execution
The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests.
When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the
transfer is completed, not even NMI.
When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are
not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at
a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction.
Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:
L1: EEPMOV.W
MOV.W R4,R4
BNE
L1
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5. Interrupt Controller
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6. Bus Controller
Section 6 Bus Controller
6.1
Overview
The H8/3006 and H8/3007 have an on-chip bus controller (BSC) that manages the external
address space divided into eight areas. The bus specifications, such as bus width and number of
access states, can be set independently for each area, enabling multiple memories to be connected
easily.
The bus controller also has a bus arbitration function that controls the operation of the internal bus
masters-the CPU, DMA controller (DMAC), and DRAM interface and can release the bus to an
external device.
6.1.1
Features
The features of the bus controller are listed below.
• Manages external address space in area units
⎯ Manages the external space as eight areas (0 to 7) of 128 kbytes in 1M-byte modes, or 2
Mbytes in 16-Mbyte modes
⎯ Bus specifications can be set independently for each area
⎯ DRAM/burst ROM interfaces can be set
• Basic bus interface
⎯ Chip select (CS0 to CS7) can be output for areas 0 to 7
⎯ 8-bit access or 16-bit access can be selected for each area
⎯ Two-state access or three-state access can be selected for each area
⎯ Program wait states can be inserted for each area
⎯ Pin wait insertion capability is provided
• DRAM interface
⎯ DRAM interface can be set for areas 2 to 5
⎯ Row address/column address multiplexed output (8/9/10 bits)
⎯ 2-CAS byte access mode
⎯ Burst operation (fast page mode)
⎯ TP cycle insertion to secure RAS precharging time
⎯ Choice of CAS-before-RAS refreshing or self-refreshing
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6. Bus Controller
• Burst ROM interface
⎯ Burst ROM interface can be set for area 0
⎯ Selection of two- or three-state burst access
• Idle cycle insertion
⎯ An idle cycle can be inserted in case of an external read cycle between different areas
⎯ An idle cycle can be inserted when an external read cycle is immediately followed by an
external write cycle
• Bus arbitration function
⎯ A built-in bus arbiter grants the bus right to the CPU, DMAC, DRAM interface, or an
external bus master
• Other features
⎯ The refresh counter (refresh timer) can be used as an interval timer
6.1.2
Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
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6. Bus Controller
CS0 to CS7
ABWCR
ASTCR
BCR
Internal address bus
Area
decoder
Internal signals
CSCR
Chip select
control signals
Bus mode control signal
Bus control
circuit
Bus size control signal
Internal data bus
Access state control signal
Wait state
controller
WAIT
Wait request signal
WCRH
WCRL
Internal signals
CPU bus request signal
DMAC bus request signal
DRAM interface bus request signal
CPU bus acknowledge signal
DMAC bus acknowledge signal
DRAM interface bus acknowledge signal
BRCR
Bus arbiter
BACK
BREQ
DRAM interface
DRAM control
DRCRA
DRCRB
RTMCSR
RTCNT
Legend:
ABWCR
ASTCR
WCRH
WCRL
BRCR
CSCR
DRCRA
DRCRB
RTMCSR
RTCNT
RTCOR
BCR
RTCOR
: Bus width control register
: Access state control register
: Wait control register H
: Wait control register L
: Bus release control register
: Chip select control register
: DRAM control register A
: DRAM control register B
: Refresh timer control/status register
: Refresh timer counter
: Refresh time constant register
: Bus control register
Figure 6.1 Block Diagram of Bus Controller
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6. Bus Controller
6.1.3
Pin Configuration
Table 6.1 summarizes the input/output pins of the bus controller.
Table 6.1
Bus Controller Pins
Name
Abbreviation
I/O
Function
Chip select 0 to 7
CS0 to CS7
Output
Strobe signals selecting areas 0 to 7
Address strobe
AS
Output
Strobe signal indicating valid address output
on the address bus
Read
RD
Output
Strobe signal indicating reading from the
external address space
High write
HWR
Output
Strobe signal indicating writing to the external
address space, with valid data on the upper
data bus (D15 to D8)
Low write
LWR
Output
Strobe signal indicating writing to the external
address space, with valid data on the lower
data bus (D7 to D0)
Wait
WAIT
Input
Wait request signal for access to external
three-state access areas
Bus request
BREQ
Input
Request signal for releasing the bus to an
external device
Bus acknowledge
BACK
Output
Acknowledge signal indicating release of the
bus to an external device
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6. Bus Controller
6.1.4
Register Configuration
Table 6.2 summarizes the bus controller's registers.
Table 6.2
Bus Controller Registers
1
Address*
Name
Abbreviation
R/W
Initial Value
H'EE020
Bus width control register
ABWCR
R/W
H'FF*
H'EE021
Access state control register
ASTCR
R/W
H'FF
H'EE022
Wait control register H
WCRH
R/W
H'FF
H'EE023
Wait control register L
WCRL
R/W
H'FF
H'EE013
Bus release control register
BRCR
R/W
H'FE*
H'EE01F
Chip select control register
CSCR
R/W
H'0F
H'EE024
Bus control register
BCR
R/W
H'C6
H'EE026
DRAM control register A
DRCRA
R/W
H'10
H'EE027
DRAM control register B
DRCRB
R/W
3
H'08
4
H'EE028
Refresh timer control/status register
RTMCSR
R/(W)*
H'EE029
Refresh timer counter
RTCNT
R/W
H'00
H'EE02A
Refresh time constant register
RTCOR
R/W
H'FF
Notes: 1.
2.
3.
4.
2
H'07
Lower 20 bits of the address in advanced mode.
In modes 2 and 4, the initial value is H'00.
In modes 3 and 4, the initial value is H'EE.
For Bit 7, only 0 can be written to clear the flag.
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6. Bus Controller
6.2
Register Descriptions
6.2.1
Bus Width Control Register (ABWCR)
ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area.
Bit
Modes
1 and 3
Initial value
Modes
2 and 4
Initial value
7
6
5
4
3
2
1
0
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write R/W
0
Read/Write R/W
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus
mode: the upper data bus (D15 to D8) is valid, and port 4 is an input/output port. When at least one
bit is cleared to 0 in ABWCR, the chip operates in 16-bit bus mode with a 16-bit data bus (D15 to
D0). In modes 1 and 3, ABWCR is initialized to H'FF by a reset and in hardware standby mode. In
modes 2 and 4, ABWCR is initialized to H'00 by a reset and in hardware standby mode. It is not
initialized in software standby mode.
Bits 7 to 0⎯Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access
or 16-bit access for the corresponding areas.
Bits 7 to 0
ABW7 to ABW0
Description
0
Areas 7 to 0 are 16-bit access areas
1
Areas 7 to 0 are 8-bit access areas
ABWCR specifies the data bus width of external memory areas. The data bus width of on-chip
memory and registers is fixed, and does not depend on ABWCR settings.
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6. Bus Controller
6.2.2
Access State Control Register (ASTCR)
ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two
states or three states.
Bit
7
6
5
4
3
2
1
0
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits selecting number of states for access to each area
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0⎯Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is accessed in two or three states.
Bits 7 to 0
AST7 to AST0
Description
0
Areas 7 to 0 are accessed in two states
1
Areas 7 to 0 are accessed in three states
(Initial value)
ASTCR specifies the number of states in which external areas are accessed. On-chip memory and
registers are accessed in a fixed number of states that does not depend on ASTCR settings.
When the corresponding area is designated as DRAM space by bits DRAS2 to DRAS0 in DRAM
control register A (DRCRA), the number of access states does not depend on the AST bit setting.
When an AST bit is cleared to 0, programmable wait insertion is not performed.
6.2.3
Wait Control Registers H and L (WCRH, WCRL)
WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait
states for each area.
On-chip memory and registers are accessed in a fixed number of states that does not depend on
WCRH/WCRL settings.
WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not
initialized in software standby mode.
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6. Bus Controller
WCRH
Bit
7
6
5
4
3
2
1
0
W71
W70
W61
W60
W51
W50
W41
W40
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7 and 6⎯Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of
program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set
to 1.
Bit 7
W71
Bit 6
W70
Description
0
0
Program wait not inserted when external space area 7 is accessed
1
1 program wait state inserted when external space area 7 is accessed
0
2 program wait states inserted when external space area 7 is accessed
1
3 program wait states inserted when external space area 7 is accessed
(Initial value)
1
Bits 5 and 4⎯Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of
program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set
to 1.
Bit 5
W61
Bit 4
W60
Description
0
0
Program wait not inserted when external space area 6 is accessed
1
1 program wait state inserted when external space area 6 is accessed
0
2 program wait states inserted when external space area 6 is accessed
1
3 program wait states inserted when external space area 6 is accessed
(Initial value)
1
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6. Bus Controller
Bits 3 and 2⎯Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of
program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set
to 1.
Bit 3
W51
Bit 2
W50
Description
0
0
Program wait not inserted when external space area 5 is accessed
1
1 program wait state inserted when external space area 5 is accessed
0
2 program wait states inserted when external space area 5 is accessed
1
3 program wait states inserted when external space area 5 is accessed
(Initial value)
1
Bits 1 and 0⎯Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of
program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set
to 1.
Bit 1
W41
Bit 0
W40
Description
0
0
Program wait not inserted when external space area 4 is accessed
1
1 program wait state inserted when external space area 4 is accessed
0
2 program wait states inserted when external space area 4 is accessed
1
3 program wait states inserted when external space area 4 is accessed
(Initial value)
1
WCRL
Bit
7
6
5
4
3
2
1
0
W31
W30
W21
W20
W11
W10
W01
W00
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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6. Bus Controller
Bits 7 and 6⎯Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of
program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set
to 1.
Bit 7
W31
Bit 6
W30
Description
0
0
Program wait not inserted when external space area 3 is accessed
1
1 program wait state inserted when external space area 3 is accessed
0
2 program wait states inserted when external space area 3 is accessed
1
3 program wait states inserted when external space area 3 is accessed
(Initial value)
1
Bits 5 and 4⎯Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of
program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set
to 1.
Bit 5
W21
Bit 4
W20
Description
0
0
Program wait not inserted when external space area 2 is accessed
1
1 program wait state inserted when external space area 2 is accessed
0
2 program wait states inserted when external space area 2 is accessed
1
3 program wait states inserted when external space area 2 is accessed
(Initial value)
1
Bits 3 and 2⎯Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of
program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set
to 1.
Bit 3
W11
Bit 2
W10
Description
0
0
Program wait not inserted when external space area 1 is accessed
1
1 program wait state inserted when external space area 1 is accessed
0
2 program wait states inserted when external space area 1 is accessed
1
3 program wait states inserted when external space area 1 is accessed
(Initial value)
1
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6. Bus Controller
Bits 1 and 0⎯Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of
program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set
to 1.
Bit 1
W01
Bit 0
W00
Description
0
0
Program wait not inserted when external space area 0 is accessed
1
1 program wait state inserted when external space area 0 is accessed
0
2 program wait states inserted when external space area 0 is accessed
1
3 program wait states inserted when external space area 0 is accessed
(Initial value)
1
6.2.4
Bus Release Control Register (BRCR)
BRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A20 and
enables or disables release of the bus to an external device.
7
6
5
4
3
2
1
0
A23E
A22E
A21E
A20E
⎯
⎯
⎯
BRLE
1
Modes
1 and 2 Read/Write ⎯
1
1
1
1
1
1
0
⎯
⎯
⎯
⎯
⎯
⎯
R/W
Modes Initial value 1
3 and 4 Read/Write R/W
1
1
0
1
1
1
0
R/W
R/W
⎯
⎯
⎯
⎯
R/W
Bit
Initial value
Reserved bits
Address 23 to 20 enable
These bits enable PA7 to PA4 to be
used for A23 to A20 address output
Bus release enable
Enables or disables
release of the bus to
an external device
BRCR is initialized to H'FE in modes 1 and 2, and to H'EE in modes 3 and 4, by a reset and in
hardware standby mode. It is not initialized in software standby mode.
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6. Bus Controller
Bit 7⎯Address 23 Enable (A23E): Enables PA4 to be used as the A23 address output pin. Writing
0 in this bit enables A23 output from PA4. In modes 1 and 2, this bit cannot be modified and PA4
has its ordinary port functions.
Bit 7
A23E
Description
0
PA4 is the A23 address output pin
1
PA4 is an input/output pin
(Initial value)
Bit 6⎯Address 22 Enable (A22E): Enables PA5 to be used as the A22 address output pin. Writing
0 in this bit enables A22 output from PA5. In modes 1 and 2, this bit cannot be modified and PA5
has its ordinary port functions.
Bit 6
A22E
Description
0
PA5 is the A22 address output pin
1
PA5 is an input/output pin
(Initial value)
Bit 5⎯Address 21 Enable (A21E): Enables PA6 to be used as the A21 address output pin. Writing
0 in this bit enables A21 output from PA6. In modes 1 and 2, this bit cannot be modified and PA6
has its ordinary port functions.
Bit 5
A21E
Description
0
PA6 is the A21 address output pin
1
PA6 is an input/output pin
(Initial value)
Bit 4⎯Address 20 Enable (A20E): Initial value of this bit varies depending on the mode. This
bit can not be modified.
Bit 4
A20E
Description
0
PA7 is the A20 address output pin (Initial value in mode 3 or 4)
1
PA7 is an input/output pin (Initial value in mode 1 or 2)
Bits 3 to 1⎯Reserved: These bits cannot be modified and are always read as 1.
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6. Bus Controller
Bit 0⎯Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0
BRLE
Description
0
The bus cannot be released to an external device
BREQ and BACK can be used as input/output pins
1
6.2.5
(Initial value)
The bus can be released to an external device
Bus Control Register (BCR)
Bit
7
6
ICIS1
ICIS0
5
4
3
BROME BRSTS1 BRSTS0
2
1
0
⎯
RDEA
WAITE
Initial value
1
1
0
0
0
1
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
⎯
R/W
R/W
BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the
area division unit, and enables or disables WAIT pin input.
BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7⎯Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read cycles for different areas.
Bit 7
ICIS1
Description
0
No idle cycle inserted in case of consecutive external read cycles for different
areas
1
Idle cycle inserted in case of consecutive external read cycles for different
areas
(Initial value)
Bit 6⎯Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read and write cycles.
Bit 6
ICIS0
Description
0
No idle cycle inserted in case of consecutive external read and write cycles
1
Idle cycle inserted in case of consecutive external read and write cycles
(Initial value)
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6. Bus Controller
Bit 5⎯Burst ROM Enable (BROME): Selects whether area 0 is a burst ROM interface area.
Bit 5
BROME
Description
0
Area 0 is a basic bus interface area
1
Area 0 is a burst ROM interface area
(Initial value)
Bit 4⎯Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycle states for the burst
ROM interface.
Bit 4
BRSTS1
Description
0
Burst access cycle comprises 2 states
1
Burst access cycle comprises 3 states
(Initial value)
Bit 3⎯Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0
Description
0
Max. 4 words in burst access (burst access on match of address bits above A3)
(Initial value)
1
Max. 8 words in burst access (burst access on match of address bits above A4)
Bit 2⎯Reserved: Read-only bit, always read as 1.
Bit 1⎯Area Division Unit Select (RDEA): Selects the memory map area division units. This bit
is valid in modes 3 and 4, and is invalid in modes 1 and 2.
Bit 1
RDEA
Description
0
Area divisions are as follows:
1
Area 0: 2 Mbytes
Area 4: 1.93 Mbytes
Area 1: 2 Mbytes
Area 5: 4 kbytes
Area 2: 8 Mbytes
Area 6: 23.75 kbytes
Area 3: 2 Mbytes
Area 7: 22 bytes
Areas 0 to 7 are the same size (2 Mbytes)
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(Initial value)
6. Bus Controller
Bit 0⎯WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the WAIT
pin.
Bit 0
WAITE
Description
0
WAIT pin wait input is disabled, and the WAIT pin can be used as an
input/output port
(Initial value)
1
WAIT pin wait input is enabled
6.2.6
Chip Select Control Register (CSCR)
CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals
(CS7 to CS4).
If output of a chip select signal is enabled by a setting in this register, the corresponding pin
functions a chip select signal (CS7 to CS4) output regardless of any other settings.
Bit
7
6
5
4
3
2
1
0
CS7E
CS6E
CS5E
CS4E
⎯
⎯
⎯
⎯
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
⎯
⎯
⎯
⎯
Chip select 7 to 4 enable
These bits enable or disable
chip select signal output
Reserved bits
CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4⎯Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable output of
the corresponding chip select signal.
Bit n
CSnE
Description
0
Output of chip select signal CSn is disabled
1
Output of chip select signal CSn is enabled
(Initial value)
Note: n = 7 to 4
Bits 3 to 0⎯Reserved: These bits cannot be modified and are always read as 1.
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6. Bus Controller
6.2.7
DRAM Control Register A (DRCRA)
Bit
7
6
5
4
3
2
1
0
DRAS2
DRAS1
DRAS0
⎯
BE
RDM
SRFMD
RFSHE
Initial value
0
0
0
1
0
0
0
0
Read/Write
R/W
R/W
R/W
⎯
R/W
R/W
R/W
R/W
DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface
function, and the access mode, and enables or disables self-refreshing and refresh pin output.
DRCRA is initialized to H'10 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 5⎯DRAM Area Select (DRAS2 to DRAS0): These bits select which of areas 2 to 5 are
to function as DRAM interface areas (DRAM space), and at the same time select the RAS output
pin corresponding to each DRAM space.
Description
Bit 7
Bit 6
Bit 5
DRAS2 DRAS1 DRAS0 Area 5
Area 4
Area 3
Area 2
0
0
1
1
0
1
0
Normal
Normal
Normal
Normal
1
Normal
Normal
Normal
DRAM space
(CS2)
0
Normal
Normal
DRAM space
(CS3)
DRAM space
(CS2)
1
Normal
Normal
0
Normal
DRAM space
(CS4)
DRAM space
(CS3)
DRAM space
(CS2)
1
DRAM space
(CS5)
DRAM space
(CS4)
DRAM space
(CS3)
DRAM space
(CS2)
0
DRAM space (CS4)*
1
Note:
*
DRAM space (CS2)*
DRAM space (CS2)*
DRAM space (CS2)*
A single CSn pin serves as a common RAS output pin for a number of areas. Unused
CSn pins can be used as input/output ports.
When any of bits DRAS2 to DRAS0 is set to 1, it is not possible to write to DRCRB, RTMCSR,
RTCNT, or RTCOR. However, 0 can be written to the CMF flag in RTMCSR to clear the flag.
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6. Bus Controller
When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than
000 must not be performed.
Bit 4⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 3⎯Burst Access Enable (BE): Enables or disables burst access to DRAM space. DRAM
space burst access is performed in fast page mode.
Bit 3
BE
Description
0
Burst disabled (always full access)
1
DRAM space access performed in fast page mode
(Initial value)
Bit 2⎯RAS Down Mode (RDM): Selects whether to wait for the next DRAM access with the
RAS signal held low (RAS down mode), or to drive the RAS signal high again (RAS up mode),
when burst access is enabled for DRAM space (BE = 1), and access to DRAM is interrupted.
Caution is required when the HWR and LWR are used as the UCAS and LCAS output pins. For
details, see RAS Down Mode and RAS Up Mode in section 6.5.10, Burst Operation.
Bit 2
RDM
Description
0
DRAM interface: RAS up mode selected
1
DRAM interface: RAS down mode selected
(Initial value)
Bit 1⎯Self-Refresh Mode (SRFMD): Specifies DRAM self-refreshing in software standby
mode.
When any of areas 2 to 5 is designated as DRAM space, DRAM self-refreshing is possible when a
transition is made to software standby mode after the SRFMD bit has been set to 1.
The normal access state is restored when software standby mode is exited, regardless of the
SRFMD setting.
Bit 1
SRFMD
Description
0
DRAM self-refreshing disabled in software standby mode
1
DRAM self-refreshing enabled in software standby mode
(Initial value)
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6. Bus Controller
Bit 0⎯Refresh Pin Enable (RFSHE): Enables or disables RFSH pin refresh signal output. If
areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1.
Bit 0
RFSHE
Description
0
RFSH pin refresh signal output disabled
(RFSH pin can be used as input/output port)
1
RFSH pin refresh signal output enabled
6.2.8
(Initial value)
DRAM Control Register B (DRCRB)
Bit
7
6
5
4
3
2
1
0
MXC1
MXC0
CSEL
RCYCE
⎯
TPC
RCW
RLW
Initial value
0
0
0
0
1
0
0
0
Read/Write
R/W
R/W
R/W
R/W
⎯
R/W
R/W
R/W
DRCRB is an 8-bit readable/writable register that selects the number of address multiplex column
address bits for the DRAM interface, the column address strobe output pin, enabling or disabling
of refresh cycle insertion, the number of precharge cycles, enabling or disabling of wait state
insertion between RAS and CAS, and enabling or disabling of wait state insertion in refresh
cycles.
DRCRB is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
The settings in this register are invalid when bits DRAS2 to DRAS0 in DRCRA are all 0.
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6. Bus Controller
Bits 7 and 6⎯Multiplex Control 1 and 0 (MXC1, MXC0): These bits select the row
address/column address multiplexing method used on the DRAM interface. In burst operation, the
row address used for comparison is determined by the setting of these bits and the bus width of the
relevant area set in ABWCR.
Bit 7
MXC1
Bit 6
MXC0
Description
0
0
Column address: 8 bits
Compared address:
1
A19 to A8
Modes 1, 2
8-bit access space
16-bit access space
A19 to A9
Modes 3, 4
8-bit access space
A23 to A8
16-bit access space
A23 to A9
8-bit access space
A19 to A9
16-bit access space
A19 to A10
8-bit access space
A23 to A9
16-bit access space
A23 to A10
8-bit access space
A19 to A10
16-bit access space
A19 to A11
8-bit access space
A23 to A10
16-bit access space
A23 to A11
Column address: 9 bits
Compared address:
Modes 1, 2
Modes 3, 4
1
0
Column address: 10 bits
Compared address:
Modes 1, 2
Modes 3, 4
1
Illegal setting
Bit 5⎯CAS Output Pin Select (CSEL): Selects the UCAS and LCAS output pins when areas 2
to 5 are designated as DRAM space.
Bit 5
CSEL
Description
0
PB4 and PB5 selected as UCAS and LCAS output pins
1
HWR and LWR selected as UCAS and LCAS output pins
(Initial value)
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6. Bus Controller
Bit 4⎯Refresh Cycle Enable (RCYCE): CAS-before-RAS enables or disables refresh cycle
insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not
inserted regardless of the setting of this bit.
Bit 4
RCYCE
Description
0
Refresh cycles disabled
1
DRAM refresh cycles enabled
(Initial value)
Bit 3⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 2⎯TP Cycle Control (TPC): Selects whether a 1-state or two-state precharge cycle (Tp) is to
be used for DRAM read/write cycles and CAS-before-RAS refresh cycles. The setting of this bit
does not affect the self-refresh function.
Bit 2
TPC
Description
0
1-state precharge cycle inserted
1
2-state precharge cycle inserted
(Initial value)
Bit 1⎯RAS-CAS Wait (RCW): Controls wait state (Trw) insertion between Tr and Tc1 in DRAM
read/write cycles. The setting of this bit does not affect refresh cycles.
Bit 1
RCW
Description
0
Wait state (Trw) insertion disabled
1
One wait state (Trw) inserted
(Initial value)
Bit 0⎯Refresh Cycle Wait Control (RLW): Controls wait state (TRW) insertion for CAS-beforeRAS refresh cycles. The setting of this bit does not affect DRAM read/write cycles.
Bit 0
RLW
Description
0
Wait state (TRW) insertion disabled
1
One wait state (TRW) inserted
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(Initial value)
6. Bus Controller
6.2.9
Refresh Timer Control/Status Register (RTMCSR)
Bit
7
6
5
4
3
2
1
0
CMF
CMIE
CKS2
CKS1
CKS0
⎯
⎯
⎯
Initial value
0
0
0
0
0
1
1
1
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
⎯
⎯
⎯
RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When
the refresh timer is used as an interval timer, RTMCSR also enables or disables interrupt requests.
Bits 7 and 6 of RTMCSR are initialized to 0 by a reset and in the standby modes. Bits 5 to 3 are
initialized to 0 by a reset and in hardware standby mode; they are not initialized in software
standby mode.
Note: Only 0 can be written to clear the flag.
Bit 7⎯Compare Match Flag (CMF): Status flag that indicates a match between the values of
RTCNT and RTCOR.
Bit 7
CMF
Description
0
[Clearing conditions]
1
•
When the chip is reset and in standby mode
•
Read CMF when CMF = 1, then write 0 in CMF
(Initial value)
[Setting condition]
When RTCNT = RTCOR
Bit 6⎯Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt
requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when
any of areas 2 to 5 is designated as DRAM space.
Bit 6
CMIE
Description
0
The CMI interrupt requested by CMF is disabled
1
The CMI interrupt requested by CMF is enabled
(Initial value)
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6. Bus Controller
Bits 5 to 3⎯Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be
input to RTCNT from among 7 clocks obtained by dividing the system clock (φ). When the input
clock is selected with bits CKS2 to CKS0, RTCNT begins counting up.
Bit 5 Bit 4 Bit 3
CKS2 CKS1 CKS0 Description
0
0
1
1
0
1
0
Count operation halted
1
φ/2 used as counter clock
0
φ/8 used as counter clock
1
φ/32 used as counter clock
(Initial value)
0
φ/128 used as counter clock
1
φ/512 used as counter clock
0
φ/2048 used as counter clock
1
φ/4096 used as counter clock
Bits 2 to 0⎯Reserved: These bits cannot be modified and are always read as 1.
6.2.10
Refresh Timer Counter (RTCNT)
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RTCNT is an 8-bit readable/writable up-counter.
RTCNT is incremented by an internal clock selected by bits CKS2 to CKS0 in RTMCSR. When
RTCNT matches RTCOR (compare match), the CMF flag in RTMCSR is set to 1 and RTCNT is
cleared to H'00. If the RCYCE bit in DRCRB is set to 1 at this time, a refresh cycle is started.
Also, if the CMIE bit in RTMCSR is set to 1, a compare match interrupt (CMI) is generated.
RTCNT is initialized to H'00 by a reset and in standby mode.
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6. Bus Controller
6.2.11
Refresh Time Constant Register (RTCOR)
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RTCOR is an 8-bit readable/writable register that sets the RTCNT compare-match interval.
RTCOR and RTCNT are constantly compared. When their values match, the CMF flag is set to 1
in RTMCSR, and RTCNT is simultaneously cleared to H'00.
RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Note: Only byte access should be used with this register.
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6. Bus Controller
6.3
Operation
6.3.1
Area Division
The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1Mbyte modes, or 2-Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the
memory map.
H'00000
H'000000
Area 0 (128 kbytes)
H'1FFFF
Area 0 (2 Mbytes)
H'1FFFFF
H'20000
H'200000
Area 1 (128 kbytes)
H'3FFFF
Area 1 (2 Mbytes)
H'3FFFFF
H'40000
H'400000
Area 2 (128 kbytes)
H'5FFFF
Area 2 (2 Mbytes)
H'5FFFFF
H'60000
H'600000
Area 3 (128 kbytes)
H'7FFFF
Area 3 (2 Mbytes)
H'7FFFFF
H'80000
H'800000
Area 4 (128 kbytes)
H'9FFFF
Area 4 (2 Mbytes)
H'9FFFFF
H'A0000
H'A00000
Area 5 (128 kbytes)
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 5 (2 Mbytes)
H'BFFFFF
H'C00000
Area 6 (128 kbytes)
Area 7 (128 Mbytes)
H'DFFFFF
H'E00000
Area 6 (2 Mbytes)
Area 7 (2 Mbytes)
H'FFFFF
H'FFFFFF
(a) 1-Mbyte modes (modes 1 and 2)
(b) 16-Mbyte modes (modes 3 and 4)
Figure 6.2 Access Area Map for Each Operating Mode
Chip select signals (CS0 to CS7) can be output for areas 0 to 7. The bus specifications for each area
are selected in ABWCR, ASTCR, WCRH, and WCRL.
In 16-Mbyte mode, the area division units can be selected with the RDEA bit in BCR.
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6. Bus Controller
Area 0
2 Mbytes
Area 0
2 Mbytes
Area 1
2 Mbytes
Area 1
2 Mbytes
2 Mbytes
H'000000
2 Mbytes
H'1FFFFF
H'200000
Area 2
8 Mbytes
2 Mbytes
Area 2
2 Mbytes
H'5FFFFF
H'600000
2 Mbytes
H'3FFFFF
H'400000
Area 3
2 Mbytes
H'7FFFFF
2 Mbytes
H'800000
Area 4
2 Mbytes
2 Mbytes
H'9FFFFF
H'A00000
Area 5
2 Mbytes
Area 6
2 Mbytes
Area 3
2 Mbytes
Area 7
1.93 Mbytes
Area 4
1.93 Mbytes
Internal I/O registers (1)
Internal I/O registers (1)
H'DFFFFF
H'E00000
2 Mbytes
H'BFFFFF
H'C00000
H'FEE000
H'FEE0FF
H'FEE100
Reserved 39.75 kbytes
H'FF7FFF
H'FF8000
Area 6
23.75 kbytes
On-chip RAM
4 kbytes
On-chip RAM
4 kbytes*
Internal I/O registers (2)
Internal I/O registers (2)
Area 7
22 bytes
Area 7
22 bytes
(a) Memory map when RDEA = 1
(b) Memory map when RDEA = 0
H'FFEF1F
H'FFEF20
2 Mbytes
Area 7
67.5 kbytes
Absolute
address 16 bits
Area 5
4 kbytes
H'FF8FFF
H'FF9000
H'FFFF1F
H'FFFF20
H'FFFFE9
H'FFFFEA
H'FFFFFF
Absolute
address 8 bits
H'FFFEFF
H'FFFF00
Note: * Area 6 when the RAME bit is cleared.
Figure 6.3 Memory Map in 16-Mbyte Mode (H8/3007)
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6. Bus Controller
6.3.2
Bus Specifications
The external space bus specifications consist of three elements: (1) bus width, (2) number of
access states, and (3) number of program wait states.
The bus width and number of access states for on-chip memory and registers are fixed, and are not
affected by the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit
bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected
functions as a16-bit access space.
If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit
access, 16-bit bus mode is set.
Number of Access States: Two or three access states can be selected with ASTCR. An area for
which two-state access is selected functions as a two-state access space, and an area for which
three-state access is selected functions as a three-state access space.
DRAM space is accessed in four states regardless of the ASTCR settings.
When two-state access space is designated, wait insertion is disabled.
Number of Program Wait States: When three-state access space is designated in ASTCR, the
number of program wait states to be inserted automatically is selected with WCRH and WCRL.
From 0 to 3 program wait states can be selected.
When ASTCR is cleared to 0 for DRAM space, a program wait (Tc1−Tc2 wait) is not inserted. Also,
no program wait is inserted in burst ROM space burst cycles.
Table 6.3 shows the bus specifications for each basic bus interface area.
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6. Bus Controller
Table 6.3
Bus Specifications for Each Area (Basic Bus Interface)
ABWCR ASTCR WCRH/WCRL
Bus Specifications (Basic Bus Interface)
ABWn
ASTn
Wn1
Wn0
Bus Width
Access States
Program Wait States
0
0
⎯
⎯
16
2
0
1
0
0
3
0
1
1
1
0
2
1
1
0
⎯
⎯
1
0
0
1
6.3.3
3
8
2
0
3
0
1
1
0
2
1
3
Memory Interfaces
The H8/3006 and H8/3007 memory interfaces comprise a basic bus interface that allows direct
connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of
DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can
be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, an area for
which the DRAM interface is designated functions as DRAM space, and area 0 for which the burst
ROM interface is designated functions as burst ROM space.
6.3.4
Chip Select Signals
For each of areas 0 to 7, the H8/3006 and H8/3007 can output a chip select signal (CS0 to CS7) that
goes low when the corresponding area is selected. Figure 6.4 shows the output timing of a CSn
signal.
Output of CS0 to CS3: Output of CS0 to CS3 is enabled or disabled in the data direction register
(DDR) of the corresponding port.
A reset leaves pin CS0 in the output state and pins CS1 to CS3 in the input state. To output chip
select signals CS1 to CS3, the corresponding DDR bits must be set to 1. For details, see section 8,
I/O Ports.
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6. Bus Controller
Output of CS4 to CS7: Output of CS4 to CS7 is enabled or disabled in the chip select control
register (CSCR). A reset leaves pins CS4 to CS7 in the input state. To output chip select signals CS4
to CS7, the corresponding CSCR bits must be set to 1. For details, see section 8, I/O Ports.
φ
Address bus
External address in area n
CSn
Figure 6.4 CSn Signal Output Timing (n = 0 to 7)
When the on-chip RAM and on-chip registers are accessed, CS0 to CS7 remain high. The CSn
signals are decoded from the address signals. They can be used as chip select signals for SRAM
and other devices.
6.4
Basic Bus Interface
6.4.1
Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL
(see table 6.3).
6.4.2
Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications
for the area being accessed (8-bit access area or 16-bit access area) and the data size.
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6. Bus Controller
8-Bit Access Areas: Figure 6.5 illustrates data alignment control for 8-bit access space. With 8-bit
access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that
can be accessed at one time is one byte: a word access is performed as two byte accesses, and a
longword access, as four byte accesses.
Upper data bus
Lower data bus
D15
D8 D7
D0
Byte size
Word size
1st bus cycle
2nd bus cycle
1st bus cycle
Longword size
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 6.5 Access Sizes and Data Alignment Control (8-Bit Access Area)
16-Bit Access Areas: Figure 6.6 illustrates data alignment control for 16-bit access areas. With
16-bit access areas, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for
accesses. The amount of data that can be accessed at one time is one byte or one word, and a
longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Upper data bus
Lower data bus
D15
D8 D7
D0
Byte size
· Even address
Byte size
· Odd address
Word size
Longword size
1st bus cycle
2nd bus cycle
Figure 6.6 Access Sizes and Data Alignment Control (16-Bit Access Area)
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6. Bus Controller
6.4.3
Valid Strobes
Table 6.4 shows the data buses used, and the valid strobes, for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
Table 6.4
Data Buses Used and Valid Strobes
Access
Size
Read/Write
Address
Valid Strobe
Upper Data Bus Lower Data Bus
(D15 to D8)
(D7 to D0)
8-bit
access
area
Byte
Read
⎯
RD
Valid
Write
⎯
HWR
16-bit
access
area
Byte
Read
Even
RD
Area
Odd
Undetermined
data
Valid
Invalid
Invalid
Valid
Even
HWR
Valid
Undetermined
data
Odd
LWR
Undetermined
data
Valid
Read
⎯
RD
Valid
Valid
Write
⎯
HWR, LWR
Valid
Valid
Write
Word
Invalid
Notes: 1. Undetermined data means that unpredictable data is output.
2. Invalid means that the bus is in the input state and the input is ignored.
6.4.4
Memory Areas
The initial state of each area is basic bus interface, three-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the following sections should be referred to for further details: 6.4, Basic Bus Interface,
6.5, DRAM Interface, 6.8, Burst ROM Interface.
Area 0: When area 0 external space is accessed, the CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
The size of area 0 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
Areas 1 and 6: When area 1 and 6 external space is accessed, the CS1 and CS6 pin signals
respectively can be output.
Only the basic bus interface can be used for areas 1 and 6.
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6. Bus Controller
The size of areas 1 and 6 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
Areas 2 to 5: When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output.
Basic bus interface or DRAM interface can be selected for areas 2 to 5. With the DRAM interface,
signals CS2 to CS5 are used as RAS signals.
The size of areas 2 to 5 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
Area 7: Area 7 includes the on-chip RAM and registers. The space excluding the on-chip RAM
and registers is external space. The on-chip RAM is enabled when the RAME bit in the system
control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is
disabled and the corresponding space becomes external space .
When area 7 external space is accessed, the CS7 signal can be output.
Only the basic bus interface can be used for the area 7 memory interface.
The size of area 7 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
Rev.5.00 Sep. 12, 2007 Page 137 of 764
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6. Bus Controller
6.4.5
Basic Bus Control Signal Timing
8-Bit, Three-State-Access Areas: Figure 6.7 shows the timing of bus control signals for an 8-bit,
three-state-access area. The upper data bus (D15 to D8) is used in accesses to these areas. The LWR
pin is always high. Wait states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
External address in area n
CSn
AS
RD
Read access
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write access
D15 to D8
D7 to D0
Valid
Undetermined data
Note: n = 7 to 0
Figure 6.7 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
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6. Bus Controller
8-Bit, Two-State-Access Areas: Figure 6.8 shows the timing of bus control signals for an 8-bit,
two-state-access area. The upper data bus (D15 to D8) is used in accesses to these areas. The LWR
pin is always high. Wait states cannot be inserted.
Bus cycle
T2
T1
φ
Address bus
External address in area n
CSn
AS
RD
Read access
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write access
D15 to D8
Valid
D7 to D0
Undetermined data
Note: n = 7 to 0
Figure 6.8 Bus Control Signal Timing for 8-Bit, Two-State-Access Area
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6. Bus Controller
16-Bit, Three-State-Access Areas: Figures 6.9 to 6.11 show the timing of bus control signals for
a 16-bit, three-state-access area. In these areas, the upper data bus (D15 to D8) is used in accesses to
even addresses and the lower data bus (D7 to D0) in accesses to odd addresses. Wait states can be
inserted.
Bus cycle
T1
T2
T3
φ
Address bus
Even external address in area n
CSn
AS
RD
Read access
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write access
D15 to D8
Valid
D7 to D0
Undetermined data
Note: n = 7 to 0
Figure 6.9 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
(Byte Access to Even Address)
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6. Bus Controller
Bus cycle
T1
T2
T3
φ
Address bus
Odd external address in area n
CSn
AS
RD
Read access
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write access
D15 to D8
Undetermined data
D7 to D0
Valid
Note: n = 7 to 0
Figure 6.10 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)
(Byte Access to Odd Address)
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6. Bus Controller
Bus cycle
T1
T2
T3
φ
Address bus
External address in area n
CSn
AS
RD
Read access
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write access
D15 to D8
Valid
D7 to D0
Valid
Note: n = 7 to 0
Figure 6.11 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)
(Word Access)
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6. Bus Controller
16-Bit, Two-State-Access Areas: Figures 6.12 to 6.14 show the timing of bus control signals for
a 16-bit, two-state-access area. In these areas, the upper data bus (D15 to D8) is used in accesses to
even addresses and the lower data bus (D7 to D0) in accesses to odd addresses. Wait states cannot
be inserted.
Bus cycle
T1
T2
φ
Address bus
Even external address in area n
CSn
AS
RD
Read access
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write access
D15 to D8
Valid
D7 to D0
Undetermined data
Note: n = 7 to 0
Figure 6.12 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
(Byte Access to Even Address)
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6. Bus Controller
Bus cycle
T1
T2
φ
Address bus
Odd external address in area n
CSn
AS
RD
Read access
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write access
D15 to D8
Undetermined data
D7 to D0
Valid
Note: n = 7 to 0
Figure 6.13 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)
(Byte Access to Odd Address)
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6. Bus Controller
Bus cycle
T1
T2
φ
Address bus
External address in area n
CSn
AS
RD
Read access
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write access
D15 to D8
Valid
D7 to D0
Valid
Note: n = 7 to 0
Figure 6.14 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)
(Word Access)
6.4.6
Wait Control
When accessing external space, the H8/3006 and H8/3007 can extend the bus cycle by inserting
one or more wait states (Tw). There are two ways of inserting wait states: (1) program wait
insertion and (2) pin wait insertion using the WAIT pin.
Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2
state and T3 state on an individual area basis in three-state access space, according to the settings
of WCRH and WCRL.
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6. Bus Controller
Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the
WAIT pin. When external space is accessed in this state, a program wait is first inserted. If the
WAIT pin is low at the falling edge of φ in the last T2 or TW state, another TW state is inserted. If
the WAIT pin is held low, TW states are inserted until it goes high.
This is useful when inserting four or more TW states, or when changing the number of TW states for
different external devices.
The WAITE bit setting applies to all areas. Pin waits cannot be inserted in DRAM space.
Figure 6.15 shows an example of the timing for insertion of one program wait state in 3-state
space.
T1
Inserted
by program wait Inserted by WAIT pin
T2
Tw
Tw
Tw
T3
φ
WAIT
Address bus
AS
RD
Read access
Data bus
Read data
HWR, LWR
Write access
Data bus
Note:
Write data
indicates the timing of WAIT pin sampling.
Figure 6.15 Example of Wait State Insertion Timing
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6. Bus Controller
6.5
DRAM Interface
6.5.1
Overview
The H8/3006 and H8/3007 are provided with a DRAM interface with functions for DRAM control
signal (RAS, UCAS, LCAS, WE) output, address multiplexing, and refreshing, that direct
connection of DRAM. In the expanded modes, external address space areas 2 to 5 can be
designated as DRAM space accessed via the DRAM interface. A data bus width of 8 or 16 bits can
be selected for DRAM space by means of a setting in ABWCR. When a 16-bit data bus width is
selected, CAS is used for byte access control. In the case of × 16-bit organization DRAM,
therefore, the 2-CAS type can be connected. A fast page mode is supported in addition to the
normal read and write access modes.
DRAM Space and RAS Output Pin Settings
6.5.2
Designation of areas 2 to 5 as DRAM space, and selection of the RAS output pin for each area
designated as DRAM space, is performed by setting bits DRAS2 to DRAS0 in DRCRA. Table 6.5
shows the correspondence between the settings of bits DRAS2 to DRAS0 and the selected DRAM
space and RAS output pin.
When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than
000 must not be performed.
Table 6.5
Settings of Bits DRAS2 to DRAS0 and Corresponding DRAM Space
(RAS Output Pin)
DRAS2 DRAS1 DRAS0 Area 5
Area 4
Area 3
Area 2
0
0
1
1
0
1
0
Normal space
Normal space
Normal space
Normal space
1
Normal space
Normal space
Normal space
DRAM space
(CS2)
0
Normal space
Normal space
DRAM space
(CS3)
DRAM space
(CS2)
1
Normal space
Normal space
0
Normal space
DRAM space
(CS4)
DRAM space
(CS3)
DRAM space
(CS2)
1
DRAM space
(CS5)
DRAM space
(CS4)
DRAM space
(CS3)
DRAM space
(CS2)
0
1
Note:
*
DRAM space (CS4)*
DRAM space (CS2)*
DRAM space (CS2)*
DRAM space (CS2)*
A single CSn pin serves as a common RAS output pin for a number of areas. Unused
CSn pins can be used as input/output ports.
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6. Bus Controller
6.5.3
Address Multiplexing
When DRAM space is accessed, the row address and column address are multiplexed. The address
multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the number
of bits in the DRAM column address. Table 6.6 shows the correspondence between the settings of
MXC1 and MXC0 and the address multiplexing method.
Table 6.6
Settings of Bits MXC1 and MXC0 and Address Multiplexing Method
DRCRB
Row
address
Note:
6.5.4
*
Address Pins
MXC1 MXC0 Bits
A23 to A13
A12 A11 A10 A9
A1
A0
0
0
A23 to A13
A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A8
1
9 bits
A23 to A13
A12 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
1
0
10 bits
A23 to A13
A12 A11 A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
1
Illegal
setting
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A23 to A13
A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
⎯
Column
address
Column
Address
8 bits
⎯
⎯
A8
A7
A6
A5
A4
A3
A2
Row address bit A20 is not multiplexed in 1-Mbyte mode.
Data Bus
If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, × 16-bit organization DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM
space both the upper and lower halves of the data bus, D15 to D0, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data
Size and Data Alignment.
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6. Bus Controller
6.5.5
Pins Used for DRAM Interface
Table 6.7 shows the pins used for DRAM interfacing and their functions.
Table 6.7
DRAM Interface Pins
Pin
With DRAM
Designated Name
I/O
Function
PB4
UCAS
Upper column
address strobe
Output
Upper column address strobe for DRAM
space access (when CSEL = 0 in DRCRB)
PB5
LCAS
Lower column
address strobe
Output
Lower column address strobe for DRAM
space access (when CSEL = 0 in DRCRB)
HWR
UCAS
Upper column
address strobe
Output
Upper column address strobe for DRAM
space access (when CSEL = 1 in DRCRB)
LWR
LCAS
Lower column
address strobe
Output
Lower column address strobe for DRAM
space access (when CSEL = 1 in DRCRB)
CS2
RAS2
Row address
strobe 2
Output
Row address strobe for DRAM space access
CS3
RAS3
Row address
strobe 3
Output
Row address strobe for DRAM space access
CS4
RAS4
Row address
strobe 4
Output
Row address strobe for DRAM space access
CS5
RAS5
Row address
strobe 5
Output
Row address strobe for DRAM space access
RD
WE
Write enable
Output
Write enable for DRAM space write access*
P80
RFSH
Refresh
Output
Goes low in refresh cycle
A12 to A0 A12 to A0
Address
Output
Row address/column address multiplexed
output
D15 to D0 D15 to D0
Data
I/O
Data input/output pins
Note:
6.5.6
*
Fixed high in a read access.
Basic Timing
Figure 6.16 shows the basic access timing for DRAM space. The basic DRAM access timing is
four states: one precharge cycle (Tp) state, one row address output cycle (Tr) state, and two column
address output cycle (Tc1, Tc2) states. Unlike the basic bus interface, the corresponding bits in
ASTCR control only enabling or disabling of wait insertion between Tc1 and Tc2, and do not affect
the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states
cannot be inserted between Tc1 and Tc2 in the DRAM access cycle.
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6. Bus Controller
If a DRAM read/write cycle is followed by an access cycle for an external area other than DRAM
space when HWR and LWR are selected as the UCAS and LCAS output pins, an idle cycle (Ti) is
inserted unconditionally immediately after the DRAM access cycle. See section 6.9, Idle Cycle,
for details.
Tp
Tr
Tc1
φ
A23 to A0
AS
Row
Column
High
CSn (RAS)
PB4 /PB5
(UCAS / LCAS)
Read access
RD(WE)
High
D15 to D0
PB4 /PB5
(UCAS / LCAS)
Write access
RD(WE)
D15 to D0
Note: n = 2 to 5
Figure 6.16 Basic Access Timing (CSEL = 0 in DRCRB)
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Tc2
6. Bus Controller
6.5.7
Precharge State Control
In the H8/3006 and H8/3007, provision is made for the DRAM RAS precharge time by always
inserting one RAS precharge state (Tp) when DRAM space is accessed. This can be changed to
two Tp states by setting the TPC bit to 1 in DRCRB. The optimum number of Tp cycles should be
set according to the DRAM connected and the operating frequency of the H8/3006 and H8/3007
chip. Figure 6.17 shows the timing when two Tp states are inserted.
When the TCP bit is set to 1, two Tp states are also used for CAS-before-RAS refresh cycles.
Tp1
Tp2
Tr
Tc1
Tc2
φ
A23 to A0
Row
AS
High
Column
CSn (RAS)
PB4 /PB5
(UCAS /LCAS)
RD(WE)
Read access
High
D15 to D0
PB4 /PB5
(UCAS /LCAS)
Write access
RD(WE)
D15 to D0
Note: n = 2 to 5
Figure 6.17 Timing with Two Precharge States (CSEL = 0 in DRCRB)
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6. Bus Controller
6.5.8
Wait Control
In a DRAM access cycle, wait states can be inserted (1) between the Tr state and Tc1 state, and (2)
between the Tc1 state and Tc2 state.
Insertion of Trw Wait State between Tr and Tc1: One Trw state can be inserted between Tr and Tc1
by setting the RCW bit to 1 in DRCRB.
Insertion of Tw Wait State(s) between Tc1 and Tc2: When the bit in ASTCR corresponding to an
area designated as DRAM space is set to 1, from 0 to 3 Tw states can be inserted between the Tc1
state and Tc2 state by means of settings in WCRH and WCRL.
Figure 6.18 shows an example of the timing for wait state insertion.
The settings of the RCW bit in DRCRB and of ASTCR, WCRH, and WCRL do not affect refresh
cycles. Wait states cannot be inserted in a DRAM space access cycle by means of the WAIT pin.
Tp
Tr
Trw
Tc1
Tw
Tw
Tc2
φ
A23 to A0
AS
Row
Column
High
CSn(RAS)
Read access
PB4 /PB5
(UCAS /LCAS)
RD(WE)
D15 to D0
High
Read data
PB4 /PB5
(UCAS /LCAS)
Write access
RD(WE)
D15 to D0
Write data
Note: n = 2 to 5
Figure 6.18 Example of Wait State Insertion Timing (CSEL = 0)
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6. Bus Controller
6.5.9
Byte Access Control and CAS Output Pin
When an access is made to DRAM space designated as a 16-bit-access area in ABWCR, column
address strobes (UCAS and LCAS) corresponding to the upper and lower halves of the external
data bus are output. In the case of × 16-bit organization DRAM, the 2-CAS type can be connected.
Either PB4 and PB5, or HWR and LWR, can be used as the UCAS and LCAS output pins, the
selection being made with the CSEL bit in DRCRB. Table 6.8 shows the CSEL bit settings and
corresponding output pin selections.
When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only
UCAS is output. When the entire DRAM space is designated as 8-bit-access space and CSEL = 0,
PB5 can be used as an input/output port.
Note that RAS down mode cannot be used when a device other than DRAM is connected to
external space and HWR and LWR are used as write strobes. In this case, also, an idle cycle (Ti) is
always inserted when an external access to other than DRAM space occurs after a DRAM space
access. For details, see section 6.9, Idle Cycle.
Table 6.8
CSEL Settings and UCAS and LCAS Output Pins
CSEL
UCAS
LCAS
0
PB4
PB5
1
HWR
LWR
Figure 6.19 shows the control timing.
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6. Bus Controller
Tp
Tr
Tc1
Row
Column
Tc2
φ
A23 to A0
CSn (RAS)
PB4(UCAS)
Byte control
PB5(LCAS)
RD(WE)
Note: n = 2 to 5
Figure 6.19 Control Timing (Upper-Byte Write Access When CSEL = 0)
6.5.10
Burst Operation
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a
row address for each access, a fast page mode is also provided which can be used when making a
number of consecutive accesses to the same row address. This mode enables fast (burst) access of
data by simply changing the column address after the row address has been output. Burst access
can be selected by setting the BE bit to 1 in DRCRA.
Burst Access (Fast Page Mode) Operation Timing: Figure 6.20 shows the operation timing for
burst access. When there are consecutive access cycles for DRAM space, the column address and
CAS signal output cycles (two states) continue as long as the row address is the same for
consecutive access cycles. In burst access, too, the bus cycle can be extended by inserting wait
states between Tc1 and Tc2. The wait state insertion method and timing are the same as for full
access: see section 6.5.8, Wait Control, for details.
The row address used for the comparison is determined by the bus width of the relevant area set in
bits MXC1 and MXC0 in BRCRB, and in ABWCR. Table 6.9 shows the compared row addresses
corresponding to the various settings of bits MXC1 and MXC0, and ABWCR.
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6. Bus Controller
Tp
Tr
Tc1
Tc2
Tc1
Tc2
φ
A23 to A0
AS
Row
Column 1
Column 2
High
CSn(RAS)
PB4 /PB5
(UCAS /LCAS)
Read access
RD(WE)
High
D15 to D0
PB4 /PB5
(UCAS/LCAS)
Write access
RD(WE)
D15 to D0
Note: n = 2 to 5
Figure 6.20 Operation Timing in Fast Page Mode
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6. Bus Controller
Table 6.9
Correspondence between Settings of MXC1 and MXC0 Bits and ABWCR, and
Row Address Compared in Burst Access
DRCRB
ABWCR
Operating Mode
MXC1
MXC0
ABWn
Bus Width
Compared Row Address
Modes 1 and 2
(1-Mbyte)
0
0
0
16 bits
A19 to A9
1
8 bits
A19 to A8
0
16 bits
A19 to A10
1
8 bits
A19 to A9
0
16 bits
A19 to A11
1
8 bits
A19 to A10
1
⎯
⎯
Illegal setting
0
0
16 bits
A23 to A9
1
8 bits
A23 to A8
1
0
16 bits
A23 to A10
1
8 bits
A23 to A9
0
16 bits
A23 to A11
1
8 bits
A23 to A10
⎯
⎯
Illegal setting
1
1
Modes 3 and 4
(16-Mbyte)
0
1
0
0
1
Note: n = 2 to 5
RAS Down Mode and RAS Up Mode: With DRAM provided with fast page mode, as long as
accesses are to the same row address, burst operation can be continued without interruption even if
accesses are not consecutive by holding the RAS signal low.
• RAS Down Mode
To select RAS down mode, set the BE and RDM bits to 1 in DRCRA. If access to DRAM
space is interrupted and another space is accessed, the RAS signal is held low during the
access to the other space, and burst access is performed if the row address of the next DRAM
space access is the same as the row address of the previous DRAM space access. Figure 6.21
shows an example of the timing in RAS down mode.
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6. Bus Controller
External space
access
DRAM access
Tp
Tr
Tc1
Tc2
T1
T2
DRAM access
Tc1
Tc2
φ
A23 to A0
AS
CSn (RAS)
PB4/PB5
(UCAS/LCAS)
D15 to D0
Note: n = 2 to 5
Figure 6.21 Example of Operation Timing in RAS Down Mode (CSEL = 0)
When RAS down mode is selected, the conditions for an asserted RASn signal to return to the
high level are as shown below. The timing in these cases is shown in figure 6.22.
⎯ When DRAM space with a different row address is accessed
⎯ Immediately before a CAS-before-RAS refresh cycle
⎯ When the BE bit or RDM bit is cleared to 0 in DRCRA
⎯ Immediately before release of the external bus
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6. Bus Controller
DRAM access cycle
φ
RASn
(a) Access to DRAM space with a different row address
CBR refresh cycle
φ
RASn
(b) CAS-before-RAS refresh cycle
DRCRA write cycle
φ
RASn
(c) BE bit or RDM bit cleared to 0 in DRCRA
External bus released
φ
High-impedance
RASn
(d) External bus released
Note: n = 2 to 5
Figure 6.22 RASn Negation Timing when RAS Down Mode Is Selected
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6. Bus Controller
When RAS down mode is selected, the CAS-before-RAS refresh function provided with this
DRAM interface must always be used as the DRAM refreshing method. When a refresh
operation is performed, the RAS signal goes high immediately beforehand. The refresh
interval setting must be made so that the maximum DRAM RAS pulse width specification is
observed.
When the self-refresh function is used, the RDM bit must be cleared to 0, and RAS up mode
selected, before executing a SLEEP instruction in order to enter software standby mode.
Select RAS down mode again after exiting software standby mode.
Note that RAS down mode cannot be used when HWR and LWR are selected for UCAS and
LCAS, a device other than DRAM is connected to external space, and HWR and LWR are
used as write strobes.
• RAS Up Mode
To select RAS up mode, clear the RDM bit to 0 in DRCRA. Each time access to DRAM space
is interrupted and another space is accessed, the RAS signal returns to the high level. Burst
operation is only performed if DRAM space is continuous. Figure 6.23 shows an example of
the timing in RAS up mode.
DRAM access
Tp
Tr
Tc1
DRAM access
Tc2
Tc1
Tc2
External space
access
T1
T2
φ
A23 to A0
AS
CSn(RAS)
PB4/PB5
(UCAS/LCAS)
D15 to D0
Note: n = 2 to 5
Figure 6.23 Example of Operation Timing in RAS Up Mode
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6. Bus Controller
6.5.11
Refresh Control
The H8/3006 and H8/3007 are provided with a CAS-before-RAS (CBR) function and self-refresh
function as DRAM refresh control functions.
CAS-Before-RAS (CBR) Refreshing: To select CBR refreshing, set the RCYCE bit to 1 in
DRCRB.
With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in
RTMCSR, and a refresh request is generated when the count matches the value set in RTCOR
(compare match). At the same time, RTCNT is reset and starts counting up again from H'00.
Refreshing is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. A
refresh cycle is executed after this refresh request has been accepted and the DRAM interface has
acquired the bus. Set a value in bits CKS2 to CKS0 in RTCOR that will meet the refresh interval
specification for the DRAM used. When RAS down mode is used, set the refresh interval so that
the maximum RAS pulse width specification is met.
RTCNT starts counting up when bits CKS2 to CKS0 are set. RTCNT and RTCOR settings should
therefore be completed before setting bits CKS2 to CKS0.
Also note that a repeat refresh request generated during a bus request, or a refresh request during
refresh cycle execution, will be ignored.
RTCNT operation is shown in figure 6.24, compare match timing in figure 6.25, and CBR refresh
timing in figures 6.26 and 6.27.
RTCNT
RTCOR
H'00
Refresh request
Figure 6.24 RTCNT Operation
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φ
RTCNT
N
H'00
RTCOR
N
Refresh request signal
and CMF bit setting signal
Figure 6.25 Compare Match Timing
TRp
TR1
TR2
φ
Address bus
Area 2 start address
CSn(RAS)
PB4/PB5
(UCAS/LCAS)
RD(WE)
High
RFSH
AS
High
Figure 6.26 CBR Refresh Timing (CSEL = 0, TPC = 0, RLW = 0)
The basic CBS refresh cycle timing comprises three states: one RAS precharge cycle (TRP) state,
and two RAS output cycle (TR1, TR2) states. Either one or two states can be selected for the RAS
precharge cycle. When the TPC bit is set to 1 in DRCRB, RAS signal output is delayed by one
cycle. This does not affect the timing of UCAS and LCAS output.
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Use the RLW bit in DRCRB to adjust the RAS signal width. A single refresh wait state (TRW) can
be inserted between the TR1 state and TR2 state by setting the RLW bit to 1.
The RLW bit setting is valid only for CBR refresh cycles, and does not affect DRAM read/write
cycles. The number of states in the CBR refresh cycle is not affected by the settings in ASTCR,
WCRH, or WCRL, or by the state of the WAIT pin.
Figure 6.27 shows the timing when the TPC bit and RLW bit are both set to 1.
TRp1
TRP2
TR1
TRW
TR2
φ
Address bus
Area 2 start address
CSn(RAS)
PB4/PB5
(UCAS/LCAS)
RD(WE)
High
RFSH
AS
High
Figure 6.27 CBR Refresh Timing (CSEL = 0, TPC = 1, RLW = 1)
DRAM must be refreshed immediately after powering on in order to stabilize its internal state.
When using the H8/3006 and H8/3007 CAS-before-RAS refresh function, therefore, a DRAM
stabilization period should be provided by means of interrupts by another timer module, or by
counting the number of times bit 7 (CMF) of RTMCSR is set, for instance, immediately after bits
DRAS2 to DRAS0 have been set in DRCRA.
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Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of
standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM.
The H8/3006 and H8/3007 have a function that places the DRAM in self-refresh mode when the
chip enters software standby mode.
To use the self-refresh function, set the SRFMD bit to 1 in DRCRA. When a SLEEP instruction is
subsequently executed in order to enter software standby mode, the CAS and RAS signals are
output and the DRAM enters self-refresh mode, as shown in figure 6.28.
When the chip exits software standby mode, CAS and RAS outputs go high.
The following conditions must be observed when the self-refresh function is used:
• When burst access is selected, RAS up mode must be selected before executing a SLEEP
instruction in order to enter software standby mode. Therefore, if RAS down mode has been
selected, the RDM bit in DRCRA must be cleared to 0 and RAS up mode selected before
executing the SLEEP instruction. Select RAS down mode again after exiting software standby
mode.
• The instruction immediately following a SLEEP instruction must not be located in an area
designated as DRAM space.
The self-refresh function will not work properly unless the above conditions are observed.
Software standby
mode
Oscillation stabilization
time
φ
Address bus
High-impedance
CSn(RAS)
PB4(UCAS)
PB5(LCAS)
RD(WE)
RFSH
Figure 6.28 Self-Refresh Timing (CSEL = 0)
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6. Bus Controller
Refresh Signal (RFSH): A refresh signal (RFSH) that transmits a refresh cycle off-chip can be
output by setting the RFSHE bit to 1 in DRCRA. RFSH output timing is shown in figures 6.26,
6.27, and 6.28.
6.5.12
Examples of Use
Examples of DRAM connection and program setup procedures are shown below. When the
DRAM interface is used, check the DRAM device characteristics and choose the most appropriate
method of use for that device.
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Connection Examples
• Figure 6.29 shows typical interconnections when using two 2-CAS type 16-Mbit DRAMs
using a × 16-bit organization, and the corresponding address map. The DRAMs used in this
example are of the 10-bit row address × 10-bit column address type. Up to four DRAMs can be
connected by designating areas 2 to 5 as DRAM space.
2-CAS 16-Mbit DRAM
10-bit row address × 10-bit column address
× 16-bit organization
H8/3006 and H8/3007
CS2 (RAS2)
CS3 (RAS3)
PB4 (UCAS)
RAS
PB5(LCAS)
RD (WE)
UCAS
LCAS
WE
A10-A1
A9-A0
D15-D0
D15-D0
No.1
OE
RAS
UCAS
LCAS
WE
No.2
A9-A0
D15-D0
OE
(a) Interconnections (example)
PB4
(UCAS)
15
PB5
(LCAS)
87
0
H'400000
Area 2
DRAM (No. 1)
CS2 (RAS2)
DRAM (No. 2)
CS3 (RAS3)
H'5FFFFE
H'600000
Area 3
H'7FFFFE
H'800000
Area 4
Normal
CS4
Normal
CS5
H'9FFFFE
H'A00000
Area 5
H'BFFFFE
(b) Address map
Figure 6.29 Interconnections and Address Map for 2-CAS 16-Mbit DRAMs with × 16-Bit
Organization
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• Figure 6.30 shows typical interconnections when using two 16-Mbit DRAMs using a × 8-bit
organization, and the corresponding address map. The DRAMs used in this example are of the
11-bit row address × 10-bit column address type. The CS2 pin is used as a common RAS
output pin for area 2 and area 3. When the DRAM address space spans a number of contiguous
areas, as in this example, the appropriate setting of bits DRAS2 to DRAS0 enables a single CS
pin to be used as the common RAS output pin for a number of areas, and makes it possible to
directly connect large-capacity DRAM with address space that spans a maximum of four areas.
Any unused CS pins (in this example, the CS3 pin) can be used as input/output ports.
2-CAS 16-Mbit DRAM
11-bit row address × 10-bit column address
× 8-bit organization
H8/3006 and H8/3007
RAS
CAS
CS2 (RAS2)
PB4 (UCAS)
PB5 (LCAS)
WE
RD (WE)
No.1
A10-A0
A21, A10-A1
D7-D0
D15-D8
D7-D0
OE
RAS
CAS
WE
No.2
A10-A0
D7-D0
OE
(a) Interconnections (example)
PB4
(UCAS)
15
PB5
(LCAS)
87
0
H'400000
Area 2
H'5FFFFE
H'600000
DRAM
(No.1)
DRAM
(No.2)
CS2(RAS2)
Area 3
H'7FFFFE
H'800000
Area 4
Normal
CS4
Normal
CS5
H'9FFFFE
H'A00000
Area 5
H'BFFFFE
16-Mbyte mode
(b) Address map
Figure 6.30 Interconnections and Address Map for 16-Mbit DRAMs with × 8-Bit
Organization
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6. Bus Controller
• Figure 6.31 shows typical interconnections when using two 4-Mbit DRAMs, and the
corresponding address map. The DRAMs used in this example are of the 9-bit row address ×
9-bit column address type. In this example, upper address decoding allows multiple DRAMs to
be connected to a single area. The RFSH pin is used in this case, since both DRAMs must be
refreshed simultaneously. However, note that RAS down mode cannot be used in this
interconnection example.
2-CAS 4-Mbit DRAM
9-bit row address × 9-bit column address
× 16-bit organization
H8/3006 and H8/3007
CS2 (RAS2)
PB4 (UCAS)
PB5 (LCAS)
RD (WE)
RAS
UCAS
LCAS
WE
No.1
RFSH
A19
A9-A1
A8-A0
D15-D0
D15-D0
RAS
UCAS
LCAS
WE
OE
No.2
A8-A0
D15-D0
OE
(a) Interconnections (example)
PB4
(UCAS)
15
PB5
(LCAS)
87
0
H'400000
DRAM (No.1)
H'47FFFE
H'480000
DRAM (No.2)
Area 2
H'4FFFFE
H'500000
CS2 (RAS2)
Not used
H'5FFFFE
16-Mbyte mode
(b) Address map
Figure 6.31 Interconnections and Address Map for 2-CAS 4-Mbit DRAMs with × 16-Bit
Organization
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Example of Program Setup Procedure: Figure 6.32 shows an example of the program setup
procedure.
Set ABWCR
Set RTCOR
Set bits CKS2 to CKS0 in RTMCSR
Set DRCRB
Set DRCRA
Wait for DRAM stabilization time
DRAM can be accessed
Figure 6.32 Example of Setup Procedure when Using DRAM Interface
6.5.13
Usage Notes
Note the following points when using the DRAM refresh function.
• Refresh cycles will not be executed when the external bus released state, software standby
mode, or a bus cycle is extended by means of wait state insertion. Refreshing must therefore be
performed by other means in these cases.
• If a refresh request is generated internally while the external bus is released, the first request is
retained and a single refresh cycle will be executed after the bus-released state is cleared.
Figure 6.33 shows the bus cycle in this case.
• When a bus cycle is extended by means of wait state insertion, the first request is retained in
the same way as when the external bus has been released.
In the event of contention with a bus request from an external bus master when a transition is
made to software standby mode, the BACK and strobe states may be indeterminate after the
transition to software standby mode (see figure 6.34).
When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before
executing the SLEEP instruction.
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6. Bus Controller
Similar contention in a transition to self-refresh mode may prevent dependable strobe
waveform output. This can also be avoided by clearing the BRLW bit to 0 in BRCR.
• Immediately after self-refreshing is cleared, external bus release is possible during a given
period until the start of a CPU cycle. Attention must be paid to the RAS state to ensure that the
specification for the RAS precharge time immediately after self-refreshing is met.
External bus released
Refresh cycle
CPU cycle
Refresh cycle
φ
RFSH
Refresh
request
BACK
Figure 6.33
Bus-Released State and Refresh Cycles
Software standby mode
φ
BREQ
BACK
Address bus
Strobe
Figure 6.34 Bus-Released State and Software Standby Mode
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Oscillation stabilization
CPU internal cycle
time on exit from software (period in which external
standby mode
bus can be released)
CPU cycle
φ
Address bus
@SP
RAS
CAS
Figure 6.35 Self-Refresh Clearing
6.6
Interval Timer
6.6.1
Operation
When DRAM is not connected to the H8/3006 and H8/3007 chip, the refresh timer can be used as
an interval timer by clearing bits DRAS2 to DRAS0 in DRCRA to 0. After setting RTCOR,
selection a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1.
Timing of Setting of Compare Match Flag and Clearing by Compare Match: The CMF flag
in RTMCSR is set to 1 by a compare match output when the RTCOR and RTCNT values match.
The compare match signal is generated in the last state in which the values match (when RTCNT
is updated from the matching value to a new value). Accordingly, when RTCNT and RTCOR
match, the compare match signal is not generated until the next counter clock pulse. Figure 6.36
shows the timing.
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φ
RTCNT
N
H'00
N
RTCOR
Compare match
signal
CMF
Figure 6.36 Timing of CMF Flag Setting
Operation in Power-Down State: The interval timer operates in sleep mode. It does not operate
in hardware standby mode. In software standby mode, RTCNT and RTMCSR bits 7 and 6 are
initialized, but RTMCSR bits 5 to 3 and RTCOR retain their settings prior to the transition to
software standby mode.
Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the
T3 state of an RTCNT write cycle, clearing of the counter takes priority and the write is not
performed. See figure 6.37.
T1
T2
T3
φ
Address bus
RTCNT address
Internal write signal
Counter clear signal
RTCNT
N
H'00
Figure 6.37 Contention between RTCNT Write and Clear
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Contention between RTCNT Write and Increment: If an increment pulse occurs in the T3 state
of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 6.38.
T1
T2
T3
φ
Address bus
RTCNT address
Internal write signal
RTCNT input clock
RTCNT
N
M
Counter write data
Figure 6.38 Contention between RTCNT Write and Increment
Contention between RTCOR Write and Compare Match: If a compare match occurs in the T3
state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited.
See figure 6.39.
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T1
T2
T3
φ
Address bus
RTCOR address
Internal write signal
RTCNT
N
N+1
RTCOR
N
M
RTCOR write data
Compare match signal
Inhibited
Figure 6.39 Contention between RTCOR Write and Compare Match
RTCNT Operation at Internal Clock Source Switchover: Switching internal clock sources may
cause RTCNT to increment, depending on the switchover timing. Table 6.10 shows the relation
between the time of the switchover (by writing to bits CKS2 to CKS0) and the operation of
RTCNT.
The RTCNT input clock is generated from the internal clock source by detecting the falling edge
of the internal clock. If a switchover is made from a high clock source to a low clock source, as in
case No. 3 in table 6.10, the switchover will be regarded as a falling edge, an RTCNT clock pulse
will be generated, and RTCNT will be incremented.
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Table 6.10 Internal Clock Switchover and RTCNT Operation
No.
1
CKS2 to CKS0
Write Timing
Low
Low
switchover*1
RTCNT Operation
Old clock source
New clock source
RTCNT clock
RTCNT
N
N+1
CKS bits rewritten
2
Low
High
switchover*2
Old clock source
New clock source
RTCNT clock
RTCNT
N
N+1
N+2
CKS bits rewritten
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No.
3
CKS2 to CKS0
Write Timing
High
Low
switchover*3
RTCNT Operation
Old clock source
New clock source
*4
RTCNT clock
RTCNT
N
N+1
N+2
CKS bits rewritten
4
High
High
switchover*4
Old clock source
New clock source
RTCNT clock
RTCNT
N
N+1
N+2
CKS bits rewritten
Notes: 1. Including switchovers from a low clock source to the halted state, and from the halted
state to a low clock source.
2. Including switchover from the halted state to a high clock source.
3. Including switchover from a high clock source to the halted state.
4. The switchover is regarded as a falling edge, causing RTCNT to increment.
6.7
Interrupt Sources
Compare match interrupts (CMI) can be generated when the refresh timer is used as an interval
timer. Compare match interrupt requests are masked/unmasked with the CMIE bit in RTMCSR.
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6.8
Burst ROM Interface
6.8.1
Overview
With the H8/3006 and H8/3007, external space area 0 can be designated as burst ROM space, and
burst ROM space interfacing can be performed. The burst ROM interface enables ROM with burst
access capability to be accessed at high speed. Area 0 is designated as burst ROM space by means
of the BROME bit in BCR.
Continuous burst access of a maximum or four or eight words can be performed on external space
area 0. Two or three states can be selected for burst access.
6.8.2
Basic Timing
The number of states in the initial cycle (full access) and a burst cycle of the burst ROM interface
is determined by the setting of the AST0 bit in ASTCR. When the AST0 bit is set to 1, wait states
can also be inserted in the initial cycle. Wait states cannot be inserted in a burst cycle.
Burst access of up to four words is performed when the BRSTS0 bit is cleared to 0 in BCR, and
burst access of up to eight words when the BRSTS0 bit is set to 1. The number of burst access
states is two when the BRSTS1 bit is cleared to 0, and three when the BRSTS1 bit is set to 1.
The basic access timing for burst ROM space is shown in figure 6.40.
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Full access
T1
T2
Burst access
T3
T1
T2
T1
T2
φ
Address bus
Only lower address changes
CS0
AS
RD
Data bus
Read data
Read data
Read data
Figure 6.40 Example of Burst ROM Access Timing
6.8.3
Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface.
Wait states cannot be inserted in a burst cycle.
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6. Bus Controller
6.9
Idle Cycle
6.9.1
Operation
When the H8/3006 and H8/3007 chip accesses external space, it can insert a 1-state idle cycle (TI)
between bus cycles in the following cases: (1) when read accesses between different areas occur
consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when external
address space other than DRAM space is accessed immediately after a DRAM space access. By
inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, which
has a long output floating time, and high-speed memory, I/O interfaces, and so on.
The ICIS1 and ICIS0 bits in BCR both have an initial value of 1, so that an idle cycle is inserted in
the initial state. If there are no data collisions, the ICIS bits can be cleared.
Consecutive Reads between Different Areas: If consecutive reads between different areas occur
while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.41 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Bus cycle A Bus cycle B
φ
T1
T2
T3
T1
T2
Bus cycle A Bus cycle B
φ
Address bus
Address bus
RD
RD
Data bus
Data bus
Data collision
Long buffer-off time
(a) Idle cycle not inserted
T1
T2
T3
Ti T1
T2
(b) Idle cycle inserted
Figure 6.41 Example of Idle Cycle Operation (1) (ICIS1 = 1)
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.
Figure 6.42 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
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6. Bus Controller
In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from
ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A Bus cycle B
φ
T1
T2
T3
T1
T2
Bus cycle A Bus cycle B
φ
T1
T2
T3
Ti T1
T2
Address bus
Address bus
RD
RD
HWR
HWR
Data bus
Data bus
Long buffer-off time
(a) Idle cycle not inserted
Data collision
(b) Idle cycle inserted
Figure 6.42 Example of Idle Cycle Operation (2) (ICIS0 = 1)
External Address Space Access Immediately after DRAM Space Access: If a DRAM space
access is followed by a non-DRAM external access when HWR and LWR have been selected as
the UCAS and LCAS output pins by means of the CSEL bit in DRCRB, a Ti cycle is inserted
regardless of the settings of bits ICIS0 and ICIS1 in BCR. Figure 6.43 shows an example of the
operation.
This is done to prevent simultaneous changing of the HWR and LWR signals used as UCAS and
LCAS in DRAM space and CSn for the space in the next cycle, and so avoid an erroneous write to
the external device in the next cycle.
A Ti cycle is not inserted when PB4 and PB5 have been selected as the UCAS and LCAS output
pins.
In the case of consecutive DRAM space access precharge cycles (Tp), the ICIS0 and ICIS1 bit
settings are invalid. In the case of consecutive reads between different areas, for example, if the
second access is a DRAM access, only a Tp cycle is inserted, and a Ti cycle is not. The timing in
this case is shown in figure 6.44.
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Bus cycle A
(DRAM access cycle) Bus cycle B
φ
Tp
Tr
Tc1 Tc2
T1
Bus cycle A
(DRAM access cycle) Bus cycle B
T2
φ
Address bus
Address bus
HWR/LWR
(UCAS/LCAS)
HWR/LWR
(UCAS/LCAS)
CSn
CSn
Tp
Tr
Tc1 Tc2
Ti
T1
T2
Simultaneous change of
HWR/LWR and CSn
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.43 Example of Idle Cycle Operation (3) (HWR/LWR Used as UCAS/LCAS)
External read
T1
T2
T3
DRAM space read
Tp
Tr
Tc1
Tc2
φ
Address bus
RD
UCAS/LCAS
Address bus
Figure 6.44 Example of Idle Cycle Operation (4) (Consecutive Precharge Cycles)
Usage Notes: When non-insertion of idle cycles is set, the rise (negation) of RD and the fall
(assertion) of CSn may occur simultaneously. An example of the operation is shown in figure
6.45.
If consecutive reads between different external areas occur while the ICIS1 bit is cleared to 0 in
BCR, or if a write cycle to a different external area occurs after an external read while the ICIS0
bit is cleared to 0, the RD negation in the first read cycle and the CSn assertion in the following
bus cycle will occur simultaneously. Therefore, depending on the output delay time of each signal,
it is possible that the low-level output of RD in the preceding read cycle and the low-level output
of CSn in the following bus cycle will overlap.
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A setting whereby idle cycle insertion is not performed can be made only when RD and CSn do
not change simultaneously, or when it does not matter if they do.
Bus cycle A
φ
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
φ
Address bus
Address bus
RD
RD
CSn
CSn
T1
T2
T3
Bus cycle B
Ti
T1
T2
Simultaneous change of RD and CSn
Possibility of mutual overlap
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.45 Example of Idle Cycle Operation (5)
6.9.2
Pin States in Idle Cycle
Table 6.11 shows the pin states in an idle cycle.
Table 6.11 Pin States in Idle Cycle
Pins
Pin State
A23 to A0
Next cycle address value
D15 to D0
High impedance
CSn
High*
UCAS, LCAS
High
AS
High
RD
High
HWR
High
LWR
Note:
High
*
Remains low in DRAM space RAS down mode.
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6.10
Bus Arbiter
The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are
four bus masters: the CPU, DMA controller (DMAC), DRAM interface, and an external bus
master. When a bus master has the bus right it can carry out read, write, or refresh access. Each
bus master uses a bus request signal to request the bus right. At fixed times the bus arbiter
determines priority and uses a bus acknowledge signal to grant the bus to a bus master, which can
the operate using the bus.
The bus arbiter checks whether the bus request signal from a bus master is active or inactive, and
returns an acknowledge signal to the bus master. When two or more bus masters request the bus,
the highest-priority bus master receives an acknowledge signal. The bus master that receives an
acknowledge signal can continue to use the bus until the acknowledge signal is deactivated.
The bus master priority order is:
(High)
External bus master > DRAM interface > DMAC > CPU
(Low)
The bus arbiter samples the bus request signals and determines priority at all times, but it does not
always grant the bus immediately, even when it receives a bus request from a bus master with
higher priority than the current bus master. Each bus master has certain times at which it can
release the bus to a higher-priority bus master.
6.10.1
Operation
CPU: The CPU is the lowest-priority bus master. If the DMAC, DRAM interface, or an external
bus master requests the bus while the CPU has the bus right, the bus arbiter transfers the bus right
to the bus master that requested it. The bus right is transferred at the following times:
• The bus right is transferred at the boundary of a bus cycle. If word data is accessed by two
consecutive byte accesses, however, the bus right is not transferred between the two byte
accesses.
• If another bus master requests the bus while the CPU is performing internal operations, such as
executing a multiply or divide instruction, the bus right is transferred immediately. The CPU
continues its internal operations.
• If another bus master requests the bus while the CPU is in sleep mode, the bus right is
transferred immediately.
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6. Bus Controller
DMAC: When the DMAC receives an activation request, it requests the bus right from the bus
arbiter. If the DMAC is bus master and the DRAM interface or an external bus master requests the
bus, the bus arbiter transfers the bus right from the DMAC to the bus master that requested the
bus. The bus right is transferred at the following times.
The bus right is transferred when the DMAC finishes transferring one byte or one word. A DMAC
transfer cycle consists of a read cycle and a write cycle. The bus right is not transferred between
the read cycle and the write cycle.
There is a priority order among the DMAC channels. For details see section 7.4.9, MultipleChannel Operation.
DRAM Interface: The DRAM interface requests the bus right from the bus arbiter when a refresh
cycle request is issued, and releases the bus at the end of the refresh cycle. For details see section
6.5, DRAM Interface.
External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an
external bus master. The external bus master has highest priority, and requests the bus right from
the bus arbiter y driving the BREQ signal low. Once the external bus master acquires the bus, it
keeps the bus until the BREQ signal goes high. While the bus is released to an external bus
master, the H8/3006 and H8/3007 chip holds the address bus, data bus, bus control signals (AS,
RD, HWR, and LWR), and chip select signals (CSn: n = 7 to 0) in the high-impedance state, and
holds the BACK pin in the low output state.
The bus arbiter samples the BREQ pin at the rise of the system clock (φ). If BREQ is low, the bus
is released to the external bus master at the appropriate opportunity. The BREQ signal should be
held low until the BACK signal goes low.
When the BREQ pin is high in two consecutive samples, the BACK pin is driven high to end the
bus-release cycle.
Figure 6.46 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state access area. There is a minimum interval of three states from when the
BREQ signal goes low until the bus is released.
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6. Bus Controller
CPU cycles
T0
φ
T1
External bus released
High-impedance
Address
Address bus
CPU cycles
T2
High-impedance
Data bus
High-impedance
AS
RD
High-impedance
High
High-impedance
HWR, LWR
BREQ
BACK
Minimum 3 cycles
(1)
(2)
(3)
(4)
(5)
(6)
Figure 6.46 Example of External Bus Master Operation
In the event of contention with a bus request from an external bus master when a transition is
made to software standby mode, the BACK and strobe states may be indeterminate after the
transition to software standby mode (see figure 6.34).
When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before
executing the SLEEP instruction.
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6. Bus Controller
6.11
Register and Pin Input Timing
6.11.1
Register Write Timing
ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR,
WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.47 shows the timing
when an instruction fetched from area 0 changes area 0 from three-state access to two-state access.
T1
T2
T3
T1
T2
T3
T1
T2
φ
Address bus
ASTCR address
3-state access to area 0
2-state access to area 0
Figure 6.47 ASTCR Write Timing
DDR and CSCR Write Timing: Data written to DDR or CSCR for the port corresponding to the
CSn pin to switch between CSn output and generic input takes effect starting from the T3 state of
the DDR write cycle. Figure 6.48 shows the timing when the CS1 pin is changed from generic
input to CS1 output.
T1
T2
T3
φ
Address bus
P8DDR address
CS1
High-impedance
Figure 6.48 DDR Write Timing
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6. Bus Controller
BRCR Write Timing: Data written to BRCR to switch between A23, A22, A21, or A20 output and
generic input or output takes effect starting from the T3 state of the BRCR write cycle. Figure 6.49
shows the timing when a pin is changed from generic input to A23, A22, A21, or A20 output.
T1
T2
T3
φ
Address bus
BRCR address
PA7 to PA4
(A23 to A20)
High-impedance
Figure 6.49 BRCR Write Timing
6.11.2
BREQ Pin Input Timing
After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high
level before BACK goes lows, the bus arbiter may operate incorrectly.
To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If
BREQ is high for too short an interval, the bus arbiter may operate incorrectly.
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7. DMA Controller
Section 7 DMA Controller
7.1
Overview
The H8/3006 and H8/3007 have an on-chip DMA controller (DMAC) that can transfer data on up
to four channels.
When the DMA controller is not used, it can be independently halted to conserve power. For
details see section 19.6, Module Standby Function.
7.1.1
Features
DMAC features are listed below.
• Selection of short address mode or full address mode
Short address mode
⎯ 8-bit source address and 24-bit destination address, or vice versa
⎯ Maximum four channels available
⎯ Selection of I/O mode, idle mode, or repeat mode
Full address mode
⎯ 24-bit source and destination addresses
⎯ Maximum two channels available
⎯ Selection of normal mode or block transfer mode
• Directly addressable 16-Mbyte address space
• Selection of byte or word transfer
• Activation by internal interrupts, external requests, or auto-request (depending on transfer
mode)
⎯ 16-bit integrated timer unit (ITU) compare match/input capture interrupts (×3)
⎯ Serial communication interface (SCI channel 0) transmit-data-empty/receive-data-full
interrupts
⎯ External requests
⎯ Auto-request
⎯ A/D converter conversion-end interrupt
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7. DMA Controller
7.1.2
Block Diagram
Figure 7.1 shows a DMAC block diagram.
Internal address bus
Address buffer
IMIA0
IMIA1
IMIA2
ADI
TXI0
RXI0
DREQ0
DREQ1
TEND0
TEND1
Arithmetic-logic unit
MAR0A
Channel
0A
Control logic
Channel
0
MAR0B
Channel
0B
DTCR0A
Interrupt DEND0A
DEND0B
signals
DEND1A
DEND1B
ETCR0B
Channel
1A
DTCR1A
MAR1B
Channel
1B
Internal data bus
Legend:
DTCR: Data transfer control register
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Figure 7.1 Block Diagram of DMAC
Functional Overview
Table 7.1 gives an overview of the DMAC functions.
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IOAR1A
ETCR1A
Channel
1
Data buffer
7.1.3
IOAR0B
MAR1A
DTCR0B
DTCR1B
IOAR0A
ETCR0A
IOAR1B
ETCR1B
Module data bus
Internal
interrupts
7. DMA Controller
Table 7.1
DMAC Functional Overview
Address
Reg. Length
Transfer Mode
Activation
Short
address
mode
•
I/O mode
•
•
•
Transfers one byte or one word
per request
Increments or decrements the memory
address by 1 or 2
Executes 1 to 65,536 transfers
Idle mode
•
•
Transfers one byte or one word per
request
Holds the memory address fixed
• Executes 1 to 65,536 transfers
Repeat mode
•
•
•
Full
address
mode
•
Auto-request
⎯ Retains the transfer request
internally
⎯ Executes a specified number(1 to
65,536) of transfers continuously
⎯ Selection of burst mode or cyclesteal mode
External request
⎯ Transfers one byte or one word per
request
⎯ Executes 1 to 65,536 transfers
Block transfer
•
•
•
•
Destination
Compare match/input
24
capture A interrupts from
16-bit timer channels 0 to 2
Transmit-data-empty
interrupt from SCI channel 0
8
Conversion-end interrupt
from A/D converter
Receive-data-full interrupt
from SCI channel 0
8
24
•
External request
24
8
•
•
Auto-request
External request
24
24
•
Compare match/ input
capture A interrupts from
16-bit timer channels 0 to 2
External request
Conversion-end interrupt
from A/D converter
24
24
•
•
•
Transfers one byte or one word per
request
Increments or decrements the memory
address by 1 or 2
Executes a specified number (1 to 255)
of transfers, then returns to the initial
state and continues
Normal mode
•
Source
Transfers one block of a specified size
per request
•
Executes 1 to 65,536 transfers
Allows either the source or destination to •
be a fixed block area
Block size can be 1 to 255 bytes or
words
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7. DMA Controller
7.1.4
Pin Configuration
Table 7.2 lists the DMAC pins.
Table 7.2
DMAC Pins
Channel
Name
Abbreviation
Input/
Output
Function
0
DMA request 0
DREQ0
Input
External request for DMAC channel 0
Transfer end 0
TEND0
Output
Transfer end on DMAC channel 0
DMA request 1
DREQ1
Input
External request for DMAC channel 1
Transfer end 1
TEND1
Output
Transfer end on DMAC channel 1
1
Note: External requests cannot be made to channel A in short address mode.
7.1.5
Register Configuration
Table 7.3 lists the DMAC registers.
Table 7.3
DMAC Registers
Channel Address* Name
Abbreviation R/W
Initial Value
0
H'FFF20
Memory address register 0AR
MAR0AR
R/W
Undetermined
H'FFF21
Memory address register 0AE
MAR0AE
R/W
Undetermined
H'FFF22
Memory address register 0AH
MAR0AH
R/W
Undetermined
H'FFF23
Memory address register 0AL
MAR0AL
R/W
Undetermined
H'FFF26
I/O address register 0A
IOAR0A
R/W
Undetermined
H'FFF24
Execute transfer count register 0AH ETCR0AH
R/W
Undetermined
H'FFF25
Execute transfer count register 0AL ETCR0AL
R/W
Undetermined
H'FFF27
Data transfer control register 0A
DTCR0A
R/W
H'00
H'FFF28
Memory address register 0BR
MAR0BR
R/W
Undetermined
H'FFF29
Memory address register 0BE
MAR0BE
R/W
Undetermined
H'FFF2A
Memory address register 0BH
MAR0BH
R/W
Undetermined
H'FFF2B
Memory address register 0BL
MAR0BL
R/W
Undetermined
H'FFF2E
I/O address register 0B
IOAR0B
R/W
Undetermined
H'FFF2C
Execute transfer count register 0BH ETCR0BH
R/W
Undetermined
H'FFF2D
Execute transfer count register 0BL ETCR0BL
R/W
Undetermined
H'FFF2F
Data transfer control register 0B
R/W
H'00
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DTCR0B
7. DMA Controller
Channel Address* Name
Abbreviation R/W
Initial Value
1
Note:
H'FFF30
Memory address register 1AR
MAR1AR
R/W
Undetermined
H'FFF31
Memory address register 1AE
MAR1AE
R/W
Undetermined
H'FFF32
Memory address register 1AH
MAR1AH
R/W
Undetermined
H'FFF33
Memory address register 1AL
MAR1AL
R/W
Undetermined
H'FFF36
I/O address register 1A
IOAR1A
R/W
Undetermined
H'FFF34
Execute transfer count register 1AH ETCR1AH
R/W
Undetermined
H'FFF35
Execute transfer count register 1AL ETCR1AL
R/W
Undetermined
H'FFF37
Data transfer control register 1A
DTCR1A
R/W
H'00
H'FFF38
Memory address register 1BR
MAR1BR
R/W
Undetermined
H'FFF39
Memory address register 1BE
MAR1BE
R/W
Undetermined
H'FFF3A
Memory address register 1BH
MAR1BH
R/W
Undetermined
H'FFF3B
Memory address register 1BL
MAR1BL
R/W
Undetermined
H'FFF3E
I/O address register 1B
IOAR1B
R/W
Undetermined
H'FFF3C
Execute transfer count register 1BH ETCR1BH
R/W
Undetermined
H'FFF3D
Execute transfer count register 1BL ETCR1BL
R/W
Undetermined
H'FFF3F
Data transfer control register 1B
R/W
H'00
The lower 20 bits of the address are indicated.
*
7.2
DTCR1B
Register Descriptions (1) (Short Address Mode)
In short address mode, transfers can be carried out independently on channels A and B. Short
address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA)
as indicated in table 7.4.
Table 7.4
Selection of Short and Full Address Modes
Bit 2
Channel DTS2A
Bit 1
DTS1A
Description
0
1
DMAC channel 0 operates as one channel in full address mode
1
1
Other than above
DMAC channels 0A and 0B operate as two independent channels
in short address mode
1
DMAC channel 1 operates as one channel in full address mode
1
Other than above
DMAC channels 1A and 1B operate as two independent channels
in short address mode
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7. DMA Controller
7.2.1
Memory Address Registers (MAR)
A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or
destination address. The transfer direction is determined automatically from the activation source.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved; they cannot be modified and are always read as 1.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Initial value 1
1
1
1
1
1
1
1
Read/Write ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
7
6
5
4
3
2
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MARR
MARE
MARH
MARL
Source or destination address
An MAR functions as a source or destination address register depending on how the DMAC is
activated: as a destination address register if activation is by a receive-data-full interrupt from the
serial communication interface (SCI) (channel 0) or by a conversion-end interrupt from the A/D
converter, and as a source address register otherwise.
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 7.3.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
7.2.2
I/O Address Registers (IOAR)
An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or
destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits
are all 1 (H'FFFF).
Bit
7
6
5
3
2
1
0
R/W
R/W
R/W
Undetermined
Initial value
Read/Write
4
R/W
R/W
R/W
R/W
R/W
Source or destination address
An IOAR functions as a source or destination address register depending on how the DMAC is
activated: as a source address register if activation is by a receive-data-full interrupt from the SCI
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7. DMA Controller
(channel 0) or by a conversion-end interrupt from the A/D converter, and as a destination address
register otherwise.
The IOAR value is held fixed. It is not incremented or decremented when a transfer is executed.
The IOARs are not initialized by a reset or in standby mode.
7.2.3
Execute Transfer Count Registers (ETCR)
An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the
number of transfers to be executed. These registers function in one way in I/O mode and idle
mode, and another way in repeat mode.
I/O mode and idle mode
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transfer counter
In I/O mode and idle mode, ETCR functions as a 16-bit counter. The count is decremented by
1 each time one transfer is executed. The transfer ends when the count reaches H'0000.
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7. DMA Controller
Repeat mode
Bit
7
6
5
Initial value
Read/Write
4
3
2
1
0
R/W
R/W
R/W
2
1
0
R/W
R/W
R/W
Undetermined
R/W
R/W
R/W
R/W
R/W
ETCRH
Transfer counter
Bit
7
6
5
R/W
R/W
R/W
Initial value
Read/Write
4
3
Undetermined
R/W
R/W
ETCRL
Initial count
In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial transfer
count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH reaches
H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated.
The ETCRs are not initialized by a reset or in standby mode.
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7. DMA Controller
7.2.4
Data Transfer Control Registers (DTCR)
A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the
operation of one DMAC channel.
Bit
7
6
5
4
3
2
1
0
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTS1
DTS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data transfer enable
Enables or disables
data transfer
Data transfer select
These bits select the data
transfer activation source
Data transfer size
Selects byte or
word size
Data transfer interrupt enable
Enables or disables the CPU interrupt
at the end of the transfer
Data transfer
increment/decrement
Selects whether to
increment or decrement
the memory address
register
Repeat enable
Selects repeat
mode
The DTCRs are initialized to H'00 by a reset and in standby mode.
Bit 7⎯Data Transfer Enable (DTE): Enables or disables data transfer on a channel. When the
DTE bit is set to 1, the channel waits for a transfer to be requested, and executes the transfer when
activated as specified by bits DTS2 to DTS0. When DTE is 0, the channel is disabled and does not
accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1.
Bit 7
DTE
Description
0
Data transfer is disabled. In I/O mode or idle mode, DTE is cleared to 0
when the specified number of transfers have been completed
1
Data transfer is enabled
(Initial value)
If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0.
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7. DMA Controller
Bit 6⎯Data Transfer Size (DTSZ): Selects the data size of each transfer.
Bit 6
DTSZ
Description
0
Byte-size transfer
1
Word-size transfer
(Initial value)
Bit 5⎯Data Transfer Increment/Decrement (DTID): Selects whether to increment or
decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode.
Bit 5
DTID
Description
0
MAR is incremented after each data transfer
1
•
If DTSZ = 0, MAR is incremented by 1 after each transfer
•
If DTSZ = 1, MAR is incremented by 2 after each transfer
MAR is decremented after each data transfer
•
If DTSZ = 0, MAR is decremented by 1 after each transfer
•
If DTSZ = 1, MAR is decremented by 2 after each transfer
MAR is not incremented or decremented in idle mode.
Bit 4⎯Repeat Enable (RPE): Selects whether to transfer data in I/O mode, idle mode, or repeat
mode.
Bit 4
RPE
Bit 3
DTIE
Description
0
0
I/O mode
(Initial value)
1
1
0
Repeat mode
1
Idle mode
Operations in these modes are described in sections 7.4.2, I/O Mode, 7.4.3, Idle Mode, and 7.4.4,
Repeat Mode.
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7. DMA Controller
Bit 3⎯Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bit 3
DTIE
Description
0
The DEND interrupt requested by DTE is disabled
1
The DEND interrupt requested by DTE is enabled
(Initial value)
Bits 2 to 0⎯Data Transfer Select (DTS2 to DTS0): These bits select the data transfer activation
source. Some of the selectable sources differ between channels A and B.*
Note: * See section 7.3.4, Data Transfer Control Registers (DTCR).
Bit 2
DTS2
Bit 1
DTS1
Bit 0
DTS0
0
0
0
1
Compare match/input capture A interrupt from 16-bit timer channel 1
1
0
Compare match/input capture A interrupt from 16-bit timer channel 2
1
Conversion-end interrupt from A/D converter
0
Transmit-data-empty interrupt from SCI channel 0
1
Receive-data-full interrupt from SCI channel 0
0
Falling edge of DREQ input (channel B)
Transfer in full address mode (channel A)
1
Low level of DREQ input (channel B)
Transfer in full address mode (channel A)
1
0
1
Description
Compare match/input capture A interrupt from 16-bit timer channel 0
(Initial value)
The same internal interrupt can be selected as an activation source for two or more channels at
once. In that case the channels are activated in a priority order, highest-priority channel first. For
the priority order, see section 7.4.9, Multiple-Channel Operation.
When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a
CPU interrupt.
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7. DMA Controller
7.3
Register Descriptions (2) (Full Address Mode)
In full address mode the A and B channels operate together. Full address mode is selected as
indicated in table 7.4.
7.3.1
Memory Address Registers (MAR)
A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the
source address register of the transfer, and MARB as the destination address register.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved; they cannot be modified and are always read as 1. (Write is invalid.)
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Initial value 1
1
1
1
1
1
1
1
Read/Write ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
MARR
8
7
6
5
4
3
2
1
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MARE
MARH
MARL
Source or destination address
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 7.3.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
7.3.2
0
I/O Address Registers (IOAR)
The I/O address registers (IOARs) are not used in full address mode.
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7. DMA Controller
7.3.3
Execute Transfer Count Registers (ETCR)
An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the
number of transfers to be executed. The functions of these registers differ between normal mode
and block transfer mode.
Normal mode
• ETCRA
15
Bit
14
13
12
10
11
9
8
6
7
5
4
3
2
1
0
Initial value
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transfer counter
• ETCRB: Is not used in normal mode.
In normal mode ETCRA functions as a 16-bit transfer counter. The count is decremented by 1
each time one transfer is executed. The transfer ends when the count reaches H'0000. ETCRB
is not used.
Block transfer mode
• ETCRA
Bit
7
6
5
R/W
R/W
R/W
Initial value
Read/Write
4
3
2
1
0
R/W
R/W
R/W
2
1
0
R/W
R/W
R/W
Undetermined
R/W
R/W
ETCRAH
Block size counter
Bit
7
6
5
R/W
R/W
R/W
Initial value
Read/Write
4
3
Undetermined
R/W
R/W
ETCRAL
Initial block size
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7. DMA Controller
• ETCRB
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Block transfer counter
In block transfer mode, ETCRAH functions as an 8-bit block size counter. ETCRAL holds the
initial block size. ETCRAH is decremented by 1 each time one byte or word is transferred.
When the count reaches H'00, ETCRAH is reloaded from ETCRAL. Blocks consisting of an
arbitrary number of bytes or words can be transferred repeatedly by setting the same initial
block size value in ETCRAH and ETCRAL.
In block transfer mode ETCRB functions as a 16-bit block transfer counter. ETCRB is
decremented by 1 each time one block is transferred. The transfer ends when the count reaches
H'0000.
The ETCRs are not initialized by a reset or in standby mode.
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7. DMA Controller
7.3.4
Data Transfer Control Registers (DTCR)
The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the
operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and
DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address
mode.
DTCRA
Bit
7
6
5
4
3
2
1
0
DTE
DTSZ
SAID
SAIDE
DTIE
DTS2A
DTS1A
DTS0A
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data transfer enable
Enables or disables
data transfer
Data transfer size
Selects byte or
word size
Data transfer
interrupt enable
Enables or disables the
CPU interrupt at the end
of the transfer
Source address
increment/decrement
Source address increment/
decrement enable
These bits select whether
the source address register
(MARA) is incremented,
decremented, or held fixed
during the data transfer
Data transfer
select 0A
Selects block
transfer mode
Data transfer select
2A and 1A
These bits must both be
set to 1
DTCRA is initialized to H'00 by a reset and in standby mode.
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7. DMA Controller
Bit 7⎯Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables
or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the
channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the
channel waits for transfers to be requested. When the specified number of transfers have been
completed, the DTE bit is automatically cleared to 0. When DTE is 0, the channel is disabled and
does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then
writing 1.
Bit 7
DTE
Description
0
Data transfer is disabled (DTE is cleared to 0 when the specified number (Initial value)
of transfers have been completed)
1
Data transfer is enabled
If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0.
Bit 6⎯Data Transfer Size (DTSZ): Selects the data size of each transfer.
Bit 6
DTSZ
Description
0
Byte-size transfer
1
Word-size transfer
(Initial value)
Bit 5⎯Source Address Increment/Decrement (SAID) and,
Bit 4⎯Source Address Increment/Decrement Enable (SAIDE): These bits select whether the
source address register (MARA) is incremented, decremented, or held fixed during the data
transfer.
Bit 5
SAID
Bit 4
SAIDE
0
0
MARA is held fixed
1
MARA is incremented after each data transfer
1
Description
•
If DTSZ = 0, MARA is incremented by 1 after each transfer
•
If DTSZ = 1, MARA is incremented by 2 after each transfer
0
MARA is held fixed
1
MARA is decremented after each data transfer
(Initial value)
•
If DTSZ = 0, MARA is decremented by 1 after each transfer
•
If DTSZ = 1, MARA is decremented by 2 after each transfer
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7. DMA Controller
Bit 3⎯Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bit 3
DTIE
Description
0
The DEND interrupt requested by DTE is disabled
1
The DEND interrupt requested by DTE is enabled
(Initial value)
Bits 2 and 1⎯Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full
address mode when DTS2A and DTS1A are both set to 1.
Bit 0⎯Data Transfer Select 0A (DTS0A): Selects normal mode or block transfer mode.
Bit 0
DTS0A
Description
0
Normal mode
1
Block transfer mode
(Initial value)
Operations in these modes are described in sections 7.4.5, Normal Mode, and 7.4.6, Block
Transfer Mode.
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7. DMA Controller
DTCRB
Bit
7
6
5
4
3
2
1
0
DTME
⎯
DAID
DAIDE
TMS
DTS2B
DTS1B
DTS0B
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data transfer master enable
Enables or disables data
transfer, together with
the DTE bit, and is cleared
to 0 by an interrupt
Reserved bit
Transfer mode select
Selects whether the
block area is the source
or destination in block
transfer mode
Destination address
increment/decrement
Destination address
increment/decrement enable
These bits select whether
the destination address
register (MARB) is incremented,
decremented, or held fixed
during the data transfer
Data transfer select
2B to 0B
These bits select the data
transfer activation source
DTCRB is initialized to H'00 by a reset and in standby mode.
Bit 7⎯Data Transfer Master Enable (DTME): Together with the DTE bit in DTCRA, this bit
enables or disables data transfer. When the DTME and DTE bits are both set to 1, the channel is
enabled. When an NMI interrupt occurs DTME is cleared to 0, suspending the transfer so that the
CPU can use the bus. The suspended transfer resumes when DTME is set to 1 again. For further
information on operation in block transfer mode, see section 7.6.6, NMI Interrupts and Block
Transfer Mode.
DTME is set to 1 by reading the register while DTME = 0, then writing 1.
Bit 7
DTME
Description
0
Data transfer is disabled (DTME is cleared to 0 when an NMI interrupt
occurs)
1
Data transfer is enabled
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(Initial value)
7. DMA Controller
Bit 6⎯Reserved: Although reserved, this bit can be written and read.
Bit 5⎯Destination Address Increment/Decrement (DAID) and,
Bit 4⎯Destination Address Increment/Decrement Enable (DAIDE): These bits select whether
the destination address register (MARB) is incremented, decremented, or held fixed during the
data transfer.
Bit 5
DAID
Bit 4
DAIDE
Description
0
0
MARB is held fixed
1
MARB is incremented after each data transfer
1
(Initial value)
•
If DTSZ = 0, MARB is incremented by 1 after each data transfer
•
If DTSZ = 1, MARB is incremented by 2 after each data transfer
0
MARB is held fixed
1
MARB is decremented after each data transfer
•
If DTSZ = 0, MARB is decremented by 1 after each data transfer
•
If DTSZ = 1, MARB is decremented by 2 after each data transfer
Bit 3⎯Transfer Mode Select (TMS): Selects whether the source or destination is the block area
in block transfer mode.
Bit 3
TMS
Description
0
Destination is the block area in block transfer mode
1
Source is the block area in block transfer mode
(Initial value)
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7. DMA Controller
Bits 2 to 0⎯Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the
data transfer activation source. The selectable activation sources differ between normal mode and
block transfer mode.
Normal mode
Bit 2
DTS2B
Bit 1
DTS1B
Bit 0
DTS0B
Description
0
0
0
Auto-request (burst mode)
1
Cannot be used
0
Auto-request (cycle-steal mode)
1
Cannot be used
0
Cannot be used
1
Cannot be used
0
Falling edge of DREQ
1
Low level input at DREQ
1
1
0
1
(Initial value)
Block transfer mode
Bit 2
DTS2B
Bit 1
DTS1B
Bit 0
DTS0B
0
0
0
Compare match/input capture A interrupt from 16-bit timer channel 0
(Initial value)
1
Compare match/input capture A interrupt from 16-bit timer channel 1
1
0
Compare match/input capture A interrupt from 16-bit timer channel 2
1
Conversion-end interrupt from A/D converter
0
0
Cannot be used
1
Cannot be used
0
Falling edge of DREQ
1
Cannot be used
1
1
Description
The same internal interrupt can be selected to activate two or more channels. The channels are
activated in a priority order, highest priority first. For the priority order, see section 7.4.9,
Multiple-Channel Operation.
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7. DMA Controller
7.4
Operation
7.4.1
Overview
Table 7.5 summarizes the DMAC modes.
Table 7.5
DMAC Modes
Transfer Mode
Short address
mode
I/O mode
Idle mode
Repeat mode
Activation
Notes
Compare match/input
capture A interrupt from
16-bit timer channels 0 to 2
•
Up to four channels
can operate
independently
Transmit-data-empty
and receive-data-full
interrupts from SCI
channel 0
•
Only the B channels
support external requests
•
A and B channels are
paired; up to two
channels are available
•
Burst mode transfer or
cycle-steal mode transfer
can be selected for
autorequests.
Conversion-end interrupt
from A/D converter
External request
Full address
mode
Normal mode
Auto-request
External request
Block transfer mode
Compare match/input
capture A interrupt from
ITU channels 0 to 2
Conversion-end interrupt
from A/D converter
External request
A summary of operations in these modes follows.
I/O Mode: One byte or word is transferred per request. A designated number of these transfers are
executed. A CPU interrupt can be requested at completion of the designated number of transfers.
One 24-bit address and one 8-bit address are specified. The transfer direction is determined
automatically from the activation source.
Idle Mode: One byte or word is transferred per request. A designated number of these transfers
are executed. A CPU interrupt can be requested at completion of the designated number of
transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed. The
transfer direction is determined automatically from the activation source.
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7. DMA Controller
Repeat Mode: One byte or word is transferred per request. A designated number of these transfers
are executed. When the designated number of transfers are completed, the initial address and
counter value are restored and operation continues. No CPU interrupt is requested. One 24-bit
address and one 8-bit address are specified. The transfer direction is determined automatically
from the activation source.
Normal Mode
• Auto-request
The DMAC is activated by register setup alone, and continues executing transfers until the
designated number of transfers have been completed. A CPU interrupt can be requested at
completion of the transfers. Both addresses are 24-bit addresses.
⎯ Cycle-steal mode
The bus is released to another bus master after each byte or word is transferred.
⎯ Burst mode
Unless requested by a higher-priority bus master, the bus is not released until the
designated number of transfers have been completed.
• External request
One byte or word is transferred per request. A designated number of these transfers are
executed. A CPU interrupt can be requested at completion of the designated number of
transfers. Both addresses are 24-bit addresses.
Block Transfer Mode: One block of a specified size is transferred per request. A designated
number of block transfers are executed. At the end of each block transfer, one address is restored
to its initial value. When the designated number of blocks have been transferred, a CPU interrupt
can be requested. Both addresses are 24-bit addresses.
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7. DMA Controller
7.4.2
I/O Mode
I/O mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in I/O mode. A designated number of these
transfers are executed. One address is specified in the memory address register (MAR), the other
in the I/O address register (IOAR). The direction of transfer is determined automatically from the
activation source. The transfer is from the address specified in IOAR to the address specified in
MAR if activated by an SCI channel 0 receive-data-full interrupt or an A/D converter conversion
end interrupt, and from the address specified in MAR to the address specified in IOAR otherwise.
Table 7.6 indicates the register functions in I/O mode.
Table 7.6
Register Functions in I/O Mode
Function
Activated by
SCI0 ReceiveData-Full
Interrupt or
A/D Converter
Conversion
Other
End Interrupt Activation
Register
23
7
All 1s
Destination
address
register
Source
address
register
Destination or
Incremented or
source address decremented
once per
transfer
0
Source
address
register
Destination
address
register
Source or
destination
address
Held fixed
0
Transfer counter
Number of
transfers
Decremented
once per
transfer until
H'0000 is
reached and
transfer ends
IOAR
15
Operation
0
MAR
23
Initial Setting
ETCR
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address, which is incremented or decremented as each byte or word is transferred.
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7. DMA Controller
IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not
incremented or decremented.
Figure 7.2 illustrates how I/O mode operates.
Transfer
Address T
IOAR
1 byte or word is
transferred per request
Address B
Legend:
L = initial setting of MAR
N = initial setting of ETCR
Address T = L
Address B = L + (−1) DTID • (2DTSZ • N − 1)
Figure 7.2 Operation in I/O Mode
The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at
each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared and the transfer ends.
If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer count
is 65,536, obtained by setting ETCR to H'0000.
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7. DMA Controller
Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit
timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0,
conversion-end interrupts from the A/D converter, and external request signals.
For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR).
Figure 7.3 shows a sample setup procedure for I/O mode.
I/O mode setup
Set source and
destination addresses
1
Set transfer count
2
Read DTCR
3
Set DTCR
4
1. Set the source and destination addresses
in MAR and IOAR. The transfer direction is
determined automatically from the activation
source.
2. Set the transfer count in ETCR.
3. Read DTCR while the DTE bit is cleared to 0.
4. Set the DTCR bits as follows.
• Select the DMAC activation source with bits
DTS2 to DTS0.
• Set or clear the DTIE bit to enable or disable
the CPU interrupt at the end of the transfer.
• Clear the RPE bit to 0 to select I/O mode.
• Select MAR increment or decrement with the
DTID bit.
• Select byte size or word size with the DTSZ bit.
• Set the DTE bit to 1 to enable the transfer.
I/O mode
Figure 7.3 I/O Mode Setup Procedure (Example)
7.4.3
Idle Mode
Idle mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in idle mode. A designated number of
these transfers are executed. One address is specified in the memory address register (MAR), the
other in the I/O address register (IOAR). The direction of transfer is determined automatically
from the activation source. The transfer is from the address specified in IOAR to the address
specified in MAR if activated by an SCI channel 0 receive-data-full interrupt or an A/D converter
conversion end interrupt, and from the address specified in MAR to the address specified in IOAR
otherwise.
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7. DMA Controller
Table 7.7 indicates the register functions in idle mode.
Table 7.7
Register Functions in Idle Mode
Function
Activated by
SCI0 ReceiveData-Full
Interrupt or
A/D Converter
Conversion
Other
End Interrupt Activation
Register
23
7
All 1s
Destination
address
register
Source
address
register
Destination or
Held fixed
source address
0
Source
address
register
Destination
address
register
Source or
destination
address
Held fixed
0
Transfer counter
Number of
transfers
Decremented
once per
transfer until
H'0000 is
reached and
transfer ends
IOAR
15
Operation
0
MAR
23
Initial Setting
ETCR
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all
1s. MAR and IOAR are not incremented or decremented.
Figure 7.4 illustrates how idle mode operates.
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7. DMA Controller
MAR
Transfer
IOAR
1 byte or word is
transferred per request
Figure 7.4 Operation in Idle Mode
The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at
each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends, and
a CPU interrupt is requested. The maximum transfer count is 65,536, obtained by setting ETCR to
H'0000.
Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit
timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0,
conversion-end interrupts from the A/D converter, and external request signals.
For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR).
Figure 7.5 shows a sample setup procedure for idle mode.
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7. DMA Controller
Idle mode setup
Set source and
destination addresses
1
Set transfer count
2
Read DTCR
3
Set DTCR
4
1. Set the source and destination addresses
in MAR and IOAR. The transfer direction is determined automatically from the activation source.
2. Set the transfer count in ETCR.
3. Read DTCR while the DTE bit is cleared to 0.
4. Set the DTCR bits as follows.
• Select the DMAC activation source with bits
DTS2 to DTS0.
• Set the DTIE and RPE bits to 1 to select idle mode.
• Select byte size or word size with the DTSZ bit.
• Set the DTE bit to 1 to enable the transfer.
Idle mode
Figure 7.5 Idle Mode Setup Procedure (Example)
7.4.4
Repeat Mode
Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable
timing pattern controller (TPC) in synchronization, for example, with 16-bit timer compare match.
Repeat mode can be selected for each channel independently.
One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number
of these transfers are executed. One address is specified in the memory address register (MAR),
the other in the I/O address register (IOAR). At the end of the designated number of transfers,
MAR and ETCRH are restored to their original values and operation continues. The direction of
transfer is determined automatically from the activation source. The transfer is from the address
specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-datafull interrupt or an A/D converter conversion end interrupt, and from the address specified in
MAR to the address specified in IOAR otherwise.
Table 7.8 indicates the register functions in repeat mode.
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7. DMA Controller
Table 7.8
Register Functions in Repeat Mode
Function
Activated by
SCI0 ReceiveData-Full
Interrupt or
A/D Converter
Conversion
Other
End Interrupt Activation
Register
23
7
All 1s
Destination
address
register
Source
address
register
Transfer
destination or
transfer source
start address
Incremented or
decremented at
each transfer
until ETCRH
reaches H'0000,
then restored to
initial value
0
Source
address
register
Destination
address
register
Source or
destination
address
Held fixed
0
Transfer counter
Number of
transfers
Decremented
once per
transfer until
H'0000 is
reached, then
reloaded from
ETCRL
Initial transfer count
Number of
transfers
Held fixed
IOAR
7
ETCRH
7
Operation
0
MAR
23
Initial Setting
0
ETCRL
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer
count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from
ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID
bits in DTCR. Specifically, MAR is restored as follows:
MAR ← MAR − (−1)
DTID
•2
DTSZ
• ETCRL
ETCRH and ETCRL should be initially set to the same value.
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7. DMA Controller
In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0,
if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No
CPU interrupt is requested.
As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a
24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper
16 bits are all 1s. IOAR is not incremented or decremented.
Figure 7.6 illustrates how repeat mode operates.
Transfer
Address T
IOAR
1 byte or word is
transferred per request
Legend:
L = initial setting of MAR
N = initial setting of ETCRH and ETCRL
Address T = L
Address B = L + (−1) DTID • (2DTSZ • N − 1)
Address B
Figure 7.6 Operation in Repeat Mode
The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer
count is 255, obtained by setting both ETCRH and ETCRL to H'FF.
Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit
timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0,
conversion-end interrupts from the A/D converter, and external request signals.
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For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR).
Figure 7.7 shows a sample setup procedure for repeat mode.
Repeat mode
Set source and
destination addresses
1
Set transfer count
2
Read DTCR
3
Set DTCR
4
1. Set the source and destination addresses in MAR
and IOAR. The transfer direction is determined
automatically from the activation source.
2. Set the transfer count in both ETCRH and ETCRL.
3. Read DTCR while the DTE bit is cleared to 0.
4. Set the DTCR bits as follows.
• Select the DMAC activation source with bits
DTS2 to DTS0.
• Clear the DTIE bit to 0 and set the RPE bit to 1
to select repeat mode.
• Select MAR increment or decrement with the DTID bit.
• Select byte size or word size with the DTSZ bit.
• Set the DTE bit to 1 to enable the transfer.
Repeat mode
Figure 7.7 Repeat Mode Setup Procedure (Example)
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7. DMA Controller
7.4.5
Normal Mode
In normal mode, the A and B channels are combined. One byte or word is transferred per request.
A designated number of these transfers are executed. Addresses are specified in MARA and
MARB. Table 7.9 indicates the register functions in I/O mode.
Table 7.9
Register Functions in Normal Mode
Register
Function
Initial Setting
Operation
Incremented or
decremented once per
transfer, or held fixed
MARA
0 Source address
register
Transfer source
start address
MARB
0 Destination
address register
Transfer destination Incremented or
start address
decremented once per
transfer, or held fixed
0 Transfer counter
Number of
transfers
23
23
15
ETCRA
Decremented once per
transfer
Legend:
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Execute transfer count register A
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred.
The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by
1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer
ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer
count is 65,536, obtained by setting ETCRA to H'0000.
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7. DMA Controller
Figure 7.8 illustrates how normal mode operates.
Transfer
Address T A
Address T B
Address BA
Address B B
Legend:
L A = initial setting of MARA
L B = initial setting of MARB
N = initial setting of ETCRA
TA = LA
BA = L A + SAIDE • (−1)SAID • (2 DTSZ • N − 1)
TB = LB
BB = L B + DAIDE • (−1)DAID • (2 DTSZ • N − 1)
Figure 7.8 Operation in Normal Mode
Transfers can be requested (activated) by an external request or auto-request. An auto-requested
transfer is activated by the register settings alone. The designated number of transfers are executed
automatically. Either cycle-steal or burst mode can be selected. In cycle-steal mode, the DMAC
releases the bus temporarily after each transfer. In burst mode, the DMAC keeps the bus until the
transfers are completed, unless there is a bus request from a higher-priority bus master.
For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR).
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7. DMA Controller
Figure 7.9 shows a sample setup procedure for normal mode.
Normal mode
Set initial source address
1
Set initial destination address
2
1.
2.
3.
4.
5.
Set transfer count
3
Set DTCRB (1)
4
Set DTCRA (1)
5
Read DTCRB
6
Set DTCRB (2)
7
Read DTCRA
8
Set DTCRA (2)
9
6.
7.
8.
9.
Set the initial source address in MARA.
Set the initial destination address in MARB.
Set the transfer count in ETCRA.
Set the DTCRB bits as follows.
• Clear the DTME bit to 0.
• Set the DAID and DAIDE bits to select whether
MARB is incremented, decremented, or held fixed.
• Select the DMAC activation source with bits
DTS2B to DTS0B.
Set the DTCRA bits as follows.
• Clear the DTE bit to 0.
• Select byte or word size with the DTSZ bit.
• Set the SAID and SAIDE bits to select whether
MARA is incremented, decremented, or held fixed.
• Set or clear the DTIE bit to enable or disable the
CPU interrupt at the end of the transfer.
• Clear the DTS0A bit to 0 and set the DTS2A
and DTS1A bits to 1 to select normal mode.
Read DTCRB with DTME cleared to 0.
Set the DTME bit to 1 in DTCRB.
Read DTCRA with DTE cleared to 0.
Set the DTE bit to 1 in DTCRA to enable the transfer.
Normal mode
Note: Carry out settings 1 to 9 with the DEND interrupt masked in the CPU.
If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in
which case the transfer will not start.
Figure 7.9 Normal Mode Setup Procedure (Example)
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7. DMA Controller
7.4.6
Block Transfer Mode
In block transfer mode, the A and B channels are combined. One block of a specified size is
transferred per request. A designated number of block transfers are executed. Addresses are
specified in MARA and MARB. The block area address can be either held fixed or cycled.
Table 7.10 indicates the register functions in block transfer mode.
Table 7.10 Register Functions in Block Transfer Mode
Register
23
Function
Initial Setting
Operation
0
Source address
register
Transfer source
start address
Incremented or
decremented once per
transfer, or held fixed
0
Destination
address register
Transfer destination Incremented or
start address
decremented once per
transfer, or held fixed
0
Block size counter
Block size
Decremented once per
transfer until H'00 is
reached, then reloaded
from ETCRL
Initial block size
Block size
Held fixed
Block transfer
counter
Number of block
transfers
Decremented once per
block transfer until H'0000
is reached and the
transfer ends
MARA
23
MARB
7
ETCRAH
7
0
ETCRAL
15
0
ETCRB
Legend:
MARA:
MARB:
ETCRA:
ETCRB:
Memory address register A
Memory address register B
Execute transfer count register A
Execute transfer count register B
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred. One of these registers operates as a
block area register: even if it is incremented or decremented, it is restored to its initial value at the
end of each block transfer. The TMS bit in DTCRB selects whether the block area is the source or
destination.
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7. DMA Controller
If M (1 to 255) is the size of the block transferred at each request and N (1 to 65,536) is the
number of blocks to be transferred, then ETCRAH and ETCRAL should initially be set to M and
ETCRB should initially be set to N.
Figure 7.10 illustrates how block transfer mode operates. In this figure, bit TMS is cleared to 0,
meaning the block area is the destination.
TA
Address T B
Transfer
Block 1
Block area
BA
Address B B
Block 2
M bytes or words are
transferred per request
Block N
Legend:
L A = initial setting of MARA
L B = initial setting of MARB
M = initial setting of ETCRAH and ETCRAL
N = initial setting of ETCRB
T A = LA
B A = L A + SAIDE • (−1)SAID • (2 DTSZ • M − 1)
T B = LB
B B = L B + DAIDE • (−1)DAID • (2 DTSZ • M − 1)
Figure 7.10 Operation in Block Transfer Mode
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7. DMA Controller
When activated by a transfer request, the DMAC executes a burst transfer. During the transfer
MARA and MARB are updated according to the DTCR settings, and ETCRAH is decremented.
When ETCRAH reaches H'00, it is reloaded from ETCRAL to restore the initial value. The
memory address register of the block area is also restored to its initial value, and ETCRB is
decremented. If ETCRB is not H'0000, the DMAC then waits for the next transfer request.
ETCRAH and ETCRAL should be initially set to the same value.
The above operation is repeated until ETCRB reaches H'0000, at which point the DTE bit is
cleared to 0 and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this
time.
Figure 7.11 shows examples of a block transfer with byte data size when the block area is the
destination. In (a), the block area address is cycled. In (b), the block area address is held fixed.
Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit
timer channels 0 to 2, by a conversion-end interrupt from the A/D converter, and by external
request signals.
For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR).
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7. DMA Controller
Start
(DTE = DTME = 1)
Transfer requested?
Start
(DTE = DTME = 1)
No
Transfer requested?
Yes
No
Yes
Get bus
Get bus
Read from MARA address
Read from MARA address
MARA = MARA + 1
MARA = MARA + 1
Write to MARB address
Write to MARB address
MARB = MARB + 1
ETCRAH = ETCRAH − 1
ETCRAH = ETCRAH − 1
No
ETCRAH = H'00
No
ETCRAH = H'00
Yes
Yes
Release bus
Release bus
ETCRAH = ETCRAL
MARB = MARB ÐÊETCRAL
ETCRAH = ETCRAL
ETCRB = ETCRB − 1
ETCRB = ETCRB − 1
ETCRB = H'0000
No
ETCRB = H'0000
Yes
Yes
Clear DTE to 0 and end transfer
Clear DTE to 0 and end transfer
a. DTSZ = TMS = 0
SAID = DAID = 0
SAIDE = DAIDE = 1
b. DTSZ = TMS = 0
SAID = 0
SAIDE = 1
DAIDE = 0
Figure 7.11 Block Transfer Mode Flowcharts
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7. DMA Controller
Figure 7.12 shows a sample setup procedure for block transfer mode.
Block transfer mode
Set source address
1
Set destination address
2
Set block transfer count
3
Set block size
4
Set DTCRB (1)
5
Set DTCRA (1)
6
Read DTCRB
7
Set DTCRB (2)
8
Read DTCRA
9
Set DTCRA (2)
10
Set the source address in MARA.
Set the destination address in MARB.
Set the block transfer count in ETCRB.
Set the block size (number of bytes or words)
in both ETCRAH and ETCRAL.
5. Set the DTCRB bits as follows.
• Clear the DTME bit to 0.
• Set the DAID and DAIDE bits to select whether
MARB is incremented, decremented, or held fixed.
• Set or clear the TMS bit to make the block area
the source or destination.
• Select the DMAC activation source with bits
DTS2B to DTS0B.
6. Set the DTCRA bits as follows.
• Clear the DTE to 0.
• Select byte size or word size with the DTSZ bit.
• Set the SAID and SAIDE bits to select whether
MARA is incremented, decremented, or held fixed.
• Set or clear the DTIE bit to enable or disable the
CPU interrupt at the end of the transfer.
• Set bits DTS2A to DTS0A all to 1 to select
block transfer mode.
7. Read DTCRB with DTME cleared to 0.
8. Set the DTME bit to 1 in DTCRB.
9. Read DTCRA with DTE cleared to 0.
10. Set the DTE bit to 1 in DTCRA to enable
the transfer.
1.
2.
3.
4.
Block transfer mode
Note: Carry out settings 1 to 10 with the DEND interrupt masked in the CPU.
If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in
which case the transfer will not start.
Figure 7.12 Block Transfer Mode Setup Procedure (Example)
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7. DMA Controller
7.4.7
DMAC Activation
The DMAC can be activated by an internal interrupt, external request, or auto-request. The
available activation sources differ depending on the transfer mode and channel as indicated in
table 7.11.
Table 7.11 DMAC Activation Sources
Short Address Mode
Channels
Channels
Activation Source
0A and 1A
0B and 1B
Normal
Block
Internal
interrupts
IMIA0
Yes
Yes
No
Yes
IMIA1
Yes
Yes
No
Yes
External
requests
Auto-request
Full Address Mode
IMIA2
Yes
Yes
No
Yes
ADI
Yes
Yes
No
Yes
TXI0
Yes
Yes
No
No
RXI0
Yes
Yes
No
No
Falling edge
of DREQ
No
Yes
Yes
Yes
Low input at
DREQ
No
Yes
Yes
No
No
No
Yes
No
Activation by Internal Interrupts: When an interrupt request is selected as a DMAC activation
source and the DTE bit is set to 1, that interrupt request is not sent to the CPU. It is not possible
for an interrupt request to activate the DMAC and simultaneously generate a CPU interrupt.
When the DMAC is activated by an interrupt request, the interrupt request flag is cleared
automatically. If the same interrupt is selected to activate two or more channels, the interrupt
request flag is cleared when the highest-priority channel is activated, but the transfer request is
held pending on the other channels in the DMAC, which are activated in their priority order.
Activation by External Request: If an external request (DREQ pin) is selected as an activation
source, the DREQ pin becomes an input pin and the corresponding TEND pin becomes an output
pin, regardless of the port data direction register (DDR) settings. The DREQ input can be levelsensitive or edge-sensitive.
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7. DMA Controller
In short address mode and normal mode, an external request operates as follows. If edge sensing is
selected, one byte or word is transferred each time a high-to-low transition of the DREQ input is
detected. If the next edge is input before the transfer is completed, the next transfer may not be
executed. If level sensing is selected, the transfer continues while DREQ is low, until the transfer
is completed. The bus is released temporarily after each byte or word has been transferred,
however. If the DREQ input goes high during a transfer, the transfer is suspended after the current
byte or word has been transferred. When DREQ goes low, the request is held internally until one
byte or word has been transferred. The TEND signal goes low during the last write cycle.
In block transfer mode, an external request operates as follows. Only edge-sensitive transfer
requests are possible in block transfer mode. Each time a high-to-low transition of the DREQ
input is detected, a block of the specified size is transferred. The TEND signal goes low during the
last write cycle in each block.
Activation by Auto-Request: The transfer starts as soon as enabled by register setup, and
continues until completed. Cycle-steal mode or burst mode can be selected.
In cycle-steal mode, the DMAC releases the bus temporarily after transferring each byte or word.
Normally, DMAC cycles alternate with CPU cycles.
In burst mode, the DMAC keeps the bus until the transfer is completed, unless there is a higherpriority bus request. If there is a higher-priority bus request, the bus is released after the current
byte or word has been transferred.
7.4.8
DMAC Bus Cycle
Figure 7.13 shows an example of the timing of the basic DMAC bus cycle. This example shows a
word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the
DMAC gets the bus from the CPU, after one dead cycle (Td), it reads from the source address and
writes to the destination address. During these read and write operations the bus is not released
even if there is another bus request. DMAC cycles comply with bus controller settings in the same
way as CPU cycles.
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7. DMA Controller
CPU cycle
T1
T2
T1
DMAC cycle (1 word transfer)
T2
Td
T1
T2
T1
T2
T3
T1
T2
CPU cycle
T3
T1
T2
T1
T2
φ
Source
address
Destination address
Address
bus
RD
HWR
LWR
Figure 7.13 DMA Transfer Bus Timing (Example)
Figure 7.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This
example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state
access area. The DMAC continues the transfer while the DREQ pin is held low.
CPU cycle
T1
T2
T3
DMAC cycle
Td
T1
T2
T1
DMAC cycle
(last transfer cycle)
CPU cycle
T2
T1
T2
Td
T1
T2
T1
T2
CPU cycle
T1
φ
DREQ
Source Destination
address address
Source Destination
address address
Address
bus
RD
HWR , LWR
TEND
Figure 7.14 Bus Timing of DMA Transfer Requested by Low DREQ Input
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T2
7. DMA Controller
Figure 7.15 shows an auto-requested burst-mode transfer. This example shows a transfer of three
words from a 16-bit two-state access area to another 16-bit two-state access area.
CPU cycle
T1
T2
CPU cycle
DMAC cycle
Td
T1
T2
T1
T2
T1
T2
T1
T2
T1
T2
T1
T2
T1
T2
φ
Source Destination
address address
Address
bus
RD
HWR ,
LWR
Figure 7.15 Burst DMA Bus Timing
When the DMAC is activated from a DREQ pin there is a minimum interval of four states from
when the transfer is requested until the DMAC starts operating*. The DREQ pin is not sampled
during the time between the transfer request and the start of the transfer. In short address mode and
normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the pin
is next sampled at the end of one block transfer.
Note: * The minimum response time is also four states when the DMAC is activated by an
internal module interrupt.
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7. DMA Controller
Figure 7.16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal
mode.
CPU cycle
T2
T1
T2
T1
CPU
cycle
DMAC cycle
T2
Td
T1
T2
T1
T2
T1
T2
DMAC cycle
Td
T1
T2
φ
DREQ
Address
bus
RD
HWR , LWR
Minimum 4 states
Next sampling point
Figure 7.16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode
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7. DMA Controller
Figure 7.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in
normal mode.
CPU cycle
T2
T1
T2
T1
DMAC cycle
T2
Td
T1
T2
T1
CPU cycle
T2
T1
T2
T1
T2
T1
φ
DREQ
Address
bus
RD
HWR , LWR
Minimum 4 states
Next sampling point
Figure 7.17 Timing of DMAC Activation by Low DREQ Level in Normal Mode
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Figure 7.18 shows the timing when the DMAC is activated by the falling edge of DREQ in block
transfer mode.
End of 1 block transfer
DMAC cycle
T1
T2
T1
T2
T1
CPU cycle
T2
T1
T2
T1
T2
T1
T2
DMAC cycle
Td
T1
T2
φ
DREQ
Address
bus
RD
HWR , LWR
TEND
Next sampling
Minimum 4 states
Figure 7.18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode
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7. DMA Controller
7.4.9
Multiple-Channel Operation
The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B.
Table 7.12 shows the complete priority order.
Table 7.12 Channel Priority Order
Short Address Mode
Full Address Mode
Priority
Channel 0A
Channel 0
High
Channel 0B
Channel 1A
Channel 1B
Channel 1
Low
If transfers are requested on two or more channels simultaneously, or if a transfer on one channel
is requested during a transfer on another channel, the DMAC operates as follows.
• When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it
starts a transfer on the highest-priority channel at that time.
• Once a transfer starts on one channel, requests to other channels are held pending until that
channel releases the bus.
• After each transfer in short address mode, and each externally-requested or cycle-steal transfer
in normal mode, the DMAC releases the bus and returns to step 1. After releasing the bus, if
there is a transfer request for another channel, the DMAC requests the bus again.
• After completion of a burst-mode transfer, or after transfer of one block in block transfer
mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a
higher-priority channel or a bus request from a higher-priority bus master, however, the
DMAC releases the bus after completing the transfer of the current byte or word. After
releasing the bus, if there is a transfer request for another channel, the DMAC requests the bus
again.
Figure 7.19 shows the timing when channel 0A is set up for I/O mode and channel 1 for burst
mode, and a transfer request for channel 0A is received while channel 1 is active.
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7. DMA Controller
DMAC cycle
(channel 1)
T2
T1
CPU
cycle
T1
T2
DMAC cycle
(channel 0A)
Td
T1
T2
T1
CPU
cycle
T2
T1
T2
DMAC cycle
(channel 1)
Td
T1
T2
T1
T2
φ
Address
bus
RD
HWR ,
LWR
Figure 7.19 Timing of Multiple-Channel Operations
7.4.10
External Bus Requests, DRAM Interface, and DMAC
During a DMAC transfer, if the bus right is requested by an external bus request signal (BREQ) or
by the DRAM interface (refresh cycle), the DMAC releases the bus after completing the transfer
of the current byte or word. If there is a transfer request at this point, the DMAC requests the bus
right again. Figure 7.20 shows an example of the timing of insertion of a refresh cycle during a
burst transfer on channel 0.
Refresh
cycle
DMAC cycle (channel 0)
T1
T2
T1
T2
T1
T2
T1
T2
T1
T2
DMAC cycle (channel 0)
Td
T1
T2
T1
φ
Address
bus
RD
HWR
Figure 7.20 Bus Timing of DRAM Interface and DMAC
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T2
T1
T2
7. DMA Controller
7.4.11
NMI Interrupts and DMAC
NMI interrupts do not affect DMAC operations in short address mode.
If an NMI interrupt occurs during a transfer in full address mode, the DMAC suspends operations.
In full address mode, a channel is enabled when its DTE and DTME bits are both set to 1. NMI
input clears the DTME bit to 0. After transferring the current byte or word, the DMAC releases the
bus to the CPU. In normal mode, the suspended transfer resumes when the CPU sets the DTME
bit to 1 again. Check that the DTE bit is set to 1 and the DTME bit is cleared to 0 before setting
the DTME bit to 1.
Figure 7.21 shows the procedure for resuming a DMAC transfer in normal mode on channel 0
after the transfer was halted by NMI input.
Resuming DMAC transfer
in normal mode
1. Check that DTE = 1 and DTME = 0.
2. Read DTCRB while DTME = 0,
then write 1 in the DTME bit.
1
DTE = 1
DTME = 0
No
Yes
Set DTME to 1
DMA transfer continues
2
End
Figure 7.21 Procedure for Resuming a DMAC Transfer Halted by NMI (Example)
For information about NMI interrupts in block transfer mode, see section 7.6.6, NMI Interrupts
and Block Transfer Mode.
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7. DMA Controller
7.4.12
Aborting a DMAC Transfer
When the DTE bit in an active channel is cleared to 0, the DMAC halts after transferring the
current byte or word. The DMAC starts again when the DTE bit is set to 1. In full address mode,
the DTME bit can be used for the same purpose. Figure 7.22 shows the procedure for aborting a
DMAC transfer by software.
DMAC transfer abort
Set DTCR
1. Clear the DTE bit to 0 in DTCR.
To avoid generating an interrupt when
aborting a DMA transfer, clear the DTIE
bit to 0 simultaneously.
1
DMAC transfer aborted
Figure 7.22 Procedure for Aborting a DMAC Transfer
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7.4.13
Exiting Full Address Mode
Figure 7.23 shows the procedure for exiting full address mode and initializing the pair of channels.
To set the channels up in another mode after exiting full address mode, follow the setup procedure
for the relevant mode.
Exiting full address mode
Halt the channel
1
Initialize DTCRB
2
Initialize DTCRA
3
1. Clear the DTE bit to 0 in DTCRA, or wait
for the transfer to end and the DTE bit
to be cleared to 0.
2. Clear all DTCRB bits to 0.
3. Clear all DTCRA bits to 0.
Initialized and halted
Figure 7.23 Procedure for Exiting Full Address Mode (Example)
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7.4.14
DMAC States in Reset State, Standby Modes, and Sleep Mode
When the chip is reset or enters hardware standby mode or software standby mode, the DMAC is
initialized and halts. DMAC operations continue in sleep mode. Figure 7.24 shows the timing of a
cycle-steal transfer in sleep mode.
Sleep mode
CPU cycle
T2
DMAC cycle
Td
T1
T2
T1
DMAC cycle
T2
Td
T1
T2
T1
T2
Td
φ
Address bus
RD
HWR
Figure 7.24 Timing of Cycle-Steal Transfer in Sleep Mode
7.5
Interrupts
The DMAC generates only DMA-end interrupts. Table 7.13 lists the interrupts and their priority.
Table 7.13 DMAC Interrupts
Description
Interrupt
Short Address Mode
Full Address Mode
Interrupt
Priority
DEND0A
End of transfer on channel 0A
End of transfer on channel 0
High
DEND0B
End of transfer on channel 0B
⎯
DEND1A
End of transfer on channel 1A
End of transfer on channel 1
DEND1B
End of transfer on channel 1B
⎯
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Low
7. DMA Controller
Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control
register (DTCR). Separate interrupt signals are sent to the interrupt controller.
The interrupt priority order among channels is channel 0 > channel 1 and channel A > channel B.
Figure 7.25 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and
DTIE = 1.
DTE
DMA-end interrupt
DTIE
Figure 7.25 DMA-End Interrupt Logic
The DMA-end interrupt for the B channels (DENDB) is unavailable in full address mode. The
DTME bit does not affect interrupt operations.
7.6
Usage Notes
7.6.1
Note on Word Data Transfer
Word data cannot be accessed starting at an odd address. When word-size transfer is selected, set
even values in the memory and I/O address registers (MAR and IOAR).
7.6.2
DMAC Self-Access
The DMAC itself cannot be accessed during a DMAC cycle. DMAC registers cannot be specified
as source or destination addresses.
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7. DMA Controller
7.6.3
Longword Access to Memory Address Registers
A memory address register can be accessed as longword data at the MARR address.
Example
MOV.L
#LBL, ER0
MOV.L
ER0, @MARR
Four byte accesses are performed. Note that the CPU may release the bus between the second byte
(MARE) and third byte (MARH).
Memory address registers should be written and read only when the DMAC is halted.
7.6.4
Note on Full Address Mode Setup
Full address mode is controlled by two registers: DTCRA and DTCRB. Care must be taken to
prevent the B channel from operating in short address mode during the register setup. The enable
bits (DTE and DTME) should not be set to 1 until the end of the setup procedure.
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7.6.5
Note on Activating DMAC by Internal Interrupts
When using an internal interrupt to activate the DMAC, make sure that the interrupt selected as
the activating source does not occur during the interval after it has been selected but before the
DMAC has been enabled. The on-chip supporting module that will generate the interrupt should
not be activated until the DMAC has been enabled. If the DMAC must be enabled while the onchip supporting module is active, follow the procedure in figure 7.26.
Enabling of DMAC
Yes
Interrupt handling by CPU
Selected interrupt
requested?
1
No
Clear selected interrupt's
enable bit to 0
2
Enable DMAC
3
Set selected interrupt's
enable bit to 1
4
1. While the DTE bit is cleared to 0,
interrupt requests are sent to the
CPU.
2. Clear the interrupt enable bit to 0
in the interrupt-generating on-chip
supporting module.
3. Enable the DMAC.
4. Enable the DMAC-activating
interrupt.
DMAC operates
Figure 7.26 Procedure for Enabling DMAC while On-Chip Supporting
Module Is Operating (Example)
If the DTE bit is set to 1 but the DTME bit is cleared to 0, the DMAC is halted and the selected
activating source cannot generate a CPU interrupt. If the DMAC is halted by an NMI interrupt, for
example, the selected activating source cannot generate CPU interrupts. To terminate DMAC
operations in this state, clear the DTE bit to 0 to allow CPU interrupts to be requested. To continue
DMAC operations, carry out steps 2 and 4 in figure 7.26 before and after setting the DTME bit
to 1.
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7. DMA Controller
When an ITU interrupt activates the DMAC, make sure the next interrupt does not occur before
the DMA transfer ends. If one 16-bit timer interrupt activates two or more channels, make sure the
next interrupt does not occur before the DMA transfers end on all the activated channels. If the
next interrupt occurs before a transfer ends, the channel or channels for which that interrupt was
selected may fail to accept further activation requests.
7.6.6
NMI Interrupts and Block Transfer Mode
If an NMI interrupt occurs in block transfer mode, the DMAC operates as follows.
• When the NMI interrupt occurs, the DMAC finishes transferring the current byte or word, then
clears the DTME bit to 0 and halts. The halt may occur in the middle of a block.
It is possible to find whether a transfer was halted in the middle of a block by checking the
block size counter. If the block size counter does not have its initial value, the transfer was
halted in the middle of a block.
• If the transfer is halted in the middle of a block, the activating interrupt flag is cleared to 0. The
activation request is not held pending.
• While the DTE bit is set to 1 and the DTME bit is cleared to 0, the DMAC is halted and does
not accept activating interrupt requests. If an activating interrupt occurs in this state, the
DMAC does not operate and does not hold the transfer request pending internally. Neither is a
CPU interrupt requested.
For this reason, before setting the DTME bit to 1, first clear the enable bit of the activating
interrupt to 0. Then, after setting the DTME bit to 1, set the interrupt enable bit to 1 again. See
section 7.6.5, Note on Activating DMAC by Internal Interrupts.
• When the DTME bit is set to 1, the DMAC waits for the next transfer request. If it was halted
in the middle of a block transfer, the rest of the block is transferred when the next transfer
request occurs. Otherwise, the next block is transferred when the next transfer request occurs.
7.6.7
Memory and I/O Address Register Values
Table 7.14 indicates the address ranges that can be specified in the memory and I/O address
registers (MAR and IOAR).
Table 7.14 Address Ranges Specifiable in MAR and IOAR
1-Mbyte Mode
16-Mbyte Mode
MAR
H'00000 to H'FFFFF
(0 to 1048575)
H'000000 to H'FFFFFF
(0 to 16777215)
IOAR
H'FFF00 to H'FFFFF
(1048320 to 1048575)
H'FFFF00 to H'FFFFFF
(16776960 to 16777215)
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7. DMA Controller
MAR bits 23 to 20 are ignored in 1-Mbyte mode.
7.6.8
Bus Cycle when Transfer Is Aborted
When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME
bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead
cycle may occur. This dead cycle does not update the halted channel's address register or counter
value. Figure 7.27 shows an example in which an auto-requested transfer in cycle-steal mode on
channel 0 is aborted by clearing the DTE bit in channel 0.
CPU cycle
T1
T2
DMAC cycle
Td
T1
T2
T1
DMAC
cycle
CPU cycle
T2
T1
T2
T3
Td
Td
CPU cycle
T1
T2
φ
Address bus
RD
HWR, LWR
DTE bit is
cleared
Figure 7.27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode
7.6.9
Transfer Requests by A/D Converter
When the A/D converter is set to scan mode and conversion is performed on more than one
channel, the A/D converter generates a transfer request when all conversions are completed. The
converted data is stored in the appropriate ADDR registers. Block transfer mode and full address
mode should therefore be used to transfer all the conversion results at one time.
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7. DMA Controller
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8. I/O Ports
Section 8 I/O Ports
8.1
Overview
The H8/3006 and H8/3007 have 6 input/output ports (ports 4, 6, 8, 9, A, and B) and one input-only
port (port 7). Table 8.1 summarizes the port functions. The pins in each port are multiplexed as
shown in table 8.1.
Each port has a data direction register (DDR) for selecting input or output, and a data register
(DR) for storing output data. In addition to these registers, port 4 has an input pull-up MOS
control register (PCR) for switching input pull-up transistors on and off.
Ports 4, 6, and 8 can drive one TTL load and a 90-pF capacitive load. Ports 9, A, and B can drive
one TTL load and a 30-pF capacitive load. Ports 4, 6 and 8 to B can drive a darlington transistor
pair. Pins P82 to P80, PA7 to PA0 have Schmitt-trigger input circuits.
For block diagrams of the ports see appendix C, I/O Port Block Diagrams.
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8. I/O Ports
Table 8.1
Port Functions
Port
Description
Pins
Mode 1
Port 4
• 8-bit I/O port
P47 to P40/
D7 to D0
Data input/output (D7 to D0) and 8-bit generic input/
output
• Built-in input
pull-up
transistors
Port 6
Port 7
Port 8
• 4-bit I/O port
• 8-bit I/O port
• 5-bit I/O port
Mode 2
Mode 3
Mode 4
8-bit bus mode: generic input/output
16-bit bus mode: data input/output
P67/φ
Clock output (φ) and generic input
P62/BACK
P61/BREQ
P60/WAIT
Bus control signal input/output (BACK, BREQ,
WAIT) and 3-bit generic input/output
P77/AN7/DA1
P76/AN6/DA0
Analog input (AN7, AN6) to A/D converter, analog
output (DA1, DA0) from D/A converter, and generic
input
P75 to P70/
AN5 to AN0
Analog input (AN5 to AN0) to A/D converter, and
generic input
P84/CS0
DDR = 0: generic input
DDR = 1 (reset value): CS0 output
• P82 to P80 have
Schmitt inputs P83/IRQ3/CS1/
ADTRG
IRQ3 input, CS1 output, external trigger input
(ADTRG) to A/D converter, and generic input
DDR = 0 (reset value): generic input
DDR = 1: CS1 output
P82/IRQ2/CS2
P81/IRQ1/CS3
IRQ2 and IRQ1 input, CS2 and CS3 output, and
generic input
DDR = 0 (reset value): generic input
DDR = 1: CS2 and CS3 output
Port 9
• 6-bit I/O port
P80/IRQ0/RFSH
IRQ0 input, RFSH output, and generic input/output
P95/IRQ5/SCK1
P94/IRQ4/SCK0
P93/RxD1
P92/RxD0
P91/TxD1
P90/TxD0
Input and output (SCK1, SCK0, RxD1, RxD0, TxD1,
TxD0) for serial communication interfaces 1 and 0
(SCI1/0), IRQ5 and IRQ4 input, and 6-bit generic
input/output
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8. I/O Ports
Port
Description
Pins
Port A
• 8-bit I/O port
Address output (A20)
PA7/TP7/TIOCB2/ Output (TP7) from proA20
grammable timing pattern
controller (TPC),
input or output (TIOCB2)
for 16-bit timer and
generic input/output
• Schmitt inputs
Port B
• 8-bit I/O port
Mode 1
Mode 2
Mode 3
Mode 4
PA6/TP6/TIOCA2/
A21
PA5/TP5/TIOCB1/
A22
PA4/TP4/TIOCA1/
A23
TPC output (TP6 to TP4),
16-bit timer input and
output (TIOCA2, TIOCB1,
TIOCA1), and generic
input/output
TPC output (TP6 to TP4),
16-bit timer input and
output (TIOCA2, TIOCB1,
TIOCA1), address output
(A23 to A21), and generic
input/output
PA3/TP3/TIOCB0/
TCLKD
PA2/TP2/TIOCA0/
TCLKC
PA1/TP1/TCLKB/
TEND1
PA0/TP0/TCLKA/
TEND0
TPC output (TP3 to TP0), 16-bit timer input and
output (TIOCB0, TIOCA0, TCLKD, TCLKC, TCLKB,
TCLKA), 8-bit timer input (TCLKD, TCLKC, TCLKB,
TCLKA), output (TEND1, TEND0) from DMA
controller (DMAC), and generic input/output
PB7/TP15/RXD2
PB6/TP14/TXD2
PB5/TP13/SCK2/
LCAS
PB4/TP12/UCAS
TPC output (TP15 to TP12), SCI2 input and output
(SCK2 , RxD2, TxD2), DRAM interface output (LCAS,
UCAS), and generic input/output
PB3/TP11/TMIO3/
DREQ1/CS4
PB2/TP10/TMO2/
CS5
PB1/TP9/TMIO1/
DREQ0/CS6
PB0/TP8/TMO0/
CS7
TPC output (TP11 to TP8), 8-bit timer input and
output (TMIO3, TMO2, TMIO1, TMO0), DMAC input
(DREQ1, DREQ0), CS7 to CS4 output, and generic
input/output
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8. I/O Ports
8.2
Port 4
8.2.1
Overview
Port 4 is an 8-bit input/output port with the pin configuration shown in figure 8.1.
When the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit-access areas, the
chip operates in 8-bit bus mode and port 4 is a generic input/output port. When at least one of
areas 0 to 7 is designated as a 16-bit-access area, the chip operates in 16-bit bus mode and port 4
becomes part of the data bus.
Port 4 has software-programmable built-in pull-up transistors.
Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Port 4 pins
Port 4
Modes 1 to 4
P47 /D7
P47 (input/output)/D7 (input/output)
P46 /D6
P46 (input/output)/D6 (input/output)
P45 /D5
P45 (input/output)/D5 (input/output)
P44 /D4
P44 (input/output)/D4 (input/output)
P43 /D3
P43 (input/output)/D3 (input/output)
P42 /D2
P42 (input/output)/D2 (input/output)
P41 /D1
P41 (input/output)/D1 (input/output)
P40 /D0
P40 (input/output)/D0 (input/output)
Figure 8.1 Port 4 Pin Configuration
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8. I/O Ports
8.2.2
Register Configuration
Table 8.2 summarizes the registers of port 4.
Table 8.2
Port 4 Registers
Address*
Name
Abbreviation R/W
Initial Value
H'EE003
Port 4 data direction register
P4DDR
W
H'00
H'FFFD3
Port 4 data register
P4DR
R/W
H'00
H'EE03E
Port 4 input pull-up MOS control register
P4PCR
R/W
H'00
Note:
*
Lower 20 bits of the address in advanced mode.
Port 4 Data Direction Register (P4DDR): P4DDR is an 8-bit write-only register that can select
input or output for each pin in port 4.
Bit
7
6
5
4
3
2
1
0
P4 7 DDR P4 6 DDR P4 5 DDR P4 4 DDR P4 3 DDR P4 2 DDR P4 1 DDR P4 0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 4 data direction 7 to 0
These bits select input or output for port 4 pins
When all areas are designated as 8-bit-access areas by the bus controller's bus width control
register (ABWCR), selecting 8-bit bus mode, port 4 functions as an input/output port. In this case,
a pin in port 4 becomes an output port if the corresponding P4DDR bit is set to 1, and an input
port if this bit is cleared to 0.
When at least one area is designated as a 16-bit-access area, selecting 16-bit bus mode, port 4
functions as part of the data bus, regardless of the P4DDR settings.
P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting.
ABWCR and P4DDR are not initialized in software standby mode. When port 4 functions as a
generic input/output port, if a P4DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
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8. I/O Ports
Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores output data
for port 4. When port 4 functions as an output port, the value of this register is output. When a bit
in P4DDR is set to 1, if port 4 is read the value of the corresponding P4DR bit is returned. When a
bit in P4DDR is cleared to 0, if port 4 is read the corresponding pin level is read.
Bit
7
6
5
4
3
2
1
0
P4 7
P4 6
P4 5
P4 4
P4 3
P4 2
P4 1
P4 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 4 data 7 to 0
These bits store data for port 4 pins
P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Port 4 Input Pull-Up MOS Control Register (P4PCR): P4PCR is an 8-bit readable/writable
register that controls the MOS input pull-up transistors in port 4.
Bit
7
6
5
4
3
2
1
0
P4 7 PCR P4 6 PCR P4 5 PCR P4 4 PCR P4 3 PCR P4 2 PCR P4 1 PCR P4 0 PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 4 input pull-up control 7 to 0
These bits control input pull-up transistors built into port 4
In 8-bit bus mode when a P4DDR bit is cleared to 0 (selecting generic input), if the corresponding
P4PCR bit is set to 1, the input pull-up transistor is turned on.
P4PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Table 8.3 summarizes the states of the input pull-ups in each operating mode.
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8. I/O Ports
Table 8.3
Input Pull-Up Transistor States (Port 4)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
Other Modes
8-bit bus mode
Off
Off
On/off
On/off
Off
Off
16-bit bus mode
Legend:
Off:
The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P4PCR = 1 and P4DDR = 0. Otherwise, it is off.
8.3
Port 6
8.3.1
Overview
Port 6 is an 4-bit input/output port that is also used for input and output of bus control signals
(BACK, BREQ, WAIT) and for clock (φ) output.
The port 6 pin configuration is shown in figure 8.2.
The pin in port 6 functions are P67 (generic input)/φ, P62/BACK, P61/BREQ, and P60/WAIT. See
table 8.5 for the selection of the pin functions.
See Section 19, Power-Down State, for clock output pin. See Section 6, Bus Controller, for bus
control I/O pin (BACK, BREQ and WAIT).
Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
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8. I/O Ports
Port 6 pins
Port 6
P67/φ
P67 (input)/φ(output)
P62/BACK
P62 (input/output)/BACK (output)
P61/BREQ
P61 (input/output)/BREQ (input)
P60/WAIT
P60 (input/output)/WAIT (input)
Figure 8.2 Port 6 Pin Configuration
8.3.2
Register Configuration
Table 8.4 summarizes the registers of port 6.
Table 8.4
Port 6 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'EE005
Port 6 data direction register
P6DDR
W
H'80
H'FFFD5
Port 6 data register
P6DR
R/W
H'80
Note:
*
Lower 20 bits of the address in advanced mode.
Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select
input or output for each pin in port 6.
Bits 7 to 3 are reserved. Bit 7 is fixed at 1, and cannot be modified.
Bit
7
⎯
6
5
4
3
2
1
0
P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
Initial value
1
0
0
0
0
0
0
0
Read/Write
⎯
W
W
W
W
W
W
W
Reserved bit
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Port 6 data direction 2 to 0
These bits select input or
output for port 6 pins
8. I/O Ports
P67 functions as the clock output pin (φ) or an input port. P67 is the clock input pin (φ) if the
PSTOP bit in MSTCRH is cleared to 0 (initial value), and an input port if this bit is set to 1.
When P62 to P60 function as input/output ports, the pin becomes an output port if the
corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0.
P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode,
it retains its previous setting. When port 6 functions as a generic input/output port, if a P6DDR bit
is set to 1, the corresponding pin maintains its output state in software standby mode.
Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores output data
for port 6. When port 6 functions as an output port, the value of this register is output.
Bit
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P63
P62
P61
P60
Initial value
*
0
0
0
0
0
0
0
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data 7, 2 to 0 for port 6 pins
Bits storing data for port 6 pins
Reserved bit
Note: * Determined by pin P67.
Bit 7 returns 1 if read when the PSTOP bit in MSTCRH is 0, and returns the logic level of pin P67
if read when the PSTOP bit is 1. This bit cannot be modified.
Bits 6 to 3 are reserved; they can be read and written to, but cannot be used as ports.
The P6DR value is returned if P6DR is read while the corresponding bit (P66DDR to P63DDR) in
P6DDR is set to 1, and an undefined value is returned if P6DR is read while the corresponding bit
is cleared to 0.
For bits 2 to 0, the pin logic level is returned if the bit is read while the corresponding bit in
P6DDR is cleared to 0, and the P6DR value is returned if the bit is read while the corresponding
bit in P6DDR is set to 1.
P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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8. I/O Ports
Table 8.5
Port 6 Pin Functions
Pin
Pin Functions and Selection Method
P67/φ
Bit PSTOP in MSTCRH selects the pin function as follows.
PSTOP
Pin function
P62/BACK
0
1
φ output
P67 input
Bit BRLE in BRCR and bit P62DDR select the pin function as follows.
BRLE
P62DDR
Pin function
P61/BREQ
0
0
1
⎯
P62 input
P62 output
BACK output
Bit BRLE in BRCR and bit P61DDR select the pin function as follows.
BRLE
P61DDR
Pin function
P60/WAIT
1
0
1
0
1
⎯
P61 input
P61 output
BREQ input
Bit WAITE in BCR and bit P60DDR select the pin function as follows.
WAITE
P60DDR
Pin function
0
1
0
1
0*
P60 input
P60 output
WAIT input
Note: * Do not set bit P60DDR to 1.
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8. I/O Ports
8.4
Port 7
8.4.1
Overview
Port 7 is an 8-bit input-only port that is also used for analog input to the A/D converter and analog
output from the D/A converter. The pin functions are the same in all operating modes. Figure 8.3
shows the pin configuration of port 7.
See section 15, A/D Converter, for details of the A/D converter analog input pins, and section 16,
D/A Converter, for details of the D/A converter analog output pins.
Port 7 pins
P77 (input)/AN 7 (input)/DA 1 (output)
P76 (input)/AN 6 (input)/DA 0 (output)
P75 (input)/AN 5 (input)
P74 (input)/AN 4 (input)
Port 7
P73 (input)/AN 3 (input)
P72 (input)/AN 2 (input)
P71 (input)/AN 1 (input)
P70 (input)/AN 0 (input)
Figure 8.3 Port 7 Pin Configuration
8.4.2
Register Configuration
Table 8.6 summarizes the port 7 register. Port 7 is an input-only port, and so has no data direction
register.
Table 8.6
Port 7 Data Register
Address*
Name
Abbreviation
R/W
Initial Value
H'FFFD6
Port 7 data register
P7DR
R
Undetermined
Note:
*
Lower 20 bits of the address in advanced mode.
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8. I/O Ports
Port 7 Data Register (P7DR)
Bit
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
Initial value
⎯*
⎯*
⎯*
⎯*
⎯*
⎯*
⎯*
⎯*
Read/Write
R
R
R
R
R
R
R
R
Note: * Determined by pins P7 7 to P70 .
When port 7 is read, the pin logic levels are always read. P7DR cannot be modified.
8.5
Port 8
8.5.1
Overview
Port 8 is a 5-bit input/output port that is also used for CS3 to CS0 output, RFSH output, IRQ3 to
IRQ0 input, and A/D converter ADTRG input. Figure 8.4 shows the pin configuration of port 8.
See table 8.8 for the selection of pin functions.
See section 15, A/D Converter, for a description of the A/D converter's ADTRG input pin.
The IRQ3 to IRQ0 functions are selected by IER settings, regardless of whether the pin is used for
input or output. Caution is therefore required. For details see section 5, Interrupt Controller.
When DRAM is connected to areas 2 to 5, the CS3 and CS2 output pins function as RAS output
pins for each area. For details see section 6.5, DRAM Interface.
Pins in port 8 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Pins P82 to P80 have Schmitt-trigger inputs.
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8. I/O Ports
Port 8
Port 8 pins
Pin functions in modes 1 to 4
P84 / CS 0
P84 (input)/ CS 0 (output)
P83 / CS 1 / IRQ 3 / ADTRG
P83 (input)/ CS 1 (output)/ IRQ 3 (input) / ADTRG (input)
P82 / CS 2 / IRQ 2
P82 (input)/ CS 2 (output)/ IRQ 2 (input)
P81 / CS 3 / IRQ 1
P81 (input/output)/CS3 (output)/IRQ1 (input)
P80 / RFSH /IRQ 0
P80 (input/output)/ RFSH (output)/ IRQ 0 (input)
Figure 8.4 Port 8 Pin Configuration
8.5.2
Register Configuration
Table 8.7 summarizes the registers of port 8.
Table 8.7
Port 8 Registers
Initial Value
Address*
Name
Abbreviation
R/W
Mode 1 to 4
H'EE007
Port 8 data direction
register
P8DDR
W
H'F0
H'FFFD7
Port 8 data register
P8DR
R/W
H'E0
Note:
*
Lower 20 bits of the address in advanced mode.
Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select
input or output for each pin in port 8.
Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified.
Bit
Modes
1 to 4
7
6
5
⎯
⎯
⎯
4
3
2
1
0
P84DDR P83DDR P82DDR P81DDR P80DDR
Initial value
1
1
1
1
0
0
0
0
Read/Write
⎯
⎯
⎯
W
W
W
W
W
Reserved bits
Port 8 data direction 4 to 0
These bits select input or
output for port 8 pins
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8. I/O Ports
When bits in P8DDR bit are set to 1, P84 to P81 become CS0 to CS3 output pins. When bits in
P8DDR are cleared to 0, the corresponding pins become input ports. Following a reset P84
functions as the CS0 output, while the other three pins are input ports.
When the refresh enable bit (RFSHE) in DRCRA is set to 1, P80 is used for RFSH output. When
RFSHE is cleared to 0, P80 becomes an input/output port according to the P8DDR setting. For
details see table 8.8.
P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P8DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode
P8DDR retains its previous setting. Therefore, when port 8 functions as an input/output port, if a
transition is made to software standby mode while a P8DDR bit is set to 1, the corresponding pin
maintains its output state.
Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores output data
for port 8. When a bit in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR
bit is returned. When a bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin level is
read.
Bits 7 to 5 are reserved. They cannot be modified and always are read as 1.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
P8 4
P8 3
P8 2
P8 1
P8 0
Initial value
1
1
1
0
0
0
0
0
Read/Write
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
Reserved bits
Port 8 data 4 to 0
These bits store data
for port 8 pins
P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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8. I/O Ports
Table 8.8
Port 8 Pin Functions
Pin
Pin Functions and Selection Method
P84/CS0
Bit P84DDR selects the pin function as follows.
P84DDR
Pin function
0
1
P84 input
CS0 output
P83/CS1/IRQ3/ADTRG Bit P83DDR selects the pin function as follows
P83DDR
Pin function
0
1
P83 input
CS1 output
IRQ3 input
ADTRG input
P82/CS2/IRQ2
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, and
bit P82DDR, select the pin function as follows.
DRAM interface
settings
(1) in table below
0
1
⎯
P82 input
CS2 output
CS2 output*
P82DDR
Pin function
(2) in table below
IRQ3 input
Note: * CS2 is output as RAS2.
DRAM interface
setting
(1)
(2)
DRAS2
0
DRAS1
DRAS0
1
0
0
1
1
0
0
1
0
1
1
0
1
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8. I/O Ports
Pin
Pin Functions and Selection Method
P81/CS3/IRQ1
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, and
bit P81DDR, select the pin function as follows.
DRAM interface
settings
(1) in table below
0
1
0
1
⎯
P81
input
CS3
output
P81
input
P81
output
CS3
output*
P81DDR
Pin function
(3) in
table
below
(2) in table below
IRQ1 input
Note: * CS3 is output as RAS3.
DRAM interface
setting
(1)
(3)
DRAS2
P80/RFSH/IRQ0
(3)
(2)
0
DRAS1
DRAS0
(2)
1
0
0
1
1
0
0
1
0
1
1
0
1
Bit RFSHE in DRCRA and bit P80DDR select the pin function as follows.
If areas 2 to 5 are not designated as DRAM space, do not set bit RFSHE
in DRCRA to 1.
RFSHE
P80DDR
Pin function
0
1
0
1
⎯
P80 input
P80 output
RFSH output
IRQ0 input
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8. I/O Ports
8.6
Port 9
8.6.1
Overview
Port 9 is a 6-bit input/output port that is also used for input and output (TxD0, TxD1, RxD0, RxD1,
SCK0, SCK1) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ5
and IRQ4 input. See table 8.10 for the selection of pin functions.
The IRQ5 and IRQ4 functions are selected by IER settings, regardless of whether the pin is used for
input or output. Caution is therefore required. For details see section 5.3.1, External Interrupts.
Port 9 has the same set of pin functions in all operating modes. Figure 8.5 shows the pin
configuration of port 9.
Pins in port 9 can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor pair.
Port 9 pins
P95 (input/output)/SCK 1 (input/output)/IRQ 5 (input)
P94 (input/output)/SCK 0 (input/output)/IRQ 4 (input)
Port 9
P93 (input/output)/RxD1 (input)
P92 (input/output)/RxD0 (input)
P91 (input/output)/TxD1 (output)
P90 (input/output)/TxD0 (output)
Figure 8.5 Port 9 Pin Configuration
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8. I/O Ports
8.6.2
Register Configuration
Table 8.9 summarizes the registers of port 9.
Table 8.9
Port 9 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'EE008
Port 9 data direction register
P9DDR
W
H'C0
H'FFFD8
Port 9 data register
P9DR
R/W
H'C0
Note:
*
Lower 20 bits of the address in advanced mode.
Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select
input or output for each pin in port 9.
Bits 7 and 6 are reserved. They cannot be modified and always read as 1.
Bit
7
6
⎯
⎯
Initial value
1
1
0
0
0
0
0
0
Read/Write
⎯
⎯
W
W
W
W
W
W
5
4
3
2
1
0
P9 5 DDR P9 4 DDR P9 3 DDR P9 2 DDR P9 1 DDR P9 0 DDR
Reserved bits
Port 9 data direction 5 to 0
These bits select input or
output for port 9 pins
When a pin in port 9 becomes an output port if the corresponding P9DDR bit is set to 1, and an
input port if this bit is cleared to 0.
P9DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. When transition is made to software standby mode while a P9DDR
bit is set to 1, the corresponding pin maintains its output state.
Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores output data
for port 9. When port 9 functions as an output port, the value of this register is output. When a bit
in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When a
bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin level is read.
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8. I/O Ports
Bits 7 and 6 are reserved. They cannot be modified and are always read as 1.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
P9 5
P9 4
P9 3
P9 2
P9 1
P9 0
Initial value
1
1
0
0
0
0
0
0
Read/Write
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Port 9 data 5 to 0
These bits store data
for port 9 pins
P9DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Table 8.10 Port 9 Pin Functions
Pin
Pin Functions and Selection Method
P95/SCK1/IRQ5
Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR, and bit P95DDR
select the pin function as follows.
CKE1
0
C/A
Pin function
1
⎯
1
⎯
⎯
0
CKE0
P95DDR
1
0
0
1
⎯
⎯
⎯
P95
input
P95
output
SCK1
output
SCK1
output
SCK1
input
IRQ5 input
P94/SCK0/IRQ4
Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR, and bit P94DDR
select the pin function as follows.
CKE1
0
C/A
Pin function
1
⎯
1
⎯
⎯
0
CKE0
P94DDR
1
0
0
1
⎯
⎯
⎯
P94
input
P94
output
SCK0
output
SCK0
output
SCK0
input
IRQ4 input
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8. I/O Ports
Pin
Pin Functions and Selection Method
P93/RxD1
Bit RE in SCR of SCI1, bit SMIF in SCMR, and bit P93DDR select the pin
function as follows.
SMIF
0
1
⎯
0
1
⎯
⎯
P93 input
P93 output
RxD1 input
RxD1 input
RE
P93DDR
Pin function
P92/RxD0
0
Bit RE in SCR of SCI0, bit SMIF in SCMR, and bit P92DDR select the pin
function as follows.
SMIF
0
RE
P92DDR
Pin function
P91/TxD1
1
0
1
1
⎯
0
1
⎯
⎯
P92 input
P92 output
RxD0 input
RxD0 input
Bit TE in SCR of SCI1, bit SMIF in SCMR, and bit P91DDR select the pin
function as follows.
SMIF
0
TE
P91 DDR
Pin function
0
0
1
P91 input
P91 output
1
1
⎯
⎯
⎯
TxD1 output TxD1 output*
Note: * Functions as the TxD1 output pin, but there are two states: one
in which the pin is driven, and another in which the pin is at highimpedance.
P90/TxD0
Bit TE in SCR of SCI0, bit SMIF in SCMR, and bit P90DDR select the pin
function as follows.
SMIF
0
TE
P90DDR
Pin function
0
0
1
P90 input
P90 output
1
1
⎯
⎯
⎯
TxD0 output TxD0 output*
Note: * Functions as the TxD0 output pin, but there are two states: one
in which the pin is driven, and another in which the pin is at highimpedance.
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8. I/O Ports
8.7
Port A
8.7.1
Overview
Port A is an 8-bit input/output port that is also used for output (TP7 to TP0) from the programmable
timing pattern controller (TPC), input and output, (TIOCB2, TIOCA2, TIOCB1, TIOCA1, TIOCB0,
TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit timer, input (TCLKD, TCLKC,
TCLKB, TCLKA) to the 8-bit timer, output (TEND1, TEND0) from the DMA controller (DMAC),
and address output (A23 to A20). A reset or hardware standby transition leaves port A as an input
port, except that in modes 3 and 4, one pin is always used for A20 output. See table 8.12 to 8.14 for
the selection of pin functions.
Usage of pins for TPC, 16-bit timer, 8-bit timer, and DMAC input and output is described in the
sections on those modules. For output of address bits A23 to A21 in modes 3 and 4, see section
6.2.4, Bus Release Control Register (BRCR). Pins not assigned to any of these functions are
available for generic input/output. Figure 8.6 shows the pin configuration of port A.
Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor pair. Port A has Schmitt-trigger inputs.
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8. I/O Ports
Port A pins
PA 7 /TP7 /TIOCB2 /A20
PA 6 /TP6 /TIOCA2 /A21
PA 5 /TP5 /TIOCB1 /A22
PA 4 /TP4 /TIOCA1 /A23
Port A
PA 3 /TP3 /TIOCB0 /TCLKD
PA 2 /TP2 /TIOCA0 /TCLKC
PA 1 /TP1 /TEND1 /TCLKB
PA 0 /TP0 /TEND0 /TCLKA
Pin functions in modes 1 and 2
PA 7 (input/output)/TP7 (output)/TIOCB 2 (input/output)
PA 6 (input/output)/TP6 (output)/TIOCA 2 (input/output)
PA 5 (input/output)/TP5 (output)/TIOCB 1 (input/output)
PA 4 (input/output)/TP4 (output)/TIOCA 1 (input/output)
PA 3 (input/output)/TP3 (output)/TIOCB 0 (input/output)/TCLKD (input)
PA 2 (input/output)/TP2 (output)/TIOCA 0 (input/output)/TCLKC (input)
PA 1 (input/output)/TP1 (output)/TEND 1 (output)/TCLKB (input)
PA 0 (input/output)/TP0 (output)/TEND 0 (output)/TCLKA (input)
Pin functions in modes 3 and 4
A 20 (output)
PA 6 (input/output)/TP 6 (output)/TIOCA 2 (input/output)/A21 (output)
PA 5 (input/output)/TP 5 (output)/TIOCB 1 (input/output)/A22 (output)
PA 4 (input/output)/TP 4 (output)/TIOCA 1 (input/output)/A23 (output)
PA 3 (input/output)/TP 3 (output)/TIOCB 0 (input/output)/TCLKD (input)
PA 2 (input/output)/TP 2 (output)/TIOCA 0 (input/output)/TCLKC (input)
PA 1 (input/output)/TP 1 (output)/TEND 1 (output)/TCLKB (input)
PA 0 (input/output)/TP 0 (output)/TEND 0 (output)/TCLKA (input)
Figure 8.6 Port A Pin Configuration
Rev.5.00 Sep. 12, 2007 Page 266 of 764
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8. I/O Ports
8.7.2
Register Configuration
Table 8.11 summarizes the registers of port A.
Table 8.11 Port A Registers
Initial Value
Address*
Name
Abbreviation
R/W
Modes 1, 2
Modes 3, 4
H'EE009
Port A data direction
register
PADDR
W
H'00
H'80
H'FFFD9
Port A data register
PADR
R/W
H'00
H'00
Note:
*
Lower 20 bits of the address in advanced mode.
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
Bit
7
6
5
4
3
2
1
0
PA 7 DDR PA 6 DDR PA 5 DDR PA 4 DDR PA 3 DDR PA 2 DDR PA 1 DDR PA 0 DDR
Modes Initial value 1
3, 4,
Read/Write ⎯
0
0
0
0
0
0
0
W
W
W
W
W
W
W
Modes Initial value 0
1, 2
Read/Write W
0
0
0
0
0
0
0
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
A pin in port A becomes an output port if the corresponding PADDR bit is set to 1, and an input
port if this bit is cleared to 0. In modes 3 and 4, PA7DDR is fixed at 1 and PA7 functions as an
address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 (modes 1 and 2) or H'80 (modes 3 and 4) by a reset and in hardware
standby mode. In software standby mode it retains it previous setting. Therefore, if a transition is
made to software standby mode while a PADDR bit is set to 1, the corresponding pin maintains its
output state.
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8. I/O Ports
Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output
data for port A. When port A functions as an output port, the value of this register is output. When
a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned.
When a bit in PADDR is cleared to 0, if port A is read the corresponding pin level is read.
Bit
7
6
5
4
3
2
1
0
PA 7
PA 6
PA 5
PA 4
PA 3
PA 2
PA 1
PA 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port A data 7 to 0
These bits store data for port A pins
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Table 8.12 Port A Pin Functions (Modes 1, 2)
Pin
Pin Functions and Selection Method
PA7/TP7/
TIOCB2
Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit
PA7DDR select the pin function as follows.
16-bit timer
channel 2
settings
(1) in table below
(2) in table below
⎯
PA7DDR
1
⎯
⎯
0
1
PA7
input
PA7
output
TP7
output
TIOCB2 input*
Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0.
16-bit timer
channel 2
settings
1
TIOCB2 output
NDER7
Pin function
0
(2)
IOB2
(1)
(2)
0
1
IOB1
0
0
1
⎯
IOB0
0
1
⎯
⎯
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8. I/O Ports
Pin
Pin Functions and Selection Method
PA6/TP6/
TIOCA2
Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, and bit
PA6DDR select the pin function as follows.
16-bit timer
channel 2
settings
(1) in table below
(2) in table below
PA6DDR
⎯
0
1
1
NDER6
⎯
⎯
0
1
TIOCA2 output
PA6
input
PA6
output
TP6
output
Pin function
TIOCA2 input*
Note: * TIOCA2 input when IOA2 = 1.
16-bit timer
channel 2
settings
(2)
(1)
PWM2
(1)
1
⎯
0
IOA2
PA5/TP5/
TIOCB1
(2)
1
0
IOA1
0
0
1
⎯
⎯
IOA0
0
1
⎯
⎯
⎯
Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, and bit
PA5DDR select the pin function as follows.
16-bit timer
channel 1
settings
(1) in table below
(2) in table below
PA5DDR
⎯
0
1
1
NDER5
⎯
⎯
0
1
TIOCB1 output
PA5
input
PA5
output
TP5
output
Pin function
TIOCB1 input*
Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0.
16-bit timer
channel 1
settings
(2)
IOB2
(1)
(2)
0
1
IOB1
0
0
1
⎯
IOB0
0
1
⎯
⎯
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8. I/O Ports
Pin
Pin Functions and Selection Method
PA4/TP4/
TIOCA1
Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, and bit
PA4DDR select the pin function as follows.
16-bit timer
channel 1
settings
(1) in table below
(2) in table below
PA4DDR
⎯
0
1
1
NDER4
⎯
⎯
0
1
TIOCA1 output
PA4
input
PA4
output
TP4
output
Pin function
TIOCA1 input*
Note: * TIOCA1 input when IOA2 = 1.
16-bit timer
channel 1
settings
(2)
(1)
PWM1
(2)
(1)
1
⎯
0
IOA2
1
0
IOA1
0
0
1
⎯
⎯
IOA0
0
1
⎯
⎯
⎯
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8. I/O Ports
Table 8.13 Port A Pin Functions (Modes 3, 4)
Pin
Pin Functions and Selection Method
PA7/TP7/
Always used as A20 output.
TIOCB2/ A20 Pin function
A20 output
PA6/TP6/
Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, bit A21E in
TIOCA2/A21 BRCR, and bit PA6DDR select the pin function as follows.
A21E
16-bit timer
channel 2
settings
1
(1) in table below
0
⎯
(2) in table below
PA6DDR
⎯
0
1
1
⎯
NDER6
⎯
⎯
0
1
⎯
TIOCA2 output
PA6
input
PA6
output
TP6
output
A21
output
Pin function
TIOCA2 input*
Note: * TIOCA2 input when IOA2 = 1.
16-bit timer channel 2 settings
(2)
(1)
PWM2
(2)
0
IOA2
(1)
1
0
1
⎯
IOA1
0
0
1
⎯
⎯
IOA0
0
1
⎯
⎯
⎯
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8. I/O Ports
Pin
Pin Functions and Selection Method
PA5/TP5/
Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, bit A22E in
TIOCB1/A22 BRCR, and bit PA5DDR select the pin function as follows.
A22E
16-bit timer
channel 1
settings
1
(1) in table below
0
⎯
(2) in table below
PA5DDR
⎯
0
1
1
⎯
NDER5
⎯
⎯
0
1
⎯
TIOCB1 output
PA5
input
PA5
output
TP5
output
A22
output
Pin function
TIOCB1 input*
Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0.
16-bit timer
channel 1
settings
(2)
IOB2
(1)
(2)
0
1
IOB1
0
0
1
⎯
IOB0
0
1
⎯
⎯
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8. I/O Ports
Pin
Pin Functions and Selection Method
PA4/TP4/
Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, bit A23E in
TIOCA1/A23 BRCR, and bit PA4DDR select the pin function as follows.
A23E
16-bit timer
channel 1
settings
1
(1) in table below
0
⎯
(2) in table below
PA4DDR
⎯
0
1
1
⎯
NDER4
⎯
⎯
0
1
⎯
TIOCA1 output
PA4
input
PA4
output
TP4
output
A23
output
Pin function
TIOCA1 input*
Note: * TIOCA1 input when IOA2 = 1.
16-bit timer
channel 1
settings
(2)
(1)
PWM1
(2)
0
IOA2
(1)
1
0
1
⎯
IOA1
0
0
1
⎯
⎯
IOA0
0
1
⎯
⎯
⎯
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8. I/O Ports
Table 8.14 Port A Pin Functions (Modes 1 to 4)
Pin
Pin Functions and Selection Method
PA3/TP3/
TIOCB0/
TCLKD
Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2
to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR2 of the 8-bit timer, bit
NDER3 in NDERA, and bit PA3DDR select the pin function as follows.
16-bit timer
channel 0
settings
(1) in table below
(2) in table below
PA3DDR
⎯
0
1
1
NDER3
⎯
⎯
0
1
TIOCB0
output
PA3
input
PA3
output
TP3
output
Pin function
TIOCB0 input*
TCLKD input*
1
2
Notes: 1. TIOCB0 input when IOB2 = 1 and PWM0 = 0.
2. TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of 16TCR2 to
16TCR0, or bits CKS2 to CKS0 in 8TCR2 are as shown in (3) in the table
below.
16-bit timer
channel 0
settings
(2)
(1)
IOB2
(2)
0
1
IOB1
0
0
1
⎯
IOB0
0
1
⎯
⎯
8-bit timer
channel 0
settings
(4)
CKS2
0
CKS1
⎯
CKS0
⎯
Rev.5.00 Sep. 12, 2007 Page 274 of 764
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(3)
1
0
0
1
1
⎯
8. I/O Ports
Pin
Pin Functions and Selection Method
PA2/TP2/
TIOCA0/
TCLKC
Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2
to 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR0 of the 8-bit timer, bit
NDER2 in NDERA, and bit PA2DDR select the pin function as follows.
16-bit timer
channel 0
settings
(1) in table below
(2) in table below
PA2DDR
⎯
0
1
1
NDER2
⎯
⎯
0
1
TIOCA0 output
PA2
input
PA2
output
TP2
output
Pin function
TIOCA0 input*
TCLKC input*
1
2
Notes: 1. TIOCA0 input when IOA2 = 1.
2. TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of
16TCR2 to 16TCR0, or bits CKS2 to CKS0 in 8TCR0 are as shown in
(3) in the table below.
16-bit timer
channel 0
settings
(2)
(1)
PWM0
(2)
(1)
0
IOA2
1
0
1
⎯
IOA1
0
0
1
⎯
⎯
IOA0
0
1
⎯
⎯
⎯
8-bit timer
channel 0
settings
(4)
CKS2
0
CKS1
⎯
CKS0
⎯
(3)
1
0
0
1
1
⎯
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8. I/O Ports
Pin
Pin Functions and Selection Method
PA1/TP1/
TCLKB/
TEND1
Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer,
bits CKS2 to CKS0 in 8TCR3 of the 8-bit timer, bit NDER1 in NDERA, and bit
PA1DDR select the pin function as follows.
PA1DDR
0
1
1
NDER1
⎯
0
1
PA1 input
PA1 output
Pin function
TP1 output
TCLKB input*
1
TEND1 output*
2
Notes: 1. TCLKB input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0, and
TPSC0 = 1 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in
8TCR3 are as shown in (1) in the table below.
2. When an external request is specified as a DMAC activation source,
TEND1 output regardless of bits PA1DDR and NDER1.
8-bit timer
channel 3
settings
(2)
CKS2
0
CKS1
⎯
CKS0
⎯
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(1)
1
0
0
1
1
⎯
8. I/O Ports
Pin
Pin Functions and Selection Method
PA0/TP0/
TCLKA/
TEND0
Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer,
bits CKS2 to CKS0 in 8TCR1 of the 8-bit timer, bit NDER0 in NDERA, and bit
PA0DDR select the pin function as follows.
PA0DDR
0
NDER0
⎯
0
PA0 input
PA0 output
Pin function
1
1
TP0 output
TCLKA input*
1
TEND0 output*
2
Notes: 1. TCLKA input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0 and
TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in
8TCR0 are as shown in (1) in the table below.
2. When an external request is specified as a DMAC activation source,
TEND0 output regardless of bits PA0DDR and NDER0.
8-bit timer
channel 1
settings
(2)
CKS2
0
CKS1
⎯
CKS0
⎯
8.8
Port B
8.8.1
Overview
(1)
1
0
0
1
1
⎯
Port B is an 8-bit input/output port that is also used for output (TP15 to TP8) from the
programmable timing pattern controller (TPC), input/output (TMIO3, TMO2, TMIO1, TMO0) by
the 8-bit timer, CS7 to CS4 output, input (DREQ1, DREQ0) to the DMA controller (DMAC), input
and output (TxD2, RxD2, SCK2) by serial communication interface channel 2 (SCI2), and output
(UCAS, LCAS) by the DRAM interface. See table 8.16 for the selection of pin functions.
A reset or hardware standby transition leaves port B as an input port. For output of CS7 to CS4 in
modes 1 to 4, see section 6.3.4, Chip Select Signals. Pins not assigned to any of these functions are
available for generic input/output. When DRAM is connected to areas 2 to 5, the CS4 and CS5
output pins function as RAS output pins for each area. For details see section 6.5, DRAM
Interface. Figure 8.7 shows the pin configuration of port B.
Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive darlington
transistor pair.
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8. I/O Ports
Port B pins
PB7/TP15 /RxD2
PB6/TP14 /TxD2
PB5/TP13 /SCK2/LCAS
PB4/TP12 /UCAS
Port B
PB3/TP11 /TMIO3/DREQ1/CS4
PB2/TP10 /TMO2/CS5
PB1/TP9 /TMIO1/DREQ0/CS6
PB0/TP8 /TMO0/CS7
Pin states in modes 1 to 4
PB7 (input/output)/TP15 (output) /RxD2 (input)
PB6 (input/output)/TP14 (output) /TxD2 (output)
PB5 (input/output)/TP13 (output) /SCK2 (input/output) /LCAS (output)
PB4 (input/output)/TP12 (output) /UCAS (output)
PB3 (input/output)/TP11 (output) /TMIO3 (input/output) /DREQ1 (input) CS4 (output)
PB2 (input/output)/TP10 (output) /TMO2 (output) /CS5 (output)
PB1 (input/output)/TP9 (output) /TMIO1 (input/output) /DREQ0 (input) /CS6 (output)
PB0 (input/output)/TP8 (output) /TMO0 (output) /CS7 (output)
Figure 8.7 Port B Pin Configuration
8.8.2
Register Configuration
Table 8.15 summarizes the registers of port B.
Table 8.15 Port B Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'EE00A
Port B data direction register
PBDDR
W
H'00
H'FFFDA
Port B data register
PBDR
R/W
H'00
Note:
*
Lower 20 bits of the address in advanced mode.
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8. I/O Ports
Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select
input or output for each pin in port B. When pins are used for TPC output, the corresponding
PBDDR bits must also be set.
Bit
7
6
5
4
3
2
1
0
PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port B data direction 7 to 0
These bits select input or output for port B pins
When a pin in port B becomes an output port if the corresponding PBDDR bit is set to 1, and an
input port if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. When transition is made to software standby mode while a PBDDR
bit is set to 1, the corresponding pin maintains its output state.
Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output data
for pins port B. When port B functions as an output port, the value of this register is output. When
a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned.
When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin level is read.
Bit
7
6
5
4
3
2
1
0
PB 7
PB 6
PB 5
PB 4
PB 3
PB 2
PB 1
PB 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port B data 7 to 0
These bits store data for port B pins
PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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8. I/O Ports
Table 8.16 Port B Pin Functions
Pin
Pin Functions and Selection Method
PB7/TP15/
RxD2
Bit RE in SCR of SCI2, bit SMIF in SCMR, bit NDER15 in NDERB, and bit PB7DDR
select the pin function as follows.
SMIF
0
RE
PB7DDR
NDER15
Pin function
PB6/TP14/
TxD2
1
0
0
1
1
1
⎯
⎯
⎯
⎯
0
1
⎯
⎯
PB7 input
PB7 output
TP15 output
RxD2 input
RxD2 input
Bit TE in SCR of SCI2, bit SMIF in SCMR, bit NDER14 in NDERB, and bit PB6DDR
select the pin function as follows.
SMIF
0
TE
1
0
1
⎯
PB6DDR
0
1
1
⎯
⎯
NDER14
⎯
0
1
⎯
⎯
PB6
input
PB6
output
TP14
output
TxD2
output
TxD2
output*
Pin function
Note: * Functions as the TxD2 output pin, but there are two states: one in which
the pin is driven, and another in which the pin is at high-impedance.
PB5/TP13/
Bit C/A in SMR of SCI2, bits CKE0 and CKE1 in SCR, bit NDER13 in NDERB, and
SCK2/LCAS bit PB5DDR select the pin function as follows.
CKE1
0
C/A
1
1
⎯
1
⎯
⎯
0
CKE0
0
PB5DDR
0
1
1
⎯
⎯
⎯
NDER13
⎯
0
1
⎯
⎯
⎯
PB5
input
PB5
output
TP13
output
SCK2
output
SCK2
output
SCK2
input
Pin function
LCAS output*
Note: * LCAS output depending on bits DRAS2 to DRAS0 in DRCRA and bit
CSEL in DRCRB, and regardless of bits C/A, CKE0 and CKE1, NDER13, and
PB5DDR. For details, see section 6, Bus Controller.
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8. I/O Ports
Pin
Pin Functions and Selection Method
PB4/TP12/
UCAS
Bit NDER12 in NDERB and bit PB4DDR select the pin function as follows.
PB4DDR
0
1
1
NDER12
⎯
0
1
PB4 input
PB4 output
TP12 output
Pin function
UCAS output*
Note: * UCAS output depending on bits DRAS2 to DRAS0 in DRCRA and bit
CSEL in DRCRB, and regardless of bits NDER12 and PB4DDR. For details, see
section 6, Bus Controller.
PB3/TP11/
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and
TMIO3/
OS1/0 in 8TCSR3, bits CCLR1 and CCLR0 in 8TCR3, bit CS4E in CSCR, bit
DREQ1/CS4 NDER11 in NDERB, and bit PB3DDR select the pin function as follows.
DRAM interface
settings
(1) in table below
OIS3/2 and
OS1/0
(2) in
table
below
Not all 0
⎯
1
⎯
⎯
All 0
CS4E
0
PB3DDR
0
1
1
⎯
⎯
⎯
NDER11
⎯
0
1
⎯
⎯
⎯
PB3
input
PB3
output
TP11
output
CS4
output
TMIO3
output
CS4
3
output*
Pin function
TMIO3 input*
1
DREQ1 input*
2
Notes: 1. TMIO3 input when CCLR1 = CCLR0 = 1.
2. When an external request is specified as a DMAC activation source,
DREQ1 input regardless of bits OIS3 and OIS2, OS1 and OS0, CCLR1
and CCLR0, CS4E, NDER11, and PB3DDR.
3. CS4 is output as RAS4.
DRAM interface
settings
(1)
DRAS2
0
DRAS1
DRAS0
(2)
1
0
0
1
1
(1)
0
0
1
0
1
1
0
1
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8. I/O Ports
Pin
Pin Functions and Selection Method
PB2/TP10/
TMO2/CS5
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and
OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and bit PB2DDR
select the pin function as follows.
DRAM interface
settings
(1) in table below
OIS3/2 and
OS1/0
(2) in
table
below
Not all 0
⎯
1
⎯
⎯
All 0
CS5E
0
PB2DDR
0
1
1
⎯
⎯
⎯
NDER10
⎯
0
1
⎯
⎯
⎯
PB2
input
PB2
output
TP10
output
CS5
output
TMO2
output
CS5
output*
Pin function
Note: * CS5 is output as RAS5.
DRAM interface
settings
(1)
DRAS2
(2)
0
DRAS1
1
0
DRAS0
0
1
1
(1)
0
0
1
0
1
1
0
1
Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCLR1 and CCLR0 in 8TCR0, bit CS6E in
PB1/TP9/
CSCR, bit NDER9 in NDERB, and bit PB1DDR select the pin function as follows.
TMIO1/
DREQ0/CS6
OIS3/2 and
OS1/0
All 0
CS6E
Not all 0
0
1
⎯
PB1DDR
0
1
1
⎯
⎯
NDER9
⎯
0
1
⎯
⎯
PB1
input
PB1
output
TP9
output
CS6
output
TMIO1
output
Pin function
TMIO1 input*
1
DREQ0 input*
2
Notes: 1. TMIO1 input when CCLR1 = CCLR0 = 1.
2. DREQ0 input when an external request is specified as a DMAC
activation source, regardless of bits OIS3/2, OS1/0, CCLR1/0, CS6E,
NDER9, PB1 DDR.
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8. I/O Ports
Pin
Pin Functions and Selection Method
PB0/TP8/
TMO0/CS7
Bits OIS3/2 and OS1/0 in 8TCSR0, bit CS7E in CSCR, bit NDER8 in NDERB, and
bit PB0DDR select the pin function as follows.
OIS3/2 and
OS1/0
All 0
CS7E
Not all 0
0
1
⎯
PB0DDR
0
1
1
⎯
⎯
NDER8
⎯
0
1
⎯
⎯
PB0
input
PB0
output
TP8
output
CS7
output
TMO0
output
Pin function
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8. I/O Ports
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9. 16-Bit Timer
Section 9 16-Bit Timer
9.1
Overview
The H8/3006 and H8/3007 have built-in 16-bit timer module with three 16-bit counter channels.
9.1.1
Features
16-bit timer features are listed below.
• Capability to process up to 6 pulse outputs or 6 pulse inputs
• Six general registers (GRs, two per channel) with independently-assignable output compare or
input capture functions
• Selection of eight counter clock sources for each channel:
Internal clocks: φ, φ/2, φ/4, φ/8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD
• Five operating modes selectable in all channels:
⎯ Waveform output by compare match
Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2)
⎯ Input capture function
Rising edge, falling edge, or both edges (selectable)
⎯ Counter clearing function
Counters can be cleared by compare match or input capture
⎯ Synchronization
Two or more timer counters (16TCNTs) can be preset simultaneously, or cleared
simultaneously by compare match or input capture. Counter synchronization enables
synchronous register input and output.
⎯ PWM mode
PWM output can be provided with an arbitrary duty cycle. With synchronization, up to
three-phase PWM output is possible
• Phase counting mode selectable in channel 2
Two-phase encoder output can be counted automatically.
• High-speed access via internal 16-bit bus
The 16TCNTs and GRs can be accessed at high speed via a 16-bit bus.
• Any initial timer output value can be set
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9. 16-Bit Timer
• Nine interrupt sources
Each channel has two compare match/input capture interrupts and an overflow interrupt. All
interrupts can be requested independently.
• Output triggering of programmable timing pattern controller (TPC)
Compare match/input capture signals from channels 0 to 2 can be used as TPC output triggers.
Table 9.1 summarizes the 16-bit timer functions.
Table 9.1
16-bit timer Functions
Item
Channel 0
Channel 1
Clock sources
Internal clocks: φ, φ/2, φ/4, φ/8
Channel 2
External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable
independently
General registers (output
compare/input
capture registers)
GRA0, GRB0
GRA1, GRB1
GRA2, GRB2
Input/output pins
TIOCA0, TIOCB0
TIOCA1, TIOCB1
TIOCA2, TIOCB2
Counter clearing function
GRA0/GRB0
compare match or
input capture
GRA1/GRB1
compare match or
input capture
GRA2/GRB2
compare match or
input capture
Initial output value setting
function
Available
Available
Available
Compare
match output
0
Available
Available
Available
1
Available
Available
Available
Toggle
Available
Available
Not available
Input capture function
Available
Available
Available
Synchronization
Available
Available
Available
PWM mode
Available
Available
Available
Phase counting mode
Not available
Not available
Available
Interrupt sources
Three sources
Three sources
Three sources
• Compare
match/input
capture A0
• Compare
match/input
capture A1
• Compare
match/input
capture A2
• Compare
match/input
capture B0
• Compare
match/input
capture B1
• Compare
match/input
capture B2
• Overflow
• Overflow
• Overflow
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9. 16-Bit Timer
9.1.2
Block Diagrams
16-bit timer Block Diagram (Overall): Figure 9.1 is a block diagram of the 16-bit timer.
TCLKA to TCLKD
IMIA0 to IMIA2
IMIB0 to IMIB2
OVI0 to OVI2
Clock selector
φ, φ/2, φ/4, φ/8
Control logic
TIOCA0 to TIOCA2
TIOCB0 to TIOCB2
TOLR
TISRA
TISRB
Internal data bus
TMDR
Bus interface
TSNC
16-bit timer channel 0
16-bit timer channel 1
16-bit timer channel 2
TSTR
TISRC
Module data bus
Legend:
TSTR: Timer start register (8 bits)
TSNC: Timer synchro register (8 bits)
TMDR: Timer mode register (8 bits)
TOLR: Timer output level setting register (8 bits)
TISRA: Timer interrupt status register A (8 bits)
TISRB: Timer interrupt status register B (8 bits)
TISRC: Timer interrupt status register C (8 bits)
Figure 9.1 16-bit timer Block Diagram (Overall)
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9. 16-Bit Timer
Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical.
Both have the structure shown in figure 9.2.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TIOCA0
TIOCB0
Clock selector
Control logic
IMIA0
IMIB0
OVI0
TIOR
16TCR
GRB
GRA
16TCNT
Comparator
Module data bus
Legend:
16TCNT:
GRA, GRB:
16TCR:
TIOR:
Timer counter (16 bits)
General registers A and B (input capture/output compare registers) (16 bits × 2)
Timer control register (8 bits)
Timer I/O control register (8 bits)
Figure 9.2 Block Diagram of Channels 0 and 1
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9. 16-Bit Timer
Block Diagram of Channel 2: Figure 9.3 is a block diagram of channel 2
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TIOCA2
TIOCB2
Clock selector
Control logic
IMIA2
IMIB2
OVI2
TIOR2
16TCR2
GRB2
GRA2
16TCNT2
Comparator
Module data bus
Legend:
16TCNT2:
Timer counter 2 (16 bits)
GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers)
(16 bits × 2)
16TCR2:
Timer control register 2 (8 bits)
TIOR2:
Timer I/O control register 2 (8 bits)
Figure 9.3 Block Diagram of Channel 2
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9. 16-Bit Timer
9.1.3
Pin Configuration
Table 9.2 summarizes the 16-bit timer pins.
Table 9.2
16-bit timer Pins
Channel Name
Abbreviation
Input/
Output
Common Clock input A
TCLKA
Input
External clock A input pin
(phase-A input pin in phase counting mode)
Clock input B
TCLKB
Input
External clock B input pin
(phase-B input pin in phase counting mode)
Clock input C
TCLKC
Input
External clock C input pin
Clock input D
TCLKD
Input
External clock D input pin
Input capture/output TIOCA0
compare A0
Input/
output
GRA0 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output TIOCB0
compare B0
Input/
output
GRB0 output compare or input capture pin
Input capture/output TIOCA1
compare A1
Input/
output
GRA1 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output TIOCB1
compare B1
Input/
output
GRB1 output compare or input capture pin
Input capture/output TIOCA2
compare A2
Input/
output
GRA2 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output TIOCB2
compare B2
Input/
output
GRB2 output compare or input capture pin
0
1
2
Rev.5.00 Sep. 12, 2007 Page 290 of 764
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Function
9. 16-Bit Timer
9.1.4
Register Configuration
Table 9.3 summarizes the 16-bit timer registers.
Table 9.3
16-bit timer Registers
Channel
Address*
Name
Abbreviation
R/W
Initial
Value
Common
H'FFF60
Timer start register
TSTR
R/W
H'F8
H'FFF61
Timer synchro register
TSNC
R/W
H'F8
H'FFF62
Timer mode register
TMDR
R/W
H'98
H'FFF63
Timer output level setting register
TOLR
W
H'C0
H'FFF64
Timer interrupt status register A
TISRA
R/(W)* H'88
H'FFF65
Timer interrupt status register B
TISRB
R/(W)* H'88
H'FFF66
Timer interrupt status register C
TISRC
R/(W)* H'88
H'FFF68
Timer control register 0
16TCR0
R/W
H'80
H'FFF69
Timer I/O control register 0
TIOR0
R/W
H'88
H'FFF6A
Timer counter 0H
16TCNT0H
R/W
H'00
H'FFF6B
Timer counter 0L
16TCNT0L
R/W
H'00
H'FFF6C
General register A0H
GRA0H
R/W
H'FF
H'FFF6D
General register A0L
GRA0L
R/W
H'FF
H'FFF6E
General register B0H
GRB0H
R/W
H'FF
H'FFF6F
General register B0L
GRB0L
R/W
H'FF
H'FFF70
Timer control register 1
16TCR1
R/W
H'80
H'FFF71
Timer I/O control register 1
TIOR1
R/W
H'88
H'FFF72
Timer counter 1H
16TCNT1H
R/W
H'00
0
1
1
2
2
2
H'FFF73
Timer counter 1L
16TCNT1L
R/W
H'00
H'FFF74
General register A1H
GRA1H
R/W
H'FF
H'FFF75
General register A1L
GRA1L
R/W
H'FF
H'FFF76
General register B1H
GRB1H
R/W
H'FF
H'FFF77
General register B1L
GRB1L
R/W
H'FF
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9. 16-Bit Timer
Channel
Address*
Name
Abbreviation
R/W
Initial
Value
2
H'FFF78
Timer control register 2
16TCR2
R/W
H'80
H'FFF79
Timer I/O control register 2
TIOR2
R/W
H'88
H'FFF7A
Timer counter 2H
16TCNT2H
R/W
H'00
H'FFF7B
Timer counter 2L
16TCNT2L
R/W
H'00
H'FFF7C
General register A2H
GRA2H
R/W
H'FF
H'FFF7D
General register A2L
GRA2L
R/W
H'FF
H'FFF7E
General register B2H
GRB2H
R/W
H'FF
H'FFF7F
General register B2L
GRB2L
R/W
H'FF
1
Notes: 1. The lower 20 bits of the address in advanced mode are indicated.
2. Only 0 can be written in bits 3 to 0, to clear the flags.
9.2
Register Descriptions
9.2.1
Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that starts and stops the timer counter (16TCNT) in
channels 0 to 2.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
STR2
STR1
STR0
Initial value
1
1
1
1
1
0
0
0
Read/Write
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
Reserved bits
Counter start 2 to 0
These bits start and
stop 16TCNT2 to 16TCNT0
TSTR is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3⎯Reserved: These bits cannot be modified and are always read as 1.
Bit 2⎯Counter Start 2 (STR2): Starts and stops timer counter 2 (16TCNT2).
Bit 2
STR2
Description
0
16TCNT2 is halted
1
16TCNT2 is counting
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(Initial value)
9. 16-Bit Timer
Bit 1⎯Counter Start 1 (STR1): Starts and stops timer counter 1 (16TCNT1).
Bit 1
STR1
Description
0
16TCNT1 is halted
1
16TCNT1 is counting
(Initial value)
Bit 0⎯Counter Start 0 (STR0): Starts and stops timer counter 0 (16TCNT0).
Bit 0
STR0
Description
0
16TCNT0 is halted
1
16TCNT0 is counting
9.2.2
(Initial value)
Timer Synchro Register (TSNC)
TSNC is an 8-bit readable/writable register that selects whether channels 0 to 2 operate
independently or synchronously. Channels are synchronized by setting the corresponding bits to 1.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
SYNC2
SYNC1
SYNC0
Initial value
1
1
1
1
1
0
0
0
Read/Write
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
Reserved bits
Timer sync 2 to 0
These bits synchronize
channels 2 to 0
TSNC is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3⎯Reserved: These bits cannot be modified and are always read as 1.
Bit 2⎯Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or
synchronously.
Bit 2
SYNC2
Description
0
Channel 2's timer counter (16TCNT2) operates independently
16TCNT2 is preset and cleared independently of other channels
1
Channel 2 operates synchronously
16TCNT2 can be synchronously preset and cleared
(Initial value)
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9. 16-Bit Timer
Bit 1⎯Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or
synchronously.
Bit 1
SYNC1
Description
0
Channel 1's timer counter (16TCNT1) operates independently
16TCNT1 is preset and cleared independently of other channels
1
Channel 1 operates synchronously
16TCNT1 can be synchronously preset and cleared
(Initial value)
Bit 0⎯Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or
synchronously.
Bit 0
SYNC0
Description
0
Channel 0's timer counter (16TCNT0) operates independently
16TCNT0 is preset and cleared independently of other channels
1
Channel 0 operates synchronously
16TCNT0 can be synchronously preset and cleared
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(Initial value)
9. 16-Bit Timer
9.2.3
Timer Mode Register (TMDR)
TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit
7
6
5
4
3
2
1
0
⎯
MDF
FDIR
⎯
⎯
PWM2
PWM1
PWM0
Initial value
1
0
0
1
1
0
0
0
Read/Write
⎯
R/W
R/W
⎯
⎯
R/W
R/W
R/W
Reserved bit
PWM mode 2 to 0
These bits select PWM
mode for channels 2 to 0
Flag direction
Selects the setting condition for the overflow
flag (OVF) in TISRC
Phase counting mode flag
Selects phase counting mode for channel 2
Reserved bit
TMDR is initialized to H'98 by a reset and in standby mode.
Bit 7⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 6⎯Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6
MDF
Description
0
Channel 2 operates normally
1
Channel 2 operates in phase counting mode
(Initial value)
When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter
and pins TCLKA and TCLKB become counter clock input pins. 16TCNT2 counts both rising and
falling edges of TCLKA and TCLKB, and counts up or down as follows.
Counting Direction
Down-Counting
TCLKA pin
TCLKB pin
Up-Counting
High
Low
Low
High
Low
High
High
Low
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9. 16-Bit Timer
In phase counting mode channel 2 operates as above regardless of the external clock edges
selected by bits CKEG1 and CKEG0 and the clock source selected by bits TPSC2 to TPSC0.
Phase counting mode takes precedence over these settings.
The counter clearing condition selected by the CCLR1 and CCLR0 bits in 16TCR2 and the
compare match/input capture settings and interrupt functions of TIOR2, TISRA, TISRB, TISRC
remain effective in phase counting mode.
Bit 5⎯Flag Direction (FDIR): Designates the setting condition for the OVF flag in TISRC. The
FDIR designation is valid in all modes in channel 2.
Bit 5
FDIR
Description
0
OVF is set to 1 in TISRC when 16TCNT2 overflows or underflows
1
OVF is set to 1 in TISRC when 16TCNT2 overflows
(Initial value)
Bits 4 and 3⎯Reserved: These bits cannot be modified and are always read as 1.
Bit 2⎯PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode.
Bit 2
PWM2
Description
0
Channel 2 operates normally
1
Channel 2 operates in PWM mode
(Initial value)
When bit PWM2 is set to 1 to select PWM mode, pin TIOCA2 becomes a PWM output pin. The
output goes to 1 at compare match with GRA2, and to 0 at compare match with GRB2.
Bit 1⎯PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode.
Bit 1
PWM1
Description
0
Channel 1 operates normally
1
Channel 1 operates in PWM mode
(Initial value)
When bit PWM1 is set to 1 to select PWM mode, pin TIOCA1 becomes a PWM output pin. The
output goes to 1 at compare match with GRA1, and to 0 at compare match with GRB1.
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9. 16-Bit Timer
Bit 0⎯PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode.
Bit 0
PWM0
Description
0
Channel 0 operates normally
1
Channel 0 operates in PWM mode
(Initial value)
When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The
output goes to 1 at compare match with GRA0, and to 0 at compare match with GRB0.
9.2.4
Timer Interrupt Status Register A (TISRA)
TISRA is an 8-bit readable/writable register that indicates GRA compare match or input capture
and enables or disables general register compare match and input capture interrupt requests.
Bit
7
⎯
6
5
4
IMIEA2 IMIEA1 IMIEA0
3
2
1
0
⎯
IMFA2
IMFA1
IMFA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
⎯
R/W
R/W
R/W
⎯
R/(W)*
R/(W)*
R/(W)*
Input capture/compare match
flags A2 to A0
Status flags indicating GRA
compare match or input capture
Reserved bit
Input capture/compare match interrupt enable A2 to A0
These bits enable or disable interrupts by the IMFA flags
Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRA is initialized to H'88 by a reset and in standby mode.
Bit 7⎯Reserved: This bit cannot be modified and is always read as 1.
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9. 16-Bit Timer
Bit 6⎯Input Capture/Compare Match Interrupt Enable A2 (IMIEA2): Enables or disables
the interrupt requested by the IMFA2 flag when IMFA2 is set to 1.
Bit 6
IMIEA2
Description
0
IMIA2 interrupt requested by IMFA2 flag is disabled
1
IMIA2 interrupt requested by IMFA2 flag is enabled
(Initial value)
Bit 5⎯Input Capture/Compare Match Interrupt Enable A1 (IMIEA1): Enables or disables
the interrupt requested by the IMFA1 flag when IMFA1 is set to 1.
Bit 5
IMIEA1
Description
0
IMIA1 interrupt requested by IMFA1 flag is disabled
1
IMIA1 interrupt requested by IMFA1 flag is enabled
(Initial value)
Bit 4⎯Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables
the interrupt requested by the IMFA0 flag when IMFA0 is set to 1.
Bit 4
IMIEA0
Description
0
IMIA0 interrupt requested by IMFA0 flag is disabled
1
IMIA0 interrupt requested by IMFA0 flag is enabled
(Initial value)
Bit 3⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 2⎯Input Capture/Compare Match Flag A2 (IMFA2): This status flag indicates GRA2
compare match or input capture events.
Bit 2
IMFA2
Description
0
[Clearing conditions]
1
•
Read IMFA2 when IMFA2 =1, then write 0 in IMFA2.
•
DMAC activated by IMIA2 interrupt.
(Initial value)
[Setting conditions]
•
16TCNT2 = GRA2 when GRA2 functions as an output compare register.
•
16TCNT2 value is transferred to GRA2 by an input capture signal when GRA2
functions as an input capture register.
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9. 16-Bit Timer
Bit 1⎯Input Capture/Compare Match Flag A1 (IMFA1): This status flag indicates GRA1
compare match or input capture events.
Bit 1
IMFA1
Description
0
[Clearing conditions]
1
(Initial value)
•
Read IMFA1 when IMFA1 =1, then write 0 in IMFA1.
•
DMAC activated by IMIA1 interrupt.
[Setting conditions]
•
16TCNT1 = GRA1 when GRA1 functions as an output compare register.
•
16TCNT1 value is transferred to GRA1 by an input capture signal when GRA1
functions as an input capture register.
Bit 0⎯Input Capture/Compare Match Flag A0 (IMFA0): This status flag indicates GRA0
compare match or input capture events.
Bit 0
IMFA0
Description
0
[Clearing conditions]
1
(Initial value)
•
Read IMFA0 when IMFA0 =1, then write 0 in IMFA0.
•
DMAC activated by IMIA0 interrupt.
[Setting conditions]
•
16TCNT0 = GRA0 when GRA0 functions as an output compare register.
•
16TCNT0 value is transferred to GRA0 by an input capture signal when GRA0
functions as an input capture register.
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9. 16-Bit Timer
9.2.5
Timer Interrupt Status Register B (TISRB)
TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture
and enables or disables general register compare match and input capture interrupt requests.
Bit
7
⎯
6
5
4
IMIEB2 IMIEB1 IMIEB0
3
2
1
0
⎯
IMFB2
IMFB1
IMFB0
Initial value
1
0
0
0
1
0
0
0
Read/Write
⎯
R/W
R/W
R/W
⎯
R/(W)*
R/(W)*
R/(W)*
Input capture/compare match
flags B2 to B0
Status flags indicating GRB
compare match or input capture
Reserved bit
Input capture/compare match interrupt enable B2 to B0
These bits enable or disable interrupts by the IMFB flags
Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRB is initialized to H'88 by a reset and in standby mode.
Bit 7⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 6⎯Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables
the interrupt requested by the IMFB2 flag when IMFB2 is set to 1.
Bit 6
IMIEB2
Description
0
IMIB2 interrupt requested by IMFB2 flag is disabled
1
IMIB2 interrupt requested by IMFB2 flag is enabled
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(Initial value)
9. 16-Bit Timer
Bit 5⎯Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables
the interrupt requested by the IMFB1 flag when IMFB1 is set to 1.
Bit 5
IMIEB1
Description
0
IMIB1 interrupt requested by IMFB1 flag is disabled
1
IMIB1 interrupt requested by IMFB1 flag is enabled
(Initial value)
Bit 4⎯Input Capture/Compare Match Interrupt Enable B0 (IMIEB0): Enables or disables
the interrupt requested by the IMFB0 flag when IMFB0 is set to 1.
Bit 4
IMIEB0
Description
0
IMIB0 interrupt requested by IMFB0 flag is disabled
1
IMIB0 interrupt requested by IMFB0 flag is enabled
(Initial value)
Bit 3⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 2⎯Input Capture/Compare Match Flag B2 (IMFB2): This status flag indicates GRB2
compare match or input capture events.
Bit 2
IMFB2
Description
0
[Clearing condition]
(Initial value)
Read IMFB2 when IMFB2 =1, then write 0 in IMFB2.
1
[Setting conditions]
•
16TCNT2 = GRB2 when GRB2 functions as an output compare register.
•
16TCNT2 value is transferred to GRB2 by an input capture signal when GRB2
functions as an input capture register.
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9. 16-Bit Timer
Bit 1⎯Input Capture/Compare Match Flag B1 (IMFB1): This status flag indicates GRB1
compare match or input capture events.
Bit 1
IMFB1
Description
0
[Clearing condition]
(Initial value)
Read IMFB1 when IMFB1 =1, then write 0 in IMFB1.
1
[Setting conditions]
•
16TCNT1 = GRB1 when GRB1 functions as an output compare register.
•
16TCNT1 value is transferred to GRB1 by an input capture signal when GRB1
functions as an input capture register.
Bit 0⎯Input Capture/Compare Match Flag B0 (IMFB0): This status flag indicates GRB0
compare match or input capture events.
Bit 0
IMFB0
Description
0
[Clearing condition]
(Initial value)
Read IMFB0 when IMFB0 =1, then write 0 in IMFB0.
1
[Setting conditions]
•
16TCNT0 = GRB0 when GRB0 functions as an output compare register.
•
16TCNT0 value is transferred to GRB0 by an input capture signal when GRB0
functions as an input capture register.
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9. 16-Bit Timer
9.2.6
Timer Interrupt Status Register C (TISRC)
TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and
enables or disables overflow interrupt requests.
Bit
7
6
5
4
3
2
1
0
⎯
OVIE2
OVIE1
OVIE0
⎯
OVF2
OVF1
OVF0
Initial value
1
0
0
0
1
0
0
0
Read/Write
⎯
R/W
R/W
R/W
⎯
R/(W)*
R/(W)*
R/(W)*
Overflow flags 2 to 0
Status flags indicating
interrupts by OVF flags
Reserved bit
Overflow interrupt enable 2 to 0
These bits enable or disable interrupts by the OVF flags
Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRC is initialized to H'88 by a reset and in standby mode.
Bit 7⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 6⎯Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by the
OVF2 flag when OVF2 is set to 1.
Bit 6
OVIE2
Description
0
OVI2 interrupt requested by OVF2 flag is disabled
1
OVI2 interrupt requested by OVF2 flag is enabled
(Initial value)
Bit 5⎯Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by the
OVF1 flag when OVF1 is set to 1.
Bit 5
OVIE1
Description
0
OVI1 interrupt requested by OVF1 flag is disabled
1
OVI1 interrupt requested by OVF1 flag is enabled
(Initial value)
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9. 16-Bit Timer
Bit 4⎯Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by the
OVF0 flag when OVF0 is set to 1.
Bit 4
OVIE0
Description
0
OVI0 interrupt requested by OVF0 flag is disabled
1
OVI0 interrupt requested by OVF0 flag is enabled
(Initial value)
Bit 3⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 2⎯Overflow Flag 2 (OVF2): This status flag indicates 16TCNT2 overflow.
Bit 2
OVF2
Description
0
[Clearing condition]
Read OVF2 when OVF2 =1, then write 0 in OVF2.
(Initial value)
1
[Setting condition]
16TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF.
Note: 16TCNT underflow occurs when 16TCNT operates as an up/down-counter. Underflow
occurs only when channel 2 operates in phase counting mode (MDF = 1 in TMDR).
Bit 1⎯Overflow Flag 1 (OVF1): This status flag indicates 16TCNT1 overflow.
Bit 1
OVF1
Description
0
[Clearing condition]
Read OVF1 when OVF1 =1, then write 0 in OVF1.
1
[Setting condition]
16TCNT1 overflowed from H'FFFF to H'0000.
(Initial value)
Bit 0⎯Overflow Flag 0 (OVF0): This status flag indicates 16TCNT0 overflow.
Bit 0
OVF0
Description
0
[Clearing condition]
Read OVF0 when OVF0 =1, then write 0 in OVF0.
1
[Setting condition]
16TCNT0 overflowed from H'FFFF to H'0000.
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REJ09B0396-0500
(Initial value)
9. 16-Bit Timer
9.2.7
Timer Counters (16TCNT)
16TCNT is a 16-bit counter. The 16-bit timer has three 16TCNTs, one for each channel.
Channel
Abbreviation
Function
0
16TCNT0
Up-counter
1
16TCNT1
2
16TCNT2
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
Phase counting mode: up/down-counter
Other modes: up-counter
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Each 16TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source.
The clock source is selected by bits TPSC2 to TPSC0 in 16TCR.
16TCNT0 and 16TCNT1 are up-counters. 16TCNT2 is an up/down-counter in phase counting
mode and an up-counter in other modes.
16TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to
GRA or GRB (counter clearing function).
When 16TCNT overflows (changes from H'FFFF to H'0000), the OVF flag is set to 1 in TISRC of
the corresponding channel.
When 16TCNT underflows (changes from H'0000 to H'FFFF), the OVF flag is set to 1 in TISRC
of the corresponding channel.
The 16TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either
word access or byte access.
Each 16TCNT is initialized to H'0000 by a reset and in standby mode.
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9. 16-Bit Timer
9.2.8
General Registers (GRA, GRB)
The general registers are 16-bit registers. The 16-bit timer has 6 general registers, two in each
channel.
Channel
Abbreviation
Function
0
GRA0, GRB0
Output compare/input capture register
1
GRA1, GRB1
2
GRA2, GRB2
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
A general register is a 16-bit readable/writable register that can function as either an output
compare register or an input capture register. The function is selected by settings in TIOR.
When a general register is used as an output compare register, its value is constantly compared
with the 16TCNT value. When the two values match (compare match), the IMFA or IMFB flag is
set to 1 in TISRA/TISRB. Compare match output can be selected in TIOR.
When a general register is used as an input capture register an external input capture signal are
detected and the current 16TCNT value is stored in the general register. The corresponding IMFA
or IMFB flag in TISRA/TISRB is set to 1 at the same time. The valid edge or edges of the input
capture signal are selected in TIOR.
TIOR settings are ignored in PWM mode.
General registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word access or byte access.
General registers are initialized to the output compare function (with no output signal) by a reset
and in standby mode. The initial value is H'FFFF.
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9. 16-Bit Timer
9.2.9
Timer Control Registers (16TCR)
16TCR is an 8-bit register. The 16-bit timer has three 16TCRs, one in each channel.
Channel
Abbreviation
Function
0
16TCR0
1
16TCR1
2
16TCR2
CR controls the timer counter. The 16TCRs in all channels are
functionally identical. When phase counting mode is selected in
channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2
to TPSC0 in 16TCR2 are ignored.
Bit
7
6
5
⎯
CCLR1
CCLR0
4
3
CKEG1 CKEG0
2
1
0
TPSC2
TPSC1
TPSC0
Initial value
1
0
0
0
0
0
0
0
Read/Write
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer prescaler 2 to 0
These bits select the
counter clock
Clock edge 1/0
These bits select external clock edges
Counter clear 1/0
These bits select the counter clear source
Reserved bit
Each 16TCR is an 8-bit readable/writable register that selects the timer counter clock source,
selects the edge or edges of external clock sources, and selects how the counter is cleared.
16TCR is initialized to H'80 by a reset and in standby mode.
Bit 7⎯Reserved: This bit cannot be modified and is always read as 1.
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9. 16-Bit Timer
Bits 6 and 5⎯Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select how 16TCNT is
cleared.
Bit 6
CCLR1
Bit 5
CCLR0
Description
0
0
16TCNT is not cleared
1
(Initial value)
1
1
16TCNT is cleared by GRA compare match or input capture*
0
16TCNT is cleared by GRB compare match or input capture*
1
Synchronous clear: 16TCNT is cleared in synchronization with other
2
synchronized timers*
1
Notes: 1. 16TCNT is cleared by compare match when the general register functions as an output
compare register, and by input capture when the general register functions as an input
capture register.
2. Selected in TSNC.
Bits 4 and 3⎯Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select external clock input
edges when an external clock source is used.
Bit 4
CKEG1
Bit 3
CKEG0
Description
0
0
Count rising edges
1
Count falling edges
⎯
Count both edges
1
(Initial value)
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in 16TCR2 are ignored.
Phase counting takes precedence.
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9. 16-Bit Timer
Bits 2 to 0⎯Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock
source.
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Function
0
0
0
Internal clock: φ
1
Internal clock: φ/2
0
Internal clock: φ/4
1
Internal clock: φ/8
0
External clock A: TCLKA input
1
External clock B: TCLKB input
0
External clock C: TCLKC input
1
External clock D: TCLKD input
1
1
0
1
(Initial value)
When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only
falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts
the edge or edges selected by bits CKEG1 and CKEG0.
When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to
TPSC0 in 16TCR2 are ignored. Phase counting takes precedence.
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9. 16-Bit Timer
9.2.10
Timer I/O Control Register (TIOR)
TIOR is an 8-bit register. The 16-bit timer has three TIORs, one in each channel.
Channel Abbreviation Function
0
TIOR0
1
TIOR1
2
TIOR2
Bit
TIOR controls the general registers. Some functions differ in PWM
mode.
7
6
5
4
3
2
1
0
⎯
IOB2
IOB1
IOB0
⎯
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
⎯
R/W
R/W
R/W
⎯
R/W
R/W
R/W
I/O control A2 to A0
These bits select GRA
functions
Reserved bit
I/O control B2 to B0
These bits select GRB functions
Reserved bit
Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture
function for GRA and GRB, and specifies the functions of the TIORA and TIORC pins. If the
output compare function is selected, TIOR also selects the type of output. If input capture is
selected, TIOR also selects the edge or edges of the input capture signal.
TIOR is initialized to H'88 by a reset and in standby mode.
Bit 7⎯Reserved: This bit cannot be modified and is always read as 1.
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9. 16-Bit Timer
Bits 6 to 4⎯I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function.
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
0
0
0
1
0
No output at compare match
(Initial value)
1
0
1 output at GRB compare match*
1
1
Output toggles at GRB compare match
1 2
(1 output in channel 2)* *
0
1
1
GRB is an output
compare register
0 output at GRB compare match*
1
1
Function
GRB is an input
compare register
0
GRB captures rising edge of input
GRB captures falling edge of input
GRB captures both edges of input
1
Notes: 1. After a reset, the output conforms to the TOLR setting until the first compare match.
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
instead.
Bit 3⎯Reserved: This bit cannot be modified and is always read as 1.
Bits 2 to 0⎯I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
0
0
0
1
GRA is an output
compare register
No output at compare match
(Initial value)
0 output at GRA compare match*
1
0
1 output at GRA compare match*
1
1
Output toggles at GRA compare match
1 2
(1 output in channel 2)* *
1
1
Function
0
0
1
0
1
GRA is an input
compare register
GRA captures rising edge of input
GRA captures falling edge of input
GRA captures both edges of input
1
Notes: 1. After a reset, the output conforms to the TOLR setting until the first compare match.
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
instead.
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9. 16-Bit Timer
9.2.11
Timer Output Level Setting Register C (TOLR)
TOLR is an 8-bit write-only register that selects the timer output level for channels 0 to 2.
7
6
5
4
3
2
1
0
⎯
⎯
TOB2
TOA2
TOB1
TOA1
TOB0
TOA0
Initial value
1
1
0
0
0
0
0
0
Read/Write
⎯
⎯
W
W
W
W
W
W
Bit
Output level setting A2 to A0, B2 to B0
These bits set the levels of the timer outputs
(TIOCA2 to TIOCA0, and TIOCB2 to TIOCB0)
Reserved bits
A TOLR setting can only be made when the corresponding bit in TSTR is 0.
TOLR is a write-only register. If it is read, all bits will return a value of 1.
TOLR is initialized to H'C0 by a reset and in standby mode.
Bits 7 and 6⎯Reserved: These bits cannot be modified.
Bit 5⎯Output Level Setting B2 (TOB2): Sets the value of timer output TIOCB2.
Bit 5
TOB2
Description
0
TIOCB2 is 0
1
TIOCB2 is 1
(Initial value)
Bit 4⎯Output Level Setting A2 (TOA2): Sets the value of timer output TIOCA2.
Bit 4
TOA2
Description
0
TIOCA2 is 0
1
TIOCA2 is 1
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(Initial value)
9. 16-Bit Timer
Bit 3⎯Output Level Setting B1 (TOB1): Sets the value of timer output TIOCB1.
Bit 3
TOB1
Description
0
TIOCB1 is 0
1
TIOCB1 is 1
(Initial value)
Bit 2⎯Output Level Setting A1 (TOA1): Sets the value of timer output TIOCA1.
Bit 2
TOA1
Description
0
TIOCA1 is 0
1
TIOCA1 is 1
(Initial value)
Bit 1⎯Output Level Setting B0 (TOB0): Sets the value of timer output TIOCB0.
Bit 0
TOB0
Description
0
TIOCB0 is 0
1
TIOCB0 is 1
(Initial value)
Bit 0⎯Output Level Setting A0 (TOA0): Sets the value of timer output TIOCA0.
Bit 0
TOA0
Description
0
TIOCA0 is 0
1
TIOCA0 is 1
(Initial value)
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9. 16-Bit Timer
9.3
CPU Interface
9.3.1
16-Bit Accessible Registers
The timer counters (16TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers,
and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a
word at a time, or a byte at a time.
Figures 9.4 and 9.5 show examples of word read/write access to a timer counter (16TCNT).
Figures 9.6, 9.7, 9.8, and 9.9 show examples of byte read/write access to 16TCNTH and
16TCNTL.
On-chip data bus
H
CPU
L
H
Bus interface
L
16TCNTH
Module
data bus
16TCNTL
Figure 9.4 Access to Timer Counter (CPU Writes to 16TCNT, Word)
On-chip data bus
H
CPU
L
H
Bus interface
L
16TCNTH
16TCNTL
Figure 9.5 Access to Timer Counter (CPU Reads 16TCNT, Word)
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Module
data bus
9. 16-Bit Timer
On-chip data bus
H
CPU
L
H
Bus interface
L
16TCNTH
Module
data bus
16TCNTL
Figure 9.6 Access to Timer Counter (CPU Writes to 16TCNTH, Upper Byte)
On-chip data bus
H
CPU
L
H
Bus interface
L
16TCNTH
Module
data bus
16TCNTL
Figure 9.7 Access to Timer Counter (CPU Writes to 16TCNTL, Lower Byte)
On-chip data bus
H
CPU
L
H
Bus interface
L
16TCNTH
Module
data bus
16TCNTL
Figure 9.8 Access to Timer Counter (CPU Reads 16TCNTH, Upper Byte)
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9. 16-Bit Timer
On-chip data bus
H
CPU
H
L
Bus interface
L
16TCNTH
Module
data bus
16TCNTL
Figure 9.9 Access to Timer Counter (CPU Reads 16TCNTL, Lower Byte)
9.3.2
8-Bit Accessible Registers
The registers other than the timer counters and general registers are 8-bit registers. These registers
are linked to the CPU by an internal 8-bit data bus.
Figures 9.10 and 9.11 show examples of byte read and write access to a 16TCR.
If a word-size data transfer instruction is executed, two byte transfers are performed.
On-chip data bus
H
CPU
H
L
Bus interface
L
Module
data bus
16TCR
Figure 9.10 16TCR Access (CPU Writes to 16TCR)
On-chip data bus
H
CPU
L
H
Bus interface
L
16TCR
Figure 9.11 16TCR Access (CPU Reads 16TCR)
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Module
data bus
9. 16-Bit Timer
9.4
Operation
9.4.1
Overview
A summary of operations in the various modes is given below.
Normal Operation: Each channel has a timer counter and general registers. The timer counter
counts up, and can operate as a free-running counter, periodic counter, or external event counter.
General registers A and B can be used for input capture or output compare.
Synchronous Operation: The timer counters in designated channels are preset synchronously.
Data written to the timer counter in any one of these channels is simultaneously written to the
timer counters in the other channels as well. The timer counters can also be cleared synchronously
if so designated by the CCLR1 and CCLR0 bits in the 16TCRs.
PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare
match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending
on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB
automatically become output compare registers.
Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and
TCLKB is detected and 16TCNT2 counts up or down accordingly. When phase counting mode is
selected TCLKA and TCLKB become clock input pins and 16TCNT2 operates as an up/downcounter.
9.4.2
Basic Functions
Counter Operation: When one of bits STR0 to STR2 is set to 1 in the timer start register (TSTR),
the timer counter (16TCNT) in the corresponding channel starts counting. The counting can be
free-running or periodic.
• Sample setup procedure for counter
Figure 9.12 shows a sample procedure for setting up a counter.
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9. 16-Bit Timer
Counter setup
Select counter clock
Type of counting?
1
No
Yes
Free-running counting
Periodic counting
Select counter clear source
2
Select output compare
register function
3
Set period
4
Start counter
5
Periodic counter
Start counter
5
Free-running counter
Figure 9.12 Counter Setup Procedure (Example)
1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock
source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of
the external clock signal.
2. For periodic counting, set CCLR1 and CCLR0 in 16TCR to have 16TCNT cleared at GRA
compare match or GRB compare match.
3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected
in step 2.
4. Write the count period in GRA or GRB, whichever was selected in step 2.
5. Set the STR bit to 1 in TSTR to start the timer counter.
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9. 16-Bit Timer
• Free-running and periodic counter operation
A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running
counters. A free-running counter starts counting up when the corresponding bit in TSTR is set
to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC.
After the overflow, the counter continues counting up from H'0000. Figure 9.13 illustrates
free-running counting.
16TCNT value
H'FFFF
H'0000
Time
STR0 to
STR2 bit
OVF
Figure 9.13 Free-Running Counter Operation
When a channel is set to have its counter cleared by compare match, in that channel 16TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit CCLR1
or CCLR0 in 16TCR to have the counter cleared by compare match, and set the count period in
GRA or GRB. After these settings, the counter starts counting up as a periodic counter when the
corresponding bit is set to 1 in TSTR. When the count matches GRA or GRB, the IMFA or IMFB
flag is set to 1 in TISRA/TISRB and the counter is cleared to H'0000. If the corresponding IMIEA
or IMIEB bit is set to 1 in TISRA/TISRB, a CPU interrupt is requested at this time. After the
compare match, 16TCNT continues counting up from H'0000. Figure 9.14 illustrates periodic
counting.
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9. 16-Bit Timer
16TCNT value
Counter cleared by general
register compare match
GR
Time
H'0000
STR bit
IMF
Figure 9.14 Periodic Counter Operation
• 16TCNT count timing
⎯ Internal clock source
Bits TPSC2 to TPSC0 in 16TCR select the system clock (φ) or one of three internal clock
sources obtained by prescaling the system clock (φ/2, φ/4, φ/8).
Figure 9.15 shows the timing.
φ
Internal
clock
16TCNT input
clock
16TCNT
N−1
N
N+1
Figure 9.15 Count Timing for Internal Clock Sources
⎯ External clock source
Bits TPSC2 to TPSC0 in 16TCR select an external clock input pin (TCLKA to TCLKD),
and its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge,
falling edge, or both edges can be selected.
The pulse width of the external clock signal must be at least 1.5 system clocks when a
single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter
pulses will not be counted correctly.
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9. 16-Bit Timer
Figure 9.16 shows the timing when both edges are detected.
φ
External
clock input
16TCNT input
clock
16TCNT
N–1
N
N+1
Figure 9.16 Count Timing for External Clock Sources (when Both Edges Are Detected)
Waveform Output by Compare Match: In 16-bit timer channels 0, 1 compare match A or B can
cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output
can only go to 0 or go to 1.
• Sample setup procedure for waveform output by compare match
Figure 9.17 shows an example of the setup procedure for waveform output by compare match.
Output setup
1. Select the compare match output mode (0, 1, or
toggle) in TIOR. When a waveform output mode
is selected, the pin switches from its generic input/
output function to the output compare function
(TIOCA or TIOCB). An output compare pin outputs
the value set in TOLR until the first compare match
occurs.
Select waveform
output mode
1
Set output timing
2
2. Set a value in GRA or GRB to designate the
compare match timing.
Start counter
3
3. Set the STR bit to 1 in TSTR to start the timer
counter.
Waveform output
Figure 9.17 Setup Procedure for Waveform Output by Compare Match (Example)
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9. 16-Bit Timer
• Examples of waveform output
Figure 9.18 shows examples of 0 and 1 output. 16TCNT operates as a free-running counter, 0
output is selected for compare match A, and 1 output is selected for compare match B. When
the pin is already at the selected output level, the pin level does not change.
16TCNT value
H'FFFF
GRB
GRA
H'0000
Time
TIOCB
No change
No change
TIOCA
No change
No change
1 output
0 output
Figure 9.18 0 and 1 Output (TOA = 1, TOB = 0)
Figure 9.19 shows examples of toggle output. 16TCNT operates as a periodic counter, cleared by
compare match B. Toggle output is selected for both compare match A and B.
16TCNT value
Counter cleared by compare match with GRB
GRB
GRA
H'0000
Time
TIOCB
Toggle
output
TIOCA
Toggle
output
Figure 9.19 Toggle Output (TOA = 1, TOB = 0)
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9. 16-Bit Timer
• Output compare output timing
The compare match signal is generated in the last state in which 16TCNT and the general
register match (when 16TCNT changes from the matching value to the next value). When the
compare match signal is generated, the output value selected in TIOR is output at the output
compare pin (TIOCA or TIOCB). When 16TCNT matches a general register, the compare
match signal is not generated until the next counter clock pulse.
Figure 9.20 shows the output compare timing.
φ
16TCNT input
clock
16TCNT
N
GR
N
N+1
Compare
match signal
TIOCA,
TIOCB
Figure 9.20 Output Compare Output Timing
Input Capture Function: The 16TCNT value can be captured into a general register when a
transition occurs at an input capture/output compare pin (TIOCA or TIOCB). Capture can take
place on the rising edge, falling edge, or both edges. The input capture function can be used to
measure pulse width or period.
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9. 16-Bit Timer
• Sample setup procedure for input capture
Figure 9.21 shows a sample procedure for setting up input capture.
Input selection
1. Set TIOR to select the input capture function of a
general register and the rising edge, falling edge,
or both edges of the input capture signal. Clear the
DDR bit to 0 before making these TIOR settings.
Select input-capture input
1
Start counter
2
2. Set the STR bit to 1 in TSTR to start the timer
counter.
Input capture
Figure 9.21 Setup Procedure for Input Capture (Example)
• Examples of input capture
Figure 9.22 illustrates input capture when the falling edge of TIOCB and both edges of TIOCA
are selected as capture edges. 16TCNT is cleared by input capture into GRB.
16TCNT value
H'0180
H'0160
H'0005
H'0000
TIOCB
TIOCA
GRA
H'0005
H'0160
GRB
H'0180
Figure 9.22 Input Capture (Example)
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9. 16-Bit Timer
• Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in
TIOR. Figure 9.23 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system
clocks for capture of both edges.
φ
Input-capture input
Input capture signal
N
16TCNT
N
GRA, GRB
Figure 9.23 Input Capture Signal Timing
9.4.3
Synchronization
The synchronization function enables two or more timer counters to be synchronized by writing
the same data to them simultaneously (synchronous preset). With appropriate 16TCR settings, two
or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization
enables additional general registers to be associated with a single time base. Synchronization can
be selected for all channels (0 to 2).
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9. 16-Bit Timer
Sample Setup Procedure for Synchronization: Figure 9.24 shows a sample procedure for
setting up synchronization.
Setup for synchronization
Select synchronization
1
Synchronous preset
Write to 16TCNT
Synchronous clear
2
Clearing
synchronized to this
channel?
No
Yes
Synchronous preset
Select counter clear source
3
Select counter clear source
4
Start counter
5
Start counter
5
Counter clear
Synchronous clear
1. Set the SYNC bits to 1 in TSNC for the channels to be synchronized.
2. When a value is written in 16TCNT in one of the synchronized channels, the same value is
simultaneously written in 16TCNT in the other channels.
3. Set the CCLR1 or CCLR0 bit in 16TCR to have the counter cleared by compare match or input capture.
4. Set the CCLR1 and CCLR0 bits in 16TCR to have the counter cleared synchronously.
5. Set the STR bits in TSTR to 1 to start the synchronized counters.
Figure 9.24 Setup Procedure for Synchronization (Example)
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9. 16-Bit Timer
Example of Synchronization: Figure 9.25 shows an example of synchronization. Channels 0, 1,
and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing
by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The
timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by
compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA0, TIOCA1,
and TIOCA2. For further information on PWM mode, see section 9.4.4, PWM Mode.
Value of 16TCNT0 to 16TCNT2
Synchronous clearing by GRB0 compare match
GRB0
GRB1
GRA0
GRB2
GRA1
GRA2
H'0000
TIOCA0
TIOCA1
TIOCA2
Figure 9.25 Synchronization (Example)
9.4.4
PWM Mode
In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin.
GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which
the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a
PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin. PWM mode can
be selected in all channels (0 to 2).
Table 9.4 summarizes the PWM output pins and corresponding registers. If the same value is set
in GRA and GRB, the output does not change when compare match occurs.
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9. 16-Bit Timer
Table 9.4
PWM Output Pins and Registers
Channel
Output Pin
1 Output
0 Output
0
TIOCA0
GRA0
GRB0
1
TIOCA1
GRA1
GRB1
2
TIOCA2
GRA2
GRB2
Sample Setup Procedure for PWM Mode: Figure 9.26 shows a sample procedure for setting up
PWM mode.
PWM mode
Select counter clock
1
Select counter clear source
2
Set GRA
3
Set GRB
4
Select PWM mode
5
Start counter
6
PWM mode
1. Set bits TPSC2 to TPSC0 in 16TCR to
select the counter clock source. If an
external clock source is selected, set
bits CKEG1 and CKEG0 in 16TCR to
select the desired edge(s) of the
external clock signal.
2. Set bits CCLR1 and CCLR0 in 16TCR
to select the counter clear source.
3. Set the time at which the PWM
waveform should go to 1 in GRA.
4. Set the time at which the PWM
waveform should go to 0 in GRB.
5. Set the PWM bit in TMDR to select
PWM mode. When PWM mode is
selected, regardless of the TIOR
contents, GRA and GRB become
output compare registers specifying
the times at which the PWM output
goes to 1 and 0. The TIOCA pin
automatically becomes the PWM
output pin. The TIOCB pin conforms
to the settings of bits IOB1 and IOB0
in TIOR. If TIOCB output is not
desired, clear both IOB1 and IOB0 to 0.
6. Set the STR bit to 1 in TSTR to start
the timer counter.
Figure 9.26 Setup Procedure for PWM Mode (Example)
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9. 16-Bit Timer
Examples of PWM Mode: Figure 9.27 shows examples of operation in PWM mode. In PWM
mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0
at compare match with GRB.
In the examples shown, 16TCNT is cleared by compare match with GRA or GRB. Synchronized
operation and free-running counting are also possible.
16TCNT value
Counter cleared by compare match A
GRA
GRB
Time
H'0000
TIOCA
a. Counter cleared by GRA (TOA = 1)
16TCNT value
Counter cleared by compare match B
GRB
GRA
Time
H'0000
TIOCA
b. Counter cleared by GRB (TOA = 0)
Figure 9.27 PWM Mode (Example 1)
Figure 9.28 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%.
If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB,
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9. 16-Bit Timer
the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a
higher value than GRA, the duty cycle is 100%.
16TCNT value
Counter cleared by compare match B
GRB
GRA
H'0000
Time
TIOCA
Write to GRA
Write to GRA
a. 0% duty cycle (TOA = 0)
16TCNT value
Counter cleared by compare match A
GRA
GRB
H'0000
Time
TIOCA
Write to GRB
Write to GRB
b. 100% duty cycle (TOA = 1)
Figure 9.28 PWM Mode (Example 2)
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9. 16-Bit Timer
9.4.5
Phase Counting Mode
In phase counting mode the phase difference between two external clock inputs (at the TCLKA
and TCLKB pins) is detected, and 16TCNT2 counts up or down accordingly.
In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock
input pins and 16TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to
TPSC0, CKEG1, and CKEG0 in 16TCR2. Settings of bits CCLR1, CCLR0 in 16TCR2, and
settings in TIOR2, TISRA, TISRB, TISRC, STR2 in TSTR, GRA2, and GRB2 are valid. The
input capture and output compare functions can be used, and interrupts can be generated.
Phase counting is available only in channel 2.
Sample Setup Procedure for Phase Counting Mode: Figure 9.29 shows a sample procedure for
setting up phase counting mode.
Phase counting mode
Select phase counting mode
1
Select flag setting condition
2
Start counter
3
1. Set the MDF bit in TMDR to 1 to select
phase counting mode.
2. Select the flag setting condition with
the FDIR bit in TMDR.
3. Set the STR2 bit to 1 in TSTR to start
the timer counter.
Phase counting mode
Figure 9.29 Setup Procedure for Phase Counting Mode (Example)
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9. 16-Bit Timer
Example of Phase Counting Mode: Figure 9.30 shows an example of operations in phase
counting mode. Table 9.5 lists the up-counting and down-counting conditions for 16TCNT2.
In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The
phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must
also be at least 1.5 states, and the pulse width must be at least 2.5 states.
16TCNT2 value
Counting up
Counting down
TCLKB
TCLKA
Figure 9.30 Operation in Phase Counting Mode (Example)
Table 9.5
Up/Down Counting Conditions
Counting Direction
Down-Counting
TCLKB pin
Up-Counting
High
TCLKA pin
High
Low
Phase
difference
Low
Phase
difference
High
Low
Low
Pulse width
High
Pulse width
TCLKA
TCLKB
Overlap
Overlap
Phase difference and overlap: at least 1.5 states
Pulse width:
at least 2.5 states
Figure 9.31 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
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9. 16-Bit Timer
9.4.6
Setting Initial Value of 16-Bit Timer Output
Any desired value can be specified for the initial 16-bit timer output value when a timer count
operation is started by making a setting in TOLR.
Figure 9.32 shows the timing for setting the initial output value with TOLR.
Only write to TOLR when the corresponding bit in TSTR is cleared to 0.
T1
T3
T2
φ
Address bus
TOLR
16-bit timer output pin
TOLR address
N
N
Figure 9.32 Example of Timing for Setting Initial Value of 16-Bit Timer Output by Writing
to TOLR
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9. 16-Bit Timer
9.5
Interrupts
The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow
interrupts.
9.5.1
Setting of Status Flags
Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a
compare match signal generated when 16TCNT matches a general register (GR). The compare
match signal is generated in the last state in which the values match (when 16TCNT is updated
from the matching count to the next count). Therefore, when 16TCNT matches a general register,
the compare match signal is not generated until the next 16TCNT clock input. Figure 9.33 shows
the timing of the setting of IMFA and IMFB.
φ
16TCNT input
clock
16TCNT
N
GR
N+1
N
Compare
match signal
IMF
IMI
Figure 9.33 Timing of Setting of IMFA and IMFB by Compare Match
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9. 16-Bit Timer
Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an
input capture signal. The 16TCNT contents are simultaneously transferred to the corresponding
general register. Figure 9.34 shows the timing.
φ
Input capture
signal
IMF
16TCNT
N
GR
N
IMI
Figure 9.34 Timing of Setting of IMFA and IMFB by Input Capture
Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from
H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 9.35 shows the timing.
φ
16TCNT
Overflow
signal
OVF
OVI
Figure 9.35 Timing of Setting of OVF
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9. 16-Bit Timer
9.5.2
Timing of Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 9.36 shows the timing.
TISR write cycle
T1
T2
T3
φ
Address
TISR address
IMF, OVF
Figure 9.36 Timing of Clearing of Status Flags
9.5.3
Interrupt Sources and DMA Controller Activation
Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare
match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt sources
of three kinds, all independently vectored. An interrupt is requested when the interrupt request flag
are set to 1.
The priority order of the channels can be modified in interrupt priority register A (IPRA). For
details see section 5, Interrupt Controller.
Compare match/input capture A interrupts in channels 0 to 2 can activate the DMA controller
(DMAC). When the DMAC is activated a CPU interrupt is not requested.
Table 9.6 lists the interrupt sources.
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9. 16-Bit Timer
Table 9.6
16-bit timer Interrupt Sources
Channel
Interrupt
Source
Description
DMAC
Activatable
Priority*
0
IMIA0
Compare match/input capture A0
Yes
High
IMIB0
Compare match/input capture B0
No
OVI0
Overflow 0
No
IMIA1
Compare match/input capture A1
Yes
IMIB1
Compare match/input capture B1
No
OVI1
Overflow 1
No
IMIA2
Compare match/input capture A2
Yes
IMIB2
Compare match/input capture B2
No
OVI2
Overflow 2
No
1
2
Note:
*
Low
The priority immediately after a reset is indicated. Inter-channel priorities can be
changed by settings in IPRA.
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9. 16-Bit Timer
9.6
Usage Notes
This section describes contention and other matters requiring special attention during 16-bit timer
operations.
Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T3 state of
a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See
figure 9.37.
16TCNT write cycle
T2
T1
T3
φ
Address bus
16TCNT address
Internal write signal
Counter clear signal
16TCNT
N
H'0000
Figure 9.37 Contention between 16TCNT Write and Clear
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9. 16-Bit Timer
Contention between 16TCNT Word Write and Increment: If an increment pulse occurs in the
T3 state of a 16TCNT word write cycle, writing takes priority and 16TCNT is not incremented.
Figure 9.38 shows the timing in this case.
16TCNT word write cycle
T2
T1
T3
φ
Address bus
16TCNT address
Internal write signal
16TCNT input clock
16TCNT
N
M
16TCNT write data
Figure 9.38 Contention between 16TCNT Word Write and Increment
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9. 16-Bit Timer
Contention between 16TCNT Byte Write and Increment: If an increment pulse occurs in the T2
or T3 state of a 16TCNT byte write cycle, writing takes priority and 16TCNT is not incremented.
The 16TCNT byte that was not written retains its previous value. See figure 9.39, which shows an
increment pulse occurring in the T2 state of a byte write to 16TCNTH.
16TCNTH byte write cycle
T1
T2
T3
φ
16TCNTH address
Address bus
Internal write signal
16TCNT input clock
16TCNTH
N
M
16TCNT write data
16TCNTL
X
X+1
X
Figure 9.39 Contention between 16TCNT Byte Write and Increment
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9. 16-Bit Timer
Contention between General Register Write and Compare Match: If a compare match occurs
in the T3 state of a general register write cycle, writing takes priority and the compare match signal
is inhibited. See figure 9.40.
General register write cycle
T2
T1
T3
φ
Address bus
GR address
Internal write signal
16TCNT
N
GR
N
N+1
M
General register write data
Compare match signal
Inhibited
Figure 9.40 Contention between General Register Write and Compare Match
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9. 16-Bit Timer
Contention between 16TCNT Write and Overflow or Underflow: If an overflow occurs in the
T3 state of a 16TCNT write cycle, writing takes priority and the counter is not incremented. OVF
is set to 1. The same holds for underflow. See figure 9.41.
16TCNT write cycle
T1
T2
T3
φ
Address bus
16TCNT address
Internal write signal
16TCNT input clock
Overflow signal
16TCNT
H'FFFF
M
16TCNT write data
OVF
Figure 9.41 Contention between 16TCNT Write and Overflow
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9. 16-Bit Timer
Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T3 state of a general register read cycle, the value before input capture is read.
See figure 9.42.
General register read cycle
T2
T1
T3
φ
GR address
Address bus
Internal read signal
Input capture signal
GR
Internal data bus
X
M
X
Figure 9.42 Contention between General Register Read and Input Capture
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9. 16-Bit Timer
Contention between Counter Clearing by Input Capture and Counter Increment: If an input
capture signal and counter increment signal occur simultaneously, the counter is cleared according
to the input capture signal. The counter is not incremented by the increment signal. The value
before the counter is cleared is transferred to the general register. See figure 9.43.
φ
Input capture signal
Counter clear signal
16TCNT input clock
16TCNT
GR
N
H'0000
N
Figure 9.43 Contention between Counter Clearing by Input Capture and Counter
Increment
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9. 16-Bit Timer
Contention between General Register Write and Input Capture: If an input capture signal
occurs in the T3 state of a general register write cycle, input capture takes priority and the write to
the general register is not performed. See figure 9.44.
General register write cycle
T1
T2
T3
φ
Address bus
GR address
Internal write signal
Input capture signal
16TCNT
GR
M
M
Figure 9.44 Contention between General Register Write and Input Capture
Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is
cleared in the last state at which the 16TCNT value matches the general register value, at the time
when this value would normally be updated to the next count. The actual counter frequency is
therefore given by the following formula:
f=
φ
(N +1)
(f: counter frequency. φ: system clock frequency. N: value set in general register.)
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9. 16-Bit Timer
Note on Writes in Synchronized Operation: When channels are synchronized, if a 16TCNT
value is modified by byte write access, all 16 bits of all synchronized counters assume the same
value as the counter that was addressed.
(Example) When channels 1 and 2 are synchronized
• Byte write to channel 1 or byte write to channel 2
16TCNT1
W
X
16TCNT2
Y
Z
Upper byte Lower byte
Write A to upper byte
of channel 1
16TCNT1
A
X
16TCNT2
A
X
Upper byte Lower byte
Write A to lower byte
of channel 2
16TCNT1
Y
A
16TCNT2
Y
A
Upper byte Lower byte
• Word write to channel 1 or word write to channel 2
16TCNT1
W
X
16TCNT2
Y
Z
Write AB word to
channel 1 or 2
Upper byte Lower byte
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16TCNT1
A
B
16TCNT2
A
B
Upper byte Lower byte
9. 16-Bit Timer
16-bit timer Operating Modes
Table 9.7 (a)
16-bit timer Operating Modes (Channel 0)
Register Settings
TSNC
Operating Mode
Synchronization
Synchronous preset
TMDR
MDF
FDIR PWM
TIOR0
IOA
IOB
16TCR0
Clear
Select
SYNC0 = 1 ⎯
⎯
PWM mode
⎯
⎯
PWM0 = 1
⎯
Output compare A
⎯
⎯
PWM0 = 0
IOA2 = 0
Other bits
unrestricted
Output compare B
⎯
⎯
Input capture A
⎯
⎯
PWM0 = 0
Input capture B
⎯
⎯
PWM0 = 0
Counter By compare
clearing match/input
capture A
⎯
⎯
CCLR1 = 0
CCLR0 = 1
By compare
match/input
capture B
⎯
⎯
CCLR1 = 1
CCLR0 = 0
SYNC0 = 1 ⎯
⎯
CCLR1 = 1
CCLR0 = 1
Synchronous
clear
Clock
Select
*
IOB2 = 0
Other bits
unrestricted
IOA2 = 1
Other bits
unrestricted
IOB2 = 1
Other bits
unrestricted
Legend:
Setting available (valid)
⎯ Setting does not affect this mode
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur
simultaneously, the compare match signal is inhibited.
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9. 16-Bit Timer
Table 9.7 (b)
16-bit timer Operating Modes (Channel 1)
Register Settings
TSNC
TMDR
TIOR1
16TCR1
Operating Mode
Synchronization
Synchronous preset
SYNC1 = 1 ⎯
⎯
PWM mode
⎯
⎯
PWM1 = 1
⎯
Output compare A
⎯
⎯
PWM1 = 0
IOA2 = 0
Other bits
unrestricted
Output compare B
⎯
⎯
Input capture A
⎯
⎯
PWM1 = 0
Input capture B
⎯
⎯
PWM1 = 0
Counter By compare
clearing match/input
capture A
⎯
⎯
CCLR1 = 0
CCLR0 = 1
By compare
match/input
capture B
⎯
⎯
CCLR1 = 1
CCLR0 = 0
SYNC1 = 1 ⎯
⎯
CCLR1 = 1
CCLR0 = 1
Synchronous
clear
MDF
FDIR PWM
IOA
IOB
Clear
Select
Clock
Select
*
IOB2 = 0
Other bits
unrestricted
IOA2 = 1
Other bits
unrestricted
IOB2 = 1
Other bits
unrestricted
Legend:
Setting available (valid)
⎯ Setting does not affect this mode
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur
simultaneously, the compare match signal is inhibited.
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9. 16-Bit Timer
Table 9.7 (c)
16-bit timer Operating Modes (Channel 2)
Register Settings
TSNC
Operating Mode
Synchronization
Synchronous preset
SYNC2 = 1
TMDR
MDF
FDIR PWM
TIOR2
IOA
IOB
16TCR2
Clear
Select
⎯
PWM mode
⎯
PWM2 = 1
⎯
Output compare A
⎯
PWM2 = 0
IOA2 = 0
Other bits
unrestricted
Output compare B
⎯
Input capture A
⎯
PWM2 = 0
Input capture B
⎯
PWM2 = 0
Counter By compare
clearing match/input
capture A
⎯
CCLR1 = 0
CCLR0 = 1
By compare
match/input
capture B
⎯
CCLR1 = 1
CCLR0 = 0
⎯
CCLR1 = 1
CCLR0 = 1
Synchronous
clear
SYNC2 = 1
Phase counting
mode
Clock
Select
MDF = 1
*
IOB2 = 0
Other bits
unrestricted
IOA2 = 1
Other bits
unrestricted
IOB2 = 1
Other bits
unrestricted
⎯
Legend:
Setting available (valid)
⎯ Setting does not affect this mode
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur
simultaneously, the compare match signal is inhibited.
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9. 16-Bit Timer
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10. 8-Bit Timers
Section 10 8-Bit Timers
10.1
Overview
The H8/3006 and H8/3007 have a built-in 8-bit timer module with four channels (TMR0, TMR1,
TMR2, and TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (8TCNT)
and two 8-bit time constant registers (TCORA and TCORB) that are constantly compared with the
8TCNT value to detect compare match events. The timers can be used as multifunctional timers in
a variety of applications, including the generation of a rectangular-wave output with an arbitrary
duty cycle.
10.1.1
Features
The features of the 8-bit timer module are listed below.
• Selection of four clock sources
The counters can be driven by one of three internal clock signals (φ/8, φ/64, or φ/8192) or an
external clock input (enabling use as an external event counter).
• Selection of three ways to clear the counters
The counters can be cleared on compare match A or B, or input capture B.
• Timer output controlled by two compare match signals
The timer output signal in each channel is controlled by two independent compare match
signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM
output.
• A/D converter can be activated by a compare match
• Two channels can be cascaded
⎯ Channels 0 and 1 can be operated as the upper and lower halves of a 16-bit timer (16-bit
count mode).
⎯ Channels 2 and 3 can be operated as the upper and lower halves of a 16-bit timer (16-bit
count mode).
⎯ Channel 1 can count channel 0 compare match events (compare match count mode).
⎯ Channel 3 can count channel 2 compare match events (compare match count mode).
• Input capture function can be set
8-bit or 16-bit input capture operation is available.
• Twelve interrupt sources
There are twelve interrupt sources: four compare match sources, four compare match/input
capture sources, four overflow sources.
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10. 8-Bit Timers
Two of the compare match sources and two of the combined compare match/input capture sources
each have an independent interrupt vector. The remaining compare match interrupts, combined
compare match/input capture interrupts, and overflow interrupts have one interrupt vector for two
sources.
10.1.2
Block Diagram
The 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0
and 1, and group 1 comprising channels 2 and 3. Figure 10.1 shows a block diagram of 8-bit timer
group 0.
External clock
sources
TCLKA
TCLKC
Internal clock
sources
φ/8
φ/64
φ/8192
Clock 1
Clock 0
Clock select
TCORA0
TCORA1
Compare match A1
Compare match A0 Comparator A0
Comparator A1
Overflow 1
TMO0
TMIO1
8TCNT0
8TCNT1
Internal bus
Overflow 0
Compare match B1
Control logic
Compare match B0 Comparator B0
Input capture B1
Comparator B1
TCORB0
TCORB1
8TCSR0
8TCSR1
8TCR0
8TCR1
CMIA0
CMIB0
CMIA1/CMIB1
OVI0/OVI1
Interrupt signals
Legend:
TCORA:
TCORB:
8TCNT:
8TCSR:
8TCR:
Timer constant register A
Timer constant register B
Timer counter
Timer control/status register
Timer control register
Figure 10.1 Block Diagram of 8-Bit Timer Unit (Two Channels: Group 0)
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10. 8-Bit Timers
10.1.3
Pin Configuration
Table 10.1 summarizes the input/output pins of the 8-bit timer module.
Table 10.1 8-Bit Timer Pins
Group
Channel Name
Abbreviation I/O
0
0
Timer output
TMO0
Output Compare match output
Timer clock input
TCLKC
Input
Counter external clock input
Timer input/output TMIO1
I/O
Compare match output/input
capture input
Timer clock input
Input
Counter external clock input
1
1
2
3
TCLKA
Input/output
Timer output
TMO2
Output Compare match output
Timer clock input
TCLKD
Input
Counter external clock input
Timer input/output TMIO3
I/O
Compare match output/input
capture input
Timer clock input
Input
Counter external clock input
TCLKB
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10. 8-Bit Timers
10.1.4
Register Configuration
Table 10.2 summarizes the registers of the 8-bit timer module.
Table 10.2 8-Bit Timer Registers
1
Channel Address*
Name
Abbreviation R/W
0
Timer control register 0
8TCR0
1
2
3
H'FFF80
Initial value
R/W
H'00
2
H'FFF82
Timer control/status register 0
8TCSR0
R/(W)* H'00
H'FFF84
Timer constant register A0
TCORA0
R/W
H'FF
H'FFF86
Timer constant register B0
TCORB0
R/W
H'FF
H'FFF88
Timer counter 0
8TCNT0
R/W
H'00
H'FFF81
Timer control register 1
8TCR1
R/W
H'00
2
H'FFF83
Timer control/status register 1
8TCSR1
R/(W)* H'00
H'FFF85
Timer constant register A1
TCORA1
R/W
H'FF
H'FFF87
Timer constant register B1
TCORB1
R/W
H'FF
H'FFF89
Timer counter 1
8TCNT1
R/W
H'00
H'FFF90
Timer control register 2
8TCR2
R/W
H'00
2
H'FFF92
Timer control/status register 2
8TCSR2
R/(W)* H'10
H'FFF94
Timer constant register A2
TCORA2
R/W
H'FF
H'FFF96
Timer constant register B2
TCORB2
R/W
H'FF
H'FFF98
Timer counter 2
8TCNT2
R/W
H'00
H'FFF91
Timer control register 3
8TCR3
R/W
H'00
2
H'FFF93
Timer control/status register 3
8TCSR3
R/(W)* H'00
H'FFF95
Timer constant register A3
TCORA3
R/W
H'FF
H'FFF97
Timer constant register B3
TCORB3
R/W
H'FF
H'FFF99
Timer counter 3
8TCNT3
R/W
H'00
Notes: 1. Indicates the lower 20 bits of the address in advanced mode.
2. Only 0 can be written to bits 7 to 5, to clear these flags.
Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the channel 0
register as the upper 8 bits and the channel 1 register as the lower 8 bits, so they can be accessed
together by word access.
Similarly, each pair of registers for channel 2 and channel 3 comprises a 16-bit register with the
channel 2 register as the upper 8 bits and the channel 3 register as the lower 8 bits, so they can be
accessed together by word access.
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10. 8-Bit Timers
10.2
Register Descriptions
10.2.1
Timer Counters (8TCNT)
8TCNT0
8TCNT1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
8TCNT2
8TCNT3
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The timer counters (8TCNT) are 8-bit readable/writable up-counters that increment on pulses
generated from an internal or external clock source. The clock source is selected by clock select
bits 2 to 0 (CKS2 to CKS0) in the timer control register (8TCR). The CPU can always read or
write to the timer counters.
The 8TCNT0 and 8TCNT1 pair, and the 8TCNT2 and 8TCNT3 pair, can each be accessed as a
16-bit register by word access.
8TCNT can be cleared by an input capture signal or compare match signal. Counter clear bits 1
and 0 (CCLR1 and CCLR0) in 8TCR select the method of clearing.
When 8TCNT overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status
register (8TCSR) is set to 1.
Each 8TCNT is initialized to H'00 by a reset and in standby mode.
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10. 8-Bit Timers
10.2.2
Time Constant Registers A (TCORA)
TCORA0
TCORA1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORA2
Bit
Initial value
Read/Write
TCORA3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORA0 to TCORA3 are 8-bit readable/writable registers. The TCORA0 and TCORA1 pair, and
the TCORA2 and TCORA3 pair, can each be accessed as a 16-bit register by word access.
The TCORA value is constantly compared with the 8TCNT value. When a match is detected, the
corresponding compare match flag A (CMFA) is set to 1 in 8TCSR.
The timer output can be freely controlled by these compare match signals and the settings of
output select bits 1 and 0 (OS1, OS0) in 8TCSR.
Each TCORA register is initialized to H'FF by a reset and in standby mode.
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10. 8-Bit Timers
10.2.3
Time Constant Registers B (TCORB)
TCORB0
TCORB1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB2
TCORB3
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB0 to TCORB3 are 8-bit readable/writable registers. The TCORB0 and TCORB1 pair, and
the TCORB2 and TCORB3 pair, can each be accessed as a 16-bit register by word access.
The TCORB value is constantly compared with the 8TCNT value. When a match is detected, the
corresponding compare match flag B (CMFB) is set to 1 in 8TCSR*.
The timer output can be freely controlled by these compare match signals and the settings of
output/input capture edge select bits 3 and 2 (OIS3, OIS2) in 8TCSR.
When TCORB is used for input capture, it stores the 8TCNT value on detection of an external
input capture signal. At this time, the CMFB flag is set to 1 in the corresponding 8TCSR register.
The detected edge of the input capture signal is set in 8TCSR.
Each TCORB register is initialized to H'FF by a reset and in standby mode.
Note: * When channel 1 and channel 3 are designated for TCORB input capture, the CMFB
flag is not set by a channel 0 or channel 2 compare match B.
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10. 8-Bit Timers
10.2.4
Timer Control Register (8TCR)
Bit
7
6
5
4
3
2
1
0
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8TCR is an 8-bit readable/writable register that selects the input clock source and the time at
which 8TCNT is cleared, and enables interrupts.
8TCR is initialized to H'00 by a reset and in standby mode.
For the timing, see section 10.4, Operation.
Bit 7⎯Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt
request when the CMFB flag is set to 1 in 8TCSR.
Bit 7
CMIEB
Description
0
CMIB interrupt requested by CMFB is disabled
1
CMIB interrupt requested by CMFB is enabled
(Initial value)
Bit 6⎯Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA interrupt
request when the CMFA flag is set to 1 in 8TCSR.
Bit 6
CMIEA
Description
0
CMIA interrupt requested by CMFA is disabled
1
CMIA interrupt requested by CMFA is enabled
(Initial value)
Bit 5⎯Timer Overflow Interrupt Enable (OVIE): Enables or disables the OVI interrupt
request when the OVF flag is set to 1 in 8TCSR.
Bit 5
OVIE
Description
0
OVI interrupt requested by OVF is disabled
1
OVI interrupt requested by OVF is enabled
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(Initial value)
10. 8-Bit Timers
Bits 4 and 3⎯Counter Clear 1 and 0 (CCLR1, CCLR0): These bits specify the 8TCNT
clearing source. Compare match A or B, or input capture B, can be selected as the clearing source.
Bit 4
CCLR1
Bit 3
CCLR0
Description
0
0
Clearing is disabled
1
Cleared by compare match A
0
Cleared by compare match B/input capture B
1
Cleared by input capture B
1
(Initial value)
Note: When input capture B is set as the 8TCNT1 and 8TCNT3 counter clear source, 8TCNT0
and 8TCNT2 are not cleared by compare match B.
Bits 2 to 0⎯Clock Select 2 to 0 (CSK2 to CSK0): These bits select whether the clock input to
8TCNT is an internal or external clock.
Three internal clocks can be selected, all divided from the system clock (φ): φ/8, φ/64, and φ/8192.
The rising edge of the selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
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10. 8-Bit Timers
When CKS2, CKS1, CKS0 = 1, 0, 0, channels 0 and 1 and channels 2 and 3 are cascaded.
The incrementing clock source is different when 8TCR0 and 8TCR2 are set, and when 8TCR1 and
8TCR3 are set.
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
0
Clock input disabled
1
Internal clock, counted on falling edge of φ/8
0
Internal clock, counted on falling edge of φ/64
1
Internal clock, counted on falling edge of φ/8192
0
Channel 0 (16-bit count mode): Count on 8TCNT1 overflow
1
signal*
1
1
0
(Initial value)
Channel 1 (compare match count mode): Count on 8TCNT0
1
compare match A*
Channel 2 (16-bit count mode): Count on 8TCNT3 overflow
2
signal*
Channel 3 (compare match count mode): Count on 8TCNT2
2
compare match A*
1
1
External clock, counted on rising edge
0
External clock, counted on falling edge
1
External clock, counted on both rising and falling edges
Notes: 1. If the clock input of channel 0 is the 8TCNT1 overflow signal and that of channel 1 is the
8TCNT0 compare match signal, no incrementing clock is generated. Do not use this
setting.
2. If the clock input of channel 2 is the 8TCNT3 overflow signal and that of channel 3 is the
8TCNT2 compare match signal, no incrementing clock is generated. Do not use this
setting.
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10. 8-Bit Timers
10.2.5
Timer Control/Status Registers (8TCSR)
8TCSR0
Bit
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ADTE
OIS3
OIS2
OS1
OS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
⎯
OIS3
OIS2
OS1
OS0
Initial value
0
0
0
1
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
⎯
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ICE
OIS3
OIS2
OS1
OS0
8TCSR2
Bit
8TCSR1, 8TCSR3
Bit
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
Note:
*
Only 0 can be written to bits 7 to 5, to clear these flags.
The timer control/status registers (8TCSR) are 8-bit registers that indicate compare match/input
capture and timer overflow statuses, and control compare match output/input capture edge
selection.
Each 8TCSR is initialized to H'00 by a reset and in standby mode.
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10. 8-Bit Timers
Bit 7⎯Compare Match/Input Capture Flag B (CMFB): Status flag that indicates the
occurrence of a TCORB compare match or input capture.
Bit 7
CMFB
Description
0
[Clearing condition]
(Initial value)
Read CMFB when CMFB = 1, then write 0 in CMFB
1
Note:
[Setting conditions]
*
•
8TCNT = TCORB*
•
The 8TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register
When bit ICE is set to 1 in 8TCSR1 and 8TCSR3, the CMFB flag is not set when
8TCNT0 = TCORB0 or 8TCNT2 = TCORB2.
Bit 6⎯Compare Match Flag A (CMFA): Status flag that indicates the occurrence of a TCORA
compare match.
Bit 6
CMFA
Description
0
Clearing condition
Read CMFA when CMFA = 1, then write 0 in CMFA
1
Setting condition
8TCNT = TCORA
(Initial value)
Bit 5⎯Timer Overflow Flag (OVF): Status flag that indicates that the 8TCNT has overflowed
(H'FF → H'00).
Bit 5
OVF
Description
0
Clearing condition
Read OVF when OVF = 1, then write 0 in OVF
1
Setting condition
8TCNT overflows from H'FF to H'00
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(Initial value)
10. 8-Bit Timers
Bit 4⎯A/D Trigger Enable (ADTE) (8TCSR0): In combination with TRGE in the A/D control
register (ADCR), enables or disables A/D converter start requests by compare match A or an
external trigger. Bit 4 of 8TCSR2 is reserved, but can be read and written.
TRGE*
Bit 4
ADTE
0
0
A/D converter start requests by compare match A or an external trigger pin
(ADTRG) input are disabled
(Initial value)
1
A/D converter start requests by compare match A or an external trigger pin
(ADTRG) input are disabled
0
A/D converter start requests by an external trigger pin (ADTRG) are enabled,
and A/D converter start requests by compare match A are disabled
1
A/D converter start requests by compare match A are enabled, and A/D
converter start requests by an external trigger pin (ADTRG) are disabled
1
Note:
*
Description
TRGE is bit 7 of the A/D control register (ADCR).
Bit 4⎯Reserved (In 8TCSR1): This bit is a reserved bit, but can be read and written.
Bit 4⎯Input Capture Enable (ICE) (In 8TCSR1 and 8TCSR3): Selects the function of
TCORB1 and TCORB3.
Bit 4
ICE
Description
0
TCORB1 and TCORB3 are compare match registers
1
TCORB1 and TCORB3 are input capture registers
(Initial value)
When bit ICE is set to 1 in 8TCSR1 or 8TCSR3, the operation of the TCORA and TCORB
registers in channels 0 to 3 is as shown in the tables below.
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10. 8-Bit Timers
Table 10.3 Operation of Channels 0 and 1 when Bit ICE is Set to 1 in 8TCSR1 Register
Register
Register Function
Status Flag Change
Timer Output
Capture Input
Interrupt Request
TCORA0 Compare match CMFA changed from 0 TMO0 output
operation
to 1 in 8TCSR0 by
controllable
compare match
CMIA0 interrupt request
generated by compare
match
TCORB0 Compare match CMFB not changed
operation
from 0 to 1 in 8TCSR0
by compare match
CMIB0 interrupt request
not generated by
compare match
No output from
TMO0
TCORA1 Compare match CMFA changed from 0 TMIO1 is dedicated
operation
to 1 in 8TCSR1 by
input capture pin
compare match
CMIA1 interrupt request
generated by compare
match
TCORB1 Input capture
operation
CMIB1 interrupt request
generated by input
capture
CMFB changed from 0 TMIO1 is dedicated
to 1 in 8TCSR1 by input input capture pin
capture
Table 10.4 Operation of Channels 2 and 3 when Bit ICE is Set to 1 in 8TCSR3 Register
Register
Register Function
Status Flag Change
Timer Output
Capture Input
Interrupt Request
TCORA2 Compare match CMFA changed from 0 TMO2 output
operation
to 1 in 8TCSR2 by
controllable
compare match
CMIA2 interrupt request
generated by compare
match
TCORB2 Compare match CMFB not changed
operation
from 0 to 1 in 8TCSR2
by compare match
CMIB2 interrupt request
not generated by
compare match
No output from
TMO2
TCORA3 Compare match CMFA changed from 0 TMIO3 is dedicated
operation
to 1 in 8TCSR3 by
input capture pin
compare match
CMIA3 interrupt request
generated by compare
match
TCORB3 Input capture
operation
CMIB3 interrupt request
generated by input
capture
CMFB changed from 0 TMIO3 is dedicated
to 1 in 8TCSR3 by input input capture pin
capture
Bits 3 and 2⎯Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination
with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the
input capture input detected edge.
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10. 8-Bit Timers
The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3).
TCORB0 and TCORB2 function as compare match registers regardless of the setting of bit 4 of
8TCSR1 (8TCSR3).
ICE Bit in
8TCSR1 Bit 3
(8TCSR3) OIS3
Bit 2
OIS2
Description
0
0
No change when compare match B occurs
1
0 is output when compare match B occurs
0
1 is output when compare match B occurs
1
Output is inverted when compare match B occurs (toggle output)
0
TCORB input capture on rising edge
1
TCORB input capture on falling edge
0
TCORB input capture on both rising and falling edges
0
1
1
0
1
(Initial value)
1
• When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
• If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
Bits 1 and 0⎯Output Select A1 and A0 (OS1, OS0): These bits select the compare match A
output level.
Bit 1
OS1
Bit 0
OS0
Description
0
0
No change when compare match A occurs
1
0 is output when compare match A occurs
0
1 is output when compare match A occurs
1
Output is inverted when compare match A occurs (toggle output)
1
(Initial value)
• When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
• If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
• When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
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10. 8-Bit Timers
10.3
CPU Interface
10.3.1
8-Bit Registers
8TCNT, TCORA, TCORB, 8TCR, and 8TCSR are 8-bit registers. These registers are connected to
the CPU by an internal 16-bit data bus and can be read and written a word at a time or a byte at a
time.
Figures 10.2 and 10.3 show the operation in word read and write accesses to 8TCNT.
Figures 10.4 to 10.7 show the operation in byte read and write accesses to 8TCNT0 and 8TCNT1.
Internal data bus
H
C
P
U
H
Bus
interface
L
L
Module data bus
8TCNT0 8TCNT1
Figure 10.2 8TCNT Access Operation (CPU Writes to 8TCNT, Word)
Internal data bus
H
C
P
U
H
Bus
interface
L
L
Module data bus
8TCNT0 8TCNT1
Figure 10.3 8TCNT Access Operation (CPU Reads 8TCNT, Word)
Internal data bus
H
C
P
U
L
H
Bus
interface
L
Module data bus
8TCNT0 8TCNT1
Figure 10.4 8TCNTH Access Operation (CPU Writes to 8TCNTH, Upper Byte)
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10. 8-Bit Timers
Internal data bus
H
C
P
U
L
H
Bus
interface
L
Module data bus
8TCNT0 8TCNT1
Figure 10.5 8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte)
Internal data bus
H
C
P
U
L
H
Bus
interface
L
Module data bus
8TCNT0 8TCNT1
Figure 10.6 8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte)
Internal data bus
H
C
P
U
L
H
Bus
interface
L
Module data bus
8TCNT0 8TCNT1
Figure 10.7 8TCNT1 Access Operation (CPU Reads 8TCNT1, Lower Byte)
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10. 8-Bit Timers
10.4
Operation
10.4.1
8TCNT Count Timing
8TCNT is incremented by input clock pulses (either internal or external).
Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the
system clock (φ) can be selected by setting bits CKS2 to CKS0 in 8TCR. Figure 10.8 shows the
count timing.
φ
Internal clock
8TCNT input clock
8TCNT
N–1
N
N+1
Figure 10.8 Count Timing for Internal Clock Input
Note: Even when the same internal clock is selected for both the 16- and 8-bit timers, they do
not operate in the same manner because the count-up edge differs.
External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in
8TCR: on the rising edge, the falling edge, and both rising and falling edges.
The pulse width of the external clock signal must be at least 1.5 serial clocks when a single edge is
selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be
counted correctly.
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10. 8-Bit Timers
Figure 10.9 shows the timing for incrementation on both edges of the external clock signal.
φ
External clock input
8TCNT input clock
8TCNT
N–1
N
N+1
Figure 10.9 Count Timing for External Clock Input (When Detecting the Both Edges)
10.4.2
Compare Match Timing
Timer Output Timing: When compare match A or B occurs, the timer output is as specified by
the OIS3, OIS2, OS1, and OS0 bits in 8TCSR (unchanged, 0 output, 1 output, or toggle output).
Figure 10.10 shows the timing when the output is set to toggle on compare match A.
φ
Compare match A
signal
Timer output
Figure 10.10 Timing of Timer Output
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10. 8-Bit Timers
Clear by Compare Match: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR,
8TCNT can be cleared when compare match A or B occurs. Figure 10.11 shows the timing of this
operation.
φ
Compare match signal
8TCNT
N
H'00
Figure 10.11 Timing of Clear by Compare Match
Clear by Input Capture: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR,
8TCNT can be cleared when input capture B occurs. Figure 10.12 shows the timing of this
operation.
φ
Input capture input
Input capture signal
8TCNT
N
Figure 10.12 Timing of Clear by Input Capture
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H '00
10. 8-Bit Timers
10.4.3
Input Capture Signal Timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in 8TCSR.
Figure 10.13 shows the timing when the rising edge is selected.
The pulse width of the input capture input signal must be at least 1.5 system clocks when a single
edge is selected, and at least 2.5 system clocks when both edges are selected.
φ
Input capture input
Input capture signal
8TCNT
TCORB
N
N
Figure 10.13 Timing of Input Capture Input Signal
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10. 8-Bit Timers
10.4.4
Timing of Status Flag Setting
Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: CMFA and CMFB in
8TCSR are set to 1 by the compare match signal output when the TCOR and 8TCNT values
match. The compare match signal is generated in the last state of the match (when the matched
8TCNT count value is updated). Therefore, after the 8TCNT and TCOR values match, the
compare match signal is not generated until an incrementing clock pulse is generated. Figure 10.14
shows the timing in this case.
φ
8TCNT
N
TCOR
N
N+1
Compare match signal
CMF
Figure 10.14 CMF Flag Setting Timing when Compare Match Occurs
Timing of CMFB Flag Setting when Input Capture Occurs: On generation of an input capture
signal, the CMFB flag is set to 1 and at the same time the 8TCNT value is transferred to TCORB.
Figure 10.15 shows the timing in this case.
φ
8TCNT
TCORB
N
N
Input capture signal
CMFB
Figure 10.15 CMFB Flag Setting Timing when Input Capture Occurs
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10. 8-Bit Timers
Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow
signal generated when 8TCNT overflows (from H'FF to H'00). Figure 10.16 shows the timing in
this case.
φ
8TCNT
H'FF
H'00
Overflow signal
OVF
Figure 10.16 Timing of OVF Setting
10.4.5
Operation with Cascaded Connection
If bits CKS2 to CKS0 are set to (100) in either 8TCR0 or 8TCR1, the 8-bit timers of channels 0
and 1 are cascaded. With this configuration, the two timers can be used as a single 16-bit timer
(16-bit count mode), or channel 0 8-bit timer compare matches can be counted in channel 1
(compare match count mode). In this case, the timer operates as below. Similarly, if bits CKS2 to
CKS0 are set to (100) in either 8TCR2 or 8TCR3, the 8-bit timers of channels 2 and 3 are
cascaded. With this configuration, the two timers can be used as a single 16-bit timer (16-bit count
mode), or channel 2 8-bit timer compare matches can be counted in channel 3 (compare match
count mode). Timer operation in these cases is described below.
16-Bit Count Mode
• Channels 0 and 1:
When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit
timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
⎯ Setting when Compare Match Occurs
• The CMF flag is set to 1 in 8TCR0 when a 16-bit compare match occurs.
• The CMF flag is set to 1 in 8TCR1 when a lower 8-bit compare match occurs.
• TMO0 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR0 is in
accordance with the 16-bit compare match conditions.
• TMIO1 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR1 is in
accordance with the lower 8-bit compare match conditions.
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10. 8-Bit Timers
⎯ Setting when Input Capture Occurs
• The CMFB flag is set to 1 in 8TCR0 and 8TCR1 when the ICE bit is 1 in 8TCSR1 and
input capture occurs.
• TMIO1 pin input capture input signal edge detection is selected by bits OIS3 and OIS2
in 8TCSR0.
⎯ Counter Clear Specification
• If counter clear on compare match or input capture has been selected by the CCLR1
and CCLR0 bits in 8TCR0, the 16-bit counter (both 8TCNT0 and 8TCNT1) is cleared.
• The settings of the CCLR1 and CCLR0 bits in 8TCR1 are ignored. The lower 8 bits
cannot be cleared independently.
⎯ OVF Flag Operation
• The OVF flag is set to 1 in 8TCSR0 when the 16-bit counter (8TCNT0 and 8TCNT1)
overflows (from H'FFFF to H'0000).
• The OVF flag is set to 1 in 8TCSR1 when the 8-bit counter (8TCNT1) overflows (from
H'FF to H'00).
• Channels 2 and 3:
When bits CKS2 to CKS0 are set to (100) in 8TCR2, the timer functions as a single 16-bit
timer with channel 2 occupying the upper 8 bits and channel 3 occupying the lower 8 bits.
⎯ Setting when Compare Match Occurs
• The CMF flag is set to 1 in 8TCR2 when a 16-bit compare match occurs.
• The CMF flag is set to 1 in 8TCR3 when a lower 8-bit compare match occurs.
• TMO2 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR2 is in
accordance with the 16-bit compare match conditions.
• TMIO3 pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR3 is in
accordance with the lower 8-bit compare match conditions.
⎯ Setting when Input Capture Occurs
• The CMFB flag is set to 1 in 8TCR2 and 8TCR3 when the ICE bit is 1 in 8TCSR3 and
input capture occurs.
• TMIO3 pin input capture input signal edge detection is selected by bits OIS3 and OIS2
in 8TCSR2.
⎯ Counter Clear Specification
• If counter clear on compare match has been selected by the CCLR1 and CCLR0 bits in
8TCR2, the 16-bit counter (both 8TCNT2 and 8TCNT3) is cleared.
• The settings of the CCLR1 and CCLR0 bits in 8TCR3 are ignored. The lower 8 bits
cannot be cleared independently.
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10. 8-Bit Timers
⎯ OVF Flag Operation
• The OVF flag is set to 1 in 8TCSR2 when the 16-bit counter (8TCNT2 and 8TCNT3)
overflows (from H'FFFF to H'0000).
• The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter (8TCNT3) overflows (from
H'FF to H'00).
Compare Match Count Mode
• Channels 0 and 1:
When bits CKS2 to CKS0 are set to (100) in 8TCR1, 8TCNT1 counts channel 0 compare
match A events.
Channels 0 and 1 are controlled independently. CMF flag setting, interrupt generation, TMO
pin output, counter clearing, and so on, is in accordance with the settings for each channel.
• Channels 2 and 3:
When bits CKS2 to CKS0 are set to (100) in 8TCR3, 8TCNT3 counts channel 2 compare
match A events.
Channels 2 and 3 are controlled independently. CMF flag setting, interrupt generation, TMO
pin output, counter clearing, and so on, is in accordance with the settings for each channel.
Caution: Do not set 16-bit count mode and compare match count mode simultaneously within the
same group, as the 8TCNT input clock will not be generated and the counters will not operate.
10.4.6
Input Capture Setting
The 8TCNT value can be transferred to TCORB on detection of an input edge on the input
capture/output compare pin (TMIO1 or TMIO3). Rising edge, falling edge, or both edge detection
can be selected. In 16-bit count mode, 16-bit input capture can be used.
Setting Input Capture Operation in 8-Bit Timer Mode (Normal Operation)
• Channel 1:
⎯ Set TCORB1 as an 8-bit input capture register with the ICE bit in 8TCSR1.
⎯ Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
signal (TMIO1) with bits OIS3 and OIS2 in 8TCSR1.
⎯ Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count.
• Channel 3:
⎯ Set TCORB3 as an 8-bit input capture register with the ICE bit in 8TCSR3.
⎯ Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
signal (TMIO3) with bits OIS3 and OIS2 in 8TCSR3.
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10. 8-Bit Timers
⎯ Select the input clock with bits CKS2 to CKS0 in 8TCR3, and start the 8TCNT count.
Note: When TCORB1 in channel 1 is used for input capture, TCORB0 in channel 0 cannot be
used as a compare match register.
Similarly, when TCORB3 in channel 3 is used for input capture, TCORB2 in channel 2
cannot be used as a compare match register.
Setting Input Capture Operation in 16-Bit Count Mode
• Channels 0 and 1:
⎯ In 16-bit count mode, TCORB0 and TCORB1 function as a 16-bit input capture register
when the ICE bit is set to 1 in 8TCSR1.
⎯ Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
signal (TMIO1) with bits OIS3 and OIS2 in 8TCSR0. (In 16-bit count mode, the settings of
bits OIS3 and OIS2 in 8TCSR1 are ignored.)
⎯ Select the input clock with bits CKS2 to CKS0 in 8TCR1, and start the 8TCNT count.
• Channels 2 and 3:
⎯ In 16-bit count mode, TCORB2 and TCORB3 function as a 16-bit input capture register
when the ICE bit is set to 1 in 8TCSR3.
⎯ Select rising edge, falling edge, or both edges as the input edge(s) for the input capture
signal (TMIO3) with bits OIS3 and OIS2 in 8TCSR2. (In 16-bit count mode, the settings of
bits OIS3 and OIS2 in 8TCSR3 are ignored.)
⎯ Select the input clock with bits CKS2 to CKS0 in 8TCR3, and start the 8TCNT count.
10.5
Interrupt
10.5.1
Interrupt Source
The 8-bit timer unit can generate three types of interrupt: compare match A and B (CMIA and
CMIB) and overflow (OVI). Table 10.5 shows the interrupt sources and their priority order. Each
interrupt source is enabled or disabled by the corresponding interrupt enable bit in 8TCR. A
separate interrupt request signal is sent to the interrupt controller by each interrupt source.
Table 10.5 Types of 8-Bit Timer Interrupt Sources and Priority Order
Interrupt Source
Description
Priority
CMIA
Interrupt by CMFA
High
CMIB
Interrupt by CMFB
TOVI
Interrupt by OVF
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Low
10. 8-Bit Timers
For compare match interrupts CMIA1/CMIB1 and CMIA3/CMIB3 and the overflow interrupts
(TOVI0/TOVI1 and TOVI2/TOVI3), one vector is shared by two interrupts.
Table 10.6 lists the interrupt sources.
Table 10.6 8-Bit Timer Interrupt Sources
Channel
Interrupt Source
Description
0
CMIA0
TCORA0 compare match
CMIB0
TCORB0 compare match/input capture
1
CMIA1/CMIB1
TCORA1 compare match, or TCORB1 compare match/input
capture
0, 1
TOVI0/TOVI1
Counter 0 or counter 1 overflow
2
CMIA2
TCORA2 compare match
CMIB2
TCORB2 compare match/input capture
3
CMIA3/CMIB3
TCORA3 compare match, or TCORB3 compare match/input
capture
2, 3
TOVI2/TOVI3
Counter 2 or counter 3 overflow
10.5.2
A/D Converter Activation
The A/D converter can only be activated by channel 0 compare match A.
When the CMFA flag in 8TCSR0 is set to 1 and the ADTE bit is also set to 1, activation of the
A/D converter will be requested on generation of channel 0 compare match A. If the TRGE bit in
ADCR is set to 1 at this time, the A/D converter will be activated. When ADTE bit in 8TCSR0 is
set to 1, the A/D converter external trigger pin (ADTRG) input is disabled.
10.6
8-Bit Timer Application Example
Figure 10.17 shows how the 8-bit timer module can be used to output pulses with any desired duty
cycle. The settings for this example are as follows:
• Clear the CCLR1 bit to 0 and set the CCLR0 bit to 1 in 8TCR so that 8TCNT is cleared by a
TCORA compare match.
• Set bits OIS3, OIS2, OS1, and OS0 to (0110) in 8TCSR so that 1 is output on a TCORA
compare match and 0 is output on a TCORB compare match.
The above settings enable a waveform with the cycle determined by TCORA and the pulse width
detected by TCORB to be output without software intervention.
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10. 8-Bit Timers
8TCNT
H'FF
Counter clear
TCORA
TCORB
H'00
TMO
Figure 10.17 Example of Pulse Output
10.7
Usage Notes
Note that the following kinds of contention can occur in 8-bit timer operation.
10.7.1
Contention between 8TCNT Write and Clear
If a timer counter clear signal occurs in the T3 state of a 8TCNT write cycle, clearing of the
counter takes priority and the write is not performed. Figure 10.18 shows the timing in this case.
8TCNT write cycle
T1
T2
T3
φ
Address bus
8TCNT address
Internal write signal
Counter clear signal
N
8TCNT
H'00
Figure 10.18 Contention between 8TCNT Write and Clear
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10. 8-Bit Timers
10.7.2
Contention between 8TCNT Write and Increment
If an increment pulse occurs in the T3 state of a 8TCNT write cycle, writing takes priority and
8TCNT is not incremented. Figure 10.19 shows the timing in this case.
8TCNT write cycle
T1
T2
T3
φ
8TCNT address
Address bus
Internal write signal
8TCNT input clock
8TCNT
N
M
8TCNT write data
Figure 10.19 Contention between 8TCNT Write and Increment
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10. 8-Bit Timers
10.7.3
Contention between TCOR Write and Compare Match
If a compare match occurs in the T3 state of a TCOR write cycle, writing takes priority and the
compare match signal is inhibited. Figure 10.20 shows the timing in this case.
TCOR write cycle
T1
T2
T3
φ
Address bus
TCOR address
Internal write signal
8TCNT
N
TCOR
N
N+1
M
TCOR write data
Compare match signal
Figure 10.20 Contention between TCOR Write and Compare Match
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Inhibited
10. 8-Bit Timers
10.7.4
Contention between TCOR Read and Input Capture
If an input capture signal occurs in the T3 state of a TCOR read cycle, the value before input
capture is read. Figure 10.21 shows the timing in this case.
TCORB read cycle
T1
T2
T3
φ
TCORB address
Address bus
Internal read signal
Input capture signal
TCORB
Internal data bus
N
M
N
Figure 10.21 Contention between TCOR Read and Input Capture
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10. 8-Bit Timers
10.7.5
Contention between Counter Clearing by Input Capture and Counter Increment
If an input capture signal and counter increment signal occur simultaneously, counter clearing by
the input capture signal takes priority and the counter is not incremented. The value before the
counter is cleared is transferred to TCORB. Figure 10.22 shows the timing in this case.
T1
T2
T3
φ
Input capture signal
Counter clear signal
8TCNT internal clock
8TCNT
N
TCORB
X
H'00
N
Figure 10.22 Contention between Counter Clearing by Input Capture and Counter
Increment
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10. 8-Bit Timers
10.7.6
Contention between TCOR Write and Input Capture
If an input capture signal occurs in the T3 state of a TCOR write cycle, input capture takes priority
and the write to TCOR is not performed. Figure 10.23 shows the timing in this case.
TCOR write cycle
T1
T2
T3
φ
Address bus
TCOR address
Internal write signal
Input capture signal
M
8TCNT
TCOR
X
M
Figure 10.23 Contention between TCOR Write and Input Capture
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10. 8-Bit Timers
10.7.7
Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection)
If an increment pulse occurs in the T2 or T3 state of a 8TCNT byte write cycle in 16-bit count
mode, writing takes priority and 8TCNT is not incremented. The byte data for which a write was
not performed retains its previous value. Figure 10.24 shows the timing when an increment pulse
occurs in the T2 state of a byte write to 8TCNTH.
8TCNTH byte write cycle
T1
T2
T3
φ
8TCNTH address
Address bus
Internal write signal
8TCNT input clock
8TCNTH
8TCNTL
N
X
8TCNT write data
X+1
Figure 10.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
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10. 8-Bit Timers
10.7.8
Contention between Compare Matches A and B
If compare matches A and B occur at the same time, the 8-bit timer operates according to the
relative priority of the output states set for compare match A and compare match B, as shown in
Table 10.5.
Table 10.5 Timer Output Priority Order
Output Setting
Priority
Toggle output
High
1 output
0 output
No change
10.7.9
Low
8TCNT Operation at Internal Clock Source Switchover
Switching internal clock sources may cause 8TCNT to increment, depending on the switchover
timing. Table 10.6 shows the relation between the time of the switchover (by writing to bits CKS1
and CKS0) and the operation of 8TCNT.
The 8TCNT input clock is generated from the internal clock source by detecting the rising edge of
the internal clock. If a switchover is made from a low clock source to a high clock source, as in
case No. 3 in Table 10.6, the switchover will be regarded as a falling edge, a 8TCNT clock pulse
will be generated, and 8TCNT will be incremented.
8TCNT may also be incremented when switching between internal and external clocks.
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10. 8-Bit Timers
Table 10.6 Internal Clock Switchover and 8TCNT Operation
No.
CKS1 and CKS0 Write Timing
8TCNT Operation
1
High → high switchover*
Old clock source
1
New clock source
8TCNT clock
8TCNT
N+1
N
CKS bits rewritten
2
High → low switchover*
2
Old clock source
New clock source
8TCNT clock
8TCNT
N
N+1
N+2
CKS bits rewritten
3
Low → high switchover*
3
Old clock source
New clock source
*4
8TCNT clock
8TCNT
N
N+1
N+2
CKS bits rewritten
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10. 8-Bit Timers
No.
CKS1 and CKS0 Write Timing
8TCNT Operation
4
Low → low switchover*
Old clock source
4
New clock source
8TCNT clock
8TCNT
N
N+1
N+2
CKS bits rewritten
Notes: 1. Including switchovers from a high clock source to the halted state, and from the halted
state to a high clock source.
2. Including switchover from the halted state to a low clock source.
3. Including switchover from a low clock source to the halted state.
4. The switchover is regarded as a rising edge, causing 8TCNT to increment.
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10. 8-Bit Timers
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11. Programmable Timing Pattern Controller (TPC)
Section 11 Programmable Timing Pattern Controller (TPC)
11.1
Overview
The H8/3006 and H8/3007 have a built-in programmable timing pattern controller (TPC) that
provides pulse outputs by using the 16-bit timer as a time base. The TPC pulse outputs are divided
into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently.
11.1.1
Features
TPC features are listed below.
• 16-bit output data
Maximum 16-bit data can be output. TPC output can be enabled on a bit-by-bit basis.
• Four output groups
Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit
outputs.
• Selectable output trigger signals
Output trigger signals can be selected for each group from the compare match signals of three
16-bit timer channels.
• Non-overlap mode
A non-overlap margin can be provided between pulse outputs.
• Can operate together with the DMA controller (DMAC)
The compare-match signals selected as trigger signals can activate the DMAC for sequential
output of data without CPU intervention.
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11. Programmable Timing Pattern Controller (TPC)
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of the TPC.
16-bit timer compare match signals
Control logic
TP15
TP14
TP13
TP12
TP11
TP10
TP 9
TP 8
TP 7
TP 6
TP 5
TP 4
TP 3
TP 2
TP 1
TP 0
Legend:
TPMR:
TPCR:
NDERB:
NDERA:
PBDDR:
PADDR:
NDRB:
NDRA:
PBDR:
PADR:
PADDR
PBDDR
NDERA
NDERB
TPMR
TPCR
Internal
data bus
Pulse output
pins, group 3
PBDR
NDRB
PADR
NDRA
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
TPC output mode register
TPC output control register
Next data enable register B
Next data enable register A
Port B data direction register
Port A data direction register
Next data register B
Next data register A
Port B data register
Port A data register
Figure 11.1 TPC Block Diagram
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11. Programmable Timing Pattern Controller (TPC)
11.1.3
Pin Configuration
Table 11.1 summarizes the TPC output pins.
Table 11.1 TPC Pins
Name
Symbol
I/O
Function
TPC output 0
TP0
Output
Group 0 pulse output
TPC output 1
TP1
Output
TPC output 2
TP2
Output
TPC output 3
TP3
Output
TPC output 4
TP4
Output
TPC output 5
TP5
Output
TPC output 6
TP6
Output
TPC output 7
TP7
Output
TPC output 8
TP8
Output
TPC output 9
TP9
Output
TPC output 10
TP10
Output
TPC output 11
TP11
Output
TPC output 12
TP12
Output
TPC output 13
TP13
Output
TPC output 14
TP14
Output
TPC output 15
TP15
Output
Group 1 pulse output
Group 2 pulse output
Group 3 pulse output
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11. Programmable Timing Pattern Controller (TPC)
11.1.4
Register Configuration
Table 11.2 summarizes the TPC registers.
Table 11.2 TPC Registers
1
Address*
Name
Abbreviation
R/W
H'EE009
Port A data direction register
PADDR
W
H'FFFD9
Port A data register
PADR
R/(W)*
H'EE00A
Port B data direction register
PBDDR
W
H'FFFDA
Port B data register
PBDR
R/(W)*
Function
H'00
2
H'00
H'00
2
H'00
H'FFFA0
TPC output mode register
TPMR
R/W
H'F0
H'FFFA1
TPC output control register
TPCR
R/W
H'FF
H'FFFA2
Next data enable register B
NDERB
R/W
H'00
H'FFFA3
Next data enable register A
NDERA
R/W
H'00
H'FFFA5/
3
H'FFFA7*
Next data register A
NDRA
R/W
H'00
H'FFFA4/
3
H'FFFA6*
Next data register B
NDRB
R/W
H'00
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Bits used for TPC output cannot be written.
3. The NDRA address is H'FFFA5 when the same output trigger is selected for TPC
output groups 0 and 1 by settings in TPCR. When the output triggers are different, the
NDRA address is H'FFFA7 for group 0 and H'FFFA5 for group 1. Similarly, the address
of NDRB is H'FFFA4 when the same output trigger is selected for TPC output groups 2
and 3 by settings in TPCR. When the output triggers are different, the NDRB address is
H'FFFA6 for group 2 and H'FFFA4 for group 3.
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11. Programmable Timing Pattern Controller (TPC)
11.2
Register Descriptions
11.2.1
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that selects input or output for each pin in port A.
Bit
7
6
5
4
3
2
1
0
PA 7 DDR PA 6 DDR PA 5 DDR PA 4 DDR PA 3 DDR PA 2 DDR PA 1 DDR PA 0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or
output for port A pins
Port A is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output must
be set to 1. For further information about PADDR, see section 8.7, Port A.
11.2.2
Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when
these TPC output groups are used.
Bit
7
6
5
4
3
2
1
0
PA
PA
PA
PA
PA
PA
PA
PA
7
6
5
4
3
Initial value
0
0
0
0
0
Read/Write
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
2
0
R/(W) *
1
0
R/(W) *
0
0
R/(W) *
Port A data 7 to 0
These bits store output data
for TPC output groups 0 and 1
Note: * Bits selected for TPC output by NDERA settings become read-only bits.
For further information about PADR, see section 8.7, Port A.
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11. Programmable Timing Pattern Controller (TPC)
11.2.3
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.
Bit
7
6
5
4
3
2
1
0
PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port B data direction 7 to 0
These bits select input or
output for port B pins
Port B is multiplexed with pins TP15 to TP8. Bits corresponding to pins used for TPC output must
be set to 1. For further information about PBDDR, see section 8.8, Port B.
11.2.4
Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when
these TPC output groups are used.
Bit
7
6
5
4
3
2
1
0
PB 7
PB 6
PB 5
PB 4
PB 3
PB 2
PB 1
PB 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W) *
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Port B data 7 to 0
These bits store output data
for TPC output groups 2 and 3
Note: * Bits selected for TPC output by NDERB settings become read-only bits.
For further information about PBDR, see section 8.8, Port B.
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11. Programmable Timing Pattern Controller (TPC)
11.2.5
Next Data Register A (NDRA)
NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups
1 and 0 (pins TP7 to TP0). During TPC output, when an 16-bit timer compare match event
specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The
address of NDRA differs depending on whether TPC output groups 0 and 1 have the same output
trigger or different output triggers.
NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by
the same compare match event, the NDRA address is H'FFFA5. The upper 4 bits belong to group
1 and the lower 4 bits to group 0. Address H'FFFA7 consists entirely of reserved bits that cannot
be modified and always read 1.
Address H'FFFA5
Bit
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
Next data 3 to 0
These bits store the next output
data for TPC output group 0
Address H'FFFA7
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value
1
1
1
1
1
1
1
1
Read/Write
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Reserved bits
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11. Programmable Timing Pattern Controller (TPC)
Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5
and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits
7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1.
Address H'FFFA5
Bit
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
⎯
⎯
⎯
⎯
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
⎯
⎯
⎯
⎯
Next data 7 to 4
These bits store the next output
data for TPC output group 1
Reserved bits
Address H'FFFA7
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
NDR3
NDR2
NDR1
NDR0
Initial value
1
1
1
1
0
0
0
0
Read/Write
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
Reserved bits
11.2.6
Next data 3 to 0
These bits store the next output
data for TPC output group 0
Next Data Register B (NDRB)
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups
3 and 2 (pins TP15 to TP8). During TPC output, when an 16-bit timer compare match event
specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The
address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output
trigger or different output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
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11. Programmable Timing Pattern Controller (TPC)
Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by
the same compare match event, the NDRB address is H'FFFA4. The upper 4 bits belong to group
3 and the lower 4 bits to group 2. Address H'FFFA6 consists entirely of reserved bits that cannot
be modified and always read 1.
Address H'FFFA4
Bit
7
6
5
4
3
2
1
0
NDR15
NDR14
NDR13
NDR12
NDR11
NDR10
NDR9
NDR8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Next data 11 to 8
These bits store the next output
data for TPC output group 2
Address H'FFFA6
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value
1
1
1
1
1
1
1
1
Read/Write
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Reserved bits
Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered
by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4
and the address of the lower 4 bits (group 2) is H'FFFA6. Bits 3 to 0 of address H'FFFA4 and bits
7 to 4 of address H'FFFA6 are reserved bits that cannot be modified and always read 1.
Address H'FFFA4
Bit
7
6
5
4
3
2
1
0
NDR15
NDR14
NDR13
NDR12
⎯
⎯
⎯
⎯
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
⎯
⎯
⎯
⎯
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Reserved bits
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11. Programmable Timing Pattern Controller (TPC)
Address H'FFFA6
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
NDR11
NDR10
NDR9
NDR8
Initial value
1
1
1
1
0
0
0
0
Read/Write
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
Reserved bits
11.2.7
Next data 11 to 8
These bits store the next output
data for TPC output group 2
Next Data Enable Register A (NDERA)
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0
(TP7 to TP0) on a bit-by-bit basis.
7
6
5
4
3
2
1
0
NDER7
NDER6
NDER5
NDER4
NDER3
NDER2
NDER1
NDER0
Bit
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data enable 7 to 0
These bits enable or disable
TPC output groups 1 and 0
If a bit is enabled for TPC output by NDERA, then when the 16-bit timer compare match event
selected in the TPC output control register (TPCR) occurs, the NDRA value is automatically
transferred to the corresponding PADR bit, updating the output value. If TPC output is disabled,
the bit value is not transferred from NDRA to PADR and the output value does not change.
NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0⎯Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC
output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis.
Bits 7 to 0
NDER7 to NDER0
Description
0
TPC outputs TP7 to TP0 are disabled
(NDR7 to NDR0 are not transferred to PA7 to PA0)
1
TPC outputs TP7 to TP0 are enabled
(NDR7 to NDR0 are transferred to PA7 to PA0)
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(Initial value)
11. Programmable Timing Pattern Controller (TPC)
11.2.8
Next Data Enable Register B (NDERB)
NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2
(TP15 to TP8) on a bit-by-bit basis.
Bit
7
6
4
5
3
2
1
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9
0
NDER8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data enable 15 to 8
These bits enable or disable
TPC output groups 3 and 2
If a bit is enabled for TPC output by NDERB, then when the 16-bit timer compare match event
selected in the TPC output control register (TPCR) occurs, the NDRB value is automatically
transferred to the corresponding PBDR bit, updating the output value. If TPC output is disabled,
the bit value is not transferred from NDRB to PBDR and the output value does not change.
NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0⎯Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC
output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis.
Bits 7 to 0
NDER15 to NDER8
Description
0
TPC outputs TP15 to TP8 are disabled
(NDR15 to NDR8 are not transferred to PB7 to PB0)
1
TPC outputs TP15 to TP8 are enabled
(NDR15 to NDR8 are transferred to PB7 to PB0)
(Initial value)
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11. Programmable Timing Pattern Controller (TPC)
11.2.9
TPC Output Control Register (TPCR)
TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a
group-by-group basis.
Bit
7
6
5
4
3
2
1
0
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Group 3 compare
match select 1 and 0
These bits select
the compare match Group 2 compare
event that triggers match select 1 and 0
TPC output group 3 These bits select
(TP15 to TP12 )
the compare match Group 1 compare
event that triggers match select 1 and 0
TPC output group 2 These bits select
(TP11 to TP 8 )
the compare match Group 0 compare
event that triggers match select 1 and 0
TPC output group 1 These bits select
(TP7 to TP4 )
the compare match
event that triggers
TPC output group 0
(TP3 to TP0 )
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6⎯Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match event that triggers TPC output group 3 (TP15 to TP12).
Bit 7
G3CMS1
Bit 6
G3CMS0
0
0
TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit
timer channel 0
1
TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit
timer channel 1
0
TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit
timer channel 2
1
TPC output group 3 (TP15 to TP12) is triggered by
compare match in 16-bit timer channel 2
1
Description
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(Initial value)
11. Programmable Timing Pattern Controller (TPC)
Bits 5 and 4⎯Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits
select the compare match event that triggers TPC output group 2 (TP11 to TP8).
Bit 5
G2CMS1
Bit 4
G2CMS0
0
0
TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit
timer channel 0
1
TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit
timer channel 1
0
TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit
timer channel 2
1
TPC output group 2 (TP11 to TP8) is triggered by
compare match in 16-bit timer channel 2
1
Description
(Initial value)
Bits 3 and 2⎯Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits
select the compare match event that triggers TPC output group 1 (TP7 to TP4).
Bit 3
G1CMS1
Bit 2
G1CMS0
0
0
TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit
timer channel 0
1
TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit
timer channel 1
0
TPC output group 1 (TP7 to TP4) is triggered by compare match in 16-bit
timer channel 2
1
TPC output group 1 (TP7 to TP4) is triggered by
compare match in 16-bit timer channel 2
1
Description
(Initial value)
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11. Programmable Timing Pattern Controller (TPC)
Bits 1 and 0⎯Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits
select the compare match event that triggers TPC output group 0 (TP3 to TP0).
Bit 1
G0CMS1
Bit 0
G0CMS0
0
0
TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit
timer channel 0
1
TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit
timer channel 1
0
TPC output group 0 (TP3 to TP0) is triggered by compare match in 16-bit
timer channel 2
1
TPC output group 0 (TP3 to TP0) is triggered by
compare match in 16-bit timer channel 2
1
Description
(Initial value)
11.2.10 TPC Output Mode Register (TPMR)
TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for
each group.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
Initial value
1
1
1
1
0
0
0
0
Read/Write
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
Reserved bits
Group 3 non-overlap
Selects non-overlapping TPC
output for group 3 (TP15 to TP12)
Group 2 non-overlap
Selects non-overlapping TPC
output for group 2 (TP11 to TP8 )
Group 1 non-overlap
Selects non-overlapping TPC
output for group 1 (TP7 to TP4 )
Group 0 non-overlap
Selects non-overlapping TPC
output for group 0 (TP3 to TP0 )
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G3NOV G2NOV
G1NOV G0NOV
11. Programmable Timing Pattern Controller (TPC)
The output trigger period of a non-overlapping TPC output waveform is set in general register B
(GRB) in the 16-bit timer channel selected for output triggering. The non-overlap margin is set in
general register A (GRA). The output values change at compare match A and B. For details see
section 11.3.4, Non-Overlapping TPC Output.
TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4⎯Reserved: These bits cannot be modified and are always read as 1.
Bit 3⎯Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for
group 3 (TP15 to TP12).
Bit 3
G3NOV
Description
0
Normal TPC output in group 3 (output values change at
compare match A in the selected 16-bit timer channel)
1
Non-overlapping TPC output in group 3 (independent 1 and 0 output at
compare match A and B in the selected 16-bit timer channel)
(Initial value)
Bit 2⎯Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for
group 2 (TP11 to TP8).
Bit 2
G2NOV
Description
0
Normal TPC output in group 2 (output values change at
compare match A in the selected 16-bit timer channel)
1
Non-overlapping TPC output in group 2 (independent 1 and 0 output at
compare match A and B in the selected 16-bit timer channel)
(Initial value)
Bit 1⎯Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for
group 1 (TP7 to TP4).
Bit 1
G1NOV
Description
0
Normal TPC output in group 1 (output values change at
compare match A in the selected 16-bit timer channel)
1
Non-overlapping TPC output in group 1 (independent 1 and 0 output at
compare match A and B in the selected 16-bit timer channel)
(Initial value)
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11. Programmable Timing Pattern Controller (TPC)
Bit 0⎯Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for
group 0 (TP3 to TP0).
Bit 0
G0NOV
Description
0
Normal TPC output in group 0 (output values change at
compare match A in the selected 16-bit timer channel)
1
Non-overlapping TPC output in group 0 (independent 1 and 0 output at
compare match A and B in the selected 16-bit timer channel)
11.3
Operation
11.3.1
Overview
(Initial value)
When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output
is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents.
When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit
contents are transferred to PADR or PBDR to update the output values.
Figure 11.2 illustrates the TPC output operation. Table 11.3 summarizes the TPC operating
conditions.
DDR
NDER
Q
Q
Output trigger signal
C
Q
DR
D
Q NDR
TPC output pin
Figure 11.2 TPC Output Operation
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D
Internal
data bus
11. Programmable Timing Pattern Controller (TPC)
Table 11.3 TPC Operating Conditions
NDER
DDR
Pin Function
0
0
Generic input port
1
Generic output port
0
Generic input port (but the DR bit is a read-only bit, and when compare
match occurs, the NDR bit value is transferred to the DR bit)
1
TPC pulse output
1
Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and
NDRB before the next compare match. For information on non-overlapping operation, see
section 11.3.4, Non-Overlapping TPC Output.
11.3.2
Output Timing
If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output
when the selected compare match event occurs. Figure 11.3 shows the timing of these operations
for the case of normal output in groups 2 and 3, triggered by compare match A.
φ
16TCNT
N
GRA
N+1
N
Compare
match A signal
NDRB
n
PBDR
m
n
TP8 to TP15
m
n
Figure 11.3 Timing of Transfer of Next Data Register Contents and Output (Example)
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11. Programmable Timing Pattern Controller (TPC)
11.3.3
Normal TPC Output
Sample Setup Procedure for Normal TPC Output: Figure 11.4 shows a sample procedure for
setting up normal TPC output.
Normal TPC output
16-bit timer
setup
Port and
TPC setup
16-bit timer
setup
Select GR functions
1
Set GRA value
2
Select counting operation
3
Select interrupt request
4
Set initial output data
5
Select port output
6
Enable TPC output
7
Select TPC output trigger
8
Set next TPC output data
9
Start counter
10
Compare match?
1.
Set TIOR to make GRA an output compare
register (with output inhibited).
2. Set the TPC output trigger period.
3. Select the counter clock source with bits
TPSC2 to TPSC0 in 16TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
4. Enable the IMFA interrupt in TISRA.
The DMAC can also be set up to transfer
data to the next data register.
5. Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
6. Set the DDR bits of the input/output port
pins to be used for TPC output to 1.
7. Set the NDER bits of the pins to be used for
TPC output to 1.
8. Select the 16-bit timer compare match event
to be used as the TPC output trigger in TPCR.
9. Set the next TPC output values in the NDR bits.
10. Set the STR bit to 1 in TSTR to start the
timer counter.
11. At each IMFA interrupt, set the next output
values in the NDR bits.
No
Yes
Set next TPC output data
11
Figure 11.4 Setup Procedure for Normal TPC Output (Example)
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11. Programmable Timing Pattern Controller (TPC)
Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11.5 shows
an example in which the TPC is used for cyclic five-phase pulse output.
TCNT value
Compare match
TCNT
GRA
H'0000
Time
NDRB
80
PBDR
00
C0
80
40
C0
60
40
20
60
30
20
10
30
18
10
08
18
88
08
80
88
C0
80
40
C0
TP15
TP14
TP13
TP12
TP11
•
•
•
•
The 16-bit timer channel to be used as the output trigger channel is set up so that GRA is an output
compare register and the counter will be cleared by compare match A. The trigger period is set in GRA.
The IMIEA bit is set to 1 in TISRA to enable the compare match A interrupt.
H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger.
Output data H'80 is written in NDRB.
The timer counter in this 16-bit timer channel is started. When compare match A occurs, the NDRB
contents are transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt
service routine writes the next output data (H'C0) in NDRB.
Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing
H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88É at successive IMFA interrupts. If the DMAC is set for
activation by this interrupt, pulse output can be obtained without loading the CPU.
Figure 11.5 Normal TPC Output Example (Five-Phase Pulse Output)
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11. Programmable Timing Pattern Controller (TPC)
11.3.4
Non-Overlapping TPC Output
Sample Setup Procedure for Non-Overlapping TPC Output: Figure 11.6 shows a sample
procedure for setting up non-overlapping TPC output.
Non-overlapping
TPC output
16-bit timer
setup
Port and
TPC setup
16-bit timer
setup
Select GR functions
1
Set GR values
2
Select counting operation
3
Select interrupt requests
4
Set initial output data
5
Set up TPC output
6
Enable TPC transfer
7
Select TPC transfer trigger
8
Select non-overlapping groups
9
Set next TPC output data
10
Start counter
11
Compare match A?
1. Set TIOR to make GRA and GRB output
compare registers (with output inhibited).
2. Set the TPC output trigger period in GRB
and the non-overlap margin in GRA.
3. Select the counter clock source with bits
TPSC2 to TPSC0 in 16TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
4. Enable the IMFA interrupt in TISRA.
The DMAC can also be set up to transfer
data to the next data register.
5. Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
6. Set the DDR bits of the input/output port pins
to be used for TPC output to 1.
7. Set the NDER bits of the pins to be used for
TPC output to 1.
8. In TPCR, select the 16-bit timer compare match
event to be used as the TPC output trigger.
9. In TPMR, select the groups that will operate
in non-overlap mode.
10. Set the next TPC output values in the NDR
bits.
11. Set the STR bit to 1 in TSTR to start the timer
counter.
12. At each IMFA interrupt, write the next output
value in the NDR bits.
No
Yes
Set next TPC output data
12
Figure 11.6 Setup Procedure for Non-Overlapping TPC Output (Example)
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11. Programmable Timing Pattern Controller (TPC)
Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 11.7 shows an example of the use of TPC output for four-phase
complementary non-overlapping pulse output.
16TCNT value
GRB
16TCNT
GRA
Time
H'0000
NDRB
95
PBDR
00
65
95
59
05
65
56
41
59
95
50
56
65
14
95
05
65
Non-overlap margin
TP15
TP14
TP13
TP12
TP11
TP10
TP9
TP8
• The 16-bit timer channel to be used as the output trigger channel is set up so that GRA and GRB are
output compare registers and the counter will be cleared by compare match B. The TPC output trigger
period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TISRA to enable
IMFA interrupts.
• H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger. Bits
G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is written in
NDRB.
• The timer counter in this 16-bit timer channel is started. When compare match B occurs, outputs change
from 1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed
by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB.
• Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95…
at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be
obtained without loading the CPU.
Figure 11.7 Non-Overlapping TPC Output Example (Four-Phase Complementary
Non-Overlapping Pulse Output)
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11. Programmable Timing Pattern Controller (TPC)
11.3.5
TPC Output Triggering by Input Capture
TPC output can be triggered by 16-bit timer input capture as well as by compare match. If GRA
functions as an input capture register in the 16-bit timer channel selected in TPCR, TPC output
will be triggered by the input capture signal. Figure 11.8 shows the timing.
φ
TIOC pin
Input capture
signal
N
NDR
M
DR
N
Figure 11.8 TPC Output Triggering by Input Capture (Example)
11.4
Usage Notes
11.4.1
Operation of TPC Output Pins
TP0 to TP15 are multiplexed with 16-bit timer, DMAC, address bus, and other pin functions. When
16-bit timer, DMAC, or address output is enabled, the corresponding pins cannot be used for TPC
output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage
of the pin.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
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11. Programmable Timing Pattern Controller (TPC)
11.4.2
Note on Non-Overlapping Output
During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as
follows.
1. NDR bits are always transferred to DR bits at compare match A.
2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Figure 11.9 illustrates the non-overlapping TPC output operation.
DDR
NDER
Q
Q
Compare match A
Compare match B
C
Q
DR
D
Q NDR
D
TPC output pin
Figure 11.9 Non-Overlapping TPC Output
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A. NDR contents should not be altered during the interval from compare match B
to compare match A (the non-overlap margin).
This can be accomplished by having the IMFA interrupt service routine write the next data in
NDR, or by having the IMFA interrupt activate the DMAC. The next data must be written before
the next compare match B occurs.
Figure 11.10 shows the timing relationships.
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11. Programmable Timing Pattern Controller (TPC)
Compare
match A
Compare
match B
NDR write
NDR write
NDR
DR
0 output
0/1 output
0 output
Write to NDR
in this interval
Do not write
to NDR in this
interval
0/1 output
Write to NDR
in this interval
Do not write
to NDR in this
interval
Figure 11.10 Non-Overlapping Operation and NDR Write Timing
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12. Watchdog Timer
Section 12 Watchdog Timer
12.1
Overview
The H8/3006 and H8/3007 have an on-chip watchdog timer (WDT). The WDT has two selectable
functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an
interval timer. As a watchdog timer, it generates a reset signal for the H8/3006 and H8/3007 chip
if a system crash allows the timer counter (TCNT) to overflow before being rewritten. In interval
timer operation, an interval timer interrupt is requested at each TCNT overflow.
12.1.1
Features
WDT features are listed below.
• Selection of eight counter clock sources
φ/2, φ /32, φ /64, φ /128, φ /256, φ /512, φ /2048, or φ /4096
• Interval timer option
• Timer counter overflow generates a reset signal or interrupt.
The reset signal is generated in watchdog timer operation. An interval timer interrupt is
generated in interval timer operation.
• Watchdog timer reset signal resets the entire H8/3006 and H8/3007 internally, and can also be
output externally.
The reset signal generated by timer counter overflow during watchdog timer operation resets
the entire H8/3006 and H8/3007 internally. An external reset signal can be output from the
RESO pin to reset other system devices simultaneously.
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12. Watchdog Timer
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the WDT.
Overflow
TCNT
Interrupt
(interval timer) control
Interrupt signal
TCSR
Reset control
Internal
data bus
Internal clock sources
φ/2
RSTCSR
Reset
(internal, external)
Read/
write
control
φ/32
φ/64
Clock
Clock
selector
φ/128
φ/256
φ/512
Legend:
TCNT:
Timer counter
TCSR:
Timer control/status register
RSTCSR: Reset control/status register
φ/2048
φ/4096
Figure 12.1 WDT Block Diagram
12.1.3
Pin Configuration
Table 12.1 describes the WDT output pin.
Table 12.1 WDT Pin
Name
Reset output
Note:
*
Abbreviation
I/O
Function
RESO
Output*
External output of the watchdog timer reset signal
Open-drain output.
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12. Watchdog Timer
12.1.4
Register Configuration
Table 12.2 summarizes the WDT registers.
Table 12.2 WDT Registers
1
Address*
Write*
2
Read
Name
Abbreviation
H'FFF8C H'FFF8C Timer control/status register
H'FFF8D Timer counter
H'FFF8E H'FFF8F Reset control/status register
R/W
TCSR
R/(W)*
TCNT
R/W
RSTCSR
R/(W)*
Initial Value
3
H'18
H'00
3
H'3F
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Write word data starting at this address.
3. Only 0 can be written in bit 7, to clear the flag.
12.2
Register Descriptions
12.2.1
Timer Counter (TCNT)
TCNT is an 8-bit readable and writable up-counter.
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: TCNT is write-protected by a password. For details see section 12.2.4, Notes on Register
Access.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when
the TME bit is cleared to 0.
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12. Watchdog Timer
12.2.2
Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and
clock source.
Bit
7
6
5
4
3
2
1
0
OVF
WT/IT
TME
⎯
⎯
CKS2
CKS1
CKS0
Initial value
0
0
0
1
1
0
0
0
Read/Write
R/(W) *
R/W
R/W
⎯
⎯
R/W
R/W
R/W
Clock select
These bits select the
TCNT clock source
Reserved bits
Timer enable
Selects whether TCNT runs or halts
Timer mode select
Selects the mode
Overflow flag
Status flag indicating overflow
Notes: TCSR is write-protected by a password. For details see section 12.2.4, Notes on Register
Access.
* Only 0 can be written, to clear the flag.
Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a
reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values.
Bit 7⎯Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed
from H'FF to H'00.
Bit 7
OVF
Description
0
[Clearing condition]
1
[Setting condition]
Cleared by reading OVF when OVF = 1, then writing 0 in OVF
Set when TCNT changes from H'FF to H'00
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(Initial value)
12. Watchdog Timer
Bit 6⎯Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when
TCNT overflows.
Bit 6
WT/IT
Description
0
Interval timer: requests interval timer interrupts
1
Watchdog timer: generates a reset signal
(Initial value)
Bit 5⎯Timer Enable (TME): Selects whether TCNT runs or is halted. When WT/IT = 1, clear
the software standby bit (SSBY) to 0 in SYSCR before setting TME. When setting SSBY to 1,
TME should be cleared to 0.
Bit 5
TME
Description
0
TCNT is initialized to H'00 and halted
1
TCNT is counting
(Initial value)
Bits 4 and 3⎯Reserved: These bits cannot be modified and are always read as 1.
Bits 2 to 0⎯Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by prescaling the system clock (φ), for input to TCNT.
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
0
φ/2
1
φ/32
0
φ/64
1
φ/128
0
φ/256
1
φ/512
0
φ/2048
1
φ/4096
1
1
0
1
(Initial value)
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12. Watchdog Timer
12.2.3
Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Bit
7
6
5
4
3
2
1
0
WRST
RSTOE
⎯
⎯
⎯
⎯
⎯
⎯
Initial value
0
0
1
1
1
1
1
1
Read/Write
R/(W)*
R/W
⎯
⎯
⎯
⎯
⎯
⎯
Reserved bits
Reset output enable
Enables or disables external output of the reset signal
Watchdog timer reset
Indicates that a reset signal has been generated
Notes: RSTCSR is write-protected by a password. For details see section 12.2.4, Notes on
Register Access.
* Only 0 can be written in bit 7, to clear the flag.
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Bit 7⎯Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3006 and
H8/3007 chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO
pin to initialize external system devices.
Bit 7
WRST
Description
0
[Clearing condition]
Reset signal at RES pin.
Read WRST when WRST =1, then write 0 in WRST.
1
(Initial value)
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
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12. Watchdog Timer
Bit 6⎯Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of
the reset signal generated if TCNT overflows during watchdog timer operation.
Bit 6
RSTOE Description
0
Reset signal is not output externally
1
Reset signal is output externally
(Initial value)
Bits 5 to 0⎯Reserved: These bits cannot be modified and are always read as 1.
12.2.4
Notes on Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte instructions. Figure 12.2 shows the format of data written to
TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be
contained in the lower byte of the written word. The upper byte must contain H'5A (password for
TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT
or TCSR.
15
TCNT write
Address
H'FFF8C *
H'5A
H'FFF8C *
0
Write data
15
TCSR write
Address
8 7
8 7
H'A5
0
Write data
Note: * Lower 20 bits of the address in advanced mode.
Figure 12.2 Format of Data Written to TCNT and TCSR
Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be
written by byte transfer instructions. Figure 12.3 shows the format of data written to RSTCSR. To
write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower
byte. The data (H'00) in the lower byte is written to RSTCSR, clearing the WRST bit to 0. To
write to the RSTOE bit, the upper byte must contain H'5A and the lower byte must contain the
write data. Writing this word transfers a write data value into the RSTOE bit.
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12. Watchdog Timer
Writing 0 in WRST bit
Address
Writing to RSTOE bit
Address
15
H'FFF8E*
8 7
H'A5
15
H'FFF8E*
0
H'00
8 7
H'5A
0
Write data
Note: * Lower 20 bits of the address in advanced mode.
Figure 12.3 Format of Data Written to RSTCSR
Reading TCNT, TCSR, and RSTCSR: For reads of TCNT, TCSR, and RSTCSR, address
H'FFF8C is assigned to TCSR, address H'FFF8D to TCNT, and address H'FFF8F to RSTCSR.
These registers are therefore read like other registers. Byte transfer instructions can be used for
reading. Table 12.3 lists the read addresses of TCNT, TCSR, and RSTCSR.
Table 12.3 Read Addresses of TCNT, TCSR, and RSTCSR
Address*
Register
H'FFF8C
TCSR
H'FFF8D
TCNT
H'FFF8F
Note:
12.3
*
RSTCSR
Lower 20 bits of the address in advanced mode.
Operation
Operations when the WDT is used as a watchdog timer and as an interval timer are described
below.
12.3.1
Watchdog Timer Operation
Figure 12.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the
WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the
TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and
overflows due to a system crash etc., the H8/3006 and H8/3007 are internally reset for a duration
of 518 states.
The watchdog reset signal can be externally output from the RESO pin to reset external system
devices. The reset signal is output externally for 132 states. External output can be enabled or
disabled by the RSTOE bit in RSTCSR.
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12. Watchdog Timer
A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can
distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR.
If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority.
WDT overflow
H'FF
TME set to 1
TCNT count
value
H'00
OVF = 1
Start
Internal
reset signal
H'00 written
in TCNT
Reset
H'00 written
in TCNT
518 states
RESO
132 states
Figure 12.4 Operation in Watchdog Timer Mode
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12. Watchdog Timer
12.3.2
Interval Timer Operation
Figure 12.5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit
WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each
TCNT overflow. This function can be used to generate interval timer interrupts at regular
intervals.
H'FF
TCNT
count value
Time t
H'00
WT/ IT = 0
TME = 1
Interval
timer
interrupt
Interval
timer
interrupt
Interval
timer
interrupt
Interval
timer
interrupt
Figure 12.5 Interval Timer Operation
12.3.3
Timing of Setting of Overflow Flag (OVF)
Figure 12.6 shows the timing of setting of the OVF flag. The OVF flag is set to 1 when TCNT
overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval
timer interrupt is generated in interval timer operation.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 12.6 Timing of Setting of OVF
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12. Watchdog Timer
12.3.4
Timing of Setting of Watchdog Timer Reset Bit (WRST)
The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR.
Figure 12.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is
set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is
generated for the entire H8/3006 and H8/3007 chip. This internal reset signal clears OVF to 0, but
the WRST bit remains set to 1. The reset routine must therefore clear the WRST bit.
φ
H'FF
TCNT
H'00
Overflow signal
OVF
WDT internal
reset
WRST
Figure 12.7 Timing of Setting of WRST Bit and Internal Reset
12.4
Interrupts
During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The
interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR.
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12. Watchdog Timer
12.5
Usage Notes
Contention between TCNT Write and Increment: If a timer counter clock pulse is generated
during the T3 state of a write cycle to TCNT, the write takes priority and the timer count is not
incremented. See figure 12.8.
CPU: TCNT write cycle
T1
T2
T3
φ
TCNT
Internal write
signal
TCNT input
clock
TCNT
N
M
Counter write data
Figure 12.8 Contention between TCNT Write and Count up
Changing CKS2 to CKS0 Bit: Halt TCNT by clearing the TME bit to 0 in TCSR before
changing the values of bits CKS2 to CKS0.
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13. Serial Communication Interface
Section 13 Serial Communication Interface
13.1
Overview
The H8/3006 and H8/3007 have a serial communication interface (SCI) with three independent
channels. All three channels have identical functions. The SCI can communicate in both
asynchronous and synchronous mode. It also has a multiprocessor communication function for
serial communication among two or more processors.
When the SCI is not used, it can be halted to conserve power. Each SCI channel can be halted
independently. For details, see section 19.6, Module Standby Function.
The SCI also has a smart card interface function conforming to the ISO/IEC 7816-3 (Identification
Card) standard. This function supports serial communication with a smart card. Switching
between the normal serial communication interface and the smart card interface is carried out by
means of a register setting.
13.1.1
Features
SCI features are listed below.
• Selection of synchronous or asynchronous mode for serial communication
Asynchronous mode
Serial data communication is synchronized one channel at a time. The SCI can communicate
with a universal asynchronous receiver/transmitter (UART), asynchronous communication
interface adapter (ACIA), or other chip that employs standard asynchronous communication. It
can also communicate with two or more other processors using the multiprocessor
communication function. There are twelve selectable serial data transfer formats.
⎯ Data length:
7 or 8 bits
⎯ Stop bit length:
1 or 2 bits
⎯ Parity:
even/odd/none
⎯ Multiprocessor bit:
1 or 0
⎯ Receive error detection: parity, overrun, and framing errors
⎯ Break detection:
by reading the RxD level directly when a framing error occurs
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13. Serial Communication Interface
Synchronous mode
Serial data communication is synchronized with a clock signal. The SCI can communicate with
other chips having a synchronous communication function.
There is a single serial data communication format.
⎯ Data length:
8 bits
⎯ Receive error detection: overrun errors
• Full-duplex communication
The transmitting and receiving sections are independent, so the SCI can transmit and receive
simultaneously. The transmitting and receiving sections are both double-buffered, so serial
data can be transmitted and received continuously.
• The following settings can be made for the serial data to be transferred:
⎯ LSB-first or MSB-first transfer
⎯ Inversion of data logic level
• Built-in baud rate generator with selectable bit rates
• Selectable transmit/receive clock sources: internal clock from baud rate generator, or external
clock from the SCK pin
• Four types of interrupts
Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested
independently. The transmit-data-empty and receive-data-full interrupts from SCI0 can
activate the DMA controller (DMAC) to transfer data.
Features of the smart card interface are listed below.
• Asynchronous communication
⎯ Data length: 8 bits
⎯ Parity bits generated and checked
⎯ Error signal output in receive mode (parity error)
⎯ Error signal detect and automatic data retransmit in transmit mode
⎯ Supports both direct convention and inverse convention
• Built-in baud rate generator with selectable bit rates
• Three types of interrupts
Transmit-data-empty, receive-data-full, and transmit/receive-error interrupts are requested
independently. The transmit-data-empty and receive-data-full interrupts can activate the DMA
controller (DMAC) to transfer data.
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13. Serial Communication Interface
13.1.2
Block Diagram
Bus interface
Figure 13.1 shows a block diagram of the SCI.
Module data bus
RDR
TDR
SSR
BRR
SCR
RxD
TxD
RSR
TSR
φ
SMR
Baud rate
generator
SCMR
Transmit/receive
control
Parity generate
Parity check
SCK
Internal
data bus
φ/ 4
φ/16
φ/64
Clock
External clock
TEI
TXI
RXI
ERI
Legend:
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
SCMR: Smart card mode register
Figure 13.1 SCI Block Diagram
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13. Serial Communication Interface
13.1.3
Pin Configuration
The SCI has serial pins for each channel as listed in table 13.1.
Table 13.1 SCI Pins
Channel Name
Abbreviation
I/O
Function
0
Serial clock pin
SCK0
Input/output
SCI0 clock input/output
Receive data pin
RxD0
Input
SCI0 receive data input
Transmit data pin
TxD0
Output
SCI0 transmit data output
Serial clock pin
SCK1
Input/output
SCI1 clock input/output
Receive data pin
RxD1
Input
SCI1 receive data input
Transmit data pin
TxD1
Output
SCI1 transmit data output
Serial clock pin
SCK2
Input/output
SCI2 clock input/output
Receive data pin
RxD2
Input
SCI2 receive data input
Transmit data pin
TxD2
Output
SCI2 transmit data output
1
2
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13. Serial Communication Interface
13.1.4
Register Configuration
The SCI has internal registers as listed in table 13.2. These registers select asynchronous or
synchronous mode, specify the data format and bit rate, control the transmitter and receiver
sections, and specify switching between the serial communication interface and smart card
interface.
Table 13.2 SCI Registers
1
Channel
Address*
Name
Abbreviation
R/W
Initial Value
0
H'FFFB0
Serial mode register
SMR
R/W
H'00
H'FFFB1
Bit rate register
BRR
R/W
H'FF
H'FFFB2
Serial control register
SCR
R/W
H'00
H'FFFB3
Transmit data register
TDR
R/W
H'FF
H'FFFB4
Serial status register
SSR
R/(W)* H'84
H'FFFB5
Receive data register
RDR
R
H'00
H'FFFB6
Smart card mode register
SCMR
R/W
H'F2
H'FFFB8
Serial mode register
SMR
R/W
H'00
H'FFFB9
Bit rate register
BRR
R/W
H'FF
H'FFFBA
Serial control register
SCR
R/W
H'00
H'FFFBB
Transmit data register
TDR
R/W
H'FFFBC
Serial status register
SSR
R/(W)* H'84
H'FFFBD
Receive data register
RDR
R
H'00
H'FFFBE
Smart card mode register
SCMR
R/W
H'F2
H'FFFC0
Serial mode register
SMR
R/W
H'00
H'FFFC1
Bit rate register
BRR
R/W
H'FF
H'FFFC2
Serial control register
SCR
R/W
H'00
H'FFFC3
Transmit data register
TDR
R/W
1
2
2
H'FF
2
H'FF
2
H'FFFC4
Serial status register
SSR
R/(W)* H'84
H'FFFC5
Receive data register
RDR
R
H'00
H'FFFC6
Smart card mode register
SCMR
R/W
H'F2
Notes: 1. Indicates the lower 20 bits of the address in advanced mode.
2. Only 0 can be written, to clear flags.
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13. Serial Communication Interface
13.2
Register Descriptions
13.2.1
Receive Shift Register (RSR)
RSR is the register that receives serial data.
Bit
7
6
5
4
3
2
1
0
Read/Write
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first,
thereby converting the data to parallel data. When one byte of data has been received, it is
automatically transferred to RDR. The CPU cannot read or write RSR directly.
13.2.2
Receive Data Register (RDR)
RDR is the register that stores received serial data.
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
When the SCI has received one byte of serial data, it transfers the received data from RSR into
RDR for storage, completing the receive operation. RSR is then ready to receive the next data.
This double-buffering allows data to be received continuously.
RDR is a read-only register. Its contents cannot be modified by the CPU. RDR is initialized to
H'00 by a reset and in standby mode.
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13. Serial Communication Interface
13.2.3
Transmit Shift Register (TSR)
TSR is the register that transmits serial data.
Bit
7
6
5
4
3
2
1
0
Read/Write
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
The SCI loads transmit data from TDR to TSR, then transmits the data serially from the TxD pin,
LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit
data from TDR into TSR and starts transmitting it. If the TDRE flag is set to 1 in SSR, however,
the SCI does not load the TDR contents into TSR. The CPU cannot read or write TSR directly.
13.2.4
Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for serial transmission.
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When the SCI detects that TSR is empty, it moves transmit data written in TDR from TDR into
TSR and starts serial transmission. Continuous serial transmission is possible by writing the next
transmit data in TDR during serial transmission from TSR.
The CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in standby
mode.
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13. Serial Communication Interface
13.2.5
Serial Mode Register (SMR)
SMR is an 8-bit register that specifies the SCI's serial communication format and selects the clock
source for the baud rate generator.
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Clock select 1/0
These bits select the
baud rate generator's
clock source
Multiprocessor mode
Selects the multiprocessor
function
Stop bit length
Selects the stop bit length
Parity mode
Selects even or odd parity
Parity enable
Selects whether a parity bit is added
Character length
Selects character length in asynchronous mode
Communication mode
Selects asynchronous or synchronous mode
The CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in standby
mode.
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13. Serial Communication Interface
Bit 7⎯Communication Mode (C/A)/GSM Mode (GM): The function of this bit differs for the
normal serial communication interface and for the smart card interface. Its function is switched
with the SMIF bit in SCMR.
For serial communication interface (SMIF bit in SCMR cleared to 0): Selects whether the SCI
operates in asynchronous or synchronous mode.
Bit 7
C/A
Description
0
Asynchronous mode
1
Synchronous mode
(Initial value)
For smart card interface (SMIF bit in SCMR set to 1): Selects GSM mode for the smart card
interface.
Bit 7
GM
Description
0
The TEND flag is set 12.5 etu after the start bit
1
The TEND flag is set 11.0 etu after the start bit
(Initial value)
Note: etu: Elementary time unit (time required to transmit one bit)
Bit 6⎯Character Length (CHR): Selects 7-bit or 8-bits data length in asynchronous mode. In
synchronous mode, the data length is 8 bits regardless of the CHR setting,
Bit 6
CHR
Description
0
8-bit data
1
Note:
(Initial value)
7-bit data*
*
When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
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13. Serial Communication Interface
Bit 5⎯Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a
parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode,
the parity bit is neither added nor checked, regardless of the PE bit setting.
Bit 5
PE
Description
0
Parity bit not added or checked
1
Parity bit added and checked*
Note:
*
(Initial value)
When PE bit is set to 1, an even or odd parity bit is added to transmit data according to
the even or odd parity mode selection by the O/E bit, and the parity bit in receive data is
checked to see that it matches the even or odd mode selected by the O/E bit.
Bit 4⎯Parity Mode (O/E): Selects even or odd parity. The O/E bit setting is only valid when the
PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit
setting is ignored in synchronous mode, or when parity addition and checking is disabled in
asynchronous mode.
Bit 4
O/E
Description
0
Even parity*
1
2
Odd parity*
1
(Initial value)
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even
number of 1s in the transmitted character and parity bit combined. Receive data must
have an even number of 1s in the received character and parity bit combined.
2. When odd parity is selected, the parity bit added to transmit data makes an odd number
of 1s in the transmitted character and parity bit combined. Receive data must have an
odd number of 1s in the received character and parity bit combined.
Bit 3⎯Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting
is used only in asynchronous mode. In synchronous mod no stop bit is added, so the STOP bit
setting is ignored.
Bit 3
STOP
Description
0
1 stop bit*
1
1
2 stop bits*
(Initial value)
2
Notes: 1. One stop bit (with value 1) is added to the end of each transmitted character.
2. Two stop bits (with value 1) are added to the end of each transmitted character.
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13. Serial Communication Interface
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit. If the second stop bit is 0, it is treated as the start bit of the
next incoming character.
Bit 2⎯Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor
format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is
valid only in asynchronous mode. It is ignored in synchronous mode.
For further information on the multiprocessor communication function, see section 13.3.3,
Multiprocessor Communication.
Bit 2
MP
Description
0
Multiprocessor function disabled
1
Multiprocessor format selected
(Initial value)
Bits 1 and 0⎯Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the onchip baud rate generator. Four clock sources are available: φ, φ/4, φ/16, and φ/64.
For the relationship between the clock source, bit rate register setting, and baud rate, see section
13.2.8, Bit Rate Register (BRR).
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
φ
0
1
φ/4
1
0
φ/16
1
1
φ/64
(Initial value)
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13. Serial Communication Interface
13.2.6
Serial Control Register (SCR)
SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock
output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock
source.
Bit
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
0
0
0
0
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
Clock enable 1/0
These bits select the
SCI clock source
Transmit-end interrupt enable
Enables or disables transmit-end
interrupts (TEI)
Multiprocessor interrupt enable
Enables or disables multiprocessor
interrupts
Receive enable
Enables or disables the receiver
Transmit enable
Enables or disables the transmitter
Receive interrupt enable
Enables or disables receive-data-full interrupts (RXI) and
receive-error interrupts (ERI)
Transmit interrupt enable
Enables or disables transmit-data-empty interrupts (TXI)
The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby
mode.
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13. Serial Communication Interface
Bit 7⎯Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from
TDR to TSR.
Bit 7
TIE
Description
0
Transmit-data-empty interrupt request (TXI) is disabled*
1
Transmit-data-empty interrupt request (TXI) is enabled
Note:
*
(Initial value)
TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then
clearing it to 0; or by clearing the TIE bit to 0.
Bit 6⎯Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI)
requested when the RDRF flag in SSR is set to 1 due to transfer of serial receive data from RSR to
RDR; also enables or disables the receive-error interrupt (ERI).
Bit 6
RIE
Description
0
Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled*
(Initial value)
1
Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled
Note:
*
RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF,
FER, PER, or ORER flag, then clearing the flag to 0; or by clearing the RIE bit to 0.
Bit 5⎯Transmit Enable (TE): Enables or disables the start of SCI serial transmitting operations.
Bit 5
TE
Description
0
Transmitting disabled*
1
2
Transmitting enabled*
1
(Initial value)
Notes: 1. The TDRE flag is fixed at 1 in SSR.
2. In the enabled state, serial transmission starts when the TDRE flag in SSR is cleared to
0 after writing of transmit data into TDR. Select the transmit format in SMR before
setting the TE bit to 1.
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13. Serial Communication Interface
Bit 4⎯Receive Enable (RE): Enables or disables the start of SCI serial receiving operations.
Bit 4
RE
Description
0
Receiving disabled*
1
Receiving enabled*
1
(Initial value)
2
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These
flags retain their previous values.
2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous
mode, or serial clock input is detected in synchronous mode. Select the receive format
in SMR before setting the RE bit to 1.
Bit 3⎯Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in
SMR. The MPIE bit setting is ignored in synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE
Description
0
Multiprocessor interrupts are disabled (normal receive operation) (Initial value)
[Clearing conditions]
1
•
The MPIE bit is cleared to 0
•
MPB = 1 in received data
Multiprocessor interrupts are enabled*
Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of
the RDRF, FER, and ORER status flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Note:
*
The SCI does not transfer receive data from RSR to RDR, does not detect receive
errors, and does not set the RDRF, FER, and ORER flags in SSR. When it receives
data in which MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the
MPIE bit to 0, enables RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to
1), and allows the FER and ORER flags to be set.
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13. Serial Communication Interface
Bit 2⎯Transmit-End interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.
Bit 2
TEIE
Description
0
Transmit-end interrupt requests (TEI) are disabled*
1
Note:
(Initial value)
Transmit-end interrupt requests (TEI) are enabled*
*
TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in
SSR, then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by
clearing the TEIE bit to 0.
Bits 1 and 0⎯Clock Enable 1 and 0 (CKE1, CKE0): The function of these bits differs for the
normal serial communication interface and for the smart card interface. Their function is switched
with the SMIF bit in SCMR.
For serial communication interface (SMIF bit in SCMR cleared to 0): These bits select the
SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings
of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or
serial clock input.
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external
clock source is selected (CKE1 = 1). Select the SCI operating mode in SMR before setting the
CKE1 and CKE0 bits. For further details on selection of the SCI clock source, see table 13.9 in
section 13.3, Operation.
Bit 1 Bit 0
CKE1 CKE0 Description
0
0
0
1
Asynchronous mode
Internal clock, SCK pin available for generic input/output*
Synchronous mode
Internal clock, SCK pin used for serial clock output*
Asynchronous mode
Internal clock, SCK pin used for clock output*
Synchronous mode
Internal clock, SCK pin used for serial clock output
External clock, SCK pin used for clock input*
1
1
2
3
1
0
Asynchronous mode
Synchronous mode
External clock, SCK pin used for serial clock input
1
1
Asynchronous mode
External clock, SCK pin used for clock input*
Synchronous mode
External clock, SCK pin used for serial clock input
3
Notes: 1. Initial value
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 times the bit rate.
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13. Serial Communication Interface
For smart card interface (SMIF bit in SCMR set to 1): These bits, together with the GM bit in
SMR, determine whether the SCK pin is used for generic input/output or as the serial clock output
pin.
SMR
GM
Bit 1 Bit 0
CKE1 CKE0 Description
0
0
0
SCK pin available for generic input/output
0
0
1
SCK pin used for clock output
1
0
0
SCK pin output fixed low
1
0
1
SCK pin used for clock output
1
1
0
SCK pin output fixed high
1
1
1
SCK pin used for clock output
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(Initial value)
13. Serial Communication Interface
13.2.7
Serial Status Register (SSR)
SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the
operating status of the SCI.
Bit
7
6
TDRE
RDRF
1
Initial value
R/(W)*
4
ORER FER/ERS
0
1
Read/Write
5
0
1
R/(W)*
R/(W)*
0
1
R/(W)*
3
2
1
0
PER
TEND
MPB
MPBT
1
0
0
R
R
R/W
0
1
1
R/(W)*
Multiprocessor
bit transfer
Value of multiprocessor
bit to be transmitted
Multiprocessor bit
Stores the received
multiprocessor bit
value
Transmit end*2
Status flag indicating end of
transmission
Parity error
Status flag indicating detection of a
receive parity error
Framing error (FER)/Error signal status (ERS)*2
Status flag indicating detection of a receive framing
error, or flag indicating detection of an error signal
Overrun error
Status flag indicating detection of a receive overrun error
Receive data register full
Status flag indicating that data has been received and stored in RDR
Transmit data register empty
Status flag indicating that transmit data has been transferred from
TDR into TSR and new data can be written in TDR
Notes: 1.
2.
Only 0 can be written, to clear the flag.
Function differs between the normal serial communication interface and
the smart card interface.
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13. Serial Communication Interface
The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER,
and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The
TEND and MPB flags are read-only bits that cannot be written.
SSR is initialized to H'84 by a reset and in standby mode.
Bit 7⎯Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from TDR into TSR and the next serial data can be written in TDR.
Bit 7
TDRE
Description
0
TDR contains valid transmit data
[Clearing conditions]
1
•
Read TDRE when TDRE = 1, then write 0 in TDRE
•
The DMAC writes data in TDR
TDR does not contain valid transmit data
(Initial value)
[Setting conditions]
•
The chip is reset or enters standby mode
•
The TE bit in SCR is cleared to 0
•
TDR contents are loaded into TSR, so new data can be written in TDR
Bit 6⎯Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.
Bit 6
RDRF
Description
0
RDR does not contain new receive data
(Initial value)
[Clearing conditions]
1
•
The chip is reset or enters standby mode
•
Read RDRF when RDRF = 1, then write 0 in RDRF
•
The DMAC reads data from RDR
RDR contains new receive data
[Setting condition]
Serial data is received normally and transferred from RSR to RDR
Note: The RDR contents and the RDRF flag are not affected by detection of receive errors or by
clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still
set to 1 when reception of the next data ends, an overrun error will occur and the receive
data will be lost.
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13. Serial Communication Interface
Bit 5⎯Overrun Error (ORER): Indicates that data reception ended abnormally due to an
overrun error.
Bit 5
ORER
Description
0
Receiving is in progress or has ended normally*
1
(Initial value)
[Clearing conditions]
1
•
The chip is reset or enters standby mode
•
Read ORER when ORER = 1, then write 0 in ORER
A receive overrun error occurred*
2
[Setting condition]
Reception of the next serial data ends when RDRF = 1
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its
previous value.
2. RDR continues to hold the receive data prior to the overrun error, so subsequent
receive data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 4⎯Framing Error (FER)/Error Signal Status (ERS): The function of this bit differs for the
normal serial communication interface and for the smart card interface. Its function is switched
with the SMIF bit in SCMR.
For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that data
reception ended abnormally due to a framing error in asynchronous mode.
Bit 4
FER
Description
0
Receiving is in progress or has ended normally*
1
(Initial value)
[Clearing conditions]
1
•
The chip is reset or enters standby mode
•
Read FER when FER = 1, then write 0 in FER
A receive framing error occurred
[Setting condition]
The stop bit at the end of the receive data is checked and found to be 0*
2
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous
value.
2. When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is not
checked. When a framing error occurs the SCI transfers the receive data into RDR but
does not set the RDRF flag. Serial receiving cannot continue while the FER flag is set
to 1. In synchronous mode, serial transmitting is also disabled.
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13. Serial Communication Interface
For smart card interface (SMIF bit in SCMR set to 1): Indicates the status of the error signal
sent back from the receiving side during transmission. Framing errors are not detected in smart
card interface mode.
Bit 4
ERS
Description
0
Normal reception, no error signal*
(Initial value)
[Clearing conditions]
1
•
The chip is reset or enters standby mode
•
Read ERS when ERS = 1, then write 0 in ERS
An error signal has been sent from the receiving side indicating detection of a
parity error
[Setting condition]
The error signal is low when sampled
Note:
*
Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous
value.
Bit 3⎯Parity Error (PER): Indicates that data reception ended abnormally due to a parity error
in asynchronous mode.
Bit 3
PER
Description
0
Receiving is in progress or has ended normally*
1
(Initial value)
[Clearing conditions]
1
•
The chip is reset or enters standby mode
•
Read PER when PER = 1, then write 0 in PER
A receive parity error occurred*
2
[Setting condition]
The number of 1s in receive data, including the parity bit, does not match the
even or odd parity setting of O/E in SMR
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous
value.
2. When a parity error occurs the SCI transfers the receive data into RDR but does not set
the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 2⎯Transmit End (TEND): The function of this bit differs for the normal serial
communication interface and for the smart card interface. Its function is switched with the SMIF
bit in SCMR.
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13. Serial Communication Interface
For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that when the
last bit of a serial character was transmitted TDR did not contain valid transmit data, so
transmission has ended. The TEND flag is a read-only bit and cannot be written.
Bit 2
TEND
Description
0
Transmission is in progress
[Clearing conditions]
1
•
Read TDRE when TDRE = 1, then write 0 in TDRE
•
The DMAC writes data in TDR
End of transmission
(Initial value)
[Setting conditions]
•
The chip is reset or enters standby mode
•
The TE bit in SCR is cleared to 0
•
TDRE is 1 when the last bit of a 1-byte serial transmit character is
transmitted
For smart card interface (SMIF bit in SCMR set to 1): Indicates that when the last bit of a
serial character was transmitted TDR did not contain valid transmit data, so transmission has
ended. The TEND flag is a read-only bit and cannot be written.
Bit 2
TEND
0
Description
Transmission is in progress
[Clearing conditions]
1
•
Read TDRE when TDRE = 1, then write 0 in TDRE
•
The DMAC writes data in TDR
End of transmission
(Initial value)
[Setting conditions]
•
The chip is reset or enters standby mode
•
The TE bit is cleared to 0 in SCR and the FER/ERS bit is also cleared to 0
•
TDRE is 1 and FER/ERS is 0 (normal transmission) 2.5 etu (when GM = 0)
or 1.0 etu (when GM = 1) after a 1-byte serial character is transmitted
Note: etu: Elementary time unit (time required to transmit one bit)
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13. Serial Communication Interface
Bit 1⎯Multiprocessor bit (MPB): Stores the value of the multiprocessor bit in the receive data
when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit, and cannot
be written.
Bit 1
MPB
Description
0
Multiprocessor bit value in receive data is 0*
1
Multiprocessor bit value in receive data is 1
Note:
(Initial value)
If the RE bit in SCR is cleared to 0 when a multiprocessor format is selected, MPB
retains its previous value.
*
Bit 0⎯Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format in selected for transmitting in asynchronous mode.
The MPBT bit setting is ignored in synchronous mode, when a multiprocessor format is not
selected, or when the SCI cannot transmit.
Bit 0
MPBT
Description
0
Multiprocessor bit value in transmit data is 0
1
Multiprocessor bit value in transmit data is 1
13.2.8
(Initial value)
Bit Rate Register (BRR)
BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR that select the baud
rate generator clock source, determines the serial communication bit rate.
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby
mode. Each SCI channel has independent baud rate generator control, so different values can be
set in the three channels.
Table 13.3 shows examples of BRR settings in asynchronous mode. Table 13.4 shows examples of
BRR settings in synchronous mode.
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13. Serial Communication Interface
Table 13.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode
φ (MHz)
2
2.097152
2.4576
3
Bit Rate
(bit/s)
n
N
110
1
141 0.03
1
148 −0.04
1
174 −0.26
1
212 0.03
150
1
103 0.16
1
108 0.21
1
127 0.00
1
155 0.16
300
0
207 0.16
0
217 0.21
0
255 0.00
1
77
600
0
103 0.16
0
108 0.21
0
127 0.00
0
155 0.16
1200
0
51
0.16
0
54
−0.70
0
63
0.00
0
77
0.16
2400
0
25
0.16
0
26
1.14
0
31
0.00
0
38
0.16
4800
0
12
0.16
0
13
−2.48
0
15
0.00
0
19
−2.34
9600
0
6
−6.99
0
6
−2.48
0
7
0.00
0
9
−2.34
19200
0
2
8.51
0
2
13.78
0
3
0.00
0
4
−2.34
31250
0
1
0.00
0
1
4.86
0
1
22.88
0
2
0.00
38400
0
1
−18.62
0
1
−14.67
0
1
0.00
⎯
⎯
⎯
Error (%) n
N
Error (%) n
N
Error (%) n
N
Error (%)
0.16
φ (MHz)
3.6864
4
4.9152
5
Bit Rate
(bit/s)
n
N
Error (%) n
N
Error (%) n
N
Error (%) n
N
Error (%)
110
2
64
0.07
2
70
0.03
2
86
0.31
2
88
−0.25
150
1
191 0.00
1
207 0.16
1
255 0.00
2
64
0.16
300
1
95
0.00
1
103 0.16
1
127 0.00
1
129 0.16
600
0
191 0.00
0
207 0.16
0
255 0.00
1
64
1200
0
95
0.00
0
103 0.16
0
127 0.00
0
129 0.16
2400
0
47
0.00
0
51
0.16
0
63
0.00
0
64
0.16
4800
0
23
0.00
0
25
0.16
0
31
0.00
0
32
−1.36
9600
0
11
0.00
0
12
0.16
0
15
0.00
0
15
1.73
19200
0
5
0.00
0
6
−6.99
0
7
0.00
0
7
1.73
31250
⎯
⎯
⎯
0
3
0.00
0
4
−1.70
0
4
0.00
38400
0
2
0.00
0
2
8.51
0
3
0.00
0
3
1.73
0.16
Rev.5.00 Sep. 12, 2007 Page 447 of 764
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13. Serial Communication Interface
φ (MHz)
6
6.144
7.3728
8
Bit Rate
(bit/s)
n
N
110
2
106 −0.44
2
108 0.08
2
130 −0.07
2
141 0.03
150
2
77
0.16
2
79
0.00
2
95
0.00
2
103 0.16
300
1
155 0.16
1
159 0.00
1
191 0.00
1
207 0.16
600
1
77
0.16
1
79
0.00
1
95
0.00
1
103 0.16
1200
0
155 0.16
0
159 0.00
0
191 0.00
0
207 0.16
2400
0
77
0.16
0
79
0.00
0
95
0.00
0
103 0.16
4800
0
38
0.16
0
39
0.00
0
47
0.00
0
51
0.16
9600
0
19
−2.34
0
19
0.00
0
23
0.00
0
25
0.16
19200
0
9
−2.34
0
9
0.00
0
11
0.00
0
12
0.16
31250
0
5
0.00
0
5
2.40
0
6
5.33
0
7
0.00
38400
0
4
−2.34
0
4
0.00
0
5
0.00
0
6
−6.99
Error (%) n
N
Error (%) n
N
Error (%) n
N
Error (%)
φ (MHz)
Bit Rate
(bit/s)
9.8304
n
N
10
Error (%) n
N
12
Error (%) n
N
12.288
Error (%) n
N
Error (%)
110
2
174 −0.26
2
177 −0.25
2
212 0.03
2
217 0.08
150
2
127 0.00
2
129 0.16
2
155 0.16
2
159 0.00
300
1
255 0.00
2
64
0.16
2
77
0.16
2
79
600
1
127 0.00
1
129 0.16
1
155 0.16
1
159 0.00
1200
0
255 0.00
1
64
0.16
1
77
0.16
1
79
2400
0
127 0.00
0
129 0.16
0
155 0.16
0
159 0.00
4800
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
31
0.00
0
32
−1.36
0
38
0.16
0
39
0.00
19200
0
15
0.00
0
15
1.73
0
19
−2.34
0
19
0.00
31250
0
9
−1.70
0
9
0.00
0
11
0.00
0
11
2.40
38400
0
7
0.00
0
7
1.73
0
9
−2.34
0
9
0.00
Rev.5.00 Sep. 12, 2007 Page 448 of 764
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0.00
0.00
13. Serial Communication Interface
φ (MHz)
13
14
14.7456
Bit
Rate
(bit/s)
n N
110
2 230 −0.08 2 248 −0.17 3 64
150
2 168 0.16
Error n N
(%)
Error n N
(%)
2 181 0.16
−0.43 2 90
300
2 84
600
1 168 0.16
0.16
1200
1 84
2400
0 168 0.16
4800
0 84
−0.43 0 90
0.16
9600
0 41
0.76
19200
0 20
31250
38400
18
20
Error n N
(%)
Error n N
(%)
Error n N
(%)
Error
(%)
0.70
0.03
−0.12 3 88
−0.25
2 191 0.00
3 70
2 207 0.16
3 79
2 233 0.16
3 64
0.16
0.00
2 103 0.16
2 116 0.16
2 129 0.16
1 191 0.00
1 207 0.16
1 233 0.16
2 64
1 95
0.00
1 103 0.16
1 116 0.16
1 129 0.16
0 191 0.00
0 207 0.16
0 233 0.16
1 64
0 95
0.00
0 103 0.16
0 116 0.16
0 129 0.16
0 45
−0.93 0 47
0.00
0 51
0.16
0 58
−0.69 0 64
0.16
0.76
0 22
−0.93 0 23
0.00
0 25
0.16
0 28
1.02
0 32
−1.36
0 12
0.00
0 13
0.00
0 14
−1.70 0 15
0.00
0 17
0.00
0 19
0.00
0 10
−3.82 0 10
3.57
0 11
0.00
0.16
0 14
−2.34 0 15
1.73
1 181 0.16
−0.43 1 90
0.16
0 181 0.16
2 95
16
0 12
0.16
0.16
Rev.5.00 Sep. 12, 2007 Page 449 of 764
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13. Serial Communication Interface
Table 13.4 Examples of Bit Rates and BRR Settings in Synchronous Mode
φ (MHz)
Bit
2
Rate
(bit/s) n
N
n
N
n
N
n
N
n
N
n
N
n
N
n
N
110
3
70
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
250
2
124
2
249
3
124
⎯
⎯
3
202
3
249
⎯
⎯
⎯
⎯
500
1
249
2
124
2
249
⎯
⎯
3
101
3
124
3
140
3
155
1k
1
124
1
249
2
124
⎯
⎯
2
202
2
249
3
69
3
77
2.5k
0
199
1
99
1
199
1
249
2
80
2
99
2
112
2
124
5k
0
99
0
199
1
99
1
124
1
162
1
199
1
224
1
249
10k
0
49
0
99
0
199
0
249
1
80
1
99
1
112
1
124
25k
0
19
0
39
0
79
0
99
0
129
0
159
0
179
0
199
50k
0
9
0
19
0
39
0
49
0
64
0
79
0
89
0
99
100k 0
4
0
9
0
19
0
24
⎯
⎯
0
39
0
44
0
49
250k 0
1
0
3
0
7
0
9
0
12
0
15
0
17
0
19
500k 0
0*
0
1
0
3
0
4
⎯
⎯
0
7
0
8
0
9
0
0*
0
1
⎯
⎯
⎯
⎯
0
3
0
4
0
4
2M
0
0*
⎯
⎯
⎯
⎯
0
1
⎯
⎯
⎯
⎯
2.5M
⎯
⎯
0
0*
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
0*
⎯
⎯
⎯
⎯
1M
4
8
10
13
16
4M
Legend:
Blank: No setting available
⎯:
Setting possible, but error occurs
*:
Continuous transmission/reception not possible
Note: Settings with an error of 1% or less are recommended.
Rev.5.00 Sep. 12, 2007 Page 450 of 764
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18
20
13. Serial Communication Interface
The BRR setting is calculated as follows:
Asynchronous mode:
N=
φ
64 ×
22n-1 ×
B
× 106 – 1
Synchronous mode:
N=
φ
8 × 22n-1 × B
× 106 – 1
Legend:
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: System clock frequency (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3)
(For the clock sources and values of n, see the following table.)
SMR Settings
n
Clock Source
CKS1
CKS0
0
φ
0
0
1
φ/4
0
1
2
φ/16
1
0
3
φ/64
1
1
The bit rate error in asynchronous mode is calculated as follows:
Error (%) =
φ × 106
(N + 1) × B × 64 × 22n-1
–1
× 100
Rev.5.00 Sep. 12, 2007 Page 451 of 764
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13. Serial Communication Interface
Table 13.5 shows the maximum bit rates in asynchronous mode for various system clock
frequencies. Table 13.6 and 13.7 shows the maximum bit rates with external clock input.
Table 13.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode)
Settings
φ (MHz)
Maximum Bit Rate (bit/s)
n
N
2
62500
0
0
2.097152
65536
0
0
2.4576
76800
0
0
3
93750
0
0
3.6864
115200
0
0
4
125000
0
0
4.9152
153600
0
0
5
156250
0
0
6
187500
0
0
6.144
192000
0
0
7.3728
230400
0
0
8
250000
0
0
9.8304
307200
0
0
10
312500
0
0
12
375000
0
0
12.288
384000
0
0
14
437500
0
0
14.7456
460800
0
0
16
500000
0
0
17.2032
537600
0
0
18
562500
0
0
20
625000
0
0
Rev.5.00 Sep. 12, 2007 Page 452 of 764
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13. Serial Communication Interface
Table 13.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bit/s)
2
0.5000
31250
2.097152
0.5243
32768
2.4576
0.6144
38400
3
0.7500
46875
3.6864
0.9216
57600
4
1.0000
62500
4.9152
1.2288
76800
5
1.2500
78125
6
1.5000
93750
6.144
1.5360
96000
7.3728
1.8432
115200
8
2.0000
125000
9.8304
2.4576
153600
10
2.5000
156250
12
3.0000
187500
12.288
3.0720
192000
14
3.5000
218750
14.7456
3.6864
230400
16
4.0000
250000
17.2032
4.3008
268800
18
4.5000
281250
20
5.0000
312500
Rev.5.00 Sep. 12, 2007 Page 453 of 764
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13. Serial Communication Interface
Table 13.7 Maximum Bit Rates with External Clock Input (Synchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bit/s)
2
0.3333
333333.3
4
0.6667
666666.7
6
1.0000
1000000.0
8
1.3333
1333333.3
10
1.6667
1666666.7
12
2.0000
2000000.0
14
2.3333
2333333.3
16
2.6667
2666666.7
18
3.0000
3000000.0
20
3.3333
3333333.3
13.3
Operation
13.3.1
Overview
The SCI can carry out serial communication in two modes: asynchronous mode in which
synchronization is achieved character by character, and synchronous mode in which
synchronization is achieved with clock pulses. A smart card interface is also supported as a serial
communication function for an IC card interface.
Selection of asynchronous or synchronous mode and the transmission format for the normal serial
communication interface is made in SMR, as shown in table 13.8. The SCI clock source is
selected by the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13.9.
For details of the procedures for switching between LSB-first and MSB-first mode and inverting
the data logic level, see section 14.2.1, Smart Card Mode Register (SCMR).
For selection of the smart card interface format, see section 14.3.3, Data Format.
Asynchronous Mode
• Data length is selectable: 7 or 8 bits
• Parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). These
selections determine the communication format and character length.
• In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break
state.
Rev.5.00 Sep. 12, 2007 Page 454 of 764
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13. Serial Communication Interface
• An internal or external clock can be selected as the SCI clock source.
⎯ When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and can output a serial clock signal with a frequency matching the bit rate.
⎯ When an external clock is selected, the external clock input must have a frequency 16 times
the bit rate. (The on-chip baud rate generator is not used.)
Synchronous Mode
• The communication format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors.
• An internal or external clock can be selected as the SCI clock source.
⎯ When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and can output a serial clock signal to external devices.
⎯ When an external clock is selected, the SCI operates on the input serial clock. The on-chip
baud rate generator is not used.
Smart Card Interface
• One frame consists of 8-bit data and a parity bit.
• In transmitting, a guard time of at least two elementary time units (2 etu) is provided between
the end of the parity bit and the start of the next frame. (An elementary time unit is the time
required to transmit one bit.)
• In receiving, if a parity error is detected, a low error signal level is output for 1 etu, beginning
10.5 etu after the start bit..
• In transmitting, if an error signal is received, the same data is automatically transmitted again
after at least 2 etu.
• Only asynchronous communication is supported. There is no synchronous communication
function.
For details of smart card interface operation, see section 14, Smart Card Interface.
Rev.5.00 Sep. 12, 2007 Page 455 of 764
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13. Serial Communication Interface
Table 13.8 SMR Settings and Serial Communication Formats
SMR Settings
SCI Communication Format
Bit 7
C/A
Bit 6
CHR
Bit 2
MP
Bit 5
PE
Bit 3
STOP Mode
Data
Length
Multiprocessor Parity
Bit
Bit
Stop Bit
Length
0
0
0
0
0
8-bit data
Absent
1 bit
1
1
Asynchronous
mode
Absent
2 bits
0
Present
1
1
0
0
7-bit data
Absent
1
1
1
0
1
1
⎯
⎯
⎯
0
⎯
1
⎯
0
⎯
1
⎯
⎯
1 bit
2 bits
Present
1
0
1 bit
2 bits
1 bit
2 bits
Asyn8-bit data
chronous
mode (multi7-bit data
processor
Present
Absent
1 bit
2 bits
1 bit
2 bits
Synchronous
mode
8-bit data
Absent
None
Table 13.9 SMR and SCR Settings and SCI Clock Source Selection
SMR
SCR Setting
SCI Transmit/Receive clock
Bit 7
C/A
Bit 1 Bit 0
CKE1 CKE0 Mode
Clock Source SCK Pin Function
0
0
Internal
0
1
1
Asynchronous
mode
0
Outputs clock with frequency matching the
bit rate
External
Inputs clock with frequency 16 times the bit
rate
Internal
Outputs the serial clock
External
Inputs the serial clock
1
1
0
0
1
1
0
Synchronous
mode
SCI does not use the SCK pin
1
Rev.5.00 Sep. 12, 2007 Page 456 of 764
REJ09B0396-0500
13. Serial Communication Interface
13.3.2
Operation in Asynchronous Mode
In asynchronous mode, each transmitted or received character begins with a start bit and ends with
one or two stop bits. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full-duplex communication
is possible. The transmitter and the receiver are both double-buffered, so data can be written and
read while transmitting and receiving are in progress, enabling continuous transmitting and
receiving.
Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous
serial communication the communication line is normally held in the mark (high) state. The SCI
monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and one or two stop bits (high), in that order.
When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit.
The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate.
Receive data is latched at the center of each bit.
Idle (mark) state
(LSB)
1
Serial
data
0
Start
bit
1 bit
D0
1
(MSB)
D1
D2
D3
D4
D5
D6
D7
0/1
Parity
bit
Transmit or receive data
7 or 8 bits
One unit of data (character or frame)
1 bit,
or
none
1
1
Stop bit(s)
1 or 2 bits
Figure 13.2 Data Format in Asynchronous Communication
(Example: 8-Bit Data with Parity and 2 Stop Bits)
Communication Formats: Table 13.10 shows the 12 communication formats that can be selected
in asynchronous mode. The format is selected by settings in SMR.
Rev.5.00 Sep. 12, 2007 Page 457 of 764
REJ09B0396-0500
13. Serial Communication Interface
Table 13.10 Serial Communication Formats (Asynchronous Mode)
SMR Settings
Serial Communication Format and Frame Length
CHR
PE
MP
STOP
1
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P STOP
1
1
0
1
S
7-bit data
P STOP STOP
0
⎯
1
0
S
8-bit data
MPB STOP
0
⎯
1
1
S
8-bit data
MPB STOP STOP
1
⎯
1
0
S
7-bit data
MPB STOP
1
⎯
1
1
S
7-bit data
MPB STOP STOP
Legend:
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB: Multiprocessor bit
Rev.5.00 Sep. 12, 2007 Page 458 of 764
REJ09B0396-0500
2
3
4
5
6
7
8
9
10
11
12
STOP
13. Serial Communication Interface
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected
by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. For details of SCI clock source
selection, see table 13.9.
When an external clock is input at the SCK pin, it must have a frequency 16 times the desired bit
rate.
When the SCI is operated on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as shown in figure 13.3
so that the rising edge of the clock occurs at the center of each transmit data bit.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 13.3 Phase Relationship between Output Clock and Serial Data
(Asynchronous Mode)
Transmitting and Receiving Data:
• SCI Initialization (Asynchronous Mode): Before transmitting or receiving data, clear the TE
and RE bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0
before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and
initializes TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags, or RDR, which retain their previous contents.
When an external clock is used the clock should not be stopped during initialization or
subsequent operation, since operation will be unreliable in this case.
Figure 13.4 shows a sample flowchart for initializing the SCI.
Rev.5.00 Sep. 12, 2007 Page 459 of 764
REJ09B0396-0500
13. Serial Communication Interface
Start of initialization
Clear TE and RE bits
to 0 in SCR
Set CKE1 and CKE0 bits in SCR
(leaving TE and RE bits
cleared to 0)
(1)
Select communication format
in SMR
(2)
Set value in BRR
(3)
Wait
(1)
Set the clock source in SCR. Clear the
RIE, TIE, TEIE, MPIE, TE, and RE bits to
0. If clock output is selected in
asynchronous mode, clock output starts
immediately after the setting is made in
SCR.
(2)
Select the communication format in SMR.
(3)
Write the value corresponding to the bit
rate in BRR.
This step is not necessary when an
external clock is used.
(4)
Wait for at least the interval required to
transmit or receive one bit, then set the
TE or RE bit to 1 in SCR. Set the RIE,
TIE, TEIE, and MPIE bits. Setting the TE
or RE bit enables the SCI to use the TxD
or RxD pin.
No
1-bit interval elapsed?
Yes
Set TE or RE bit to 1 in SCR
Set RIE, TIE, TEIE, and MPIE bits
(4)
<End of initialization>
Note: In simultaneous transmitting and receiving, the TE and RE bits should be cleared to 0 or
set to 1 simultaneously.
Figure 13.4 Sample Flowchart for SCI Initialization
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13. Serial Communication Interface
• Transmitting Serial Data (Asynchronous Mode): Figure 13.5 shows a sample flowchart for
transmitting serial data and indicates the procedure to follow.
Initialize
(1)
(1) SCI initialization:
the transmit data output function of the TxD pin is
selected automatically.
After the TE bit is set to 1, one frame of 1s is output,
then transmission is possible.
(2)
(2) SCI status check and transmit data write:
read SSR and check that the TDRE flag is set to 1,
then write transmit data in TDR and clear the TDRE
flag to 0.
Start transmitting
Read TDRE flag in SSR
No
TDRE = 1
(3) To continue transmitting serial data:
after checking that the TDRE flag is 1, indicating that
data can be written, write data in TDR, then clear the
TDRE flag to 0. When the DMAC is activated by a
transmit-data-empty interrupt request (TXI) to write
data in TDR, the TDRE flag is checked and cleared
automatically.
Yes
Write transmit data in TDR
and clear TDRE flag to 0 in SSR
All data transmitted?
No
Yes
(3)
Read TEND flag in SSR
TEND = 1
(4) To output a break signal at the end of serial
transmission:
set the DDR bit to 1 and clear the DR bit to 0 (DDR
and DR are I/O port registers), then clear the TE bit
to 0 in SCR.
No
Yes
Output break signal?
No
(4)
Yes
Clear DR bit to 0 and set
DDR bit to 1
Clear TE bit to 0 in SCR
<End>
Figure 13.5 Sample Flowchart for Transmitting Serial Data
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13. Serial Communication Interface
In transmitting serial data, the SCI operates as follows:
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
⎯ Start bit: One 0 bit is output.
⎯ Transmit data: 7 or 8 bits are output, LSB first.
⎯ Parity bit or multiprocessor bit: One parity bit (even or odd parity),or one multiprocessor
bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can
also be selected.
⎯ Stop bit(s): One or two 1 bits (stop bits) are output.
⎯ Mark state: Output of 1 bits continues until the start bit of the next transmit data.
• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop bit,
then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmitend interrupt (TEI) is requested at this time
Figure 13.6 shows an example of SCI transmit operation in asynchronous mode.
1
0
Parity Stop Start
bit
bit
bit
Data
Start bit
D0
D1
D7
0/1
1
0
Parity Stop
bit
bit
Data
D0
D1
D7
0/1
TDRE
TEND
1 frame
TXI interrupt
request
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
TXI interrupt
request
TEI interrupt
request
Figure 13.6 Example of SCI Transmit Operation in Asynchronous Mode
(8-Bit Data with Parity and One Stop Bit)
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1
1
Idle state
(mark state)
13. Serial Communication Interface
• Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for
receiving serial data and indicates the procedure to follow.
(1)
Initialize
(1)
SCI initialization:
the receive data input function of the RxD
pin is selected automatically.
(2)(3)
Receive error handling and break detection:
if a receive error occurs, read the ORER,
PER, and FER flags in SSR to identify the
error. After executing the necessary error
handling, clear the ORER, PER, and FER
flags all to 0. Receiving cannot resume if
any of these flags remains set to 1. When a
framing error occurs, the RxD pin can be
read to detect the break state.
Start receiving
Read ORER, PER, and FER
flags in SSR
(2)
Yes
PER∨FER∨OPER = 1
(3)
Error handling
No
(continued on next page)
Read RDRF flag in SSR
No
(4)
(4)
SCI status check and receive data read:
read SSR, check that the RDRF flag is set
to 1, then read receive data from RDR and
clear the RDRF flag to 0. Notification that
the RDRF flag has changed from 0 to 1 can
also be given by the RXI interrupt.
(5)
To continue receiving serial data:
check the RDRF flag, read RDR, and clear
the RDRF flag to 0 before the stop bit of the
current frame is received. When the DMAC
is activated by a receive-data-full interrupt
request (RXI) to read RDR, the RDRF flag
is cleared automatically.
RDRF = 1
Yes
Read receive data from RDR, and
clear RDRF flag to 0 in SSR
No
All data received?
(5)
Yes
Clear RE bit to 0 in SCR
<End>
Figure 13.7 Sample Flowchart for Receiving Serial Data (1)
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13. Serial Communication Interface
(3)
Error handling
No
ORER = 1
Yes
Overrun error handling
No
FER = 1
Yes
Break?
Yes
No
Framing error handling
No
Clear RE bit to 0 in SCR
PER = 1
Yes
Parity error handling
Clear ORER, PER, and FER flags
to 0 in SSR
<End>
Figure 13.7 Sample Flowchart for Receiving Serial Data (2)
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13. Serial Communication Interface
In receiving, the SCI operates as follows:
• The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI
synchronizes internally and starts receiving.
• Receive data is stored in RSR in order from LSB to MSB.
• The parity bit and stop bit are received.
After receiving these bits, the SCI carries out the following checks:
⎯ Parity check: The number of 1s in the receive data must match the even or odd parity
setting of in the O/E bit in SMR.
⎯ Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first is
checked.
⎯ Status check: The RDRF flag must be 0, indicating that the receive data can be transferred
from RSR into RDR.
If these all checks pass, the RDRF flag is set to 1 and the received data is stored in RDR. If one
of the checks fails (receive error*), the SCI operates as shown in table 13.11.
Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag
is not set to 1. Be sure to clear the error flags to 0.
• When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
(RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also
set to 1, a receive-error interrupt (ERI) is requested.
Table 13.11 Receive Error Conditions
Receive Error Abbreviation Condition
Data Transfer
Overrun error ORER
Receiving of next data ends while Receive data is not transferred
RDRF flag is still set to 1 in SSR from RSR to RDR
Framing error FER
Stop bit is 0
Parity error
Parity of received data differs from Receive data is transferred from
even/odd parity setting in SMR
RSR to RDR
PER
Receive data is transferred from
RSR to RDR
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13. Serial Communication Interface
Figure 13.8 shows an example of SCI receive operation in asynchronous mode.
1
Start
bit
0
Parity Stop
bit
bit
Data
D0
D1
D7
0/1
Start
bit
1
0
Data
D0
D1
Stop Parity Stop
bit
bit
bit
D7
0/1
1
1
Idle (mark) state
RDRF
FER
RXI request
1 frame
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
Framing error,
ERI request
Figure 13.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
13.3.3
Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles.
The transmitting processor stars by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 13.9 shows an example of communication among different processors using a
multiprocessor format.
Communication Formats: Four formats are available. Parity bit settings are ignored when a
multiprocessor format is selected. For details see table 13.10.
Clock: See the description of asynchronous mode.
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13. Serial Communication Interface
Transmitting
processor
Serial communication line
Serial data
Receiving
processor A
Receiving
processor B
Receiving
processor C
Receiving
processor D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
H'01
H'AA
(MPB = 1)
ID-sending cycle:
receiving processor address
(MPB = 0)
Data-sending cycle:
data sent to receiving processor
specified by ID
Legend:
MPB : Multiprocessor bit
Figure 13.9 Example of Communication among Processors using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A)
Transmitting and Receiving Data:
• Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for
transmitting multiprocessor serial data and indicates the procedure to follow.
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13. Serial Communication Interface
(1)
Initialize
(1)
SCI initialization:
the transmit data output function of the TxD pin
is selected automatically.
(2)
SCI status check and transmit data write:
read SSR, check that the TDRE flag is 1, then
write transmit data in TDR. Also set the MPBT
flag to 0 or 1 in SSR. Finally, clear the TDRE
flag to 0.
(3)
To continue transmitting serial data:
after checking that the TDRE flag is 1,
indicating that data can be written, write data
in TDR, then clear the TDRE flag to 0. When
the DMAC is activated by a transmit-dataempty interrupt request (TXI) to write data in
TDR, the TDRE flag is checked and cleared
automatically.
(4)
To output a break signal at the end of serial
transmission:
set the DDR bit to 1 and clear the DR bit to 0
(DDR and DR are I/O port registers), then
clear the TE bit to 0 in SCR.
Start transmitting
Read TDRE flag in SSR
TDRE = 1
(2)
No
Yes
Write transmit data in TDR
and set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
No
(3)
Yes
Read TEND flag in SSR
TEND = 1
No
Yes
Output break signal?
No
(4)
Yes
Clear DR bit to 0 and set DDR to 1
Clear TE bit to 0 in SCR
<End>
Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data
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13. Serial Communication Interface
In transmitting serial data, the SCI operates as follows:
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
⎯ Start bit: One 0 bit is output.
⎯ Transmit data: 7 or 8 bits are output, LSB first.
⎯ Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
⎯ Stop bit(s): One or two 1 bits (stop bits) are output.
⎯ Mark state: Output of 1 bits continues until the start bit of the next transmit data.
• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop bit,
then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmitend interrupt (TEI) is requested at this time
Figure 13.11 shows an example of SCI transmit operation using a multiprocessor format.
1
Start
bit
0
Data
D0
D1
Multiprocessor Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Multiprocessor Stop
bit
bit
D7
0/1
1
Idle (mark)
state
TDRE
TEND
TXI interrupt TXI interrupt handler
writes data in TDR and
request
clears TDRE flag to 0
TXI interrupt
request
TEI interrupt
request
1 frame
Figure 13.11 Example of SCI Transmit Operation
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
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13. Serial Communication Interface
• Receiving Multiprocessor Serial Data: Figure 13.12 shows a sample flowchart for receiving
multiprocessor serial data and indicates the procedure to follow.
(1)
Initialize
(1)
SCI initialization:
the receive data input function of the
RxD pin is selected automatically.
(2)
ID receive cycle:
set the MPIE bit to 1 in SCR.
(3)
SCI status check and ID check:
read SSR, check that the RDRF flag
is set to 1, then read data from RDR
and compare it with the processor's
own ID. If the ID does not match, set
the MPIE bit to 1 again and clear the
RDRF flag to 0. If the ID matches,
clear the RDRF flag to 0.
(4)
SCI status check and data receiving:
read SSR, check that the RDRF flag
is set to 1, then read data from RDR.
(5)
Receive error handling and break
detection:
if a receive error occurs, read the
ORER and FER flags in SSR to
identify the error. After executing the
necessary error handling, clear the
ORER and FER flags both to 0.
Receiving cannot resume while either
the ORER or FER flag remains set to
1. When a framing error occurs, the
RxD pin can be read to detect the
break state.
Start receiving
(2)
Set MPIE bit to 1 in SCR
Read ORER and FER flags
in SSR
FER∨ORER = 1
Yes
No
Read RDRF flag in SSR
No
(3)
RDRF = 1
Yes
Read RDRF flag in SSR
No
Own ID?
Yes
Read ORER and FER flags
in SSR
FER∨ORER = 1
Yes
No
(4)
Read RDRF flag in SSR
RDRF = 1
No
Yes
Read receive data from RDR
No
Finished receiving?
Yes
(5)
Error handling
Clear RE bit to 0 in SCR
(continued on next page)
<End>
Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (1)
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13. Serial Communication Interface
(5)
Error handling
No
ORER = 1
Yes
Overrun error handling
No
FER = 1
Yes
Break?
Yes
No
Clear RE bit to 0 in SCR
Framing error handling
Clear ORER, PER, and FER
flags to 0 in SSR
<End>
Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2)
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13. Serial Communication Interface
Figure 13.13 shows an example of SCI receive operation using a multiprocessor format.
1
Start
bit
0
Stop
MPB bit
Data (ID1)
D0
D7
D1
1
Start
bit
0
1
Stop
MPB bit
Data (data1)
D0
D1
D7
1
0
1
Idle (mark)
state
MPIE
RDRF
RDR value
ID1
MPB detection
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
RXI interrupt handler reads
RDR data and clears
RDRF flag to 0
Not own ID, so MPIE
bit is set to 1 again
No RXI interrupt
request, RDR not
updated
a. Own ID does not match data
1
Start
bit
0
Data (ID2)
D0
D1
MPB
D7
1
Stop
bit
1
Start
bit
Data (data1)
0
D0
D1
Stop
bit
MPB
D7
0
1
1
Idle (mark)
state
MPIE
RDRF
RDR value
ID1
MPB detection
MPIE = 0
ID2
RXI interrupt
request
(multiprocessor
interrupt)
RXI interrupt handler
reads RDR data and
clears RDRF flag to 0
Own ID, so receiving MPIE bit is set to
continues, with data 1 again
received by RXI
interrupt handler
b. Own ID matches data
Figure 13.13 Example of SCI Receive Operation
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
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Data2
13. Serial Communication Interface
13.3.4
Synchronous Operation
In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses.
This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver share the same clock but are otherwise independent, so fullduplex communication is possible. The transmitter and the receiver are also double-buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Figure 13.14 shows the general format in synchronous serial communication.
One unit (character or frame) of transfer data
*
*
Serial clock
LSB
Bit 0
Serial data
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don't care
Don't care
Note: * High except in continuous transmitting or receiving
Figure 13.14 Data Format in Synchronous Communication
In synchronous serial communication, each data bit is placed on the communication line from one
falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock.
In each character, the serial data bits are transferred in order from LSB (first) to MSB (last). After
output of the MSB, the communication line remains in the state of the MSB. In synchronous mode
the SCI receives data by synchronizing with the rise of the serial clock.
Communication Format: The data length is fixed at 8 bits. No parity bit or multiprocessor bit
can be added.
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected by means of the C/A bit in SMR and the CKE1 and CKE0 bits
in SCR. See table 13.9 for details of SCI clock source selection.
When the SCI operates on an internal clock, it outputs the clock source at the SCK pin. Eight
clock pulses are output per transmitted or received character. When the SCI is not transmitting or
receiving, the clock signal remains in the high state. If receiving in single-character units is
required, an external clock should be selected.
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13. Serial Communication Interface
Transmitting and Receiving Data:
• SCI Initialization (Synchronous Mode): Before transmitting or receiving data, clear the TE and
RE bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0
before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and
initializes TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags, or RDR, which retain their previous contents.
Figure 13.15 shows a sample flowchart for initializing the SCI.
Start of initialization
Clear TE and RE bits to 0 in SCR
Set RIE, TIE, TEIE, MPIE, CKE1
and CKE0 bits in SCR (leaving
TE and RE bits cleared to 0)
(1)
Select communication format
in SMR
(2)
Set value in BRR
Wait
1-bit interval elapsed?
(1)
Set the clock source in SCR. Clear the RIE,
TIE, TEIE, MPIE, TE, and RE bits to 0.
(2)
Select the communication format in SMR.
(3)
Write the value corresponding to the bit rate in
BRR.
This step is not necessary when an external
clock is used.
(4)
Wait for at least the interval required to transmit
or receive one bit, then set the TE or RE bit to
1 in SCR. Set the RIE, TIE, TEIE, and MPIE
bits. Setting the TE or RE bit enables the SCI
to use the TxD or RxD pin.
(3)
Yes
Yes
Set TE or RE bit to 1 in SCR
Set RIE, TIE, TEIE, and MPIE
bits as necessary
(4)
<Start transmitting or receiving>
Note: In simultaneous transmitting and receiving, the TE and RE bits should be cleared to 0 or
set to 1 simultaneously.
Figure 13.15 Sample Flowchart for SCI Initialization
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13. Serial Communication Interface
• Transmitting Serial Data (Synchronous Mode): Figure 13.16 shows a sample flowchart for
transmitting serial data and indicates the procedure to follow.
(1)
Initialize
(1)
SCI initialization: the transmit data output
function of the TxD pin is selected
automatically.
(2)
SCI status check and transmit data write:
read SSR, check that the TDRE flag is 1,
then write transmit data in TDR and clear
the TDRE flag to 0.
(3)
To continue transmitting serial data: after
checking that the TDRE flag is 1, indicating
that data can be written, write data in TDR,
then clear the TDRE flag to 0. When the
DMAC is activated by a transmit-data-empty
interrupt request (TXI) to write data in TDR,
the TDRE flag is checked and cleared
automatically.
Start transmitting
Read TDRE flag in SSR
TDRE = 1
(2)
No
Yes
Write transmit data in TDR
and clear TDRE flag to 0 in SSR
All data transmitted?
No
(3)
Yes
Read TEND flag in SSR
TEND = 1
No
Yes
Clear TE bit to 0 in SCR
<End>
Figure 13.16 Sample Flowchart for Serial Transmitting
In transmitting serial data, the SCI operates as follows.
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
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13. Serial Communication Interface
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source
is selected, the SCI outputs data in synchronization with the input clock. Data is output from
the TxD pin n order from LSB (bit 0) to MSB (bit 7).
• The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the SCI
loads data from TDR into TSR and begins serial transmission of the next frame. If the TDRE
flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB, holds the
TxD pin in the MSB state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is
requested at this time
• After the end of serial transmission, the SCK pin is held in a constant state.
Figure 13.17 shows an example of SCI transmit operation.
Transmit direction
Serial clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt
request
TXI interrupt handler TXI interrupt
writes data in TDR
request
and clears TDRE
flag to 0
1 frame
Figure 13.17 Example of SCI Transmit Operation
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TEI interrupt
request
13. Serial Communication Interface
• Receiving Serial Data (Synchronous Mode): Figure 13.18 shows a sample flowchart for
receiving serial data and indicates the procedure to follow. When switching from asynchronous
to synchronous mode, make sure that the ORER, PER, and FER flags are cleared to 0. If the
FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving
will be disabled.
(1)
Initialize
(1)
Start receiving
Read ORER flag in SSR
(2)
Yes
ORER = 1
(3)
No
Error handling
(2)(3) Receive error handling: if a receive
error occurs, read the ORER flag in
SSR, then after executing the
necessary error handling, clear the
ORER flag to 0. Neither transmitting
nor receiving can resume while the
ORER flag remains set to 1.
(4)
SCI status check and receive data
read: read SSR, check that the RDRF
flag is set to 1, then read receive data
from RDR and clear the RDRF flag to
0. Notification that the RDRF flag
has changed from 0 to 1 can also be
given by the RXI interrupt.
(5)
To continue receiving serial data:
check the RDRF flag, read RDR, and
clear the RDRF flag to 0 before the
MSB (bit 7) of the current frame is
received. When the DMAC is
activated by a receive-data-full
interrupt request (RXI) to read RDR,
the RDRF flag is cleared
automatically.
(continued on next page)
Read RDRF flag in SSR
No
(4)
RDRF = 1
Yes
Read receive data from
RDR, and clear RDRF
flag to 0 in SSR
No
Finished receiving?
(5)
SCI initialization: the receive data
input function of the RxD pin is
selected automatically.
Yes
Clear RE bit to 0 in SCR
<End>
Figure 13.18 Sample Flowchart for Serial Receiving (1)
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13. Serial Communication Interface
(3)
Error handling
Overrun error handling
Clear ORER flag to 0 in SSR
<End>
Figure 13.18 Sample Flowchart for Serial Receiving (2)
In receiving, the SCI operates as follows:
• The SCI synchronizes with the serial clock input or output and performs receive operation.
• Receive data is stored in RSR in order from LSB to MSB.
After receiving the data, the SCI checks that the RDRF flag is 0, so that receive data can be
transferred from RSR to RDR. If this check passes, the RDRF flag is set to 1 and the received
data is stored in RDR. If the checks fails (receive error), the SCI operates as shown in table
13.11.
When a receive error has been identified in the error check, subsequent transmit and receive
operations are disabled.
• When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
(RXI) is requested. If the ORER flag is set to 1 and the RIE bit in SCR is also set to 1, a
receive-error interrupt (ERI) is requested.
Figure 13.19 shows an example of SCI receive operation.
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13. Serial Communication Interface
Serial clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI interrupt
request
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
RXI interrupt
request
Overrun error,
ERI interrupt
request
1 frame
Figure 13.19 Example of SCI Receive Operation
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13. Serial Communication Interface
• Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 13.20 shows a
sample flowchart for transmitting and receiving serial data simultaneously and indicates the
procedure to follow.
Initialize
(1)
(1)
SCI initialization: the transmit data output function of the
TxD pin and the read data input function of the RxD pin
are selected, enabling simultaneous transmitting and
receiving.
(2)
SCI status check and transmit data write: read SSR, check
that the TDRE flag is 1, then write transmit data in TDR
and clear the TDRE flag to 0.
Notification that the TDRE flag has changed from 0 to 1
can also be given by the TXI interrupt.
(3)
Receive error handling: if a receive error occurs, read the
ORER flag in SSR, then after executing the necessary
error handling, clear the ORER flag to 0.
Neither transmitting nor receiving can resume while the
ORER flag remains set to 1.
(4)
SCI status check and receive data read: read SSR, check
that the RDRF flag is 1, then read receive data from RDR
and clear the RDRF flag to 0. Notification that the RDRF
flag has changed from 0 to 1 can also be given by the RXI
interrupt.
(5)
To continue transmitting and receiving serial data: check
the RDRF flag, read RDR, and clear the RDRF flag to 0
before the MSB (bit 7) of the current frame is received.
Also check that the TDRE flag is set to 1, indicating that
data can be written, write data in TDR, then clear the
TDRE flag to 0 before the MSB (bit 7) of the current frame
is transmitted. When the DMAC is activated by a transmitdata-empty interrupt request (TXI) to write data in TDR,
the TDRE flag is checked and cleared automatically.
When the DMAC is activated by a receive-data-full
interrupt request (RXI) to read RDR, the RDRF flag is
cleared automatically.
Start of transmitting and receiving
Read TDRE flag in SSR
No
(2)
TDRE = 1
Yes
Write transmit data in TDR and
clear TDRE flag to 0 in SSR
Read ORER flag in SSR
ORER = 1
Yes
(3)
No
Error handling
Read RDRF flag in SSR
No
(4)
RDRF = 1
Yes
Read receive data from RDR, and
clear RDRF flag to 0 in SSR
No
End of transmitting
and receiving?
(5)
Yes
Clear TE and RE bits to 0 in SCR
<End>
Note: When switching from transmitting or receiving to simultaneous transmitting and receiving, clear both the TE bit
and the RE bit to 0, then set both bits to 1 simultaneously.
Figure 13.20 Sample Flowchart for Simultaneous Serial Transmitting and Receiving
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13. Serial Communication Interface
13.4
SCI Interrupts
The SCI has four interrupt request sources: transmit-end interrupt (TEI), receive-error (ERI),
receive-data-full (RXI), and transmit-data-empty interrupt (TXI). Table 13.12 lists the interrupt
sources and indicates their priority. These interrupts can be enabled or disabled by the TIE, RIE,
and TEIE bits in SCR. Each interrupt request is sent separately to the interrupt controller.
A TXI interrupt is requested when the TDRE flag is set to 1 in SSR. A TEI interrupt is requested
when the TEND flag is set to 1 in SSR. A TXI interrupt request can activate the DMAC to transfer
data. Data transfer by the DMAC automatically clears the TDRE flag to 0. A TEI interrupt request
cannot activate the DMAC.
An RXI interrupt is requested when the RDRF flag is set to 1 in SSR. An ERI interrupt is
requested when the ORER, PER, or FER flag is set to 1 in SSR. An RXI interrupt can activate the
DMAC to transfer data. Data transfer by the DMAC automatically clears the RDRF flag to 0. An
ERI interrupt request cannot activate the DMAC.
The DMAC can be activated by interrupts from SCI channel 0.
Table 13.12 SCI Interrupt Sources
Interrupt Source
Description
Priority
ERI
Receive error (ORER, FER, or PER)
High
RXI
Receive data register full (RDRF)
TXI
Transmit data register empty (TDRE)
TEI
Transmit end (TEND)
Low
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13. Serial Communication Interface
13.5
Usage Notes
13.5.1
Notes on Use of SCI
Note the following points when using the SCI.
TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of
transmit data from TDR to TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR
to TSR.
Data can be written into TDR regardless of the state of the TDRE flag. If new data is written in
TDR when the TDRE flag is 0, the old data stored in TDR will be lost because this data has not
yet been transferred to TSR. Before writing transmit data in TDR, be sure to check that the TDRE
flag is set to 1.
Simultaneous Multiple Receive Errors: Table 13.13 shows the state of the SSR status flags
when multiple receive errors occur simultaneously. When an overrun error occurs the RSR
contents are not transferred to RDR, so receive data is lost.
Table 13.13 SSR Status Flags and Transfer of Receive Data
SSR Status Flags
RDRF
ORER
FER
PER
Receive Data Transfer
RSR → RDR
Receive Errors
1
1
0
0
Not transferred
Overrun error
0
0
1
0
Transferred
Framing error
0
0
0
1
Transferred
Parity error
1
1
1
0
Not transferred
Overrun error +
framing error
1
1
0
1
Not transferred
Overrun error +
parity error
0
0
1
1
Transferred
Framing error +
parity error
1
1
1
1
Not transferred
Overrun error +
framing error +
parity error
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state the input from the RxD pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the
SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
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13. Serial Communication Interface
Sending a Break Signal: The input/output condition and level of the TxD pin are determined by
DR and DDR bits. This feature can be used to send a break signal.
After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE
bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR
bits should therefore be set to 1 beforehand.
To send a break signal during serial transmission, clear the DR bit to 0 , then clear the TE bit to 0.
When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the
TxD pin becomes an input/output outputting the value 0.
Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive
error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE
flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that
clearing the RE bit to 0 does not clear the receive error flags to 0.
Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous
mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI
synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive
data is latched at the rising edge of the eighth base clock pulse. See figure 13.21.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal base clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode
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13. Serial Communication Interface
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M=
(0.5 −
1
2N
) − (L − 0.5) F −
D − 0.5
N
(1 + F)
× 100%
. . . . . . . . (1)
M:
N:
D:
L:
F:
Receive margin (%)
Ratio of clock frequency to bit rate (N = 16)
Clock duty cycle (L = 0 to 1.0)
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
D = 0.5, F = 0
M = (0.5 −
1
2 × 16
) × 100%
= 46.875%
. . . . . . . . (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Use of DMAC:
• When an external clock source is used for the serial clock, after the DMAC updates TDR,
allow an inversion of at least five system clock (φ) cycles before input of the serial clock to
start transmitting. If the serial clock is input within four states of the TDR update, a
malfunction may occur. (See figure 13.22)
• To have the DMAC read RDR, be sure to select the corresponding SCI receive-data-full
interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR.
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13. Serial Communication Interface
SCK
t
TDRE
D0
D1
D2
D3
D4
D5
D6
D7
Note: In operation with an external clock source, be sure that t >4 states.
Figure 13.22 Example of Synchronous Transmission Using DMAC
Switching from SCK Pin Function to Port Pin Function:
• Problem in Operation: When switching the SCK pin function to the output port function (highlevel output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0,
CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.
1. End of serial data transmission
2. TE bit = 0
3. C/A bit = 0 ... switchover to port output
4. Occurrence of low-level output (see figure 13.23)
Half-cycle low-level output
SCK/port
1. End of transmission
Data
TE
C/A
Bit 6
4. Low-level output
Bit 7
2. TE = 0
3.C/A = 0
CKE1
CKE0
Figure 13.23 Operation when Switching from SCK Pin Function to Port Pin Function
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13. Serial Communication Interface
• Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily
places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an
external circuit.
With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following
settings in the order shown.
1. End of serial data transmission
2. TE bit = 0
3. CKE1 bit = 1
4. C/A bit = 0 ... switchover to port output
5. CKE1 bit = 0
High-level output
SCK/port
1. End of transmission
Data
TE
Bit 6
Bit 7
2.TE = 0
4.C/A = 0
C/A
3.CKE1 = 1
CKE1
5.CKE1 = 0
CKE0
Figure 13.24 Operation when Switching from SCK Pin Function to Port Pin Function
(Example of Preventing Low-Level Output)
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14. Smart Card Interface
Section 14 Smart Card Interface
14.1
Overview
An IC card (smart card) interface conforming to the ISO/IEC 7816-3 (Identification Card)
standard is supported as an extension of the serial communication interface (SCI) functions.
Switchover between the normal serial communication interface and the smart card interface is
controlled by a register setting.
14.1.1
Features
Features of the smart card interface supported by the H8/3067 Group are listed below.
• Asynchronous communication
⎯ Data length: 8 bits
⎯ Parity bit generation and checking
⎯ Transmission of error signal (parity error) in receive mode
⎯ Error signal detection and automatic data retransmission in transmit mode
⎯ Direct convention and inverse convention both supported
• Built-in baud rate generator allows any bit rate to be selected
• Three interrupt sources
⎯ There are three interrupt sources ⎯ transmit-data-empty, receive-data-full, and
transmit/receive error ⎯ that can issue requests independently.
⎯ The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA
controller (DMAC) to execute data transfer.
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14. Smart Card Interface
14.1.2
Block Diagram
Bus interface
Figure 14.1 shows a block diagram of the smart card interface.
Module data bus
RxD
RDR
TDR
RSR
TSR
TxD
SCMR
SSR
SCR
SMR
Transmission/
reception
control
Parity generation
BRR
φ
Baud rate
generator
φ/4
φ/16
φ/64
Clock
Parity check
External clock
SCK
TXI
RXI
ERI
Legend:
SCMR: Smart card mode register
RSR: Receive shift register
RDR: Receive data register
TSR:
Transmit shift register
TDR:
Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR:
Serial status register
BRR: Bit rate register
Figure 14.1 Block Diagram of Smart Card Interface
14.1.3
Pin Configuration
Table 14.1 shows the smart card interface pins.
Table 14.1 Smart Card Interface Pins
Pin Name
Abbreviation
I/O
Function
Serial clock pin
SCK
I/O
Clock input/output
Receive data pin
RxD
Input
Receive data input
Transmit data pin
TxD
Output
Transmit data output
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Internal
data bus
14. Smart Card Interface
14.1.4
Register Configuration
The smart card interface has the internal registers listed in table 14.2. The BRR, TDR, and RDR
registers have their normal serial communication interface functions, as described in section 13,
Serial Communication Interface.
Table 14.2 Smart Card Interface Registers
1
Channel
Address*
Name
Abbreviation
R/W
Initial Value
0
H'FFFB0
Serial mode register
SMR
R/W
H'00
H'FFFB1
Bit rate register
BRR
R/W
H'FF
H'FFFB2
Serial control register
SCR
R/W
H'00
H'FFFB3
Transmit data register
TDR
R/W
H'FF
H'FFFB4
Serial status register
SSR
R/(W)*
H'FFFB5
Receive data register
RDR
R
H'00
H'FFFB6
Smart card mode register
SCMR
R/W
H'F2
H'FFFB8
Serial mode register
SMR
R/W
H'00
H'FFFB9
Bit rate register
BRR
R/W
H'FF
H'FFFBA
Serial control register
SCR
R/W
H'00
1
2
2
H'84
H'FFFBB
Transmit data register
TDR
R/W
H'FFFBC
Serial status register
SSR
R/(W)*
H'FF
H'FFFBD
Receive data register
RDR
R
H'00
H'FFFBE
Smart card mode register
SCMR
R/W
H'F2
H'FFFC0
Serial mode register
SMR
R/W
H'00
H'FFFC1
Bit rate register
BRR
R/W
H'FF
H'FFFC2
Serial control register
SCR
R/W
H'00
H'FFFC3
Transmit data register
TDR
R/W
2
H'84
H'FF
2
H'FFFC4
Serial status register
SSR
R/(W)*
H'FFFC5
Receive data register
RDR
R
H'84
H'00
H'FFFC6
Smart card mode register
SCMR
R/W
H'F2
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Only 0 can be written in bits 7 to 3, to clear the flags.
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14. Smart Card Interface
14.2
Register Descriptions
This section describes the new or modified registers and bit functions in the smart card interface.
14.2.1
Smart Card Mode Register (SCMR)
SCMR is an 8-bit readable/writable register that selects smart card interface functions.
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
SDIR
SINV
⎯
SMIF
Initial value
1
1
1
1
0
0
1
0
Read/Write
⎯
⎯
⎯
⎯
R/W
R/W
⎯
R/W
Bit
Reserved bits
Reserved bit
Smart card interface
mode select
Enables or disables
the smart card interface
function
Smart card data invert
Inverts data logic levels
Smart card data transfer direction
Selects the serial/parallel conversion format
SCMR is initialized to H'F2 by a reset and in standby mode.
Bits 7 to 4⎯Reserved: Read-only bits, always read as 1.
Bit 3⎯Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
1
format.*
Bit 3
SDIR
Description
0
TDR contents are transmitted LSB-first
Receive data is stored LSB-first in RDR
1
TDR contents are transmitted MSB-first
Receive data is stored MSB-first in RDR
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(Initial value)
14. Smart Card Interface
Bit 2⎯Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This
function is used in combination with the SDIR bit to communicate with inverse-convention
2
cards.* The SINV bit does not affect the logic level of the parity bit. For parity settings, see
section 14.3.4, Register Settings.
Bit 2
SINV
Description
0
Unmodified TDR contents are transmitted
(Initial value)
Receive data is stored unmodified in RDR
1
Inverted TDR contents are transmitted
Receive data is inverted before storage in RDR
Bit 1⎯Reserved: Read-only bit, always read as 1.
Bit 0⎯Smart Card Interface Mode Select (SMIF): Enables the smart card interface function.
Bit 0
SMIF
Description
0
Smart card interface function is disabled
1
Smart card interface function is enabled
(Initial value)
Notes: 1. The function for switching between LSB-first and MSB-first mode can also be used
with the normal serial communication interface. Note that when the communication
format data length is set to 7 bits and MSB-first mode is selected for the serial data to
be transferred, bit 0 of TDR is not transmitted, and only bits 7 to 1 of the received data
are valid.
2. The data logic level inversion function can also be used with the normal serial
communication interface. Note that, when inverting the serial data to be transferred,
parity transmission and parity checking is based on the number of high-level periods at
the serial data I/O pin, and not on the register value.
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14. Smart Card Interface
14.2.2
Serial Status Register (SSR)
The function of SSR bit 4 is modified in smart card interface mode. This change also causes a
modification to the setting conditions for bit 2 (TEND).
Bit
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
ERS
PER
TEND
MPB
MPBT
Initial value
1
0
0
0
0
1
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Transmit end
Status flag indicating end
of transmission
Error signal status (ERS)
Status flag indicating that an error
signal has been received
Note: * Only 0 can be written, to clear the flag.
Bits 7 to 5: These bits operate as in normal serial communication. For details see section 13.2.7,
Serial Status Register (SSR).
Bit 4⎯Error Signal Status (ERS): In smart card interface mode, this flag indicates the status of
the error signal sent from the receiving device to the transmitting device. The smart card interface
does not detection framing errors.
Bit 4
ERS
Description
0
Indicates normal transmission, with no error signal returned
(Initial value)
[Clearing conditions]
1
•
The chip is reset, or enters standby mode or module stop mode
•
Software reads ERS while it is set to 1, then writes 0.
Indicates that the receiving device sent an error signal reporting a parity error
[Setting condition]
A low error signal was sampled.
Note: Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous
value.
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14. Smart Card Interface
Bits 3 to 0: These bits operate as in normal serial communication. For details see section 13.2.7,
Serial Status Register (SSR). The setting conditions for transmit end (TEND, bit 2), however, are
modified as follows.
Bit 2
TEND
Description
0
Transmission is in progress
[Clearing conditions]
1
•
Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
•
The DMAC writes data in TDR.
End of transmission
[Setting conditions]
(Initial value)
•
The chip is reset or enters standby mode.
•
The TE bit and FER/ERS bit are both cleared to 0 in SCR.
•
TDRE is 1 and ERS is 0 at a time 2.5 etu after the last bit of a 1-byte serial
character is transmitted (normal transmission).
Note: An etu (elementary time unit) is the time needed to transmit one bit.
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14. Smart Card Interface
14.2.3
Serial Mode Register (SMR)
The function of SMR bit 7 is modified in smart card interface mode. This change also causes a
modification to the function of bits 1 and 0 in the serial control register (SCR).
Bit
7
6
5
4
3
2
1
0
GM
CHR
PE
O/E
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7⎯GSM Mode (GM): With the normal smart card interface, this bit is cleared to 0. Setting
this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the
TEND flag that indicates completion of transmission, and the type of clock output used. The
details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in
the serial control register (SCR).
Bit 7
GM
Description
0
Normal smart card interface mode operation
1
•
The TEND flag is set 12.5 etu after the beginning of the start bit.
•
Clock output on/off control only.
(Initial value)
GSM mode smart card interface mode operation
•
The TEND flag is set 11.0 etu after the beginning of the start bit.
•
Clock output on/off and fixed-high/fixed-low control.
Bits 6 to 0: These bits operate as in normal serial communication. For details see section 13.2.5,
Serial Mode Register (SMR).
14.2.4
Serial Control Register (SCR)
The function of SCR bits 1 and 0 is modified in smart card interface mode.
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bits 7 to 2: These bits operate as in normal serial communication. For details see section 13.2.6,
Serial Control Register (SCR).
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14. Smart Card Interface
Bits 1 and 0⎯Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to
specify a fixed high level or fixed low level for the clock output, in addition to the usual switching
between enabling and disabling of the clock output.
Bit 7
GM
Bit 1
CKE1
Bit 0
CKE0
Description
0
0
0
Internal clock/SCK pin is I/O port
1
Internal clock/SCK pin is clock output
0
Internal clock/SCK pin is fixed at low output
1
Internal clock/SCK pin is clock output
0
Internal clock/SCK pin is fixed at high output
1
Internal clock/SCK pin is clock output
1
1
14.3
Operation
14.3.1
Overview
(Initial value)
The main features of the smart card interface are as follows.
• One frame consists of 8-bit data plus a parity bit.
• In transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of
one bit) is provided between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for a1 etu period
10.5 etu after the start bit.
• If an error signal is detected during transmission, the same data is transmitted automatically
after the elapse of 2 etu or longer.
• Only asynchronous communication is supported; there is no synchronous communication
function.
14.3.2
Pin Connections
Figure 14.2 shows a pin connection diagram for the smart card interface.
In communication with a smart card, since both transmission and reception are carried out on a
single data transmission line, the TxD pin and RxD pin should both be connected to this line. The
data transmission line should be pulled up to VCC with a resistor.
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14. Smart Card Interface
When the smart card uses the clock generated on the smart card interface, the SCK pin output is
input to the CLK pin of the smart card. If the smart card uses an internal clock, this connection is
unnecessary.
The reset signal should be output from one of this LSI's generic ports.
In addition to these pin connections, power and ground connections will normally also be
necessary.
VCC
TxD
RxD
I/O
Data line
SCK
Clock line
This chip
Px (port)
Reset line
CLK
RST
Smart card
Card-processing device
Figure 14.2 Smart Card Interface Connection Diagram
Note: If a smart card is not connected, and both TE and RE are set to 1, closed transmission/
reception is possible, enabling self-diagnosis to be carried out.
14.3.3
Data Format
Figure 14.3 shows the smart card interface data format. In reception in this mode, a parity check is
carried out on each frame, and if an error is detected an error signal is sent back to the transmitting
device to request retransmission of the data. In transmission, the error signal is sampled and the
same data is retransmitted if the error signal is low.
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14. Smart Card Interface
No parity error
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
D7
Dp
Output from transmitting device
Parity error
Ds
D0
D1
D2
D3
D4
D5
D6
DE
Output from transmitting device
Legend:
Ds:
D0 to D7:
Dp:
DE:
Output from
receiving
device
Start bit
Data bits
Parity bit
Error signal
Figure 14.3 Smart Card Interface Data Format
The operating sequence is as follows.
1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor.
2. The transmitting device starts transfer of one frame of data. The data frame starts with a start
bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
3. With the smart card interface, the data line then returns to the high-impedance state. The data
line is pulled high with a pull-up resistor.
4. The receiving device carries out a parity check. If there is no parity error and the data is
received normally, the receiving device waits for reception of the next data. If a parity error
occurs, however, the receiving device outputs an error signal (DE, low-level) to request
retransmission of the data. After outputting the error signal for the prescribed length of time,
the receiving device places the signal line in the high-impedance state again. The signal line is
pulled high again by a pull-up resistor.
5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data
frame. If it receives an error signal, however, it returns to step 2 and transmits the same data
again.
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14. Smart Card Interface
14.3.4
Register Settings
Table 14.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or
1 must be set to the value shown. The setting of other bits is described in this section.
Table 14.3 Smart Card Interface Register Settings
Bit
1
Register Address*
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMR
H'FFFB0
GM
0
1
O/E
1
0
CKS1
CKS0
BRR
H'FFFB1
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
SCR
H'FFFB2
TIE
RIE
TE
RE
0
0
CKE1*
TDR
H'FFFB3
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
SSR
H'FFFB4
TDRE
RDRF
ORER
ERS
PER
TEND
0
0
RDR
H'FFFB5
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
SCMR
H'FFFB6
⎯
⎯
⎯
⎯
SDIR
SINV
⎯
SMIF
2
CKE0
Notes: ⎯ Unused bit.
1. Lower 20 bits of the address in advanced mode.
2. When GM is cleared to 0 in SMR, the CKE1 bit must also be cleared to 0.
Serial Mode Register (SMR) Settings: Clear the GM bit to 0 when using the normal smart card
interface mode, or set to 1 when using GSM mode. Clear the O/E bit to 0 if the smart card is of the
direct convention type, or set to 1 if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the built-in baud rate generator. See section
14.3.5, Clock.
Bit Rate Register (BRR) Settings: BRR is used to set the bit rate. See section 14.3.5, Clock, for
the method of calculating the value to be set.
Serial Control Register (SCR) Settings: The TIE, RIE, TE, and RE bits have their normal serial
communication functions. See section 13, Serial Communication Interface, for details. The CKE1
and CKE0 bits specify clock output. To disable clock output, clear these bits to 00; to enable clock
output, set these bits to 01. Clock output is not performed when the GM bit is set to 1 in SMR.
Clock output can also be fixed low or high.
Smart Card Mode Register (SCMR) Settings: Clear both the SDIR bit and SINV bit cleared to
0 if the smart card is of the direct convention type, and set both to 1 if of the inverse convention
type. To use the smart card interface, set the SMIF bit to 1.
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14. Smart Card Interface
The register settings and examples of starting character waveforms are shown below for two smart
cards, one following the direct convention and one the inverse convention.
1. Direct Convention (SDIR = SINV = O/E = 0)
(Z)
A
Z
Z
A
Z
Z
Z
A
A
Z
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
(Z)
State
With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to
state A, and transfer is performed in LSB-first order. In the example above, the first character
data is H'3B. The parity bit is 1, following the even parity rule designated for smart cards.
2. Indirect Convention (SDIR = SINV = O/E = 1)
(Z)
A
Z
Z
A
A
A
A
A
A
Z
Ds
D7
D6
D5
D4
D3
D2
D1
D0
Dp
(Z)
State
With the indirect convention type, the logic 1 level corresponds to state A and the logic 0 level
to state Z, and transfer is performed in MSB-first order. In the example above, the first
character data is H'3F. The parity bit is 0, corresponding to state Z, following the even parity
rule designated for smart cards.
In the H8/3067 Group, inversion specified by the SINV bit applies only to the data bits, D7 to
D0. For parity bit inversion, the O/E bit in SMR must be set to odd parity mode. This applies
to both transmission and reception.
14.3.5
Clock
Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register
(BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for
calculating the bit rate is shown below. Table 14.5 shows some sample bit rates.
If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is
output from the SCK pin.
B=
φ
1488 ×
22n–1
× (N + 1)
× 106
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14. Smart Card Interface
where, N: BRR setting (0 ≤ N ≤ 255)
B: Bit rate (bit/s)
φ: Operating frequency (MHz)
n: See table 14.4
Table 14.4 n-Values of CKS1 and CKS0 Settings
n
CKS1
CKS0
0
0
0
1
1
2
1
0
3
1
Note: If the gear function is used to divide the clock frequency, use the divided frequency to
calculate the bit rate. The equation above applies directly to 1/1 frequency division.
Table 14.5 Bit Rates (bits/s) for Various BRR Settings (When n = 0)
φ (MHz)
N
7.1424
10.00
10.7136
13.00
14.2848
16.00
18.00
20.00
0
9600.0
13440.9
14400.0
17473.1
19200.0
21505.4
24193.5
26881.7
1
4800.0
6720.4
7200.0
8736.6
9600.0
10752.7
12096.8
13440.9
2
3200.0
4480.3
4800.0
5824.4
6400.0
7168.5
8064.5
8960.6
Note: Bit rates are rounded off to one decimal place.
The following equation calculates the bit rate register (BRR) setting from the operating frequency
and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error.
N=
φ
1488 × 22n–1 × B
× 106 – 1
Table 14.6 BRR Settings for Typical Bit Rates (bits/s) (When n = 0)
φ (MHz)
7.1424
10.00
10.7136
13.00
14.2848
16.00
18.00
20.00
bit/s
N Error
N Error
N Error
N Error
N Error
N Error
N Error
N Error
9600
0 0.00
1 30
1 25
1 8.99
1 0.00
1 12.01
2 15.99
2 6.66
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14. Smart Card Interface
Table 14.7 Maximum Bit Rates for Various Frequencies (Smart Card Interface Mode)
φ (MHz)
Maximum Bit Rate (bits/s)
N
n
7.1424
9600
0
0
10.00
13441
0
0
10.7136
14400
0
0
13.00
17473
0
0
14.2848
19200
0
0
16.00
21505
0
0
18.00
24194
0
0
20.00
26882
0
0
The bit rate error is given by the following equation:
Error (%) =
14.3.6
φ
1488 ×
22n-1
× B × (N + 1)
× 106 – 1
× 100
Transmitting and Receiving Data
Initialization: Before transmitting or receiving data, the smart card interface must be initialized as
described below. Initialization is also necessary when switching from transmit mode to receive
mode, or vice versa.
1. Clear the TE and RE bits to 0 in the serial control register (SCR).
2. Clear error flags ERS, PER, and ORER to 0 in the serial status register (SSR).
3. Set the parity bit (O/E) and baud rate generator select bits (CKS1 and CKS0) in the serial
mode register (SMR). Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to
1.
4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCMR).
When the SMIF bit is set to 1, the TxD pin and RxD pin are both switched from port to SCI pin
functions and go to the high-impedance state.
5. Set a value corresponding to the desired bit rate in the bit rate register (BRR).
6. Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE, and CKE1 bits to 0. If the
CKE0 bit is set to 1, the clock is output from the SCK pin.
7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE
bit and RE bit at the same time, except for self-diagnosis.
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14. Smart Card Interface
Transmitting Serial Data: As data transmission in smart card mode involves error signal
sampling and retransmission processing, the processing procedure is different from that for the
normal SCI. Figure 14.5 shows a sample transmission processing flowchart.
1. Perform smart card interface mode initialization as described in Initialization above.
2. Check that the ERS error flag is cleared to 0 in SSR.
3. Repeat steps 2 and 3 until it can be confirmed that the TEND flag is set to 1 in SSR.
4. Write the transmit data in TDR, clear the TDRE flag to 0, and perform the transmit operation.
The TEND flag is cleared to 0.
5. To continue transmitting data, go back to step 2.
6. To end transmission, clear the TE bit to 0.
The above processing may include interrupt handling DMA transfer.
If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt
requests are enabled, a transmit-data-empty interrupt (TXI) will be requested. If an error occurs in
transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are
enabled, a transmit/receive-error interrupt (ERI) will be requested.
The timing of TEND flag setting depends on the GM bit in SMR (see figure 14.4).
If the TXI interrupt activates the DMAC, the number of bytes designated in the DMAC can be
transmitted automatically, including automatic retransmission.
For details, see Interrupt Operations and Data Transfer by DMAC in this section.
Serial data
Dp
Ds
DE
Guard time
(1) GM = 0
TEND
12.5 etu
(2) GM = 1
TEND
11.0 etu
Figure 14.4 Timing of TEND Flag Setting
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14. Smart Card Interface
Start
Initialization
Start transmitting
No
FER/ERS = 0?
Yes
Error handling
No
TEND = 1?
Yes
Write transmit data in TDR,
and clear TDRE flag
to 0 in SSR
No
All data transmitted?
Yes
No
FER/ERS = 0?
Yes
Error handling
No
TEND = 1?
Yes
Clear TE bit to 0
End
Figure 14.5 Sample Transmission Processing Flowchart
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14. Smart Card Interface
TSR
(shift register)
TDR
1. Data write
Data 1
2. Transfer from TDR to TSR
Data 1
3. Serial data output
Data 1
Data 1
Data remains in TDR
Data 1
I/O signal
output
In case of normal transmission: TEND flag is set
In case of transmit error:
ERS flag is set
Steps 2 and 3 above are repeated until the
TEND flag is set.
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
transmission, D0 in MSB-first transmission) of the retransmit data to be transmitted next has
been completed.
Figure 14.6 Relation Between Transmit Operation and Internal Registers
I/O data
Ds
Da
Db
Dc
Dd
De
Df
Dg
Dh
Dp
DE
Guard time
TXI (TEND
interrupt)
12.5 etu
11.0 etu
When GM = 0
When GM = 1
Figure 14.7 Timing of TEND Flag Setting
Receiving Serial Data: Data reception in smart card mode uses the same processing procedure as
for the normal SCI. Figure 14.8 shows a sample reception processing flowchart.
1. Perform smart card interface mode initialization as described in Initialization above.
2. Check that the ORER flag and PER flag are cleared to 0 in SSR. If either is set, perform the
appropriate receive error handling, then clear both the ORER and the PER flag to 0.
3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1.
4. Read the receive data from RDR.
5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2.
6. To end reception, clear the RE bit to 0.
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14. Smart Card Interface
Start
Initialization
Start receiving
ORER = 0
and PER = 0?
No
Yes
Error handling
No
RDRF = 1?
Yes
Read RDR and clear
RDRF flag to 0 in SSR
No
All data received?
Yes
Clear RE bit to 0
Figure 14.8 Sample Reception Processing Flowchart
The above procedure may include interrupt handling and DMA transfer.
If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests
are enabled, a receive-data-full interrupt (RXI) will be requested. If an error occurs in reception
and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) will
be requested.
If the RXI interrupt activates the DMAC, the number of bytes designated in the DMAC will be
transferred, skipping receive data in which an error occurred.
For details, see Interrupt Operations and Data Transfer by DMAC in this section.
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14. Smart Card Interface
If a parity error occurs during reception and the PER flag is set to 1, the received data is
transferred to RDR, so the erroneous data can be read.
Switching Modes: When switching from receive mode to transmit mode, first confirm that the
receive operation has been completed, then start from initialization, clearing RE to 0 and setting
TE to 1. The RDRF, PER, or ORER flag can be used to check that the receive operation has been
completed.
When switching from transmit mode to receive mode, first confirm that the transmit operation has
been completed, then start from initialization, clearing TE to 0 and setting RE to 1. The TEND
flag can be used to check that the transmit operation has been completed.
Fixing Clock Output: When the GM bit is set to 1 in SMR, clock output can be fixed by means
of the CKE1 and CKE0 bits in SCR. The minimum clock pulse width can be set to the specified
width in this case.
Figure 14.9 shows the timing for fixing clock output. In this example, GM = 1, CKE1 = 0, and the
CKE0 bit is controlled.
Specified pulse
width
Specified pulse
width
CKE1 value
SCK
SCR write
(CKE0 = 0)
SCR write
(CKE0 = 1)
Figure 14.9 Timing for Fixing Cock Output
Interrupt Operations: The smart card interface has three interrupt sources: transmit-data-empty
(TXI), transmit/receive-error (ERI), and receive-data-full (RXI). The transmit-end interrupt
request (TEI) is not available in smart card mode.
A TXI interrupt is requested when the TEND flag is set to 1 in SSR. An RXI interrupt is requested
when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER, PER, or
ERS flag is set to 1 in SSR. These relationships are shown in table 14.8.
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14. Smart Card Interface
Table 14.8 Smart Card Interface Mode Operating States and Interrupt Sources
Flag
Enable Bit
Interrupt
Source
DMAC
Activation
Normal
operation
TEND
TIE
TXI
Available
Error
ERS
RIE
ERI
Not available
Normal
operation
RDRF
RIE
RXI
Available
Error
PER, ORER
RIE
ERI
Not available
Operating State
Transmit Mode
Receive Mode
Data Transfer by DMAC: The DMAC can be used to transmit and receive data in smart card
mode, as in normal SCI operations. In transmit mode, when the TEND flag is set to 1 in SSR, the
TDRE flag is set simultaneously, generating a TXI interrupt. If the TXI request is designated
beforehand as a DMAC activation source, the DMAC will be activated by the TXI request and
will transfer the next transmit data. This data transfer by the DMAC automatically clears the
TDRE and TEND flags to 0. In the event of an error, the SCI automatically retransmits the same
data, keeping the TEND flag cleared to 0 so that the DMAC is not activated. The SCI and DMAC
will therefore automatically transmit the designated number of bytes, including retransmission
when an error occurs. When an error occurs, the ERS flag is not cleared automatically, so the RIE
bit should be set to 1 to enable the error to generate an ERI request, and the ERI interrupt handler
should clear ERS.
When using the DMAC to transmit or receive, first set up and enable the DMAC, then make SCI
settings. DMAC settings are described in section 7, DMA controller.
In receive operations, an RXI interrupt is requested when the RDRF flag is set to 1 in SSR. If the
RXI request is designated beforehand as a DMAC activation source, the DMAC will be activated
by the RXI request and will transfer the received data. This data transfer by the DMAC
automatically clears the RDRF flag to 0. When an error occurs, the RDRF flag is not set and an
error flag is set instead. The DMAC is not activated. The ERI interrupt request is directed to the
CPU. The ERI interrupt handler should clear the error flags.
Examples of Operation in GSM Mode: When switching between smart card interface mode and
software standby mode, use the following procedures to maintain the clock duty cycle.
• Switching from smart card interface mode to software standby mode
1. Set the P94 data register (DR) and data direction register (DDR) to the values for the fixed
output state in software standby mode.
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14. Smart Card Interface
2. Write 0 in the TE and RE bits in the serial control register (SCR) to stop transmit/receive
operations. At the same time, set the CKE1 bit to the value for the fixed output state in
software standby mode.
3. Write 0 in the CKE0 bit in SCR to stop the clock.
4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock output
is fixed at the specified level.
5. Write H'00 in the serial mode register (SMR) and smart card mode register (SCMR).
6. Make the transition to the software standby state.
• Returning from software standby mode to smart card interface mode
1′. Clear the software standby state.
2′. Set the CKE1 bit in SCR to the value for the fixed output state at the start of software standby
(the current P94 pin state).
3′. Set smart card interface mode and output the clock. Clock signal generation is started with the
normal duty cycle.
Software
standby
Normal operation
1 2 3
4 5 6
Normal operation
1′ 2′ 3′
Figure 14.10 Procedure for Stopping and Restarting the Clock
Use the following procedure to secure the clock duty cycle after powering on.
1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the
potential.
2. Fix at the output specified by the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card interface mode operation.
4. Set the CKE0 bit to 1 in SCR to start clock output.
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14. Smart Card Interface
14.4
Usage Notes
The following points should be noted when using the SCI as a smart card interface.
Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart
card interface mode, the SCI operates on a base clock with a frequency of 372 times the transfer
rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on
the base clock. Receive data is latched at the rising edge of the 186th base clock pulse. The timing
is shown in figure 14.11.
372 clocks
186 clocks
185
0
185
371 0
371 0
Internal base
clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 14.11 Receive Data Sampling Timing in Smart Card Interface Mode
The receive margin can therefore be expressed as follows.
Receive margin in smart card interface mode:
M = (0.5 –
1
2N
) – (L – 0.5) F –
D – 0.5
(1 + F) × 100%
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 372)
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14. Smart Card Interface
D:
L:
F:
Clock duty cycle (D = 0 to 1.0)
Frame length (L =10)
Absolute deviation of clock frequency
From the above equation, if F = 0 and D = 0.5, the receive margin is as follows.
When D = 0.5 and F = 0:
M = (0.5 − 1/2 × 372) × 100%
= 49.866%
Retransmission: Retransmission is performed by the SCI in receive mode and transmit mode as
described below.
• Retransmission when SCI is in Receive Mode
Figure 14.12 illustrates retransmission when the SCI is in receive mode.
1. If an error is found when the received parity bit is checked, the PER bit is automatically set to
1. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The PER bit
should be cleared to 0 in SSR before the next parity bit sampling timing.
2. The RDRF bit in SSR is not set for the frame in which the error has occurred.
3. If no error is found when the received parity bit is checked, the PER bit is not set to 1 in SSR.
4. If no error is found when the received parity bit is checked, the receive operation is assumed to
have been completed normally, and the RDRF bit is automatically set to 1 in SSR. If the RIE
bit in SCR is set to the enable state, an RXI interrupt is requested. If RXI is enabled as a DMA
transfer activation source, the RDR contents can be read automatically. When the DMAC
reads the RDR data, the RDRF flag is automatically cleared to 0.
5. When a normal frame is received, the data pin is held in the high-impedance state at the error
signal transmission timing.
Frame n
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Frame n+1
Retransmitted frame
DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
RDRF
[2]
[4]
[1]
[3]
PER
Figure 14.12 Retransmission in SCI Receive Mode
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14. Smart Card Interface
• Retransmission when SCI is in Transmit Mode
Figure 14.13 illustrates retransmission when the SCI is in transmit mode.
6. If an error signal is sent back from the receiving device after transmission of one frame is
completed, the ERS bit is set to 1 in SSR. If the RIE bit in SCR is set to the enable state, an
ERI interrupt is requested. The ERS bit should be cleared to 0 in SSR before the next parity bit
sampling timing.
7. The TEND bit in SSR is not set for the frame for which the error signal was received.
8. If an error signal is not sent back from the receiving device, the ERS flag is not set in SSR.
9. If an error signal is not sent back from the receiving device, transmission of one frame,
including retransmission, is assumed to have been completed, and the TEND bit is set to 1 in
SSR. If the TIE bit in SCR is set to the enable state, a TXI interrupt is requested. If TXI is
enabled as a DMA transfer activation source, the next data can be written in TDR
automatically. When the DMAC writes data in TDR, the TDRE bit is automatically cleared to
0.
Frame n
Frame n+1
Retransmitted frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
TDRE
Transfer from TDR to TSR
Transfer from TDR to TSR
Transfer from TDR to TSR
TEND
[7]
[9]
ERS
[6]
[8]
Figure 14.13 Retransmission in SCI Transmit Mode
Note on Block Transfer Mode Support: The smart card interface installed in the H8/3006 and
H8/3007 support an IC card (smart card) interface with provision for ISO/IEC7816-3 T=0
(character transmission). Therefore, block transfer operations are not supported (error signal
transmission, detection, and automatic data retransmission are not performed).
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15. A/D Converter
Section 15 A/D Converter
15.1
Overview
The H8/3006 and H8/3007 include a 10-bit successive-approximations A/D converter with a
selection of up to eight analog input channels.
When the A/D converter is not used, it can be halted independently to conserve power. For details
see section 19.6, Module Standby Function.
The H8/3006 and H8/3007 support 70/134-state conversion as a high-speed conversion mode.
Note that it differs in this respect from the H8/3048 Group, which supports 134/266-state
conversion.
15.1.1
Features
A/D converter features are listed below.
• 10-bit resolution
• Eight input channels
• Selectable analog conversion voltage range
The analog voltage conversion range can be programmed by input of an analog reference
voltage at the VREF pin.
• High-speed conversion
Conversion time: maximum 3.5 μs per channel (with 20 MHz system clock)
• Two conversion modes
Single mode: A/D conversion of one channel
Scan mode: continuous conversion on one to four channels
• Four 16-bit data registers
A/D conversion results are transferred for storage into data registers corresponding to the
channels.
• Sample-and-hold function
• Three conversion start sources
The A/D converter can be activated by software, an external trigger, or an 8-bit timer compare
match.
• A/D interrupt requested at end of conversion
At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.
• DMA controller (DMAC) activation
The DMAC can be activated at the end of A/D conversion.
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15. A/D Converter
15.1.2
Block Diagram
Figure 15.1 shows a block diagram of the A/D converter.
On-chip
data bus
AVSS
AN 0
ADCR
ADCSR
ADDRD
–
AN 2
AN 4
ADDRC
+
AN 1
AN 3
ADDRB
10-bit D/A
ADDRA
VREF
Successiveapproximations register
AVCC
Bus interface
Module data bus
Analog
multiplexer
AN 5
φ/4
Comparator
Control circuit
Sample-andhold circuit
φ/8
AN 6
AN 7
ADI
interrupt signal
ADTRG
Compare match A0
ADTE
8-bit timer 8TCSR0
Legend:
ADCR:
ADCSR:
ADDRA:
ADDRB:
ADDRC:
ADDRD:
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
A/D data register D
Figure 15.1 A/D Converter Block Diagram
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15. A/D Converter
15.1.3
Pin Configuration
Table 15.1 summarizes the A/D converter's input pins. The eight analog input pins are divided into
two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power
supply for the analog circuits in the A/D converter. VREF is the A/D conversion reference voltage.
Table 15.1 A/D Converter Pins
Pin Name
Abbreviation
I/O
Function
Analog power supply pin
AVCC
Input
Analog power supply
Analog ground pin
AVSS
Input
Analog ground and reference voltage
Reference voltage pin
VREF
Input
Analog reference voltage
Analog input pin 0
AN0
Input
Group 0 analog inputs
Analog input pin 1
AN1
Input
Analog input pin 2
AN2
Input
Analog input pin 3
AN3
Input
Analog input pin 4
AN4
Input
Analog input pin 5
AN5
Input
Analog input pin 6
AN6
Input
Analog input pin 7
AN7
Input
A/D external trigger input pin ADTRG
Input
Group 1 analog inputs
External trigger input for starting A/D conversion
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15. A/D Converter
15.1.4
Register Configuration
Table 15.2 summarizes the A/D converter's registers.
Table 15.2 A/D Converter Registers
1
Address*
Name
Abbreviation
R/W
Initial Value
H'FFFE0
A/D data register AH
ADDRAH
R
H'00
H'FFFE1
A/D data register AL
ADDRAL
R
H'00
H'FFFE2
A/D data register BH
ADDRBH
R
H'00
H'FFFE3
A/D data register BL
ADDRBL
R
H'00
H'FFFE4
A/D data register CH
ADDRCH
R
H'00
H'FFFE5
A/D data register CL
ADDRCL
R
H'00
H'FFFE6
A/D data register DH
ADDRDH
R
H'00
H'FFFE7
A/D data register DL
ADDRDL
R
H'00
H'FFFE8
A/D control/status register
ADCSR
R/(W)*
H'FFFE9
A/D control register
ADCR
R/W
2
H'00
H'7E
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Only 0 can be written in bit 7, to clear the flag.
15.2
Register Descriptions
15.2.1
A/D Data Registers A to D (ADDRA to ADDRD)
Bit
ADDRn
14
12
10
8
6
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯
⎯
⎯
⎯
⎯
⎯
15
13
11
9
7
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
(n = A to D)
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
A/D conversion data
10-bit data giving an
A/D conversion result
Reserved bits
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
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15. A/D Converter
data register are reserved bits that are always read as 0. Table 15.3 indicates the pairings of analog
input channels and A/D data registers.
The CPU can always read the A/D data registers. The upper byte can be read directly, but the
lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 15.3 Analog Input Channels and A/D Data Registers
Analog Input Channel
Group 0
Group 1
A/D Data Register
AN0
AN4
ADDRA
AN1
AN5
ADDRB
AN2
AN6
ADDRC
AN3
AN7
ADDRD
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15. A/D Converter
15.2.2
A/D Control/Status Register (ADCSR)
Bit
7
6
5
4
3
2
1
0
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W) *
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Channel select 2 to 0
These bits select analog
input channels
Clock select
Selects the A/D conversion time
Scan mode
Selects single mode or scan mode
A/D start
Starts or stops A/D conversion
A/D interrupt enable
Enables and disables A/D end interrupts
A/D end flag
Indicates end of A/D conversion
Note: * Only 0 can be written, to clear the flag.
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'00 by a reset and in standby mode.
Bit 7⎯A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7
ADF
Description
0
[Clearing conditions]
1
•
Read ADF when ADF =1, then write 0 in ADF.
•
DMAC activated by ADI interrupt.
[Setting conditions]
•
Single mode: A/D conversion ends
•
Scan mode: A/D conversion ends in all selected channels
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(Initial value)
15. A/D Converter
Bit 6⎯A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the
end of A/D conversion.
Bit 6
ADIE
Description
0
A/D end interrupt request (ADI) is disabled
1
A/D end interrupt request (ADI) is enabled
(Initial value)
Bit 5⎯A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during
A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin, or by an 8-bit
timer compare match.
Bit 5
ADST
Description
0
A/D conversion is stopped
1
Single mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends.
(Initial value)
Scan mode: A/D conversion starts and continues, cycling among the selected
channels, until ADST is cleared to 0 by software, by a reset, or by a transition to
standby mode.
Bit 4⎯Scan Mode (SCAN): Selects single mode or scan mode. For further information on
operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching
the conversion mode.
Bit 4
SCAN
Description
0
Single mode
1
Scan mode
(Initial value)
Bit 3⎯Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before
switching the conversion time.
Bit 3
CKS
Description
0
Conversion time = 134 states (maximum)
1
Conversion time = 70 states (maximum)
(Initial value)
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15. A/D Converter
Bits 2 to 0⎯Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog
input channels. Clear the ADST bit to 0 before changing the channel selection.
Group
Selection
Channel Selection
Description
CH2
CH1
CH0
Single Mode
Scan Mode
0
0
0
AN0 (Initial value)
AN0
1
AN1
AN0, AN1
0
AN2
AN0 to AN2
1
AN3
AN0 to AN3
0
AN4
AN4
1
AN5
AN4, AN5
0
AN6
AN4 to AN6
1
AN7
AN4 to AN7
1
1
0
1
15.2.3
A/D Control Register (ADCR)
Bit
7
6
5
4
3
2
1
0
TRGE
⎯
⎯
⎯
⎯
⎯
—
⎯
Initial value
0
1
1
1
1
1
1
0
Read/Write
R/W
⎯
⎯
⎯
⎯
⎯
—
R/W
Reserved bits
Trigger enable
Enables or disables starting of A/D conversion
by an external trigger or 8-bit timer compare match
ADCR is an 8-bit readable/writable register that enables or disables starting of A/D conversion by
external trigger input or an 8-bit timer compare match signal. ADCR is initialized to H'7E by a
reset and in standby mode.
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15. A/D Converter
Bit 7⎯Trigger Enable (TRGE): Enables or disables starting of A/D conversion by an external
trigger or 8-bit timer compare match.
Bit 7
TRGE
Description
0
Starting of A/D conversion by an external trigger or 8-bit timer
compare match is disabled
1
A/D conversion is started at the falling edge of the external trigger
signal (ADTRG) or by an 8-bit timer compare match
(Initial value)
External trigger pin and 8-bit timer selection are performed by the 8-bit timer. For details, see
section 10, 8-Bit Timers.
Bits 6 to 1⎯Reserved: These bits cannot be modified and are always read as 1.
Bit 0⎯Reserved: This bit can be read or written, but should not be set to 1.
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15. A/D Converter
15.3
CPU Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read
through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 15.2 shows the data flow for access to an A/D data register.
Upper-byte read
CPU
(H'AA)
Module data bus
Bus interface
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
Lower-byte read
CPU
(H'40)
Module data bus
Bus interface
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
Note: n = A to D
Figure 15.2 A/D Data Register Access Operation (Reading H'AA40)
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15. A/D Converter
15.4
Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode.
15.4.1
Single Mode (SCAN = 0)
Single mode should be selected when only one A/D conversion on one channel is required. A/D
conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The
ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when
conversion ends.
When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is
requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF.
When the mode or analog input channel must be switched during analog conversion, to prevent
incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making
the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be
set at the same time as the mode or channel is changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next.
Figure 15.3 shows a timing diagram for this example.
1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0,
CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started
(ADST = 1).
2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time
the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The routine reads ADCSR, then writes 0 in the ADF flag.
6. The routine reads and processes the conversion result (ADDRB).
7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1,
A/D conversion starts again and steps 2 to 7 are repeated.
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Note: * Vertical arrows ( ) indicate instructions executed by software.
ADDRD
ADDRC
ADDRB
Read conversion result
A/D conversion result (2)
Idle
Clear *
A/D conversion result (1)
A/D conversion (2)
Set *
Read conversion result
Idle
State of channel 3
(AN 3)
ADDRA
Idle
State of channel 2
(AN 2)
Idle
Clear *
State of channel 1
(AN 1)
A/D conversion (1)
Set *
Idle
Idle
A/D conversion
starts
State of channel 0
(AN 0)
ADF
ADST
ADIE
Set *
15. A/D Converter
Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
15. A/D Converter
15.4.2
Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first
channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are
selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5)
starts immediately. A/D conversion continues cyclically on the selected channels until the ADST
bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers
corresponding to the channels.
When the mode or analog input channel selection must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the
first channel in the group. The ADST bit can be set at the same time as the mode or channel
selection is changed.
Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are
described next. Figure 15.4 shows a timing diagram for this example.
1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels
AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1
and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI
interrupt is requested at this time.
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
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Figure 15.4 Example of A/D Converter Operation (Scan Mode,
Channels 3 AN0 to AN2 Selected)
Idle
Idle
Idle
A/D conversion (1)
Transfer
A/D conversion result (1)
Idle
Idle
Clear*1
Idle
A/D conversion result (3)
A/D conversion result (2)
A/D conversion result (4)
Idle
A/D conversion (5)*2
A/D conversion time
A/D conversion (4)
Idle
A/D conversion (3)
Idle
A/D conversion (2)
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.
2. Data currently being converted is ignored.
ADDRD
ADDRC
ADDRB
ADDRA
State of channel 3
(AN 3)
State of channel 2
(AN 2)
State of channel 1
(AN 1)
State of channel 0
(AN 0)
ADF
ADST
Set *1
Continuous A/D conversion
Clear*1
15. A/D Converter
15. A/D Converter
15.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D
conversion timing. Table 15.4 indicates the A/D conversion time.
As indicated in figure 15.5, the A/D conversion time includes tD and the input sampling time. The
length of tD varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 15.4.
In scan mode, the values given in table 15.4 apply to the first conversion. In the second and
subsequent conversions the conversion time is fixed at 128 states when CKS = 0 or 66 states when
CKS = 1.
(1)
φ
Address bus
(2)
Write signal
Input sampling
timing
ADF
tD
t SPL
t CONV
Legend:
(1):
ADCSR write cycle
(2):
ADCSR address
tD :
Synchronization delay
t SPL : Input sampling time
t CONV : A/D conversion time
Figure 15.5 A/D Conversion Timing
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15. A/D Converter
Table 15.4 A/D Conversion Time (Single Mode)
CKS = 0
CKS = 1
Symbol
Min
Typ
Max
Min
Typ
Max
Synchronization delay
tD
6
⎯
9
4
⎯
5
Input sampling time
tSPL
⎯
31
⎯
⎯
15
⎯
A/D conversion time
tCONV
131
⎯
134
69
⎯
70
Note: Values in the table are numbers of states.
15.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR and the 8-bit
timer's ADTE bit is cleared to 0, external trigger input is enabled at the ADTRG pin. A falling
edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other
operations, in both single and scan modes, are the same as if the ADST bit had been set to 1 by
software. Figure 15.6 shows the timing.
φ
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 15.6 External Trigger Input Timing
15.5
Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt
request can be enabled or disabled by the ADIE bit in ADCSR. The ADI interrupt request can be
designated as a DMAC activation source. In this case, an interrupt request is not sent to the CPU.
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15. A/D Converter
15.6
Usage Notes
When using the A/D converter, note the following points:
1. Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input
pins should be in the range AVSS ≤ ANn ≤ VREF.
2. Relationships of AVCC and AVSS to VCC and VSS: AVCC, AVSS, VCC, and VSS should be related as
follows: AVSS = VSS. AVCC and AVSS must not be left open, even if the A/D converter is not
used.
3. VREF Programming Range: The reference voltage input at the VREF pin should be in the range
VREF ≤ AVCC.
4. Note on Board Design: In board layout, separate the digital circuits from the analog circuits as
much as possible. Particularly avoid layouts in which the signal lines of digital circuits cross or
closely approach the signal lines of analog circuits. Induction and other effects may cause the
analog circuits to operate incorrectly, or may adversely affect the accuracy of A/D conversion.
The analog input signals (AN0 to AN7), analog reference voltage (VREF), and analog supply
voltage (AVCC) must be separated from digital circuits by the analog ground (AVSS). The
analog ground (AVSS) should be connected to a stable digital ground (VSS) at one point on the
board.
5. Note on Noise: To prevent damage from surges and other abnormal voltages at the analog
input pins (AN0 to AN7) and analog reference voltage pin (VREF), connect a protection circuit
like the one in figure 15.7 between AVCC and AVSS. The bypass capacitors connected to AVCC
and VREF and the filter capacitors connected to AN0 to AN7 must be connected to AVSS. If filter
capacitors like the ones in figure 15.7 are connected, the voltage values input to the analog
input pins (AN0 to AN7) will be smoothed, which may give rise to error. Error can also occur if
A/D conversion is frequently performed in scan mode so that the current that charges and
discharges the capacitor in the sample-and-hold circuit of the A/D converter becomes greater
than that input to the analog input pins via input impedance Rin. The circuit constants should
therefore be selected carefully.
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15. A/D Converter
AV CC
VREF
Rin*2
*1
100 Ω
AN0 to AN7
*1
0.1 μF
AV SS
Notes: 1.
10 μF
0.01 μF
2. Rin: input impedance
Figure 15.7 Example of Analog Input Protection Circuit
Table 15.5 Analog Input Pin Ratings
Item
min
max
Unit
Analog input capacitance
⎯
20
pF
Allowable signal-source impedance
⎯
10*
kΩ
Note:
*
When conversion time 134 states, VCC = 4.0 V to 5.5 V and φ ≤ 13 MHz. For details see
section 20, Electrical Characteristics.
10 kΩ
AN0 to AN7
To A/D converter
20 pF
Figure 15.8 Analog Input Pin Equivalent Circuit
Note: Numeric values are approximate, except in table 15.5
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15. A/D Converter
6. A/D Conversion Accuracy Definitions: A/D conversion accuracy in the H8/3006 and H8/3007
are defined as follows:
⎯ Resolution
Digital output code length of A/D converter
⎯ Offset error
Deviation from ideal A/D conversion characteristic of analog input voltage required to
raise digital output from minimum voltage value 0000000000 to 0000000001 (figure
15.10)
⎯ Full-scale error
Deviation from ideal A/D conversion characteristic of analog input voltage required to
raise digital output from 1111111110 to 1111111111 (figure 15.10)
⎯ Quantization error
Intrinsic error of the A/D converter; 1/2 LSB (figure 15.9)
⎯ Nonlinearity error
Deviation from ideal A/D conversion characteristic in range from zero volts to full scale,
exclusive of offset error, full-scale error, and quantization error.
⎯ Absolute accuracy
Deviation of digital value from analog input value, including offset error, full-scale error,
quantization error, and nonlinearity error.
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15. A/D Converter
Digital
output
111
Ideal A/D conversion
characteristic
110
101
100
011
010
Quantization error
001
000
1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS
Analog input
voltage
Figure 15.9 A/D Converter Accuracy Definitions (1)
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15. A/D Converter
Full-scale
error
Digital
output
Ideal A/D
conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
FS
Offset error
Analog input
voltage
Figure 15.10 A/D Converter Accuracy Definitions (2)
7. Allowable Signal-Source Impedance: The analog inputs of the H8/3006 and H8/3007 are
designed to assure accurate conversion of input signals with a signal-source impedance not
exceeding 10 kΩ. The reason for this rating is that it enables the input capacitor in the sampleand-hold circuit in the A/D converter to charge within the sampling time. If the sensor output
impedance exceeds 10 kΩ, charging may be inadequate and the accuracy of A/D conversion
cannot be guaranteed.
If a large external capacitor is provided in single mode, then the internal 10-kΩ input
resistance becomes the only significant load on the input. In this case the impedance of the
signal source is not a problem.
A large external capacitor, however, acts as a low-pass filter. This may make it impossible to
track analog signals with high dv/dt (e.g. a variation of 5 mV/μs) (figure 15.11). To convert
high-speed analog signals or to use scan mode, insert a low-impedance buffer.
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15. A/D Converter
8. Effect on Absolute Accuracy: Attaching an external capacitor creates a coupling with ground,
so if there is noise on the ground line, it may degrade absolute accuracy. The capacitor must be
connected to an electrically stable ground, such as AVSS.
If a filter circuit is used, be careful of interference with digital signals on the same board, and
make sure the circuit does not act as an antenna.
H8/3006 and
H8/3007
Sensor output impedance
Sensor
input
Equivalent circuit of
A/D converter
10 kΩ
Up to 10 kΩ
Cin =
15 pF
Low-pass
filter
C Up to 0.1μF
Figure 15.11 Analog Input Circuit (Example)
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20 pF
16. D/A Converter
Section 16 D/A Converter
16.1
Overview
The H8/3006 and H8/3007 include a D/A converter with two channels.
16.1.1
Features
D/A converter features are listed below.
• Eight-bit resolution
• Two output channels
• Conversion time: maximum 10 μs (with 20-pF capacitive load)
• Output voltage: 0 V to VREF
• D/A outputs can be sustained in software standby mode
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16. D/A Converter
16.1.2
Block Diagram
Bus interface
Figure 16.1 shows a block diagram of the D/A converter.
Module data bus
On-chip
data bus
DACR
8-bit D/A
DADR1
DA 0
DADR0
AVCC
DASTCR
VREF
DA 1
AVSS
Control circuit
Legend:
D/A control register
DACR:
DADR0: D/A data register 0
DADR1: D/A data register 1
DASTCR: D/A standby control register
Figure 16.1 D/A Converter Block Diagram
16.1.3
Pin Configuration
Table 16.1 summarizes the D/A converter's input and output pins.
Table 16.1 D/A Converter Pins
Pin Name
Abbreviation I/O
Function
Analog power supply pin
AVCC
Input
Analog power supply and reference voltage
Analog ground pin
AVSS
Input
Analog ground and reference voltage
Analog output pin 0
DA0
Output
Analog output, channel 0
Analog output pin 1
DA1
Output
Analog output, channel 1
Reference voltage input pin
VREF
Input
Analog reference voltage
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16. D/A Converter
16.1.4
Register Configuration
Table 16.2 summarizes the D/A converter's registers.
Table 16.2 D/A Converter Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFF9C
D/A data register 0
DADR0
R/W
H'00
H'FFF9D
D/A data register 1
DADR1
R/W
H'00
H'FFF9E
D/A control register
DACR
R/W
H'1F
H'EE01A
D/A standby control register
DASTCR
R/W
H'FE
Note:
Lower 20 bits of the address in advanced mode.
*
16.2
Register Descriptions
16.2.1
D/A Data Registers 0 and 1 (DADR0/1)
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the
data to be converted. When analog output is enabled, the D/A data register values are constantly
converted and output at the analog output pins.
The D/A data registers are initialized to H'00 by a reset and in standby mode.
When the DASTE bit is set to 1 in the D/A standby control register (DASTCR), the D/A registers
are not initialized in software standby mode.
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16. D/A Converter
16.2.2
D/A Control Register (DACR)
Bit
7
6
5
4
3
2
1
0
DAOE1
DAOE0
DAE
⎯
⎯
⎯
⎯
⎯
Initial value
0
0
0
1
1
1
1
1
Read/Write
R/W
R/W
R/W
⎯
⎯
⎯
⎯
⎯
D/A enable
Controls D/A conversion
D/A output enable 0
Controls D/A conversion and analog output
D/A output enable 1
Controls D/A conversion and analog output
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter.
DACR is initialized to H'1F by a reset and in standby mode.
When the DASTE bit is set to 1 in DASTCR, the DACR is not initialized in software standby
mode.
Bit 7⎯D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output.
Bit 7
DAOE1
Description
0
DA1 analog output is disabled
1
Channel-1 D/A conversion and DA1 analog output are enabled
Bit 6⎯D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output.
Bit 6
DAOE0
Description
0
DA0 analog output is disabled
1
Channel-0 D/A conversion and DA0 analog output are enabled
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16. D/A Converter
Bit 5⎯D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1.
When the DAE bit is cleared to 0, analog conversion is controlled independently in channels 0
and 1. When the DAE bit is set to 1, analog conversion is controlled together in channels 0 and 1.
Output of the conversion results is always controlled independently by DAOE0 and DAOE1.
Bit 7
Bit 6
Bit 5
DAOE1 DAOE0 DAE
0
Description
0
⎯
D/A conversion is disabled in channels 0 and 1
1
0
D/A conversion is enabled in channel 0
D/A conversion is disabled in channel 1
1
0
1
D/A conversion is enabled in channels 0 and 1
0
D/A conversion is disabled in channel 0
D/A conversion is enabled in channel 1
1
1
D/A conversion is enabled in channels 0 and 1
⎯
D/A conversion is enabled in channels 0 and 1
When the DAE bit is set to 1, even if bits DAOE0 and DAOE1 in DACR and the ADST bit in
ADCSR are cleared to 0, the same current is drawn from the analog power supply as during A/D
and D/A conversion.
Bits 4 to 0⎯Reserved: These bits cannot be modified and are always read as 1.
16.2.3
D/A Standby Control Register (DASTCR)
DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software
standby mode.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DASTE
Initial value
1
1
1
1
1
1
1
0
Read/Write
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R/W
Reserved bits
D/A standby enable
Enables or disables D/A output
in software standby mode
DASTCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 1⎯Reserved: These bits cannot be modified and are always read as 1.
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16. D/A Converter
Bit 0⎯D/A Standby Enable (DASTE): Enables or disables D/A output in software standby
mode.
Bit 0
DASTE
Description
0
D/A output is disabled in software standby mode
1
D/A output is enabled in software standby mode
16.3
(Initial value)
Operation
The D/A converter has two built-in D/A conversion circuits that can perform conversion
independently.
D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value
is modified, conversion of the new data begins immediately. The conversion results are output
when bits DAOE0 and DAOE1 are set to 1.
An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 16.2.
1. Data to be converted is written in DADR0.
2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an output pin. The
converted result is output after the conversion time.
DADR contents
The output value is
× VREF
256
Output of this conversion result continues until the value in DADR0 is modified or the
DAOE0 bit is cleared to 0.
3. If the DADR0 value is modified, conversion starts immediately, and the result is output after
the conversion time.
4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.
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16. D/A Converter
DADR0
write cycle
DACR
write cycle
DADR0
write cycle
DACR
write cycle
φ
Address
Conversion data 1
DADR0
Conversion data 2
DAOE0
DA 0
Conversion
result 2
Conversion
result 1
High-impedance state
t DCONV
t DCONV
Legend:
t DCONV : D/A conversion time
Figure 16.2 Example of D/A Converter Operation
16.4
D/A Output Control
In the H8/3006 and H8/3007, D/A converter output can be enabled or disabled in software standby
mode.
When the DASTE bit is set to 1 in DASTCR, D/A converter output is enabled in software standby
mode. The D/A converter registers retain the values they held prior to the transition to software
standby mode.
When D/A output is enabled in software standby mode, the reference supply current is the same as
during normal operation.
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16. D/A Converter
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17. RAM
Section 17 RAM
17.1
Overview
The H8/3007 has 4 kbytes of high-speed static RAM on-chip. The H8/3006 has 2 kbytes. The
RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word
data in two states, making the RAM useful for rapid data transfer.
The on-chip RAM of the H8/3007 is assigned to addresses H'FEF20 to H'FFF1F in modes 1 and 2,
and to addresses H'FFEF20 to H'FFFF1F in modes 3 and 4. The on-chip RAM of the H8/3006 are
assigned to addresses H'FF720 to H'FFF1F in modes 1 and 2, and to addresses H'FFF720 to
H'FFFF1F in modes 3 and 4. The RAM enable bit (RAME) in the system control register
(SYSCR) can enable or disable the on-chip RAM.
17.1.1
Block Diagram
Figure 17.1 shows a block diagram of the on-chip RAM.
On-chip data bus (upper 8 bits)
On-chip data bus (lower 8 bits)
SYSCR
Bus interface
H'FEF20*
H'FEF21*
H'FEF22*
H'FEF23*
On-chip RAM
H'FFF1E*
Even addresses
Legend:
SYSCR: System control register
H'FFF1F*
Odd addresses
Note: * This example is of the H8/3007 operating in mode 1 and 2. The lower 20 bits of the address
are shown.
Figure 17.1 RAM Block Diagram
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17. RAM
17.1.2
Register Configuration
The on-chip RAM is controlled by SYSCR. Table 17.1 gives the address and initial value of
SYSCR.
Table 17.1 System Control Register
Address*
H'EE012
Note:
17.2
Name
Abbreviation
R/W
Initial Value
System control register
SYSCR
R/W
H'09
Lower 20 bits of the address in advanced mode.
*
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
SSOE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAM enable bit
Enables or
disables
on-chip RAM
Software standby
output port enable
NMI edge select
User bit enable
Standby timer select 2 to 0
Software standby
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is
enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,
System Control Register (SYSCR).
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17. RAM
Bit 0⎯RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the RES pin. It is not initialized in software standby
mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
17.3
(Initial value)
Operation
When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FEF20 to
H'FFF1F in the H8/3007 in modes 1 and 2, and to addresses H'FFEF20 to H'FFFF1F in the
H8/3007 in modes 3 and 4, are directed to the on-chip RAM. In the H8/3006, accesses to
addresses H'FF720 to H'FFF1F in modes 1 and 2, to addresses H'FFF720 to H'FFFF1F in modes 3
and 4, are directed to the on-chip RAM. In modes 1 to 4, when the RAME bit is cleared to 0, the
off-chip address space is accessed.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written
and read by word access. It can also be written and read by byte access. Byte data is accessed in
two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed
in two states using all 16 bits of the data bus.
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18. Clock Pulse Generator
Section 18 Clock Pulse Generator
18.1
Overview
The H8/3006 and H8/3007 have a built-in clock pulse generator (CPG) that generates the system
clock (φ) and other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency
divider divides the clock frequency to generate the system clock (φ). The system clock is output at
1
the φ pin* and furnished as a master clock to prescalers that supply clock signals to the on-chip
supporting modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the
2
frequency divider by settings in a division control register (DIVCR)* . Power consumption in the
chip is reduced in almost direct proportion to the frequency division ratio.
Notes: 1. Usage of the φ pin differs depending on the chip operating mode and the PSTOP bit
setting in the module standby control register (MSTCR). For details, see section 19.7,
System Clock Output Disabling Function.
2. The division ratio of the frequency divider can be changed dynamically during
operation. The clock output at the φ pin also changes when the division ratio is
changed. The frequency output at the φ pin is shown below.
φ = EXTAL × n
where, EXTAL:Frequency of crystal resonator or external clock signal
n:
18.1.1
Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)
Block Diagram
Figure 18.1 shows a block diagram of the clock pulse generator.
CPG
XTAL
Oscillator
EXTAL
Duty
adjustment
circuit
Frequency
divider
Prescalers
Division
control
register
Data bus
φ
φ/2 to φ/4096
Figure 18.1 Block Diagram of Clock Pulse Generator
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18. Clock Pulse Generator
18.2
Oscillator Circuit
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock
signal.
18.2.1
Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as in the example in figure 18.2.
The damping resistance Rd should be selected according to table 18.1. An AT-cut parallelresonance crystal should be used.
C L1
EXTAL
XTAL
Rd
C L1 = C L2 = 10 pF to 22 pF
C L2
Figure 18.2 Connection of Crystal Resonator (Example)
Table 18.1 Damping Resistance Value
Damping
Resistance
Value
2
2<f≤4
4<f≤8
8 < f ≤ 10
10 < f ≤ 13
13 < f ≤ 16
16 < f ≤ 18
18 < f ≤ 20
Rd (Ω)
500
200
0
0
0
0
0
1k
Frequency f (MHz)
Note: A crystal resonator between 2 MHz and 20 MHz can be used. If the chip is to be operated
at less than 2 MHz, the on-chip frequency divider should be used. (A crystal resonator of
less than 2 MHz cannot be used.)
Crystal Resonator: Figure 18.3 shows an equivalent circuit of the crystal resonator. The crystal
resonator should have the characteristics listed in table 18.2.
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18. Clock Pulse Generator
CL
L
Rs
XTAL
EXTAL
AT-cut parallel-resonance type
C0
Figure 18.3 Crystal Resonator Equivalent Circuit
Table 18.2 Crystal Resonator Parameters
Frequency (MHz)
2
4
8
10
12
16
18
20
Rs max (Ω)
500
120
80
70
60
50
40
40
Co (pF)
7 pF max
Use a crystal resonator with a frequency equal to the system clock frequency (φ).
Notes on Board Design: When a crystal resonator is connected, the following points should be
noted:
Other signal lines should be routed away from the oscillator circuit to prevent induction from
interfering with correct oscillation. See figure 18.4.
When the board is designed, the crystal resonator and its load capacitors should be placed as close
as possible to the XTAL and EXTAL pins.
Avoid
C L2
Signal A
Signal B
H8/3006 and H8/3007
XTAL
EXTAL
C L1
Figure 18.4 Example of Incorrect Board Design
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18. Clock Pulse Generator
18.2.2
External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in figure
18.5. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. If the stray
capacitance at the XTAL pin exceeds 10 pF, use configuration b instead and hold the clock high in
standby mode.
External clock input
EXTAL
Open
XTAL
a. XTAL pin left open
EXTAL
External clock input
XTAL
b. Complementary clock input at XTAL pin
Figure 18.5 External Clock Input (Examples)
External Clock: The external clock frequency should be equal to the system clock frequency
when not divided by the on-chip frequency divider. Table 18.3 shows the clock timing, figure 18.6
shows the external clock input timing, and figure 18.7 shows the external clock output settling
delay timing. When the appropriate external clock is input via the EXTAL pin, its waveform is
corrected by the on-chip oscillator and duty adjustment circuit.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (tDEXT) has passed after the clock input. The system
must remain reset with the reset signal low during tDEXT, while the clock output is unstable.
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18. Clock Pulse Generator
Table 18.3 Clock Timing
VCC = 2.7 V
to 5.5 V
Item
Symbol Min
VCC = 3.0 V
to 5.5 V
VCC = 5.0 V
±10%
Max
Min
Max
Min
Max
Unit Test Conditions
External clock input tEXL
low pulse width
40
⎯
30
⎯
15
⎯
ns
External clock input tEXH
high pulse width
40
⎯
30
⎯
15
⎯
ns
External clock rise
time
tEXr
⎯
10
⎯
8
⎯
5
ns
External clock fall
time
tEXf
⎯
10
⎯
8
⎯
5
ns
Clock low pulse
width
tCL
0.4
0.6
0.4
0.6
0.4
0.6
tcyc
80
⎯
80
⎯
80
⎯
ns
φ ≥ 5 MHz Figure
20.3
φ < 5 MHz
Clock high pulse
width
tCH
0.4
0.6
0.4
0.6
0.4
0.6
tcyc
φ ≥ 5 MHz
80
⎯
80
⎯
80
⎯
ns
φ < 5 MHz
External clock
output settling
delay time
tDEXT*
500
⎯
500
⎯
500
⎯
µs
Figure 18.7
Note:
*
Figure 18.6
tDEXT includes a 10 tcyc of RES pulse width (tRESW).
tEXH
tEXL
VCC × 0.7
EXTAL
VCC × 0.5
0.3 V
tEXr
tEXf
Figure 18.6 External Clock Input Timing
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18. Clock Pulse Generator
VCC
STBY
VIH
EXTAL
φ (internal or
external)
RES
tDEXT*
Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW).
Figure 18.7 External Clock Output Settling Delay Timing
18.3
Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate φ.
18.4
Prescalers
The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).
18.5
Frequency Divider
The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
φ pin.
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18. Clock Pulse Generator
18.5.1
Register Configuration
Table 18.4 summarizes the frequency division register.
Table 18.4 Frequency Division Register
Address*
Name
Abbreviation
R/W
Initial Value
H'EE01B
Division control register
DIVCR
R/W
H'FC
Note:
18.5.2
Lower 20 bits of the address in advanced mode.
*
Division Control Register (DIVCR)
DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency
divider.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
DIV1
DIV0
Initial value
1
1
1
1
1
1
0
0
Read/Write
⎯
⎯
⎯
⎯
⎯
⎯
R/W
R/W
Reserved bits
Divide bits 1 and 0
These bits select the
frequency division ratio
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 2⎯Reserved: These bits cannot be modified and are always read as 1.
Bits 1 and 0⎯Divide (DIV1, DIV0): These bits select the frequency division ratio, as follows.
Bit 1
DIV1
Bit 0
DIV0
Frequency Division Ratio
0
0
1/1
1
1/2
0
1/4
1
1/8
1
(Initial value)
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18. Clock Pulse Generator
18.5.3
Usage Notes
The DIVCR setting changes the φ frequency, so note the following points.
• Select a frequency division ratio that stays within the assured operation range specified for the
clock cycle time tcyc in the AC electrical characteristics. Set φmin to the lower limit of the
operating frequency range, and ensure that φ does not fall below this lower limit.
• All on-chip module operations are based on φ. Note that the timing of timer operations, serial
communication, and other time-dependent processing differs before and after any change in
the division ratio. The waiting time for exit from software standby mode also changes when
the division ratio is changed. For details, see section 19.4.3, Selection of Waiting Time for Exit
from Software Standby Mode.
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19. Power-Down State
Section 19 Power-Down State
19.1
Overview
The H8/3006 and H8/3007 have a power-down state that greatly reduces power consumption by
halting the CPU, and a module standby function that reduces power consumption by selectively
halting on-chip modules.
The power-down state includes the following three modes:
• Sleep mode
• Software standby mode
• Hardware standby mode
The module standby function can halt on-chip supporting modules independently of the powerdown state. The modules that can be halted are the 16-bit timer, 8-bit timer, SCI0, SCI1, SCI2,
DMAC, DRAM interface, and A/D converter.
Table 19.1 indicates the methods of entering and exiting the power-down modes and module
standby mode, and gives the status of the CPU and on-chip supporting modules in each mode.
Rev.5.00 Sep. 12, 2007 Page 555 of 764
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Entering
Active
Active
SCI2
Active
A/D
Held
Held
Active
φ output
I/O
Ports
φ clock
Modules RAM output *4
Other
• Interrupt
Conditions
Exiting
while SSBY = 1
mode
Rev.5.00 Sep. 12, 2007 Page 556 of 764
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reset
MSTCRH and
reset
and
Halted
and
reset
Halted
and
reset
reset
and
Halted
reset
and
Halted
reset
and
Halted
reset
and
Halted
reset
and
Halted
reset
and
Halted
reset
and
Halted
reset
and
Halted
and
reset
and
held*1
reset
and
reset
and
reset
and
reset
and
reset
and
reset
and
Halted
reset
and
Halted
⎯
Held*3
Held
impedance*2
High
impedance
High
output
High
• STBY
• STBY
• RES
• IRQ0 to IRQ2
• NMI
⎯
bit to 0*5
• Clear MSTCR
• RES
• STBY
impedance • RES
High
Held
Software standby bit
MSTCRL: Module standby control register L
MSTCRH: Module standby control register H
System control register
SSBY:
then set up the module registers again.
SYSCR:
Legend:
5. When a MSTCR bit is set to 1, the registers of the corresponding on-chip supporting module are initialized. To restart the module, first clear the MSTCR bit to 0,
4. When P67 is used as the φ output pin.
3. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode.
Module Standby Control Register L (MSTCRL).
2. State in which the corresponding MSTCR bit was set to 1. For details see section 19.2.2, Module Standby Control Register H (MSTCRH) and section 19.2.3,
Notes: 1. RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their previous states.
MSTCRL
and
reset
held*1
Halted
and
and
reset
Halted
Halted
and
Halted
Halted*2 Halted*2 Halted*2 Halted*2 Halted*2 Halted*2 Halted*2 Halted*2 Active
bit set to 1 in
reset
and
Corresponding Active Active ⎯
mined
Halted Halted Undeter- Halted
standby
STBY pin
Module
mode
standby
Hardware Low input at
in SYSCR
and
tion executed
standby
reset
Halted
Software SLEEP instruc- Halted Halted Held
in SYSCR
• STBY
Active
SCI1
• RES
Active
Active
Active
SCI0
while SSBY = 0
Active
Timer
tion executed
8-Bit
16-Bit
Interface Timer
DRAM
SLEEP instruc- Active Halted Held
Registers DMAC
CPU
mode
Clock CPU
Sleep
Function Conditions
Mode/
State
19. Power-Down State
Table 19.1 Power-Down State and Module Standby Function
19. Power-Down State
19.2
Register Configuration
The H8/3006 and H8/3007 have a system control register (SYSCR) that controls the power-down
state, and module standby control registers H (MSTCRH) and L (MSTCRL) that control the
module standby function. Table 19.2 summarizes these registers.
Table 19.2 Control Register
Address*
Name
Abbreviation
R/W
Initial Value
H'EE012
System control register
SYSCR
R/W
H'09
H'EE01C
Module standby control register H
MSTCRH
R/W
H'78
Module standby control register L
MSTCRL
R/W
H'00
H'EE01D
Note:
19.2.1
Lower 20 bits of the address in advanced mode.
*
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
SSOE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAM enable
Software standby
output port enable
NMI edge select
User bit enable
Standby timer select 2 to 0
These bits select the
waiting time of the CPU
and peripheral functions
Software standby
Enables transition to
software standby mode
SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY), bits 6 to 4 (STS2 to STS0), and bit 1
(SSOE) control the power-down state. For information on the other SYSCR bits, see section 3.3,
System Control Register (SYSCR).
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19. Power-Down State
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal
operation. To clear this bit, write 0.
Bit 7
SSBY
Description
0
SLEEP instruction causes transition to sleep mode
1
SLEEP instruction causes transition to software standby mode
(Initial value)
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the clock to settle when software standby mode is exited
by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to
the clock frequency so that the waiting time will be at least 7 ms (oscillation settling time). See
table 19.3. If an external clock is used, any setting is permitted.
Bit 6
STS2
Bit 5
STS1
Bit 4
STS0
Description
0
0
0
Waiting time = 8,192 states
1
Waiting time = 16,384 states
1
0
Waiting time = 32,768 states
1
Waiting time = 65,536 states
0
0
Waiting time = 131,072 states
1
Waiting time = 262,144 states
0
Waiting time = 1,024 states
1
Illegal setting
1
1
(Initial value)
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (CS0 to CS7, AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as
outputs or fixed high, or placed in the high-impedance state in software standby mode.
Bit 1
SSOE
Description
0
In software standby mode, the address bus and bus control signals are (Initial value)
all high-impedance
1
In software standby mode, the address bus retains its output state and
bus control signals are fixed high
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19. Power-Down State
19.2.2
Module Standby Control Register H (MSTCRH)
MSTCRH is an 8-bit readable/writable register that controls output of the system clock (φ). It also
controls the module standby function, which places individual on-chip supporting modules in the
standby state. Module standby can be designated for the SCI0, SCI1, SCI2.
Bit
7
6
5
4
3
PSTOP
⎯
⎯
⎯
⎯
2
1
0
MSTPH2 MSTPH1 MSTPH0
Initial value
0
1
1
1
1
0
0
0
Read/Write
R/W
⎯
⎯
⎯
⎯
R/W
R/W
R/W
Reserved bit
Module standby H2 to 0
These bits select modules
to be placed in standby
φ clock stop
Enables or disables
output of the system clock
MSTCRH is initialized to H'78 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Stop (PSTOP): Enables or disables output of the system clock (φ).
Bit 1
PSTOP
Description
0
System clock output is enabled
1
System clock output is disabled
(Initial value)
Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—Module Standby H2 (MSTPH2): Selects whether to place the SCI2 in standby.
Bit 2
MSTPH2
Description
0
SCI2 operates normally
1
SCI2 is in standby state
(Initial value)
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19. Power-Down State
Bit 1—Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby.
Bit 1
MSTPH1
Description
0
SCI1 operates normally
1
SCI1 is in standby state
(Initial value)
Bit 0—Module Standby H0 (MSTPH0): Selects whether to place the SCI0 in standby.
Bit 0
MSTPH0
Description
0
SCI0 operates normally
1
SCI0 is in standby state
19.2.3
(Initial value)
Module Standby Control Register L (MSTCRL)
MSTCRL is an 8-bit readable/writable register that controls the module standby function, which
places individual on-chip supporting modules in the standby state. Module standby can be
designated for the DMAC, 16-bit timer, DRAM interface, 8-bit timer, and A/D converter modules.
Bit
7
6
5
4
3
2
1
0
MSTPL7
⎯
⎯
MSTPL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPL5 MSTPL4 MSTPL3 MSTPL2
Module standby L7, L5 to L2, L0
These bits select modules to be
placed in standby
Reserved bits
MSTCRL is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
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19. Power-Down State
Bit 7—Module Standby L7 (MSTPL7): Selects whether to place the DMAC in standby.
Bit 7
MSTPL7
Description
0
DMAC operates normally
1
DMAC is in standby state
(Initial value)
Bit 6—Reserved: This bit can be written and read.
Bit 5—Module Standby L5 (MSTPL5): Selects whether to place the DRAM interface in
standby.
Bit 5
MSTPL5
Description
0
DRAM interface operates normally
1
DRAM interface is in standby state
(Initial value)
Bit 4—Module Standby L4 (MSTPL4): Selects whether to place the 16-bit timer in standby.
Bit 4
MSTPL4
Description
0
16-bit timer operates normally
1
16-bit timer is in standby state
(Initial value)
Bit 3—Module Standby L3 (MSTPL3): Selects whether to place 8-bit timer channels 0 and 1 in
standby.
Bit 3
MSTPL3
Description
0
8-bit timer channels 0 and 1 operate normally
1
8-bit timer channels 0 and 1 are in standby state
(Initial value)
Bit 2—Module Standby L2 (MSTPL2): Selects whether to place 8-bit timer channels 2 and 3 in
standby.
Bit 2
MSTPL2
Description
0
8-bit timer channels 2 and 3 operate normally
1
8-bit timer channels 2 and 3 are in standby state
(Initial value)
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19. Power-Down State
Bit 1—Reserved: This bit can be written and read.
Bit 0—Module Standby L0 (MSTPL0): Selects whether to place the A/D converter in standby.
Bit 0
MSTPL0
Description
0
A/D converter operates normally
1
A/D converter is in standby state
19.3
Sleep Mode
19.3.1
Transition to Sleep Mode
(Initial value)
When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a
transition from the program execution state to sleep mode. Immediately after executing the SLEEP
instruction the CPU halts, but the contents of its internal registers are retained. The DMA
controller (DMAC), DRAM interface, and on-chip supporting modules do not halt in sleep mode.
Modules which have been placed in standby by the module standby function, however, remain
halted.
19.3.2
Exit from Sleep Mode
Sleep mode is exited by an interrupt, or by input at the RES or STBY pin.
Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt
exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting
module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by
an interrupt other than NMI if the interrupt is masked by interrupt priority settings and the settings
of the I and UI bits in CCR, IPR.
Exit by RES Input: Low input at the RES pin exits from sleep mode to the reset state.
Exit by STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby
mode.
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19. Power-Down State
19.4
Software Standby Mode
19.4.1
Transition to Software Standby Mode
To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in
SYSCR.
In software standby mode, current dissipation is reduced to an extremely low level because the
CPU, clock, and on-chip supporting modules all halt. The DMAC and on-chip supporting modules
are reset and halted. As long as the specified voltage is supplied, however, CPU register contents
and on-chip RAM data are retained. The settings of the I/O ports and DRAM interface* are also
held.
When the WDT is used as a watchdog timer (WT/IT = 1), the TME bit must be cleared to 0 before
setting SSBY. Also, when setting TME to 1, SSBY should be cleared to 0.
Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software
standby mode.
Note: * RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their
previous states.
19.4.2
Exit from Software Standby Mode
Software standby mode can be exited by input of an external interrupt at the NMI, IRQ0, IRQ1, or
IRQ2 pin, or by input at the RES or STBY pin.
Exit by Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2 interrupt request signal is received, the
clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0
in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and
interrupt exception handling begins. Software standby mode is not exited if the interrupt enable
bits of interrupts IRQ0, IRQ1, and IRQ2 are cleared to 0, or if these interrupts are masked in the
CPU.
Exit by RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are
supplied immediately to the entire chip. The RES signal must be held low long enough for the
clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling.
Exit by STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.
Rev.5.00 Sep. 12, 2007 Page 563 of 764
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19. Power-Down State
19.4.3
Selection of Waiting Time for Exit from Software Standby Mode
Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows.
Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to
stabilize) is at least 7 ms. Table 19.3 indicates the waiting times that are selected by STS2 to
STS0, DIV1, and DIV0 settings at various system clock frequencies.
External Clock: Any values may be set.
Table 19.3 Clock Frequency and Waiting Time for Clock to Settle
DIV1 DIV0 STS2 STS1 STS0 Waiting Time
0
0
0
0
0
8192 states
0
0
1
16384 states
0
1
0
32768 states
0
1
1
65536 states
1
0
0
131072 states
1
0
1
262144 states
1
1
0
1024 states
1
1
1
0
1
0
0
0
8192 states
0
0
1
16384 states
0
1
0
32768 states
0
1
1
65536 states
1
0
0
131072 states
1
0
1
262144 states
1
1
0
1024 states
1
1
1
1
0
0
0
0
8192 states
0
0
1
16384 states
0
1
0
32768 states
0
1
1
65536 states
1
0
0
131072 states
1
0
1
262144 states
1
1
0
1024 states
1
1
1
1
1
0
0
0
8192 states
0
0
1
16384 states
0
1
0
32768 states
0
1
1
65536 states
1
0
0
131072 states
1
0
1
262144 states
1
1
0
1024 states
1
1
1
Note: * Recommended setting
20 MHz
0.4
0.8
1.6
3.3
6.6
13.1*
0.05
18 MHz
0.46
0.91
1.8
3.6
7.3*
14.6
0.057
16 MHz
0.51
1.0
2.0
4.1
8.2*
16.4
0.064
12 MHz
0.65
1.3
2.7
5.5
10.9*
21.8
0.085
0.8
1.6
3.3
6.6
13.1*
26.2
0.10
0.91
1.8
3.6
7.3*
14.6
29.1
0.11
1.02
2.0
4.1
8.2*
16.4
32.8
0.13
1.4
2.7
5.5
10.9*
21.8
43.7
0.17
1.6
3.3
6.6
13.1*
26.2
52.4
0.20
1.8
3.6
7.3*
14.6
29.1
58.3
0.23
2.0
4.1
8.2*
16.4
32.8
65.5
0.26
2.7
5.5
10.9*
21.8
43.7
87.4
0.34
3.3
6.6
13.1*
26.2
52.4
104.9
0.41
3.6
7.3*
14.6
29.1
58.3
116.5
0.46
4.1
8.2*
16.4
32.8
65.5
131.1
0.51
5.5
10.9*
21.8
43.7
87.4
174.8
0.68
Rev.5.00 Sep. 12, 2007 Page 564 of 764
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10 MHz 8 MHz
0.8
1.0
1.6
2.0
3.3
4.1
6.6
8.2*
13.1* 16.4
26.2
32.8
0.10
0.13
Illegal setting
1.6
2.0
3.3
4.1
6.6
8.2*
13.1* 16.4
26.2
32.8
52.4
65.5
0.20
0.26
Illegal setting
3.3
4.1
6.6
8.2*
13.1* 16.4
26.2
32.8
52.4
65.5
104.9 131.1
0.41
0.51
Illegal setting
6.6
8.2*
13.1* 16.4
26.2
32.8
52.4
65.5
104.9 131.1
209.7 262.1
0.82
1.0
Illegal setting
6 MHz
1.3
2.7
5.5
10.9*
21.8
43.7
0.17
4 MHz
2.0
4.1
8.2*
16.4
32.8
65.5
0.26
2 MHz
4.1
8.2*
16.4
32.8
65.5
131.1
0.51
1 MHz Unit
8.2* ms
16.4
32.8
65.5
131.1
262.1
1.0
2.7
5.5
10.9*
21.8
43.7
87.4
0.34
4.1
8.2*
16.4
32.8
65.5
131.1
0.51
8.2*
16.4
32.8
65.5
131.1
262.1
1.0
16.4* ms
32.8
65.5
131.1
262.1
524.3
2.0
5.5
10.9*
21.8
43.7
87.4
174.8
0.68
8.2*
16.4
32.8
65.5
131.1
262.1
1.02
16.4*
32.8
65.5
131.1
262.1
524.3
2.0
32.8* ms
65.5
131.1
262.1
524.3
1048.6
4.1
10.9*
21.8
43.7
87.4
174.8
349.5
1.4
16.4*
32.8
65.5
131.1
262.1
524.3
2.0
32.8*
65.5
131.1
262.1
524.3
1048.6
4.1
65.5 ms
131.1
262.1
524.3
1048.6
2097.1
8.2*
19. Power-Down State
19.4.4
Sample Application of Software Standby Mode
Figure 19.1 shows an example in which software standby mode is entered at the fall of NMI and
exited at the rise of NMI.
With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an
NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY bit
is set to 1; then the SLEEP instruction is executed to enter software standby mode.
Software standby mode is exited at the next rising edge of the NMI signal.
Clock
oscillator
φ
NMI
NMIEG
SSBY
NMI interrupt
handler
NMIEG = 1
SSBY = 1
Software standby
mode (powerdown state)
Oscillator
settling time
(tosc2)
NMI exception
handling
SLEEP
instruction
Figure 19.1 NMI Timing for Software Standby Mode (Example)
19.4.5
Note
The I/O ports retain their existing states in software standby mode. If a port is in the high output
state, its output current is not reduced.
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19. Power-Down State
19.5
Hardware Standby Mode
19.5.1
Transition to Hardware Standby Mode
Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin
goes low. Hardware standby mode reduces power consumption drastically by halting all functions
of the CPU, DMAC, DRAM interface, and on-chip supporting modules. All modules are reset
except the on-chip RAM. As long as the specified voltage is supplied, on-chip RAM data is
retained. I/O ports are placed in the high-impedance state.
Clear the RAME bit to 0 in SYSCR before STBY goes low to retain on-chip RAM data.
The inputs at the mode pins (MD2 to MD0) should not be changed during hardware standby
mode.
19.5.2
Exit from Hardware Standby Mode
Hardware standby mode is exited by inputs at the STBY and RES pins. While RES is low, when
STBY goes high, the clock oscillator starts running. RES should be held low long enough for the
clock oscillator to settle. When RES goes high, reset exception handling begins, followed by a
transition to the program execution state.
19.5.3
Timing for Hardware Standby Mode
Figure 19.2 shows the timing relationships for hardware standby mode. To enter hardware standby
mode, first drive RES low, then drive STBY low. To exit hardware standby mode, first drive
STBY high, wait for the clock to settle, then bring RES from low to high.
Clock
oscillator
RES
STBY
Oscillator
settling time
Reset
exception
handling
Figure 19.2 Hardware Standby Mode Timing
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19. Power-Down State
19.6
Module Standby Function
19.6.1
Module Standby Timing
The module standby function can halt several of the on-chip supporting modules (SCI2, SCI1,
SCI0, the DMAC, 16-bit timer, 8-bit timer, DRAM interface, and A/D converter) independently in
the power-down state. This standby function is controlled by bits MSTPH2 to MSTPH0 in
MSTCRH and bits MSTPL7 to MSTPL0 in MSTCRL. When one of these bits is set to 1, the
corresponding on-chip supporting module is placed in standby and halts at the beginning of the
next bus cycle after the MSTCR write cycle.
19.6.2
Read/Write in Module Standby
When an on-chip supporting module is in module standby, read/write access to its registers is
disabled. Read access always results in H'FF data. Write access is ignored.
19.6.3
Usage Notes
When using the module standby function, note the following points.
DMAC: When setting a bit in MSTCR to 1 to place the DMAC or DRAM interface in module
standby, make sure that the DMAC or DRAM interface is not currently requesting the bus right. If
the corresponding bit in MSTCR is set to 1 when a bus request is present, operation of the bus
arbiter becomes ambiguous and a malfunction may occur.
DRAM Interface: When the module standby function is used on the DRAM interface, set the
MSTCR bit to 1 while DRAM space is deselected.
Cancellation of Interrupt Handling: Before setting a module standby bit, first disable interrupts
by that module. When an on-chip supporting module is placed in standby by the module standby
function, its registers are initialized, including registers with interrupt request flags.
Pin States: Pins used by an on-chip supporting module lose their module functions when the
module is placed in module standby. What happens after that depends on the particular pin. For
details, see section 8, I/O Ports. Pins that change from the input to the output state require special
care. For example, if SCI1 is placed in module standby, the receive data pin loses its receive data
function and becomes a port pin. If its port DDR bit is set to 1, the pin becomes a data output pin,
and its output may collide with external SCI transmit data. Data collision should be prevented by
clearing the port DDR bit to 0 or taking other appropriate action.
Register Resetting: When an on-chip supporting module is halted by the module standby
function, all its registers are initialized. To restart the module, after its MSTCR bit is cleared to 0,
its registers must be set up again. It is not possible to write to the registers while the MSTCR bit is
set to 1.
Rev.5.00 Sep. 12, 2007 Page 567 of 764
REJ09B0396-0500
19. Power-Down State
MSTCR Access from DMAC Disabled: To prevent malfunctions, MSTCR can only be accessed
from the CPU. It can be read by the DMAC, but it cannot be written by the DMAC.
19.7
System Clock Output Disabling Function
Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCRH. When the
PSTOP bit is set to 1, output of the system clock halts and the φ pin is placed in the highimpedance state. Figure 19.3 shows the timing of the stopping and starting of system clock output.
When the PSTOP bit is cleared to 0, output of the system clock is enabled. Table 19.4 indicates
the state of the φ pin in various operating states.
MSTCRH write cycle
MSTCRH write cycle
(PSTOP = 1)
(PSTOP = 0)
T1
T2
T3
T1
T2
T3
φ pin
High impedance
Figure 19.3 Starting and Stopping of System Clock Output
Table 19.4 φ Pin State in Various Operating States
Operating State
PSTOP = 0
PSTOP = 1
Hardware standby
High impedance
High impedance
Software standby
Always high
High impedance
Sleep mode
System clock output
High impedance
Normal operation
System clock output
High impedance
Rev.5.00 Sep. 12, 2007 Page 568 of 764
REJ09B0396-0500
20. Electrical Characteristics
Section 20 Electrical Characteristics
20.1
Absolute Maximum Ratings
Table 20.1 lists the absolute maximum ratings.
Table 20.1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Power supply voltage
VCC
–0.3 to +7.0
V
Input voltage (except for port 7)
Vin
–0.3 to VCC +0.3
V
Input voltage (port 7)
Vin
–0.3 to AVCC +0.3
V
Reference voltage
VREF
–0.3 to AVCC +0.3
V
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Analog input voltage
VAN
–0.3 to AVCC +0.3
V
Operating temperature
Topr
Regular specifications: –20 to +75
°C
Wide-range specifications: –40 to +85
°C
–55 to +125
°C
Storage temperature
Tstg
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
Rev.5.00 Sep. 12, 2007 Page 569 of 764
REJ09B0396-0500
20. Electrical Characteristics
20.2
Electrical Characteristics
20.2.1
DC Characteristics
Tables 20.2, 20.3 and 20.4 list the DC characteristics. Table 20.4 lists the permissible output
currents.
Table 20.2 DC Characteristics (1)
Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 4.5 V to AVCC* ,
1
VSS = AVSS = 0 V* , Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
1
Item
Min
Typ
Max
Unit Test Conditions
1.0
⎯
⎯
V
⎯
⎯
VCC × 0.7
V
VT – VT
0.4
⎯
⎯
V
VIH
VCC –0.7
⎯
VCC +0.3
V
EXTAL
VCC × 0.7 ⎯
VCC +0.3
V
Port 7
2.0
⎯
AVCC +0.3
V
Ports 4, 6,
P83, P84, P95 to
P90, port B,
D15 to D8
2.0
⎯
VCC +0.3
V
–0.3
⎯
0.5
V
NMI, EXTAL,
ports 4, 6, 7,
P83, P84, P95 to
P90, port B,
D15 to D8
–0.3
⎯
0.8
V
Output high
voltage
All output pins VOH
(except RESO)
VCC –0.5
⎯
⎯
V
IOH = –200 μA
3.5
⎯
⎯
V
IOH = –1 mA
Output low
voltage
All output pins VOL
(except RESO)
⎯
⎯
0.4
V
IOL = 1.6 mA
A19 to A0
⎯
⎯
1.0
V
IOL = 10 mA
RESO
⎯
⎯
0.4
V
IOL = 2.6 mA
Schmitt
trigger input
voltages
Input high
voltage
Input low
voltage
Symbol
Port A,
P82 to P80
–
VT
+
VT
+
RES, STBY,
NMI, MD2 to
MD0
RES, STBY,
MD2 to MD0
–
VIL
Rev.5.00 Sep. 12, 2007 Page 570 of 764
REJ09B0396-0500
20. Electrical Characteristics
Item
Symbol
Min
Typ
Max
Unit Test Conditions
Input leakage STBY, NMI,
current
RES,
MD2 to MD0
|Iin|
⎯
⎯
1.0
μA
Vin = 0.5 V to
VCC –0.5 V
⎯
⎯
1.0
μA
Vin = 0.5 V to
AVCC –0.5 V
⎯
⎯
1.0
μA
Vin = 0.5 V to
VCC –0.5 V
⎯
⎯
10.0
μA
Vin = 0 V
Port 7
Three-state
leakage
current
Ports 4, 6,
8 to B,
A19 to A0,
D15 to D8
|ITSI|
RESO
Input pull-up
MOS current
Port 4
–Ip
50
⎯
300
μA
Vin = 0 V
Input
capacitance
NMI
Cin
⎯
⎯
50
pF
⎯
⎯
15
pF
Vin = 0 V
f = 1 MHz
Ta = 25°C
Current
2
dissipation*
Normal
operation
⎯
45
(5.0 V)
100
mA
f = 20 MHz
Sleep mode
⎯
35
(5.0 V)
73
mA
f = 20 MHz
Module
standby mode
⎯
18
(5.0 V)
51
mA
f = 20 MHz
Standby mode
⎯
0.01
5.0
μA
Ta ≤ 50°C
⎯
⎯
20.0
μA
50°C ≤ Ta
⎯
0.6
1.5
mA
During A/D
and D/A
conversion
⎯
0.6
1.5
mA
Idle
⎯
0.01
5.0
μA
⎯
0.5
0.8
mA
During A/D
and D/A
conversion
⎯
2.0
3.0
mA
Idle
⎯
0.01
5.0
μA
2.0
⎯
⎯
V
All input pins
except NMI
Analog power During A/D
supply current conversion
Reference
current
During A/D
conversion
RAM standby voltage
ICC*
3
AICC
AICC
VRAM
DASTE = 0
DASTE = 0
Notes: 1. Do not open the pin connections of the AVCC, VREF and AVSS pins while the A/D converter
is not in use.
Rev.5.00 Sep. 12, 2007 Page 571 of 764
REJ09B0396-0500
20. Electrical Characteristics
Connect the AVCC and VREF pins to the VCC and connect the AVSS pin to the VSS,
respectively.
2. Given current consumption values are when all the output pins are made to unloaded
state and, furthermore, when the on-chip pull-up MOS is turned off under conditions
that VIH min = VCC – 0.5 V and VIL max = 0.5 V.
Also, the aforesaid current consumption values are when VIH min = VCC × 0.9 and VIL
max = 0.3 V under the condition of VRAM ≤ VCC < 4.5 V.
3. ICC max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz × V)) × VCC × f
ICC max. (when using the sleeve)
= 1.0 (mA) + 0.65 (mA/(MHz × V)) × VCC × f
ICC max. (when the sleeve + module are standing by)
= 1.0 (mA) + 0.45 (mA/(MHz × V)) × VCC × f
Also, the typ. values for current dissipation are reference values.
Rev.5.00 Sep. 12, 2007 Page 572 of 764
REJ09B0396-0500
20. Electrical Characteristics
Table 20.3 DC Characteristics (2)
Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 V to AVCC*1,
1
VSS = AVSS = 0 V* , Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Schmitt
trigger input
voltages
Input high
voltage
Input low
voltage
Symbol
Min
Typ
Max
Unit Test Conditions
–
VCC × 0.2
⎯
⎯
V
+
⎯
⎯
VCC × 0.7
V
VT – VT
VCC × 0.07
⎯
⎯
V
VIH
VCC × 0.9
⎯
VCC +0.3
V
EXTAL
VCC × 0.7
⎯
VCC +0.3
V
Port 7
VCC × 0.7
⎯
AVCC +0.3
V
Ports 4, 6,
P83, P84, P95 to
P90, port B,
D15 to D8
VCC × 0.7
⎯
VCC +0.3
V
–0.3
⎯
VCC × 0.1
V
–0.3
⎯
VCC × 0.2
V
VCC < 4.0 V
0.8
V
VCC = 4.0 to 5.5 V
Port A,
P82 to P80
VT
VT
+
RES, STBY,
NMI, MD2 to
MD0
RES, STBY,
MD2 to MD0
VIL
NMI, EXTAL,
Ports 4, 6, 7,
D15 to D8
–
P83, P84, P95 to
P90, port B
Output high
voltage
All output pins VOH
(except RESO)
VCC –0.5
⎯
⎯
V
IOH = –200 μA
VCC –1.0
⎯
⎯
V
IOH = –1 mA
Output low
voltage
All output pins VOL
(except RESO)
⎯
⎯
0.4
V
IOL = 1.6 mA
A19 to A0
⎯
⎯
1.0
V
IOL = 5 mA
(VCC < 4.0 V)
IOL = 10 mA
(VCC = 4.0 to
5.5 V)
RESO
⎯
⎯
0.4
V
IOL = 1.6 mA
Rev.5.00 Sep. 12, 2007 Page 573 of 764
REJ09B0396-0500
20. Electrical Characteristics
Item
Symbol
Min
Typ
Max
Unit Test Conditions
Input leakage STBY, NMI,
current
RES,
MD2 to MD0
|Iin|
⎯
⎯
1.0
μA
Vin = 0.5 V to
VCC –0.5 V
⎯
⎯
1.0
μA
Vin = 0.5 V to
AVCC –0.5 V
⎯
⎯
1.0
μA
Vin = 0.5 V to
VCC –0.5 V
⎯
⎯
10.0
μA
Vin = 0 V
Port 7
Three-state
leakage
current
Ports 4, 6,
8 to B,
A19 to A0,
D15 to D8
|ITSI|
RESO
Input pull-up
MOS current
Port 4
–Ip
10
⎯
300
μA
Vin = 0 V
Input
capacitance
NMI
Cin
⎯
⎯
50
pF
⎯
⎯
15
pF
Vin = 0 V
f = 1 MHz
Ta = 25°C
Current
2
dissipation*
Normal
operation
⎯
15
(3.0 V)
51
mA
f = 10 MHz
Sleep mode
⎯
9
(3.0 V)
37
mA
f = 10 MHz
Module
standby mode
⎯
6
(3.0 V)
26
mA
f = 10 MHz
Standby mode
⎯
0.01
5.0
μA
Ta ≤ 50°C
⎯
⎯
20.0
μA
50°C ≤ Ta
⎯
0.2
0.5
mA
AVCC = 3.0 V
⎯
0.6
⎯
mA
AVCC = 5.0 V
During A/D
and D/A
conversion
⎯
0.2
0.5
mA
AVCC = 3.0 V
⎯
0.6
⎯
mA
AVCC = 5.0 V
Idle
⎯
0.01
5.0
μA
DASTE = 0
⎯
0.3
0.5
mA
VREF = 3.0 V
⎯
0.5
⎯
mA
VREF = 5.0 V
During A/D
and D/A
conversion
⎯
1.2
2.0
mA
VREF = 3.0 V
⎯
2.0
⎯
mA
VREF = 5.0 V
Idle
⎯
0.01
5.0
μA
DASTE = 0
2.0
⎯
⎯
V
All input pins
except NMI
Analog power During A/D
supply current conversion
Reference
current
During A/D
conversion
RAM standby voltage
ICC*
3
AICC
AICC
VRAM
Notes: 1. Do not open the pin connections of the AVCC, VREF and AVSS pins while the A/D converter
is not in use.
Rev.5.00 Sep. 12, 2007 Page 574 of 764
REJ09B0396-0500
20. Electrical Characteristics
Connect the AVCC and VREF pins to the VCC and connect the AVSS pin to the VSS,
respectively.
2. Given current consumption values are when all the output pins are made to unloaded
state and, furthermore, when the on-chip pull-up MOS is turned off under conditions
that VIH min = VCC – 0.5 V and VIL max = 0.5 V.
Also, the aforesaid current consumption values are when VIH min = VCC × 0.9 and VIL
max = 0.3 V under the condition of VRAM ≤ VCC < 2.7 V.
3. ICC max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz × V)) × VCC × f
ICC max. (when using the sleeve)
= 1.0 (mA) + 0.65 (mA/(MHz × V)) × VCC × f
ICC max. (when the sleeve + module are standing by)
= 1.0 (mA) + 0.45 (mA/(MHz × V)) × VCC × f
Also, the typ. values for current dissipation are reference values.
Rev.5.00 Sep. 12, 2007 Page 575 of 764
REJ09B0396-0500
20. Electrical Characteristics
Table 20.4 DC Characteristics (3)
1
Conditions: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 V to AVCC* ,
1
VSS = AVSS = 0 V* , Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Schmitt
trigger input
voltages
Input high
voltage
Input low
voltage
Symbol
Port A,
P82 to P80
Min
Typ
Max
Unit Test Conditions
–
VCC × 0.2
⎯
⎯
V
+
⎯
⎯
VCC × 0.7
V
VT
VT
VT – VT
VCC × 0.07 ⎯
⎯
V
VIH
VCC × 0.9
⎯
VCC +0.3
V
EXTAL
VCC × 0.7
⎯
VCC +0.3
V
Port 7
VCC × 0.7
⎯
AVCC +0.3
V
Ports 4, 6,
P83, P84, P95 to
P90, Port B, D15
to D8
VCC × 0.7
⎯
VCC +0.3
V
–0.3
⎯
VCC × 0.1
V
–0.3
⎯
VCC × 0.2
V
VCC < 4.0 V
0.8
V
VCC = 4.0 to
5.5 V
+
RES, STBY,
NMI, MD2 to
MD0
RES, STBY,
MD2 to MD0
–
VIL
NMI, EXTAL,
Ports 4, 6, 7
P83, P84, P95 to
P90, Port B, D15
to D8
Output high
voltage
All output pins VOH
(except RESO)
VCC –0.5
⎯
⎯
V
IOH = –200 μA
VCC –1.0
⎯
⎯
V
IOH = –1 mA
Output low
voltage
All output pins VOL
(except RESO)
⎯
⎯
0.4
V
IOL = 1.6 mA
A19 to A0
⎯
⎯
1.0
V
IOL = 5 mA
(VCC < 4.0 V)
IOL = 10 mA
(VCC = 4.0 to
5.5 V)
RESO
Rev.5.00 Sep. 12, 2007 Page 576 of 764
REJ09B0396-0500
⎯
⎯
0.4
V
IOL = 1.6 mA
20. Electrical Characteristics
Item
Symbol
Min
Typ
Max
Unit Test Conditions
Input leakage STBY, NMI,
current
RES,
MD2 to MD0
|Iin|
⎯
⎯
1.0
μA
Vin = 0.5 V to
VCC – 0.5 V
Port 7
⎯
⎯
1.0
μA
Vin = 0.5 V to
AVCC – 0.5 V
Ports 4, 6, 8 to |ITSI|
B, A19 to A0,
D15 to D8
⎯
⎯
1.0
μA
Vin = 0.5 V to
VCC – 0.5 V
RESO
⎯
⎯
10.0
μA
Vin = 0 V
Three-state
leakage
current
Input pull-up
MOS current
Port 4
–Ip
10
⎯
300
μA
Vin = 0 V
Input
capacitance
NMI
Cin
⎯
⎯
50
pF
⎯
⎯
15
pF
Vin = 0 V
f = 1 MHz
Ta = 25°C
Current
2
dissipation*
Normal
operation
⎯
20
(3.5 V)
66
mA
f = 13 MHz
Sleep mode
⎯
15
(3.5 V)
48
mA
f = 13 MHz
Module
standby mode
⎯
9
(3.5 V)
34
mA
f = 13 MHz
Standby mode
⎯
0.01
5.0
μA
Ta ≤ 50°C
⎯
⎯
20.0
μA
50°C ≤ Ta
⎯
0.2
0.5
mA
AVCC = 3.0 V
⎯
0.6
⎯
mA
AVCC = 5.0 V
During A/D
and D/A
conversion
⎯
0.2
0.5
mA
AVCC = 3.0 V
⎯
0.6
⎯
mA
AVCC = 5.0 V
Idle
⎯
0.01
5.0
μA
DASTE = 0
⎯
0.3
0.5
mA
VREF = 3.0 V
⎯
0.5
⎯
mA
VREF = 5.0 V
During A/D
and D/A
conversion
⎯
1.2
2.0
mA
VREF = 3.0 V
⎯
2.0
⎯
mA
VREF = 5.0 V
Idle
⎯
0.01
5.0
μA
DASTE = 0
2.0
⎯
⎯
V
All input pins
except NMI
Analog power During A/D
supply current conversion
Reference
current
During A/D
conversion
RAM standby voltage
ICC*
3
AICC
AICC
VRAM
Notes: 1. Do not open the pin connections of the AVCC, VREF and AVSS pins while the A/D converter
is not in use.
Rev.5.00 Sep. 12, 2007 Page 577 of 764
REJ09B0396-0500
20. Electrical Characteristics
Connect the AVCC and VREF pins to the VCC and connect the AVSS pin to the VSS,
respectively.
2. Given current consumption values are when all the output pins are made to unloaded
state and, furthermore, when the on-chip pull-up MOS is turned off under conditions
that VIH min = VCC – 0.5 V and VIL max = 0.5 V.
Also, the aforesaid current consumption values are when VIH min = VCC × 0.9 and VIL
max = 0.3 V under the condition of VRAM ≤ VCC < 3.0 V.
3. ICC max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz × V)) × VCC × f
ICC max. (when using the sleeve)
= 1.0 (mA) + 0.65 (mA/(MHz × V)) × VCC × f
ICC max. (when the sleeve + module are standing by)
= 1.0 (mA) + 0.45 (mA/(MHz × V)) × VCC × f
Also, the typ. values for current dissipation are reference values.
Rev.5.00 Sep. 12, 2007 Page 578 of 764
REJ09B0396-0500
20. Electrical Characteristics
Table 20.5 Permissible Output Currents
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Permissible output
low current (per pin)
A19 to A0
Permissible output
low current (total)
Total of 20 pins in
A19 to A0
Symbol
Min
Typ
Max
Unit
IOL
⎯
⎯
10
mA
⎯
⎯
2.0
mA
⎯
⎯
80
mA
⎯
⎯
120
mA
Other output pins
ΣIOL
Total of all output pins,
including the above
Permissible output
high current (per pin)
All output pins
|–IOH|
⎯
⎯
2.0
mA
Permissible output
high current (total)
Total of all output pins
|Σ–IOH|
⎯
⎯
40
mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 20.5.
2. When driving a darlington pair, always insert a current-limiting resistor in the output line,
as shown in figures 20.1.
H8/3006 and H8/3007
2 kΩ
Port
Darlington pair
Figure 20.1 Darlington Pair Drive Circuit (Example)
Rev.5.00 Sep. 12, 2007 Page 579 of 764
REJ09B0396-0500
20. Electrical Characteristics
20.2.2
AC Characteristics
Clock timing parameters are listed in table 20.6, control signal timing parameters in table 20.7,
and bus timing parameters in table 20.8. Timing parameters of the on-chip supporting modules are
listed in table 20.9.
Table 20.6 Clock Timing
Condition:
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V,
φ = 1 to 10 MHz
Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V,
φ = 1 to 13 MHz
Condition C: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,
φ = 1 to 20 MHz
Condition A
Condition B
Condition C
Item
Symbol
Min
Max
Min
Max
Min
Max
Test
Unit Conditions
Clock cycle time
tcyc
100
1000
76.9
1000
50
1000
ns
Clock pulse low
width
tCL
30
⎯
20
⎯
15
⎯
ns
Clock pulse high
width
tCH
30
⎯
20
⎯
15
⎯
ns
Clock rise time
tCr
⎯
20
⎯
15
⎯
10
ns
Clock fall time
tCf
⎯
20
⎯
15
⎯
10
ns
Clock oscillator
settling time at
reset
tOSC1
20
⎯
20
⎯
20
⎯
ms
Figure 20.4
Clock oscillator
settling time in
software standby
tOSC2
7
⎯
7
⎯
7
⎯
ms
Figure 19.1
Rev.5.00 Sep. 12, 2007 Page 580 of 764
REJ09B0396-0500
Figure 20.3
20. Electrical Characteristics
Table 20.7 Control Signal Timing
Condition:
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V,
φ = 1 to 10 MHz
Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V,
φ = 1 to 13 MHz
Condition C: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,
φ = 1 to 20 MHz
Condition A
Condition B
Condition C
Item
Symbol
Min
Max
Min
Max
Min
Max
Unit
Test
Conditions
RES setup time
tRESS
200
⎯
200
⎯
150
⎯
ns
Figure 20.5
RES pulse width
tRESW
10
⎯
10
⎯
10
⎯
tcyc
Mode programming
setup time
tMDS
200
⎯
200
⎯
200
⎯
ns
RESO output delay
time
tRESD
⎯
100
⎯
100
⎯
50
ns
RESO output pulse
width
tRESOW
132
⎯
132
⎯
132
⎯
tcyc
NMI, IRQ setup time tNMIS
200
⎯
200
⎯
150
⎯
ns
NMI, IRQ hold time
tNMIH
10
⎯
10
⎯
10
⎯
ns
NMI, IRQ pulse
width (in recovery
from software
standby mode)
tNMIW
200
⎯
200
⎯
200
⎯
ns
Figure 20.6
Figure 20.7
Rev.5.00 Sep. 12, 2007 Page 581 of 764
REJ09B0396-0500
20. Electrical Characteristics
Table 20.8 Bus Timing
Condition:
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V,
φ = 1 to 10 MHz
Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V,
φ = 1 to 13 MHz
Condition C: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,
φ = 1 to 20 MHz
Condition A
Condition B
Condition C
Max
Min
Max
Min
Max
Test
Unit Conditions
⎯
50
⎯
40
⎯
25
ns
tAH
0.5 tcyc
– 45
⎯
0.5 tcyc
– 35
⎯
0.5 tcyc
– 20
⎯
ns
Read strobe
delay time
tRSD
⎯
60
⎯
50
⎯
25
ns
Address strobe
delay time
tASD
⎯
60
⎯
50
⎯
25
ns
Write strobe
delay time
tWSD
⎯
60
⎯
50
⎯
25
ns
Strobe delay time tSD
⎯
60
⎯
50
⎯
25
ns
Write strobe
pulse width 1
tWSW1
1.0 tcyc
– 50
⎯
1.0 tcyc
– 40
⎯
1.0 tcyc
– 25
⎯
ns
Write strobe
pulse width 2
tWSW2
1.5 tcyc
– 50
⎯
1.5 tcyc
– 40
⎯
1.5 tcyc
– 25
⎯
ns
Address setup
time 1
tAS1
0.5 tcyc
– 45
⎯
0.5 tcyc
– 35
⎯
0.5 tcyc
– 20
⎯
ns
Address setup
time 2
tAS2
1.0 tcyc
– 45
⎯
1.0 tcyc
– 35
⎯
1.0 tcyc
– 20
⎯
ns
Read data setup tRDS
time
50
⎯
40
⎯
25
⎯
ns
Read data hold
time
tRDH
0
⎯
0
⎯
0
⎯
ns
Write data delay
time
tWDD
⎯
60
⎯
50
⎯
35
ns
Item
Symbol Min
Address delay
time
tAD
Address hold
time
Rev.5.00 Sep. 12, 2007 Page 582 of 764
REJ09B0396-0500
Figure 20.8,
figure 20.9,
figure 20.11,
figure 20.12
20. Electrical Characteristics
Condition A
Condition B
Condition C
Item
Symbol Min
Max
Min
Max
Min
Max
Test
Unit Conditions
Write data setup
time 1
tWDS1
1.0 tcyc
– 50
⎯
1.0 tcyc
– 40
⎯
1.0 tcyc
– 30
⎯
ns
Write data setup
time 2
tWDS2
2.0 tcyc
– 50
⎯
2.0 tcyc
– 40
⎯
2.0 tcyc
– 30
⎯
ns
Write data hold
time
tWDH
0.5 tcyc
– 30
⎯
0.5 tcyc
– 25
⎯
0.5 tcyc
– 15
⎯
ns
Read data
access time 1
tACC1
⎯
2.0 tcyc
– 100
⎯
2.0 tcyc
– 80
⎯
2.0 tcyc ns
– 45
Read data
access time 2
tACC2
⎯
3.0 tcyc
– 100
⎯
3.0 tcyc
– 80
⎯
3.0 tcyc ns
– 45
Read data
access time 3
tACC3
⎯
1.5 tcyc
– 100
⎯
1.5 tcyc
– 80
⎯
1.5 tcyc ns
– 45
Read data
access time 4
tACC4
⎯
2.5 tcyc
– 100
⎯
2.5 tcyc
– 80
⎯
2.5 tcyc ns
– 45
Precharge time 1 tPCH1
1.0 tcyc
– 40
⎯
1.0 tcyc
– 30
⎯
1.0 tcyc
– 20
⎯
ns
Precharge time 2 tPCH2
0.5 tcyc
– 40
⎯
0.5 tcyc
– 30
⎯
0.5 tcyc
– 20
⎯
ns
Wait setup time
tWTS
40
⎯
40
⎯
25
⎯
ns
Wait hold time
tWTH
5
⎯
5
⎯
5
⎯
ns
Bus request
setup time
tBRQS
40
⎯
40
⎯
25
⎯
ns
Bus acknowledge tBACD1
delay time 1
⎯
60
⎯
50
⎯
30
ns
Bus acknowledge tBACD2
delay time 2
⎯
60
⎯
50
⎯
30
ns
Bus-floating time tBZD
⎯
60
⎯
50
⎯
30
ns
RAS precharge
time
tRP
1.5 tcyc
– 50
⎯
1.5 tcyc
– 40
⎯
1.5 tcyc
– 25
⎯
ns
CAS precharge
time
tCP
0.5 tcyc
– 30
⎯
0.5 tcyc
– 25
⎯
0.5 tcyc
– 15
⎯
ns
Low address hold tRAH
time
0.5 tcyc
– 30
⎯
0.5 tcyc
– 25
⎯
0.5 tcyc
– 15
⎯
ns
RAS delay time 1 tRAD1
⎯
60
⎯
50
⎯
25
ns
RAS delay time 2 tRAD2
⎯
60
⎯
50
⎯
30
ns
Figure 20.8,
figure 20.9,
figure 20.11,
figure 20.12
Figure 20.10
Figure 20.13
Figure 20.14
to
figure 20.16
Rev.5.00 Sep. 12, 2007 Page 583 of 764
REJ09B0396-0500
20. Electrical Characteristics
Condition A
Item
Symbol Min
Condition B
Condition C
Max
Min
Max
Min
Max
Test
Unit Conditions
CAS delay time 1 tCASD1
⎯
60
⎯
50
⎯
25
ns
CAS delay time 2 tCASD2
⎯
60
⎯
50
⎯
25
ns
WE delay time
⎯
60
⎯
50
⎯
25
ns
CAS pulse width tCAS1
1
1.5 tcyc
– 50
⎯
1.5 tcyc
– 40
⎯
1.5 tcyc
– 20
⎯
ns
CAS pulse width tCAS2
2
1.0 tcyc
– 50
⎯
1.0 tcyc
– 40
⎯
1.0 tcyc
– 20
⎯
ns
CAS pulse width tCAS3
3
1.0 tcyc
– 50
⎯
1.0 tcyc
– 40
⎯
1.0 tcyc
– 20
⎯
ns
RAS access time tRAC
⎯
2.5 tcyc
– 80
⎯
2.5 tcyc
– 70
⎯
2.5 tcyc ns
– 40
Address access
time
⎯
2.0 tcyc
– 100
⎯
2.0 tcyc
– 80
⎯
2.0 tcyc ns
– 50
CAS access time tCAC
⎯
1.5 tcyc
– 100
⎯
1.5 tcyc
– 80
⎯
1.5 tcyc ns
– 50
WE setup time
tWCS
0.5 tcyc
– 45
⎯
0.5 tcyc
– 35
⎯
0.5 tcyc
– 20
⎯
ns
WE hold time
tWCH
0.5 tcyc
– 40
⎯
0.5 tcyc
– 28
⎯
0.5 tcyc
– 15
⎯
ns
Write data setup
time
tWDS
0.5 tcyc
– 45
⎯
0.5 tcyc
– 35
⎯
0.5 tcyc
– 20
⎯
ns
WE write data
hold time
tWDH
0.5 tcyc
– 30
⎯
0.5 tcyc
– 25
⎯
0.5 tcyc
– 15
⎯
ns
CAS setup time 1 tCSR1
0.5 tcyc
– 30
⎯
0.5 tcyc
– 25
⎯
0.5 tcyc
– 20
⎯
ns
CAS setup time 2 tCSR2
0.5 tcyc
– 30
⎯
0.5 tcyc
– 25
⎯
0.5 tcyc
– 15
⎯
ns
CAS hold time
tCHR
0.5 tcyc
– 30
⎯
0.5 tcyc
– 25
⎯
0.5 tcyc
– 15
⎯
ns
RAS pulse width tRAS
1.5 tcyc
– 30
⎯
1.5 tcyc
– 25
⎯
1.5 tcyc
– 15
⎯
ns
tWCD
tAA
Rev.5.00 Sep. 12, 2007 Page 584 of 764
REJ09B0396-0500
Figure 20.14
to
figure 20.16
20. Electrical Characteristics
Table 20.9 Timing of On-Chip Supporting Modules
Condition:
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V,
φ = 1 to 10 MHz
Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V,
φ = 1 to 13 MHz
Condition C: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,
φ = 1 to 20 MHz
Condition
A
Condition
B
Condition
C
Min
Max
Min
Max
Min
Max
Unit
Test
Conditions
Output data delay tPWD
time
⎯
100
⎯
100
⎯
50
ns
Figure 20.17
Input data setup
time
tPRS
50
⎯
50
⎯
50
⎯
ns
Input data hold
time
tPRH
50
⎯
50
⎯
50
⎯
ns
tTOCD
⎯
100
⎯
100
⎯
50
ns
Timer input setup tTICS
time
50
⎯
50
⎯
50
⎯
ns
Timer clock input tTCKS
setup time
50
⎯
50
⎯
50
⎯
ns
Timer
clock
pulse
width
Item
Ports
and
TPC
Symbol
16-bit Timer output
timer delay time
8-bit
timer
Single
edge
tTCKWH
1.5
⎯
1.5
⎯
1.5
⎯
tcyc
Both
edges
tTCKWL
2.5
⎯
2.5
⎯
2.5
⎯
tcyc
Timer output
delay time
tTOCD
⎯
100
⎯
100
⎯
50
ns
Timer input
setup time
tTICS
50
⎯
50
⎯
50
⎯
ns
Timer clock
input setup time
tTCKS
50
⎯
50
⎯
50
⎯
ns
Timer
clock
pulse
width
Single
edge
tTCKWH
1.5
⎯
1.5
⎯
1.5
⎯
tcyc
Both
edges
tTCKWL
2.5
⎯
2.5
⎯
2.5
⎯
tcyc
Figure 20.18
Figure 20.19
Figure 20.18
Figure 20.19
Rev.5.00 Sep. 12, 2007 Page 585 of 764
REJ09B0396-0500
20. Electrical Characteristics
Condition
A
Condition
B
Condition
C
Min
Max
Min
Max
Min
Max
Unit
Test
Conditions
AsyntScyc
chronous
4
⎯
4
⎯
4
⎯
tcyc
Figure 20.20
Synchronous
6
⎯
6
⎯
6
⎯
tcyc
Item
SCI
Symbol
Input
clock
cycle
Input clock rise
time
tSCKr
1.5
⎯
1.5
⎯
1.5
⎯
tcyc
Input clock fall
time
tSCKf
1.5
⎯
1.5
⎯
1.5
⎯
tcyc
Input clock
pulse width
tSCKW
0.4
0.6
0.4
0.6
0.4
0.6
tScyc
Transmit data
delay time
tTXD
⎯
100
⎯
100
⎯
100
ns
Receive data
setup time
(synchronous)
tRXS
100
⎯
100
⎯
100
⎯
ns
Receive
data hold
time (synchronous)
tRXH
100
⎯
100
⎯
100
⎯
ns
0
⎯
0
⎯
0
⎯
ns
Clock
input
Clock
output
DMAC TEND delay
time 1
tTED1
⎯
100
⎯
100
⎯
50
ns
TEND delay
time 2
tTED2
⎯
100
⎯
100
⎯
50
ns
DREQ setup
time
tDRQS
40
⎯
40
⎯
25
⎯
ns
DREQ hold
time
tDRQH
10
⎯
10
⎯
10
⎯
ns
Rev.5.00 Sep. 12, 2007 Page 586 of 764
REJ09B0396-0500
Figure 20.21
Figure 20.22,
figure 20.23
Figure 20.24
20. Electrical Characteristics
RL
C = 90 pF: Ports 4, 6, 8, A19 to A0,
D15 to D8
C = 30 pF: Ports 9, A, B, RESO
H8/3006 and
H8/3007
output pin
R L = 2.4 k Ω
R H = 12 k Ω
C
RH
Input/output timing measurement levels
• Low: 0.8 V
• High: 2.0 V
Figure 20.2 Output Load Circuit
Rev.5.00 Sep. 12, 2007 Page 587 of 764
REJ09B0396-0500
20. Electrical Characteristics
20.2.3
A/D Conversion Characteristics
Table 20.10 lists the A/D conversion characteristics.
Table 20.10 A/D Conversion Characteristics
Condition:
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V,
fmax = 10 MHz
Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V,
fmax = 13 MHz
Condition C: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,
fmax = 20 MHz
Condition A
Condition B
Condition C
Min Typ Max
Min Typ Max
Min Typ Max
Unit
Resolution
10
10
10
10
10
10
10
10
10
bits
Conversion time
(single mode)
⎯
⎯
134
⎯
⎯
134
⎯
⎯
134
tcyc
Analog input capacitance ⎯
⎯
20
⎯
⎯
20
⎯
⎯
20
pF
Permissible φ ≤ 13 MHz ⎯
signalφ > 13 MHz ⎯
source
impedance 4.0 V ≤ AVCC ⎯
≤ 5.5 V
⎯
⎯
⎯
⎯
⎯
⎯
⎯
10
kΩ
⎯
⎯
⎯
⎯
⎯
⎯
⎯
5
kΩ
⎯
10
⎯
⎯
10
⎯
⎯
⎯
kΩ
2.7 V ≤ AVCC ⎯
< 4.0 V
⎯
5
⎯
⎯
5
⎯
⎯
⎯
kΩ
Nonlinearity error
⎯
⎯
±7.5
⎯
⎯
±7.5
⎯
⎯
±3.5
LSB
Item
Conversion
time: 134
states
Offset error
⎯
⎯
±7.5
⎯
⎯
±7.5
⎯
⎯
±3.5
LSB
Full-scale error
⎯
⎯
±7.5
⎯
⎯
±7.5
⎯
⎯
±3.5
LSB
Quantization error
⎯
⎯
±0.5
⎯
⎯
±0.5
⎯
⎯
±0.5
LSB
Absolute accuracy
⎯
⎯
±8.0
⎯
⎯
±8.0
⎯
⎯
±4.0
LSB
Rev.5.00 Sep. 12, 2007 Page 588 of 764
REJ09B0396-0500
20. Electrical Characteristics
Condition A
Condition B
Condition C
Min Typ Max
Min Typ Max
Min Typ Max
Unit
Resolution
10
10
10
10
10
10
10
10
10
bits
Conversion time
(single mode)
⎯
⎯
70
⎯
⎯
70
⎯
⎯
70
tcyc
Analog input capacitance ⎯
⎯
20
⎯
⎯
20
⎯
⎯
20
pF
Permissible φ ≤ 13 MHz ⎯
signalφ > 13 MHz ⎯
source
impedance 4.0 V ≤ AVCC ⎯
≤ 5.5 V
⎯
⎯
⎯
⎯
⎯
⎯
⎯
5
kΩ
⎯
⎯
⎯
⎯
⎯
⎯
⎯
3
kΩ
⎯
5
⎯
⎯
5
⎯
⎯
⎯
kΩ
2.7 V ≤ AVCC ⎯
< 4.0 V
⎯
3
⎯
⎯
3
⎯
⎯
⎯
kΩ
Nonlinearity error
⎯
⎯
±15.5 ⎯
⎯
±15.5 ⎯
⎯
±7.5
LSB
Offset error
⎯
⎯
±15.5 ⎯
⎯
±15.5 ⎯
⎯
±7.5
LSB
Full-scale error
⎯
⎯
±15.5 ⎯
⎯
±15.5 ⎯
⎯
±7.5
LSB
Quantization error
⎯
⎯
±0.5
⎯
⎯
±0.5
⎯
⎯
±0.5
LSB
Absolute accuracy
⎯
⎯
±16
⎯
⎯
±16
⎯
⎯
±8.0
LSB
Item
Conversion
time: 70
states
Rev.5.00 Sep. 12, 2007 Page 589 of 764
REJ09B0396-0500
20. Electrical Characteristics
20.2.4
D/A Conversion Characteristics
Table 20.11 lists the D/A conversion characteristics.
Table 20.11 D/A Conversion Characteristics
Condition:
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VREF = 2.7 to AVCC, VSS = AVSS = 0 V,
fmax = 10 MHz
Condition B: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, VREF = 3.0 to AVCC, VSS = AVSS = 0 V,
fmax = 13 MHz
Condition C: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 4.5 to AVCC, VSS = AVSS = 0 V,
fmax = 20 MHz
Condition A
Condition B
Condition C
Item
Min Typ Max
Min Typ Max
Min Typ Max
Test
Unit Conditions
Resolution
8
8
8
8
8
8
8
8
8
Bits
Conversion time
(centering time)
⎯
⎯
10
⎯
⎯
10
⎯
⎯
10
μs
Absolute accuracy
⎯
±2.0 ±3.0
⎯
±2.0 ±3.0
⎯
±1.5 ±2.0
LSB 2 MΩ
resistive load
⎯
⎯
⎯
⎯
⎯
⎯
LSB 4 MΩ
resistive load
±2.0
Rev.5.00 Sep. 12, 2007 Page 590 of 764
REJ09B0396-0500
±2.0
±1.5
20 pF
capacitive
load
20. Electrical Characteristics
20.3
Operational Timing
This section shows timing diagrams.
20.3.1
Clock Timing
Clock timing is shown as follows:
• System clock timing
Figure 20.3 shows the system clock timing.
• Oscillator settling timing
Figure 20.4 shows the oscillator settling timing.
tcyc
tCH
φ
tCf
tCL
tCr
Figure 20.3 System Clock Timing
φ
VCC
STBY
tOSC1
tOSC1
RES
Figure 20.4 Oscillator Settling Timing
Rev.5.00 Sep. 12, 2007 Page 591 of 764
REJ09B0396-0500
20. Electrical Characteristics
20.3.2
Control Signal Timing
Control signal timing is shown as follows:
• Reset input timing
Figure 20.5 shows the reset input timing.
• Reset output timing
Figure 20.6 shows the reset output timing.
• Interrupt input timing
Figure 20.7 shows the interrupt input timing for NMI and IRQ5 to IRQ0.
φ
tRESS
tRESS
RES
tMDS
tRESW
MD2 to MD0
Figure 20.5 Reset Input Timing
φ
tRESD
tRESD
RESO
tRESOW
Figure 20.6 Reset Output Timing
Rev.5.00 Sep. 12, 2007 Page 592 of 764
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20. Electrical Characteristics
φ
tNMIS
tNMIH
tNMIS
tNMIH
NMI
IRQ E
tNMIS
IRQ L
IRQ E : Edge-sensitive IRQ i
IRQ L : Level-sensitive IRQ i (i = 0 to 5)
tNMIW
NMI
IRQ j
(j = 0 to 5)
Figure 20.7 Interrupt Input Timing
20.3.3
Bus Timing
Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 20.8 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 20.9 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 20.10 shows the timing of the external three-state access cycle with one wait state
inserted.
• Burst ROM access timing: burst cycle two-state
Figure 20.11 shows the timing of the burst cycle two-state access.
• Burst ROM access timing: burst cycle three-state
Figure 20.12 shows the timing of the burst cycle three-state access.
• Bus-release mode timing
Figure 20.13 shows the bus-release mode timing.
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20. Electrical Characteristics
T1
tcyc
T2
tCH
tCL
φ
tCf
tAD
tcyc
tCr
A23 to A0,
CSn
tPCH1
AS
RD
(read)
tASD
tACC3
tASD
tACC3
tSD
tAH
tAS1
tRSD
tAS1
tPCH2
tRDH*
tACC1
tRDS
D15 to D0
(read)
tPCH1
tASD
HWR, LWR
(write)
tSD
tAH
tAS1
tWDD
tWSW1
tWDS1
tWDH
D15 to D0
(write)
Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD.
Figure 20.8 Basic Bus Cycle: Two-State Access
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20. Electrical Characteristics
T1
T2
T3
φ
A23 to A0,
CSn
tACC4
AS
tACC4
RD
(read)
tACC2
tRDS
D15 to D0
(read)
tWSD
HWR, LWR
(write)
tWSW2
tAS2
tWDD
tWDS2
D15 to D0
(write)
Figure 20.9 Basic Bus Cycle: Three-State Access
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20. Electrical Characteristics
T1
T2
TW
T3
φ
A23 to A0,
CSn
AS
RD (read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
tWTS
tWTH
tWTS
tWTH
WAIT
Figure 20.10 Basic Bus Cycle: Three-State Access with One Wait State
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20. Electrical Characteristics
T1
T2
T3
T1
T2
φ
tAD
tAD
A23 to A3,
CSn
A2 to A0
tASD
AS
tACC4
tAH
tAS1
tASD
tSD
tAH
tAS1
tASD
RD
tSD
tRSD
tACC4
tAS1
tRDH*
tACC2
tRDS
tACC1
tRDS
D15 to D0
Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD.
Figure 20.11 Burst ROM Access Timing: Two-State Access
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20. Electrical Characteristics
T1
T2
T3
T1
T2
T3
φ
tAD
tAD
A23 to A3,
CSn
A2 to A0
tASD
AS
tACC4
tAH
tAS1
tASD
tSD
tAH
tAS1
tASD
RD
tSD
tRSD
tACC4
tAS1
tRDH*
tACC2
tACC2
tRDS
tRDS
D15 to D0
Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD.
Figure 20.12 Burst ROM Access Timing: Three-State Access
φ
tBRQS
tBRQS
BREQ
tBACD2
tBACD1
BACK
tBZD
A23 to A0,
AS, RD,
HWR, LWR
Figure 20.13 Bus-Release Mode Timing
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tBZD
20. Electrical Characteristics
20.3.4
DRAM Interface Bus Timing
DRAM interface bus timing is shown as follows:
• DRAM bus timing: read and write access
Figure 20.14 shows the timing of the read and write access.
• DRAM bus timing: CAS before RAS refresh
Figure 20.15 shows the timing of the CAS before RAS refresh.
• DRAM bus timing: self-refresh
Figure 20.16 shows the timing of the self-refresh.
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20. Electrical Characteristics
Tp
Tr
TC1
TC2
φ
tAD
tAD
tAD
A23 to A0
tAS1
tRAH
tRAD2
tRP
CS5 to CS2
(RAS5 to RAS2)
tRAD1
tCASD2
tASD
tCAS1
UCAS, LCAS
(read)
RD (WE)
(read)
tCP
(High)
tRAC
tRDS
tRDH*
tAA
D15 to D0
(read)
tCAC
tCASD2
tCASD1
tCAS2
UCAS, LCAS
(write)
tCP
tASD
tWCD
RD (WE)
(write)
tWCS
tWDD
tWCH
tWDS
D15 to D0
(write)
RFSH
(High)
Note: * Specification from the earliest negation timing of RAS and CAS.
Figure 20.14 DRAM Bus Timing (Read/Write)
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tWDH
20. Electrical Characteristics
TRp
TR1
TR2
φ
tRAD1
tRAD2
tRP
CS5 to CS2
(RAS5 to
RAS2)
tRAS
tCASD1
tCASD2
tCSR1
tCAS3
UCAS,
LCAS
RD (WE)
(High)
tRAD2
tRAD1
tCSR1
RFSH
tCHR
tCHR
tRAS
Figure 20.15 DRAM Bus Timing (CAS before RAS Refresh)
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20. Electrical Characteristics
φ
tCSR2
CS5 to CS2
(RAS5 to
RAS2)
UCAS,
LCAS
RD (WE)
(High)
tCSR2
RFSH
Figure 20.16 DRAM Bus Timing (Self-Refresh)
20.3.5
TPC and I/O Port Timing
Figure 20.17 shows the TPC and I/O port input/output timing.
T1
T2
T3
φ
tPRS
tPRH
Port 4,
6 to B
(read)
tPWD
Port 4, 6,
8 to B
(write)
Figure 20.17 TPC and I/O Port Input/Output Timing
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20. Electrical Characteristics
20.3.6
Timer Input/Output Timing
The timings of 16-bit and 8-bit timer are shown as follows:
• Timer input/output timing
Figure 20.18 shows the timer input/output timing.
• Timer external clock input timing
Figure 20.19 shows the timer external clock input timing.
φ
tTOCD
Output
compare*1
tTICS
Input
capture*2
Notes: 1. TIOCA 0 to TIOCA 2, TIOCB 0 to TIOCB 2 , TMO0, TMO2, TMIO1,TMIO3
2. TIOCA 0 to TIOCA 2, TIOCB 0 to TIOCB 2 , TMIO1, TMIO3
Figure 20.18 Timer Input/Output Timing
tTCKS
φ
tTCKS
TCLKA to
TCLKD
tTCKWL
tTCKWH
Figure 20.19 Timer External Clock Input Timing
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20. Electrical Characteristics
20.3.7
SCI Input/Output Timing
SCI timing is shown as follows:
• SCI input clock timing
Figure 20.20 shows the SCI input clock timing.
• SCI input/output timing (synchronous mode)
Figure 20.21 shows the SCI input/output timing in synchronous mode.
tSCKW
tSCKr
tSCKf
SCK0 to SCK2
tScyc
Figure 20.20 SCI Input Clock Timing
tScyc
SCK0 to
SCK2
tTXD
TxD0 to TxD2
(transmit
data)
tRXS
tRXH
RxD0 to RxD2
(receive
data)
Figure 20.21 SCI Input/Output Timing in Synchronous Mode
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20. Electrical Characteristics
20.3.8
DMAC Timing
DMAC timing is shown as follows.
• DMAC TEND output timing for 2 state access
Figure 20.22 shows the DMAC TEND output timing for 2 state access.
• DMAC TEND output timing for 3 state access
Figure 20.23 shows the DMAC TEND output timing for 3 state access.
• DMAC DREQ input timing
Figure 20.24 shows DMAC DREQ input timing.
T1
T2
φ
tTED1
tTED2
TEND
Figure 20.22 DMAC TEND Output Timing for 2 State Access
T1
T2
T3
φ
tTED2
tTED1
TEND
Figure 20.23 DMAC TEND Output Timing for 3 State Access
φ
tDRQS
tDRQH
DREQ
Figure 20.24 DMAC DREQ Input Timing
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20. Electrical Characteristics
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Appendix A Instruction Set
Appendix A Instruction Set
A.1
Instruction List
Operand Notation
Symbol
Description
Rd
General destination register
Rs
General source register
Rn
General register
ERd
General destination register (address register or 32-bit register)
ERs
General source register (address register or 32-bit register)
ERn
General register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
PC
Program counter
SP
Stack pointer
CCR
Condition code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
disp
Displacement
→
Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
+
Addition of the operands on both sides
–
Subtraction of the operand on the right from the operand on the left
×
Multiplication of the operands on both sides
÷
Division of the operand on the left by the operand on the right
∧
Logical AND of the operands on both sides
∨
Logical OR of the operands on both sides
⊕
Exclusive logical OR of the operands on both sides
¬
NOT (logical complement)
( ), < >
Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers
(R0 to R7 and E0 to E7).
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Appendix A Instruction Set
Condition Code Notation
Symbol
Description
Changed according to execution result
*
Undetermined (no guaranteed value)
0
Cleared to 0
1
Set to 1
⎯
Not affected by execution of the instruction
Δ
Varies depending on conditions, described in notes
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Appendix A Instruction Set
Table A.1
Instruction Set
1. Data transfer instructions
#xx:8 → Rd8
2
2
I
H N
⎯ ⎯
Z
V
C
Normal
Operation
Advanced
No. of
States*1
Condition Code
⎯
@@aa
B
@(d, PC)
B
MOV.B @ERs, Rd
@aa
MOV.B Rs, Rd
@–ERn/@ERn+
2
@(d, ERn)
B
@ERn
#xx
MOV.B #xx:8, Rd
Rn
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
0 ⎯
2
Rs8 → Rd8
⎯ ⎯
0 ⎯
2
@ERs → Rd8
⎯ ⎯
0 ⎯
4
MOV.B @(d:16, ERs), B
Rd
4
@(d:16, ERs) → Rd8
⎯ ⎯
0 ⎯
6
MOV.B @(d:24, ERs), B
Rd
8
@(d:24, ERs) → Rd8
⎯ ⎯
0 ⎯
10
@ERs → Rd8
ERs32+1 → ERs32
⎯ ⎯
0 ⎯
6
⎯ ⎯
0 ⎯
4
MOV.B @ERs+, Rd
B
MOV.B @aa:8, Rd
B
2
@aa:8 → Rd8
MOV.B @aa:16, Rd
B
4
@aa:16 → Rd8
⎯ ⎯
0 ⎯
6
MOV.B @aa:24, Rd
B
6
@aa:24 → Rd8
⎯ ⎯
0 ⎯
8
MOV.B Rs, @ERd
B
Rs8 → @ERd
⎯ ⎯
0 ⎯
4
MOV.B Rs, @(d:16,
ERd)
B
4
Rs8 → @(d:16, ERd)
⎯ ⎯
0 ⎯
6
MOV.B Rs, @(d:24,
ERd)
B
8
Rs8 → @(d:24, ERd)
⎯ ⎯
0 ⎯
10
MOV.B Rs, @–ERd
B
ERd32–1 → ERd32
Rs8 → @ERd
⎯ ⎯
0 ⎯
6
MOV.B Rs, @aa:8
B
2
Rs8 → @aa:8
⎯ ⎯
0 ⎯
4
MOV.B Rs, @aa:16
B
4
Rs8 → @aa:16
⎯ ⎯
0 ⎯
6
MOV.B Rs, @aa:24
B
6
Rs8 → @aa:24
⎯ ⎯
0 ⎯
8
MOV.W #xx:16, Rd
W 4
#xx:16 → Rd16
⎯ ⎯
0 ⎯
4
MOV.W Rs, Rd
W
Rs16 → Rd16
⎯ ⎯
0 ⎯
2
MOV.W @ERs, Rd
W
2
2
2
2
@ERs → Rd16
⎯ ⎯
0 ⎯
4
MOV.W @(d:16, ERs), W
Rd
4
@(d:16, ERs) → Rd16
⎯ ⎯
0 ⎯
6
MOV.W @(d:24, ERs), W
Rd
8
@(d:24, ERs) → Rd16
⎯ ⎯
0 ⎯
10
@ERs → Rd16
ERs32+2 → @ERd32
⎯ ⎯
0 ⎯
6
@aa:16 → Rd16
⎯ ⎯
0 ⎯
6
MOV.W @ERs+, Rd
W
MOV.W @aa:16, Rd
W
2
2
4
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Appendix A Instruction Set
W
8
Rs16 → @(d:24, ERd)
MOV.W Rs, @–ERd
W
MOV.W Rs, @aa:16
W
MOV.W Rs, @aa:24
W
MOV.L #xx:32, Rd
L
MOV.L ERs, ERd
L
MOV.L @ERs, ERd
L
MOV.L @(d:16, ERs),
ERd
L
MOV.L @(d:24, ERs),
ERd
L
MOV.L @ERs+, ERd
L
MOV.L @aa:16, ERd
L
MOV.L @aa:24, ERd
L
⎯
Operation
I
H N
Z
V
C
0 ⎯
8
⎯ ⎯
0 ⎯
4
⎯ ⎯
0 ⎯
6
⎯ ⎯
0 ⎯
10
ERd32–2 → ERd32
Rs16 → @ERd
⎯ ⎯
0 ⎯
6
4
Rs16 → @aa:16
⎯ ⎯
0 ⎯
6
6
Rs16 → @aa:24
⎯ ⎯
0 ⎯
8
#xx:32 → Rd32
⎯ ⎯
0 ⎯
6
6
2
2
6
@aa:24 → Rd16
⎯ ⎯
Normal
MOV.W Rs, @(d:24,
ERd)
@@aa
Rs16 → @(d:16, ERd)
@(d, PC)
4
@aa
Rs16 → @ERd
W
@(d, ERn)
W
MOV.W Rs, @(d:16,
ERd)
@ERn
MOV.W Rs, @ERd
Rn
W
#xx
Mnemonic
MOV.W @aa:24, Rd
Condition Code
Advanced
No. of
States*1
Operand Size
@–ERn/@ERn+
Addressing Mode and
Instruction Length (bytes)
ERs32 → ERd32
⎯ ⎯
0 ⎯
2
@ERs → ERd32
⎯ ⎯
0 ⎯
8
6
@(d:16, ERs) → ERd32 ⎯ ⎯
0 ⎯
10
10
@(d:24, ERs) → ERd32 ⎯ ⎯
0 ⎯
14
@ERs → ERd32
ERs32+4 → ERs32
⎯ ⎯
0 ⎯
10
6
@aa:16 → ERd32
⎯ —
0 ⎯
10
8
@aa:24 → ERd32
⎯ —
0 ⎯
12
ERs32 → @ERd
⎯ ⎯
0 ⎯
8
2
4
4
MOV.L ERs, @ERd
L
MOV.L ERs, @(d:16,
ERd)
L
6
ERs32 → @(d:16, ERd) ⎯ ⎯
0 ⎯
10
MOV.L ERs, @(d:24,
ERd)
L
10
ERs32 → @(d:24, ERd) ⎯ ⎯
0 ⎯
14
MOV.L ERs, @–ERd
L
ERd32–4 → ERd32
ERs32 → @ERd
⎯ ⎯
0 ⎯
10
MOV.L ERs, @aa:16
L
6
ERs32 → @aa:16
⎯ ⎯
0 ⎯
10
MOV.L ERs, @aa:24
L
8
⎯ ⎯
0 ⎯
12
POP.W Rn W
W
2 @SP → Rn16
SP+2 → SP
⎯ ⎯
0 ⎯
6
POP.L ERn L
L
4 @SP → ERn32
SP+4 → SP
⎯ ⎯
0 ⎯
10
4
4
Rev.5.00 Sep. 12, 2007 Page 610 of 764
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ERs32 → @aa:24
Appendix A Instruction Set
No. of
States*1
L
4 SP–4 → SP
ERn32 → @SP
⎯ ⎯
0 ⎯
10
MOVFPE @aa:16,
Rd
B
4
Cannot be used in the
H8/3006 and H8/3007
Cannot be used in the
H8/3006 and H8/3007
MOVTPE Rs,
@aa:16
B
4
Cannot be used in the
H8/3006 and H8/3007
Cannot be used in the
H8/3006 and H8/3007
Operation
I
H N
Z
V
C
Normal
⎯
Condition Code
Advanced
PUSH.L ERn
@@aa
6
@(d, PC)
0 ⎯
@aa
⎯ ⎯
@(d, ERn)
2 SP–2 → SP
Rn16 → @SP
@ERn
W
Rn
PUSH.W Rn
#xx
Mnemonic
Operand Size
@–ERn/@ERn+
Addressing Mode and
Instruction Length (bytes)
2. Arithmetic instructions
2
I
H N
Z
V
C
Normal
Operation
Advanced
No. of
States*1
Condition Code
⎯
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
2
@(d, ERn)
B
@ERn
#xx
ADD.B #xx:8, Rd
Rn
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
Rd8+#xx:8 → Rd8
⎯
2
Rd8+Rs8 → Rd8
⎯
2
Rd16+#xx:16 → Rd16
⎯ (1)
4
Rd16+Rs16 → Rd16
⎯ (1)
2
ERd32+#xx:32 →
ERd32
⎯ (2)
6
ERd32+ERs32 →
ERd32
⎯ (2)
2
Rd8+#xx:8 +C → Rd8
⎯
(3)
2
(3)
2
ADD.B Rs, Rd
B
ADD.W #xx:16, Rd
W 4
ADD.W Rs, Rd
W
ADD.L #xx:32, ERd
L
ADD.L ERs, ERd
L
ADDX.B #xx:8, Rd
B
ADDX.B Rs, Rd
B
2
Rd8+Rs8 +C → Rd8
⎯
ADDS.L #1, ERd
L
2
ERd32+1 → ERd32
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
ADDS.L #2, ERd
L
2
ERd32+2 → ERd32
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
ADDS.L #4, ERd
L
2
ERd32+4 → ERd32
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
INC.B Rd
B
2
Rd8+1 → Rd8
⎯ ⎯
⎯
2
INC.W #1, Rd
W
2
Rd16+1 → Rd16
⎯ ⎯
⎯
2
INC.W #2, Rd
W
2
Rd16+2 → Rd16
⎯ ⎯
⎯
2
2
6
2
2
Rev.5.00 Sep. 12, 2007 Page 611 of 764
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Appendix A Instruction Set
No. of
States*1
2
DAA Rd
B
2
Rd8 decimal adjust
→ Rd8
⎯ *
* ⎯
2
SUB.B Rs, Rd
B
2
Rd8–Rs8 → Rd8
⎯
2
Rd16–#xx:16 → Rd16
⎯ (1)
4
Rd16–Rs16 → Rd16
⎯ (1)
2
ERd32–#xx:32
→ ERd32
⎯ (2)
6
ERd32–ERs32
→ ERd32
⎯ (2)
2
Rd8–#xx:8–C → Rd8
⎯
(3)
2
(3)
2
SUB.W #xx:16, Rd
W 4
SUB.W Rs, Rd
W
2
I
H N
Z
V
C
Normal
⎯
Condition Code
Operation
Advanced
2
⎯
@@aa
⎯
⎯ ⎯
@(d, PC)
⎯ ⎯
ERd32+2 → ERd32
@aa
ERd32+1 → ERd32
2
@(d, ERn)
2
L
@ERn
L
INC.L #2, ERd
Rn
INC.L #1, ERd
#xx
Mnemonic
Operand Size
@–ERn/@ERn+
Addressing Mode and
Instruction Length (bytes)
SUB.L #xx:32, ERd
L
SUB.L ERs, ERd
L
SUBX.B #xx:8, Rd
B
SUBX.B Rs, Rd
B
2
Rd8–Rs8–C → Rd8
⎯
SUBS.L #1, ERd
L
2
ERd32–1 → ERd32
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
SUBS.L #2, ERd
L
2
ERd32–2 → ERd32
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
SUBS.L #4, ERd
L
2
ERd32–4 → ERd32
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
⎯
2
6
2
2
DEC.B Rd
B
2
Rd8–1 → Rd8
⎯ ⎯
DEC.W #1, Rd
W
2
Rd16–1 → Rd16
⎯ ⎯
⎯
2
DEC.W #2, Rd
W
2
Rd16–2 → Rd16
⎯ ⎯
⎯
2
DEC.L #1, ERd
L
2
ERd32–1 → ERd32
⎯ ⎯
⎯
2
DEC.L #2, ERd
L
2
ERd32–2 → ERd32
⎯ ⎯
⎯
2
DAS.Rd
B
2
Rd8 decimal adjust
→ Rd8
⎯ *
* ⎯
2
MULXU. B Rs, Rd
B
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Rd8 × Rs8 → Rd16
(unsigned multiplication)
14
MULXU. W Rs, ERd
W
2
Rd16 × Rs16 → ERd32 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
(unsigned multiplication)
MULXS. B Rs, Rd
B
4
Rd8 × Rs8 → Rd16
(signed multiplication)
⎯ ⎯
⎯ ⎯
16
MULXS. W Rs, ERd
W
4
Rd16 × Rs16 → ERd32
(signed multiplication)
⎯ ⎯
⎯ ⎯
24
DIVXU. B Rs, Rd
B
2
Rd16 ÷ Rs8 → Rd16
(RdH: remainder, RdL:
quotient)
(unsigned division)
⎯ ⎯ (6) (7) ⎯ ⎯
14
Rev.5.00 Sep. 12, 2007 Page 612 of 764
REJ09B0396-0500
22
Appendix A Instruction Set
No. of
States*1
4
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(signed division)
⎯ ⎯ (8) (7) ⎯ ⎯
16
DIVXS. W Rs, ERd
W
4
ERd32 ÷ Rs16 → ERd32 ⎯ ⎯ (8) (7) ⎯ ⎯
(Ed: remainder,
Rd: quotient)
(signed division)
24
CMP.B #xx:8, Rd
B
2
CMP.B Rs, Rd
B
CMP.W #xx:16, Rd
W 4
CMP.W Rs, Rd
W
CMP.L #xx:32, ERd
L
2
2
6
Operation
I
H N
Z
V
C
Normal
⎯
Condition Code
Advanced
B
@@aa
DIVXS. B Rs, Rd
@(d, PC)
22
@aa
ERd32 ÷ Rs16 → ERd32 ⎯ ⎯ (6) (7) ⎯ ⎯
(Ed: remainder,
Rd: quotient)
(unsigned division)
@(d, ERn)
2
@ERn
W
Rn
DIVXU. W Rs, ERd
#xx
Mnemonic
Operand Size
@–ERn/@ERn+
Addressing Mode and
Instruction Length (bytes)
Rd8–#xx:8
⎯
2
Rd8–Rs8
⎯
2
Rd16–#xx:16
⎯ (1)
4
Rd16–Rs16
⎯ (1)
2
ERd32–#xx:32
⎯ (2)
6
CMP.L ERs, ERd
L
2
ERd32–ERs32
⎯ (2)
2
NEG.B Rd
B
2
0–Rd8 → Rd8
⎯
2
NEG.W Rd
W
2
0–Rd16 → Rd16
⎯
2
NEG.L ERd
L
2
0–ERd32 → ERd32
⎯
2
EXTU.W Rd
W
2
0 → (<bits 15 to 8>
of Rd16)
⎯ ⎯ 0
0 ⎯
2
EXTU.L ERd
L
2
0 → (<bits 31 to 16>
of ERd32)
⎯ ⎯ 0
0 ⎯
2
EXTS.W Rd
W
2
⎯ ⎯
(<bit 7> of Rd16) →
(<bits 15 to 8> of Rd16)
0 ⎯
2
EXTS.L ERd
L
2
(<bit 15> of ERd32) →
(<bits 31 to 16> of
ERd32)
⎯ ⎯
0 ⎯
2
Rev.5.00 Sep. 12, 2007 Page 613 of 764
REJ09B0396-0500
Appendix A Instruction Set
3. Logic instructions
L
AND.L ERs, ERd
L
OR.B #xx:8, Rd
B
OR.B Rs, Rd
B
OR.W #xx:16, Rd
W 4
OR.W Rs, Rd
W
OR.L #xx:32, ERd
L
OR.L ERs, ERd
L
XOR.B #xx:8, Rd
B
XOR.B Rs, Rd
B
XOR.W #xx:16, Rd
W 4
XOR.W Rs, Rd
W
XOR.L #xx:32, ERd
L
XOR.L ERs, ERd
L
4
NOT.B Rd
B
2
¬ Rd8 → Rd8
NOT.W Rd
W
2
¬ Rd16 → Rd16
NOT.L ERd
L
2
¬ Rd32 → Rd32
⎯ ⎯
⎯
I
H N
Z
V
C
Advanced
AND.L #xx:32, ERd
Condition Code
Operation
Normal
W
@@aa
W 4
AND.W Rs, Rd
@(d, PC)
AND.W #xx:16, Rd
@aa
2
B
@(d, ERn)
B
AND.B Rs, Rd
@ERn
AND.B #xx:8, Rd
Rn
Mnemonic
#xx
No. of
States*1
Operand Size
@–ERn/@ERn+
Addressing Mode and
Instruction Length (bytes)
Rd8∧#xx:8 → Rd8
⎯ ⎯
0 ⎯
2
2
Rd8∧Rs8 → Rd8
⎯ ⎯
0 ⎯
2
Rd16∧#xx:16 → Rd16
⎯ ⎯
0 ⎯
4
2
Rd16∧Rs16 → Rd16
⎯ ⎯
0 ⎯
2
ERd32∧#xx:32 → ERd32 ⎯ ⎯
0 ⎯
6
ERd32∧ERs32 → ERd32 ⎯ ⎯
0 ⎯
4
6
4
2
2
2
6
4
2
2
2
6
Rev.5.00 Sep. 12, 2007 Page 614 of 764
REJ09B0396-0500
Rd8∨#xx:8 → Rd8
⎯ ⎯
0 ⎯
2
Rd8∨Rs8 → Rd8
⎯ ⎯
0 ⎯
2
Rd16∨#xx:16 → Rd16
⎯ ⎯
0 ⎯
4
Rd16∨Rs16 → Rd16
⎯ ⎯
0 ⎯
2
ERd32∨#xx:32 → ERd32 ⎯ ⎯
0 ⎯
6
ERd32∨ERs32 → ERd32 ⎯ ⎯
0 ⎯
4
Rd8⊕#xx:8 → Rd8
⎯ ⎯
0 ⎯
2
Rd8⊕Rs8 → Rd8
⎯ ⎯
0 ⎯
2
Rd16⊕#xx:16 → Rd16
⎯ ⎯
0 ⎯
4
Rd16⊕Rs16 → Rd16
⎯ ⎯
0 ⎯
2
ERd32⊕#xx:32 → ERd32 ⎯ ⎯
0 ⎯
6
ERd32⊕ERs32 → ERd32 ⎯ ⎯
0 ⎯
4
⎯ ⎯
0 ⎯
2
⎯ ⎯
0 ⎯
2
0 ⎯
2
Appendix A Instruction Set
4. Shift instructions
SHAL.B Rd
B
2
SHAL.W Rd
W
2
SHAL.L ERd
L
2
SHAR.B Rd
B
2
SHAR.W Rd
W
2
SHAR.L ERd
L
2
SHLL.B Rd
B
2
SHLL.W Rd
W
2
SHLL.L ERd
L
2
SHLR.B Rd
B
2
SHLR.W Rd
W
2
SHLR.L ERd
L
2
ROTXL.B Rd
B
2
ROTXL.W Rd
W
2
ROTXL.L ERd
L
2
ROTXR.B Rd
B
2
ROTXR.W Rd
W
2
ROTXR.L ERd
L
2
ROTL.B Rd
B
2
ROTL.W Rd
W
2
ROTL.L ERd
L
2
ROTR.B Rd
B
2
ROTR.W Rd
W
2
ROTR.L ERd
L
2
I
C
0
MSB
LSB
LSB
C
0
MSB
LSB
0
C
MSB
LSB
C
MSB
LSB
C
MSB
LSB
C
MSB
LSB
C
MSB
LSB
Z
V
C
⎯ ⎯
2
⎯ ⎯
2
⎯ ⎯
C
MSB
H N
Normal
Operation
Advanced
No. of
States*1
Condition Code
⎯
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
⎯ ⎯
0
2
Rev.5.00 Sep. 12, 2007 Page 615 of 764
REJ09B0396-0500
Appendix A Instruction Set
5. Bit manipulation instructions
B
BCLR #xx:3, @ERd
B
BCLR #xx:3, @aa:8
B
BCLR Rn, Rd
B
BCLR Rn, @ERd
B
BCLR Rn, @aa:8
B
BNOT #xx:3, Rd
B
BNOT #xx:3, @ERd
B
BNOT #xx:3, @aa:8
B
BNOT Rn, Rd
B
BNOT Rn, @ERd
B
BNOT Rn, @aa:8
B
BTST #xx:3, Rd
B
BTST #xx:3, @ERd
B
BTST #xx:3, @aa:8
B
BTST Rn, Rd
B
BTST Rn, @ERd
B
BTST Rn, @aa:8
B
BLD #xx:3, Rd
B
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
Rev.5.00 Sep. 12, 2007 Page 616 of 764
REJ09B0396-0500
I
H N
Z
V
C
Advanced
BCLR #xx:3, Rd
4
Operation
Normal
B
4
2
No. of
States*1
Condition Code
⎯
B
BSET Rn, @aa:8
4
@@aa
BSET Rn, @ERd
2
@(d, PC)
B
@aa
B
BSET Rn, Rd
@–ERn/@ERn+
BSET #xx:3, @aa:8
@(d, ERn)
B
@ERn
B
BSET #xx:3, @ERd
Rn
BSET #xx:3, Rd
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
(#xx:3 of Rd8) ← 1
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
(#xx:3 of @ERd) ← 1
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
(#xx:3 of @aa:8) ← 1
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
(Rn8 of Rd8) ← 1
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
(Rn8 of @ERd) ← 1
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
(Rn8 of @aa:8) ← 1
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
(#xx:3 of Rd8) ← 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
(#xx:3 of @ERd) ← 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
(#xx:3 of @aa:8) ← 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
(Rn8 of Rd8) ← 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
(Rn8 of @ERd) ← 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
(Rn8 of @aa:8) ← 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
(#xx:3 of Rd8) ←
¬ (#xx:3 of Rd8)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
(#xx:3 of @ERd) ←
¬ (#xx:3 of @ERd)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
(#xx:3 of @aa:8) ←
¬ (#xx:3 of @aa:8)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
(Rn8 of Rd8) ←
¬ (Rn8 of Rd8)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
(Rn8 of @ERd) ←
¬ (Rn8 of @ERd)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
(Rn8 of @aa:8) ←
¬ (Rn8 of @aa:8)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
¬ (#xx:3 of Rd8) → Z
⎯ ⎯ ⎯
⎯ ⎯
2
¬ (#xx:3 of @ERd) → Z
⎯ ⎯ ⎯
⎯ ⎯
6
¬ (#xx:3 of @aa:8) → Z
⎯ ⎯ ⎯
⎯ ⎯
6
¬ (Rn8 of @Rd8) → Z
⎯ ⎯ ⎯
⎯ ⎯
2
¬ (Rn8 of @ERd) → Z
⎯ ⎯ ⎯
⎯ ⎯
6
¬ (Rn8 of @aa:8) → Z
⎯ ⎯ ⎯
⎯ ⎯
6
(#xx:3 of Rd8) → C
⎯ ⎯ ⎯ ⎯ ⎯
2
Appendix A Instruction Set
B
BST #xx:3, @aa:8
B
BIST #xx:3, Rd
B
BIST #xx:3, @ERd
B
BIST #xx:3, @aa:8
B
BAND #xx:3, Rd
B
BAND #xx:3, @ERd
B
BAND #xx:3, @aa:8
B
BIAND #xx:3, Rd
B
2
4
4
2
4
4
2
4
4
2
BIAND #xx:3, @ERd B
4
BIAND #xx:3, @aa:8 B
BOR #xx:3, Rd
B
BOR #xx:3, @ERd
B
BOR #xx:3, @aa:8
B
BIOR #xx:3, Rd
B
BIOR #xx:3, @ERd
B
BIOR #xx:3, @aa:8
B
BXOR #xx:3, Rd
B
BXOR #xx:3, @ERd
B
BXOR #xx:3, @aa:8
B
BIXOR #xx:3, Rd
B
BIXOR #xx:3, @ERd B
BIXOR #xx:3, @aa:8 B
4
2
4
4
2
4
4
2
4
4
2
4
4
I
H N
Z
V
C
Advanced
B
BST #xx:3, @ERd
4
Operation
Normal
BST #xx:3, Rd
4
No. of
States*1
Condition Code
⎯
B
4
2
@@aa
B
BILD #xx:3, @aa:8
4
@(d, PC)
BILD #xx:3, @ERd
@aa
B
@–ERn/@ERn+
B
BILD #xx:3, Rd
@(d, ERn)
BLD #xx:3, @aa:8
@ERn
B
Rn
BLD #xx:3, @ERd
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
(#xx:3 of @ERd) → C
⎯ ⎯ ⎯ ⎯ ⎯
6
(#xx:3 of @aa:8) → C
⎯ ⎯ ⎯ ⎯ ⎯
6
¬(#xx:3 of Rd8) → C
⎯ ⎯ ⎯ ⎯ ⎯
2
¬(#xx:3 of @ERd) → C
⎯ ⎯ ⎯ ⎯ ⎯
6
¬(#xx:3 of @aa:8) → C
⎯ ⎯ ⎯ ⎯ ⎯
6
C → (#xx:3 of Rd8)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
C → (#xx:3 of @ERd24)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
C → (#xx:3 of @aa:8)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
¬C → (#xx:3 of Rd8)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
¬C → (#xx:3 of @ERd24)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
¬C → (#xx:3 of @aa:8)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
C∧(#xx:3 of Rd8) → C
⎯ ⎯ ⎯ ⎯ ⎯
2
C∧(#xx:3 of @ERd24) → C
⎯ ⎯ ⎯ ⎯ ⎯
6
C∧(#xx:3 of @aa:8) → C
⎯ ⎯ ⎯ ⎯ ⎯
6
C∧¬(#xx:3 of Rd8) → C
⎯ ⎯ ⎯ ⎯ ⎯
2
C∧¬(#xx:3 of @ERd24) → C ⎯ ⎯ ⎯ ⎯ ⎯
6
C∧¬(#xx:3 of @aa:8) → C
⎯ ⎯ ⎯ ⎯ ⎯
6
C∨(#xx:3 of Rd8) → C
⎯ ⎯ ⎯ ⎯ ⎯
2
C∨(#xx:3 of @ERd24) → C
⎯ ⎯ ⎯ ⎯ ⎯
6
C∨(#xx:3 of @aa:8) → C
⎯ ⎯ ⎯ ⎯ ⎯
6
C∨¬(#xx:3 of Rd8) → C
⎯ ⎯ ⎯ ⎯ ⎯
2
C∨¬(#xx:3 of @ERd24) → C ⎯ ⎯ ⎯ ⎯ ⎯
6
C∨¬(#xx:3 of @aa:8) → C
⎯ ⎯ ⎯ ⎯ ⎯
6
C⊕(#xx:3 of Rd8) → C
⎯ ⎯ ⎯ ⎯ ⎯
2
C⊕(#xx:3 of @ERd24) → C
⎯ ⎯ ⎯ ⎯ ⎯
6
C⊕(#xx:3 of @aa:8) → C
⎯ ⎯ ⎯ ⎯ ⎯
6
C⊕¬(#xx:3 of Rd8) → C
⎯ ⎯ ⎯ ⎯ ⎯
2
C⊕¬(#xx:3 of @ERd24) → C ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯
6
C⊕¬(#xx:3 of @aa:8) → C
Rev.5.00 Sep. 12, 2007 Page 617 of 764
REJ09B0396-0500
Appendix A Instruction Set
6. Branching instructions
⎯
2
BHI d:16
⎯
4
BLS d:8
⎯
2
BLS d:16
⎯
4
BCC d:8 (BHS d:8)
⎯
2
BCC d:16 (BHS d:16) ⎯
4
⎯
2
BCS d:16 (BLO d:16) ⎯
4
BNE d:8
⎯
2
BNE d:16
⎯
4
BEQ d:8
⎯
2
BEQ d:16
⎯
4
BVC d:8
⎯
2
BVC d:16
⎯
4
BVS d:8
⎯
2
BVS d:16
⎯
4
BPL d:8
⎯
2
BPL d:16
⎯
4
BMI d:8
⎯
2
BMI d:16
⎯
4
BGE d:8
⎯
2
BGE d:16
⎯
4
BLT d:8
⎯
2
BLT d:16
⎯
4
BGT d:8
⎯
2
BGT d:16
⎯
4
BCS d:8 (BLO d:8)
Rev.5.00 Sep. 12, 2007 Page 618 of 764
REJ09B0396-0500
Branch
Operation Condition
If condition Always
is true then
PC ←
PC+d else Never
next;
C∨Z=0
C∨Z=1
C=0
C=1
Z=0
Z=1
V=0
V=1
N=0
N=1
N⊕V = 0
N⊕V = 1
Z ∨ (N⊕V)
=0
Condition Code
I
H N
Z
V
C
Advanced
BHI d:8
No. of
States*1
Normal
4
⎯
2
⎯
@@aa
⎯
BRN d:16 (BF d:16)
@(d, PC)
BRN d:8 (BF d:8)
@aa
4
@(d, ERn)
2
⎯
@ERn
⎯
BRA d:16 (BT d:16)
Rn
BRA d:8 (BT d:8)
#xx
Mnemonic
Operand Size
@–ERn/@ERn+
Addressing Mode and
Instruction Length (bytes)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
Appendix A Instruction Set
JMP @@aa:8
⎯
BSR d:8
⎯
2
BSR d:16
⎯
4
JSR @ERn
⎯
JSR @aa:24
⎯
JSR @@aa:8
⎯
RTS
⎯
2
4
2
2
4
2
Condition Code
I
H N
Z
V
C
Advanced
⎯
Branch
Operation Condition
Normal
⎯
JMP @aa:24
No. of
States*1
⎯
JMP @ERn
@@aa
4
@(d, PC)
⎯
@aa
BLE d:16
@(d, ERn)
2
@ERn
⎯
Rn
BLE d:8
#xx
Mnemonic
Operand Size
@–ERn/@ERn+
Addressing Mode and
Instruction Length (bytes)
If condition Z ∨ (N⊕V) = 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
is true then
Z ∨ (N⊕V) = 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
PC ←
PC+d else
next;
4
PC ← ERn
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
4
PC ← aa:24
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
PC ← @aa:8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
10
PC → @–SP
PC ← PC+d:8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
8
PC → @–SP
PC ← PC+d:16
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
10
PC → @–SP
PC ← @ERn
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
8
PC → @–SP
PC ← @aa:24
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
10
PC → @–SP
PC ← @aa:8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
12
2 PC ← @SP+
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
10
6
Rev.5.00 Sep. 12, 2007 Page 619 of 764
REJ09B0396-0500
Appendix A Instruction Set
7. System control instructions
No. of
States*1
SLEEP
⎯
Transition to powerdown ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
state
2
LDC #xx:8, CCR
B
#xx:8 → CCR
2
Rs8 → CCR
2
@ERs → CCR
6
2
I
H N
Z
V
C
Normal
⎯
Condition Code
Operation
Advanced
10
@@aa
CCR ← @SP+
PC ← @SP+
@(d, PC)
⎯
@aa
RTE
@(d, ERn)
2 PC → @–SP
CCR → @–SP
<vector> → PC
@ERn
⎯
Rn
TRAPA #x:2
#xx
Mnemonic
Operand Size
@–ERn/@ERn+
Addressing Mode and
Instruction Length (bytes)
1 ⎯ ⎯ ⎯ ⎯ ⎯ 14 16
LDC Rs, CCR
B
LDC @ERs, CCR
W
LDC @(d:16, ERs),
CCR
W
6
@(d:16, ERs) → CCR
8
LDC @(d:24, ERs),
CCR
W
10
@(d:24, ERs) → CCR
12
LDC @ERs+, CCR
W
@ERs → CCR
ERs32+2 → ERs32
8
LDC @aa:16, CCR
W
6
@aa:16 → CCR
8
LDC @aa:24, CCR
W
8
@aa:24 → CCR
10
2
4
4
CCR → Rd8
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
CCR → @ERd
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
6
6
CCR → @(d:16, ERd)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
10
CCR → @(d:24, ERd)
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
12
ERd32–2 → ERd32
CCR → @ERd
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
6
CCR → @aa:16
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8
8
CCR → @aa:24
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
10
STC CCR, Rd
B
STC CCR, @ERd
W
STC CCR, @(d:16,
ERd)
W
STC CCR, @(d:24,
ERd)
W
STC CCR, @–ERd
W
STC CCR, @aa:16
W
STC CCR, @aa:24
W
ANDC #xx:8, CCR
B
2
CCR∧#xx:8 → CCR
2
ORC #xx:8, CCR
B
2
CCR∨#xx:8 → CCR
2
XORC #xx:8, CCR
B
2
NOP
⎯
2
4
4
Rev.5.00 Sep. 12, 2007 Page 620 of 764
REJ09B0396-0500
CCR⊕#xx:8 → CCR
2 PC ← PC+2
2
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2
Appendix A Instruction Set
8. Block transfer instructions
Operation
I
H N
Z
V
C
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Normal
Condition Code
⎯
@@aa
4 if R4 ≠ 0
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4–1 → R4
until
R4=0
else next;
@(d, PC)
⎯
@aa
EEPMOV. W
@(d, ERn)
4 if R4L ≠ 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8+
repeat @R5 → @R6
4n*2
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
until
R4L=0
else next;
@ERn
⎯
Rn
EEPMOV. B
#xx
Mnemonic
Advanced
No. of
States*1
Operand Size
@–ERn/@ERn+
Addressing Mode and
Instruction Length (bytes)
8+
4n*2
Notes: 1. The number of states is the number of states required for execution when the
instruction and its operands are located in on-chip memory. For other cases see
appendix A.3, Number of States Required for Execution. Normal mode is not available
in the H8/3006 and H8/3007.
2. n is the value set in register R4L or R4.
(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
(3) Retains its previous value when the result is zero; otherwise cleared to 0.
(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous
value.
(5) The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
(6) Set to 1 when the divisor is negative; otherwise cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cleared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Rev.5.00 Sep. 12, 2007 Page 621 of 764
REJ09B0396-0500
Rev.5.00 Sep. 12, 2007 Page 622 of 764
REJ09B0396-0500
MULXU
5
STC
LDC
3
SUBX
OR
XOR
AND
MOV
C
D
E
F
BILD
BIST
BLD
BST
TRAPA
BNQ
B
BIAND
BAND
AND
RTE
BNE
CMP
BIXOR
BXOR
XOR
BSR
BCS
A
BIOR
BOR
OR
RTS
BCC
MOV.B
Table A.2
(2)
LDC
7
ADDX
BTST
DIVXU
BLS
AND.B
ANDC
6
9
BCLR
MULXU
BHI
XOR.B
XORC
5
ADD
BNOT
DIVXU
BRN
OR.B
ORC
4
8
7
BSET
BRA
6
2
1
Table A.2
(2)
Table A.2 Table A.2 Table A.2 Table A.2
(2)
(2)
(2)
(2)
NOP
4
3
2
1
0
0
MOV
BVS
9
A
B
JMP
BPL
BMI
MOV
Table A.2 Table A.2
(2)
(2)
Table A.2 Table A.2
(2)
(2)
Table A.2 Table A.2
EEPMOV
(2)
(2)
SUB
ADD
Table A.2
(2)
BVC
8
BSR
BGE
C
CMP
MOV
Instruction when most significant bit of BH is 1.
Instruction when most significant bit of BH is 0.
E
JSR
BGT
SUBX
ADDX
Table A.2
(3)
BLT
D
F
BLE
Table A.2
(2)
Table A.2
(2)
Table A.2
AL
1st byte 2nd byte
AH AL BH BL
A.2
AH
Instruction code:
Appendix A Instruction Set
Operation Code Maps
Operation Code Map (1)
SUBS
DAS
BRA
MOV
MOV
1B
1F
58
79
7A
1
ADD
ADD
BRN
NOT
17
DEC
ROTXR
13
1A
ROTXL
12
DAA
0F
SHLR
ADDS
0B
11
INC
0A
SHLL
MOV
01
10
0
CMP
CMP
BHI
2
SUB
SUB
BLS
NOT
ROTXR
ROTXL
SHLR
SHLL
3
4
OR
OR
BCC
LDC/STC
1st byte 2nd byte
AH AL BH BL
XOR
XOR
BCS
DEC
EXTU
INC
5
AND
AND
BNE
6
BEQ
DEC
EXTU
INC
7
BVC
SUBS
NEG
9
BVS
ROTR
ROTL
SHAR
SHAL
ADDS
SLEEP
8
BPL
A
MOV
BMI
SUB
CMP
NEG
ROTR
ROTL
SHAR
C
D
BGE
BLT
DEC
EXTS
INC
Table A.2 Table A.2
(3)
(3)
ADD
SHAL
B
BGT
E
BLE
DEC
EXTS
INC
Table A.2
(3)
F
Table A.2
BH
AH AL
Instruction code:
Appendix A Instruction Set
Operation Code Map (2)
Rev.5.00 Sep. 12, 2007 Page 623 of 764
REJ09B0396-0500
Rev.5.00 Sep. 12, 2007 Page 624 of 764
REJ09B0396-0500
DIVXS
3
BSET
7Faa7 * 2
BNOT
BNOT
BCLR
BCLR
Notes: 1. r is the register designation field.
2. aa is the absolute address field.
BSET
7Faa6 * 2
BTST
BCLR
7Eaa7 * 2
BNOT
BTST
BSET
7Dr07 * 1
7Eaa6 * 2
BSET
7Dr06 * 1
BTST
BCLR
MULXS
2
7Cr07 * 1
BNOT
DIVIXS
1
BTST
MULXS
0
7Cr06 * 1
01F06
01D05
01C05
01406
CL
BIOR
BOR
BIOR
BOR
OR
4
BIXOR
BXOR
BIXOR
BXOR
XOR
5
BIAND
BAND
BIAND
BAND
AND
6
7
BIST
BILD
BST
BLD
BIST
BILD
BST
BLD
1st byte 2nd byte 3rd byte 4th byte
AH AL BH BL CH CL DH DL
8
LDC
STC
9
A
LDC
STC
B
C
LDC
STC
D
E
LDC
STC
F
Instruction when most significant bit of DH is 1.
Instruction when most significant bit of DH is 0.
Table A.2
AH
ALBH
BLCH
Instruction code:
Appendix A Instruction Set
Operation Code Map (3)
Appendix A Instruction Set
A.3
Number of States Required for Execution
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data
read/write, and other cycles occurring in each instruction. Table A.3 indicates the number of states
required per cycle according to the bus size. The number of states required for execution of an
instruction can be calculated from these two tables as follows:
Number of states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples of Calculation of Number of States Required for Execution
Examples: Advanced mode, stack located in external address space, on-chip supporting modules
accessed with 8-bit bus width, external devices accessed in three states with one wait state and
16-bit bus width.
BSET #0, @FFFFC7:8
From table A.4, I = L = 2 and J = K = M = N = 0
From table A.3, SI = 4 and SL = 3
Number of states = 2 × 4 + 2 × 3 = 14
JSR @@30
From table A.4, I = J = K = 2 and L = M = N = 0
From table A.3, SI = SJ = SK = 4
Number of states = 2 × 4 + 2 × 4 + 2 × 4 = 24
Rev.5.00 Sep. 12, 2007 Page 625 of 764
REJ09B0396-0500
Appendix A Instruction Set
Table A.3
Number of States per Cycle
Access Conditions
On-Chip
Supporting
Module
Cycle
Instruction fetch
SI
External Device
8-Bit Bus
16-Bit Bus
On-Chip 8-Bit
Memory Bus
16-Bit
Bus
2-State
Access
3-State
Access
2-State
Access
3-State
Access
2
3
4
6 + 2m
2
3+m
6
Branch address read SJ
Stack operation
SK
Byte data access
SL
3
2
3+m
Word data access
SM
6
4
6 + 2m
Internal operation
SN 1
Legend:
m: Number of wait states inserted into external device access
Rev.5.00 Sep. 12, 2007 Page 626 of 764
REJ09B0396-0500
Appendix A Instruction Set
Table A.4
Number of Cycles per Instruction
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
ADD
ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W #xx:16, Rd
ADD.W Rs, Rd
ADD.L #xx:32, ERd
ADD.L ERs, ERd
1
1
2
1
3
1
ADDS
ADDS #1/2/4, ERd
1
ADDX
ADDX #xx:8, Rd
ADDX Rs, Rd
1
1
AND
AND.B #xx:8, Rd
AND.B Rs, Rd
AND.W #xx:16, Rd
AND.W Rs, Rd
AND.L #xx:32, ERd
AND.L ERs, ERd
1
1
2
1
3
2
ANDC
ANDC #xx:8, CCR
1
BAND
BAND #xx:3, Rd
BAND #xx:3, @
BAND #xx:3, @aa:8
1
2
2
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Bcc
1
1
Rev.5.00 Sep. 12, 2007 Page 627 of 764
REJ09B0396-0500
Appendix A Instruction Set
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Bcc
BRA d:16 (BT d:16)
BRN d:16 (BF d:16)
BHI d:16
BLS d:16
BCC d:16 (BHS d:16)
BCS d:16 (BLO d:16)
BNE d:16
BEQ d:16
BVC d:16
BVS d:16
BPL d:16
BMI d:16
BGE d:16
BLT d:16
BGT d:16
BLE d:16
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BCLR
BCLR #xx:3, Rd
BCLR #xx:3, @ERd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @ERd
BCLR Rn, @aa:8
1
2
2
1
2
2
BIAND #xx:3,
BIAND #xx:3, @ERd
BIAND #xx:3, @aa:8
1
2
2
1
1
BILD #xx:3, Rd
BILD #xx:3, @ERd
BILD #xx:3, @aa:8
1
2
2
1
1
BIOR #xx:8, Rd
BIOR #xx:8, @
BIOR #xx:8, @aa:8
1
2
2
1
1
BIST #xx:3, Rd
BIST #xx:3, @ERd
BIST #xx:3, @aa:8
1
2
2
2
2
BIXOR #xx:3, Rd
BIXOR #xx:3, @
BIXOR #xx:3, @aa:8
1
2
2
1
1
BLD #xx:3, Rd
BLD #xx:3, @ERd
BLD #xx:3, @aa:8
1
2
2
1
1
BIAND
BILD
BIOR
BIST
BIXOR
BLD
Rev.5.00 Sep. 12, 2007 Page 628 of 764
REJ09B0396-0500
2
2
2
2
Appendix A Instruction Set
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
Instruction Mnemonic
BNOT
BOR
BSET
BSR
BNOT #xx:3,
BNOT #xx:3, @ERd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @ERd
BNOT Rn, @aa:8
1
2
2
1
2
2
BOR #xx:3, Rd
BOR #xx:3, @ERd
BOR #xx:3, @aa:8
1
2
2
BSET #xx:3, Rd
BSET #xx:3, @ERd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @ERd
BSET Rn, @aa:8
1
2
2
1
2
2
BSR d:8
BSR d:16
BST
Normal*1
1
1
2
2
2
2
1
Advanced 2
2
Normal*
1
2
1
2
Advanced 2
2
2
1
2
2
BTST #xx:3, Rd
BTST #xx:3, @ERd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @ERd
BTST Rn, @aa:8
1
2
2
1
2
2
BXOR #xx:3, Rd
BXOR #xx:3, @ERd
BXOR #xx:3, @aa:8
1
2
2
CMP
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
1
1
2
1
3
1
DAA
DAA Rd
1
DAS
DAS Rd
1
BXOR
2
2
2
BST #xx:3, Rd
BST #xx:3, @ERd
BST #xx:3, @aa:8
BTST
2
2
2
2
1
1
1
1
1
1
Rev.5.00 Sep. 12, 2007 Page 629 of 764
REJ09B0396-0500
Appendix A Instruction Set
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
Instruction Mnemonic
DEC
DEC.B Rd
DEC.W #1/2, Rd
DEC.L #1/2, ERd
1
1
1
DIVXS
DIVXS.B Rs, Rd
DIVXS.W Rs, ERd
2
2
12
20
DIVXU
DIVXU.B Rs, Rd
DIVXU.W Rs, ERd
1
1
12
20
EEPMOV
EEPMOV.B
EEPMOV.W
2
2
EXTS
EXTS.W Rd
EXTS.L ERd
1
1
EXTU
EXTU.W Rd
EXTU.L ERd
1
1
INC
INC.B Rd
INC.W #1/2, Rd
INC.L #1/2, ERd
1
1
JMP
JMP @ERn
2
JMP @aa:24
2
1
JSR
2n + 2*2
2n + 2*2
2
JMP @@aa:8 Normal* 2
1
2
Advanced 2
2
2
JSR @ERn
JSR @aa:24
1
Normal* 2
1
Advanced 2
2
1
Normal* 2
Advanced 2
LDC
1
2
2
2
JSR @@aa:8 Normal*1 2
1
1
Advanced 2
2
2
1
LDC #xx:8, CCR
1
LDC Rs, CCR
2
LDC @ERs, CCR
LDC @(d:16, ERs), CCR 3
LDC @(d:24, ERs), CCR 5
2
LDC @ERs+, CCR
3
LDC @aa:16, CCR
4
LDC @aa:24, CCR
Rev.5.00 Sep. 12, 2007 Page 630 of 764
REJ09B0396-0500
1
1
1
1
1
1
2
Appendix A Instruction Set
Instruction Mnemonic
MOV
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
MOV.B #xx:8, Rd
1
MOV.B Rs, Rd
1
MOV.B @ERs, Rd
1
MOV.B @(d:16, ERs), Rd 2
MOV.B @(d:24, ERs), Rd 4
MOV.B @ERs+, Rd
1
MOV.B @aa:8, Rd
1
MOV.B @aa:16, Rd
2
MOV.B @aa:24, Rd
3
MOV.B Rs, @ERd
1
MOV.B Rs, @(d:16, ERd) 2
MOV.B Rs, @(d:24, ERd) 4
MOV.B Rs, @–ERd
1
MOV.B Rs, @aa:8
1
MOV.B Rs, @aa:16
2
MOV.B Rs, @aa:24
3
MOV.W #xx:16, Rd
2
MOV.W Rs, Rd
1
MOV.W @ERs, Rd
1
MOV.W @(d:16, ERs), Rd 2
MOV.W @(d:24, ERs), Rd 4
MOV.W @ERs+, Rd
1
MOV.W @aa:16, Rd
2
MOV.W @aa:24, Rd
3
MOV.W Rs, @ERd
1
MOV.W Rs, @(d:16, ERd) 2
MOV.W Rs, @(d:24, ERd) 4
MOV.W Rs, @–ERd
1
MOV.W Rs, @aa:16
2
MOV.W Rs, @aa:24
3
MOV.L #xx:32, ERd
3
MOV.L ERs, ERd
1
MOV.L @ERs, ERd
2
MOV.L @(d:16, ERs), ERd 3
MOV.L @(d:24, ERs), ERd 5
MOV.L @ERs+, ERd
2
MOV.L @aa:16, ERd
3
MOV.L @aa:24, ERd
4
MOV.L ERs, @ERd
2
MOV.L ERs, @(d:16, ERd) 3
MOV.L ERs, @(d:24, ERd) 5
MOV.L ERs, @–ERd
2
MOV.L ERs, @aa:16
3
MOV.L ERs, @aa:24
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Rev.5.00 Sep. 12, 2007 Page 631 of 764
REJ09B0396-0500
Appendix A Instruction Set
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
MOVFPE
MOVFPE @aa:16, Rd*12
1
MOVTPE
MOVTPE Rs, @aa:16*1 2
1
MULXS
MULXS.B Rs, Rd
MULXS.W Rs, ERd
2
2
12
20
MULXU
MULXU.B Rs, Rd
MULXU.W Rs, ERd
1
1
12
20
NEG
NEG.B Rd
NEG.W Rd
NEG.L ERd
1
1
1
NOP
NOP
1
NOT
NOT.B Rd
NOT.W Rd
NOT.L ERd
1
1
1
OR
OR.B #xx:8, Rd
OR.B Rs, Rd
OR.W #xx:16, Rd
OR.W Rs, Rd
OR.L #xx:32, ERd
OR.L ERs, ERd
1
1
2
1
3
2
ORC
ORC #xx:8, CCR
1
POP
POP.W Rn
POP.L ERn
1
2
1
2
2
2
PUSH
PUSH.W Rn
PUSH.L ERn
1
2
1
2
2
2
ROTL
ROTL.B Rd
ROTL.W Rd
ROTL.L ERd
1
1
1
ROTR
ROTR.B Rd
ROTR.W Rd
ROTR.L ERd
1
1
1
ROTXL
ROTXL.B Rd
ROTXL.W Rd
ROTXL.L ERd
1
1
1
ROTXR
ROTXR.B Rd
ROTXR.W Rd
ROTXR.L ERd
1
1
1
RTE
RTE
2
Rev.5.00 Sep. 12, 2007 Page 632 of 764
REJ09B0396-0500
2
2
Appendix A Instruction Set
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
Instruction Mnemonic
RTS
RTS
Normal*1 2
1
2
Advanced 2
2
2
SHAL
SHAL.B Rd
SHAL.W Rd
SHAL.L ERd
1
1
1
SHAR
SHAR.B Rd
SHAR.W Rd
SHAR.L ERd
1
1
1
SHLL
SHLL.B Rd
SHLL.W Rd
SHLL.L ERd
1
1
1
SHLR
SHLR.B Rd
SHLR.W Rd
SHLR.L ERd
1
1
1
SLEEP
SLEEP
1
STC
1
STC CCR, Rd
2
STC CCR, @ERd
STC CCR, @(d:16, ERd) 3
STC CCR, @(d:24, ERd) 5
2
STC CCR, @–ERd
3
STC CCR, @aa:16
4
STC CCR, @aa:24
1
1
1
1
1
1
2
SUB
SUB.B Rs, Rd
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
1
2
1
3
1
SUBS
SUBS #1/2/4, ERd
1
SUBX
SUBX #xx:8, Rd
SUBX Rs, Rd
1
1
TRAPA
TRAPA #x:2 Normal*1 2
1
2
4
Advanced 2
2
2
4
XOR
XOR.B #xx:8, Rd
XOR.B Rs, Rd
XOR.W #xx:16, Rd
XOR.W Rs, Rd
XOR.L #xx:32, ERd
XOR.L ERs, ERd
1
1
2
1
3
2
XORC
XORC #xx:8, CCR
1
Notes: 1. Not available in the H8/3006 and H8/3007.
2. n is the value set in register R4L or R4. The source and destination are accessed n + 1
times each.
Rev.5.00 Sep. 12, 2007 Page 633 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
Appendix B Internal I/O Registers
B.1
Addresses
Address
(Low)
Data
Register Bus
Width Bit 7
Name
H'EE000
Reserved area (access prohibited)
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
name
P41DDR
P40DDR
Port 4
Port 6
H'EE001
H'EE002
H'EE003
P4DDR
8
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR
H'EE004
Reserved area (access prohibited)
⎯
P66DDR P65DDR P64DDR P63DDR P62DDR
P61DDR
P60DDR
⎯
⎯
⎯
⎯
8
⎯
8
⎯
PADDR
8
H'EE00A
PBDDR
8
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR
H'EE00B
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE00C
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE00D
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE00E
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE00F
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE010
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE011
MDCR
8
⎯
⎯
⎯
⎯
⎯
MDS2
MDS1
MDS0
H'EE012
SYSCR
8
SSBY
STS2
STS1
STS0
UE
NMIEG
SSOE
RAME
H'EE013
BRCR
8
A23E
A22E
A21E
A20E
⎯
⎯
⎯
BRLE
Bus controller
H'EE014
ISCR
8
⎯
⎯
IRQ5SC IRQ4SC IRQ3SC IRQ2SC
IRQ1SC
IRQ0SC
H'EE015
IER
8
⎯
⎯
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
Interrupt
controller
H'EE016
ISR
8
⎯
⎯
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
H'EE017
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE018
IPRA
8
IPRA7
IPRA6
IPRA5
IPRA4
IPRA3
IPRA2
IPRA1
IPRA0
H'EE019
IPRB
8
IPRB7
IPRB6
IPRB5
⎯
IPRB3
IPRB2
IPRB1
⎯
H'EE01A
DASTCR 8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DASTE
D/A converter
H'EE01B
DIVCR
⎯
⎯
⎯
⎯
⎯
⎯
DIV1
DIV0
⎯
⎯
⎯
⎯
MSTPH2 MSTPH1 MSTPH0
System
control
H'EE005
P6DDR
H'EE006
⎯
H'EE007
P8DDR
H'EE008
P9DDR
H'EE009
8
8
⎯
⎯
⎯
⎯
⎯
⎯
P84DDR P83DDR P82DDR
P81DDR
P80DDR
⎯
P95DDR P94DDR P93DDR P92DDR
P91DDR
P90DDR
Port 9
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR
PA1DDR
PA0DDR
Port A
PB1DDR
PB0DDR
Port B
⎯
⎯
H'EE01C
MSTCRH 8
PSTOP
H'EE01D
MSTCRL 8
MSTPL7 ⎯
MSTPL5 MSTPL4 MSTPL3 MSTPL2 ⎯
MSTPL0
H'EE01E
⎯
⎯
⎯
⎯
⎯
Rev.5.00 Sep. 12, 2007 Page 634 of 764
REJ09B0396-0500
⎯
⎯
⎯
⎯
Port 8
System
control
Appendix B Internal I/O Registers
Address
(Low)
Data
Register Bus
Name
Width Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
name
H'EE01F
CSCR
CS6E
CS5E
CS4E
⎯
⎯
⎯
⎯
Bus controller
8
CS7E
Register Name
H'EE020
ABWCR
8
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
H'EE021
ASTCR
8
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
H'EE022
WCRH
8
W71
W70
W61
W60
W51
W50
W41
W40
H'EE023
WCRL
8
W31
W30
W21
W20
W11
W10
W01
W00
H'EE024
BCR
8
ICIS1
ICIS0
BROME BRSTS1 BRSTS0 ⎯
RDEA
WAITE
H'EE025
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE026
DRCRA
8
DRAS2
DRAS1
DRAS0
⎯
BE
RDM
SRFMD
RFSHE
H'EE027
DRCRB
8
MXC1
MXC0
CSEL
RCYCE ⎯
TPC
RCW
RLW
CMF
CMIE
CKS2
CKS1
CKS0
⎯
⎯
⎯
H'EE028
RTMCSR 8
H'EE029
RTCNT
8
H'EE02A
RTCOR
8
H'EE02B
Reserved area (access prohibited)
DRAM
interface
H'EE02C
H'EE02D
H'EE02E
H'EE02F
H'EE030
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE031
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE032
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE033
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE034
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE035
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE036
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE037
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE038
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE039
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE03A
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE03B
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'EE03C
Reserved area (access prohibited)
⎯
⎯
⎯
⎯
⎯
⎯
P41PCR
P40PCR
H'EE03D
⎯
H'EE03E
P4PCR
⎯
H'EE03F
Reserved area (access prohibited)
8
⎯
P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR
Port 4
Rev.5.00 Sep. 12, 2007 Page 635 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
Address
(Low)
Register
Name
Data
Bus
Width Bit 7
H'FFF20
MAR0AR
8
H'FFF21
MAR0AE
8
H'FFF22
MAR0AH
8
H'FFF23
MAR0AL
8
H'FFF24
ETCR0AH 8
H'FFF25
ETCR0AL 8
H'FFF26
IOAR0A
8
H'FFF27
DTCR0A
8
H'FFF28
MAR0BR
H'FFF29
MAR0BE
8
H'FFF2A
MAR0BH
8
H'FFF2B
MAR0BL
8
H'FFF2C
ETCR0BH 8
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DMAC channel 0A
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTE
DTSZ
SAID
SAIDE
DTIE
DTS2A DTS1A DTS0A Full address mode
DTS1
DTS0
8
H'FFF2D
ETCR0BL 8
H'FFF2E
IOAR0B
8
H'FFF2F
DTCR0B
8
H'FFF30
MAR1AR
8
H'FFF31
MAR1AE
8
H'FFF32
MAR1AH
8
H'FFF33
MAR1AL
8
H'FFF34
ETCR1AH 8
H'FFF35
ETCR1AL 8
H'FFF36
IOAR1A
8
H'FFF37
DTCR1A
8
H'FFF38
MAR1BR
8
H'FFF39
MAR1BE
8
H'FFF3A
MAR1BH
8
H'FFF3B
MAR1BL
8
H'FFF3C
ETCR1BH 8
H'FFF3D
ETCR1BL 8
H'FFF3E
IOAR1B
8
H'FFF3F
DTCR1B
8
Module name
Short address mode
DMAC channel 0B
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTME
⎯
DAID
DAIDE
TMS
DTS2B DTS1B DTS0B Full address mode
DTS1
DTS0
Short address mode
DMAC channel 1A
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTE
DTSZ
SAID
SAIDE
DTIE
DTS2A DTS1A DTS0A Full address mode
DTS1
DTS0
Short address mode
DMAC channel 1B
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTME
⎯
DAID
DAIDE
TMS
DTS2B DTS1B DTS0B Full address mode
Rev.5.00 Sep. 12, 2007 Page 636 of 764
REJ09B0396-0500
DTS1
DTS0
Short address mode
Appendix B Internal I/O Registers
Address
(Low)
Data
Register Bus
Name
Width Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'FFF40
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF41
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF42
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF43
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF44
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF45
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF46
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF47
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF48
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF49
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF4A
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF4B
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF4C
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF4D
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF4E
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF4F
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF50
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF51
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF52
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF53
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF54
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF55
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF56
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF57
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF58
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF59
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF5A
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF5B
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF5C
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF5D
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF5E
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF5F
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Register Name
Module
name
Rev.5.00 Sep. 12, 2007 Page 637 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
Address Register
(Low)
Name
Data
Bus
Width Bit 7
H'FFF60 TSTR
8
H'FFF61 TSNC
H'FFF62 TMDR
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
⎯
⎯
⎯
⎯
⎯
STR2
STR1
STR0
8
⎯
⎯
⎯
⎯
⎯
SYNC2
SYNC1
SYNC0
8
⎯
MDF
FDIR
⎯
⎯
PWM2
PWM1
PWM0
H'FFF63 TOLR
8
⎯
⎯
TOB2
TOA2
TOB1
TOA1
TOB0
TOA0
H'FFF64 TISRA
8
⎯
IMIEA2
IMIEA1
IMIEA0
⎯
IMFA2
IMFA1
IMFA0
H'FFF65 TISRB
8
⎯
IMIEB2
IMIEB1
IMIEB0
⎯
IMFB2
IMFB1
IMFB0
H'FFF66 TISRC
8
⎯
OVIE2
OVIE1
OVIE0
⎯
OVF2
OVF1
OVF0
H'FFF68 16TCR0
8
⎯
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
H'FFF69 TIOR0
8
⎯
IOB2
IOB1
IOB0
⎯
IOA2
IOA1
IOA0
Module
name
16-bit timer,
(all
channels)
H'FFF67
16-bit timer
channel 0
H'FFF6A 16TCNT0H 16
H'FFF6B 16TCNT0L
H'FFF6C GRA0H
16
H'FFF6D GRA0L
H'FFF6E GRB0H
16
H'FFF6F GRB0L
H'FFF70 16TCR1
8
⎯
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
H'FFF71 TIOR1
8
⎯
IOB2
IOB1
IOB0
⎯
IOA2
IOA1
IOA0
16-bit timer
channel 1
H'FFF72 16TCNT1H 16
H'FFF73 16TCNT1L
H'FFF74 GRA1H
16
H'FFF75 GRA1L
H'FFF76 GRB1H
16
H'FFF77 GRB1L
H'FFF78 16TCR2
8
⎯
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
H'FFF79 TIOR2
8
⎯
IOB2
IOB1
IOB0
⎯
IOA2
IOA1
IOA0
H'FFF7A 16TCNT2H 16
H'FFF7B 16TCNT2L
H'FFF7C GRA2H
16
H'FFF7D GRA2L
H'FFF7E GRB2H
16
H'FFF7F GRB2L
Rev.5.00 Sep. 12, 2007 Page 638 of 764
REJ09B0396-0500
16-bit timer
channel 2
Appendix B Internal I/O Registers
Address Register
(Low)
Name
Data
Bus
Width Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'FFF80
8TCR0
8
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
H'FFF81
8TCR1
8
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
H'FFF82
8TCSR0
8
CMFB
CMFA
OVF
ADTE
OIS3
OIS2
OS1
OS0
H'FFF83
8TCSR1
8
CMFB
CMFA
OVF
ICE
OIS3
OIS2
OS1
OS0
H'FFF84
TCORA0
8
H'FFF85
TCORA1
8
H'FFF86
TCORB0
8
H'FFF87
TCORB1
8
H'FFF88
8TCNT0
8
H'FFF89
8TCNT1
8
H'FFF8A ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF8B ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
OVF
WT/IT
TME
⎯
⎯
CKS2
CKS1
CKS0
H'FFF8C TCSR*1
8
H'FFF8D TCNT*1
8
H'FFF8E ⎯
Register Name
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF8F RSTCSR
1
*
8
WRST
RSTOE
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF90
8TCR2
8
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
H'FFF91
8TCR3
8
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
H'FFF92
8TCSR2
8
CMFB
CMFA
OVF
⎯
OIS3
OIS2
OS1
OS0
H'FFF93
8TCSR3
8
CMFB
CMFA
OVF
ICE
OIS3
OIS2
OS1
OS0
H'FFF94
TCORA2
8
H'FFF95
TCORA3
8
H'FFF96
TCORB2
8
H'FFF97
TCORB3
8
H'FFF98
8TCNT2
8
H'FFF99
8TCNT3
8
H'FFF9A ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF9B ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFF9C DADR0
8
H'FFF9D DADR1
8
Module
name
8-bit timer
channels 0
and 1
WDT
8-bit timer
channels 2
and 3
D/A
converter
H'FFF9E DACR
8
DAOE1
DAOE0
DAE
⎯
⎯
⎯
⎯
⎯
H'FFF9F ⎯
8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Rev.5.00 Sep. 12, 2007 Page 639 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
Data
Address Register Bus
(Low)
Name
Width Bit 7
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
name
⎯
⎯
⎯
G3NOV
G2NOV
G1NOV
G0NOV
TPC
H'FFFA0 TPMR
8
⎯
H'FFFA1 TPCR
8
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
H'FFFA2 NDERB
8
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9
NDER8
H'FFFA3 NDERA
8
NDER7
NDER1
NDER0
2
8
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9
NDER8
H'FFFA4 NDRB*
NDER6
NDER5
NDER4
NDER3
NDER2
NDER15 NDER14 NDER13 NDER12 ⎯
⎯
⎯
⎯
NDER2
NDER1
NDER0
H'FFFA5 NDRA*
2
8
NDER7
NDER6
NDER5
NDER4
NDER7
NDER6
NDER5
NDER4
⎯
⎯
⎯
⎯
H'FFFA6 NDRB*
2
8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
NDER11 NDER10 NDER9
H'FFFA7 NDRA*
2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
NDER3
NDER2
NDER1
NDER0
H'FFFA8 ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFA9 ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFAA ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFAB ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFAC ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFAD ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFAE ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFAF ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDRE
RDRF
ORER
FER/ERS PER
TEND
MPB
MPBT
⎯
⎯
⎯
⎯
SDIR
SINV
⎯
SMIF
8
H'FFFB0 SMR
8
H'FFFB1 BRR
8
H'FFFB2 SCR
8
H'FFFB3 TDR
8
H'FFFB4 SSR
8
H'FFFB5 RDR
8
H'FFFB6 SCMR
8
NDER3
NDER8
SCI
channel 0
H'FFFB7 Reserved area (access prohibited)
H'FFFB8 SMR
8
H'FFFB9 BRR
8
H'FFFBA SCR
8
H'FFFBB TDR
8
H'FFFBC SSR
8
H'FFFBD RDR
8
H'FFFBE SCMR
8
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDRE
RDRF
ORER
FER/ERS PER
TEND
MPB
MPBT
⎯
⎯
⎯
⎯
SINV
⎯
SMIF
H'FFFBF Reserved area (access prohibited)
Rev.5.00 Sep. 12, 2007 Page 640 of 764
REJ09B0396-0500
SDIR
SCI
channel 1
Appendix B Internal I/O Registers
Address
(Low)
Data
Register Bus
Name
Width Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'FFFC0
SMR
8
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
H'FFFC1
BRR
8
H'FFFC2
SCR
8
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
H'FFFC3
TDR
8
TDRE
RDRF
ORER
FER/ERS PER
TEND
MPB
MPBT
⎯
⎯
⎯
⎯
SDIR
SINV
⎯
SMIF
Register Name
Module
name
SCI
channel 2
H'FFFC4
SSR
8
H'FFFC5
RDR
8
H'FFFC6
SCMR
8
H'FFFC7
Reserved area (access prohibited)
H'FFFC8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFC9
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFCA
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFCB
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFCC
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFCD
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFCE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFCF
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFD0
Reserved area (access prohibited)
P45
P44
P43
P42
P41
P40
Port 4
P66
P65
P64
P63
P62
P61
P60
Port 6
H'FFFD1
H'FFFD2
H'FFFD3
P4DR
H'FFFD4
Reserved area (access prohibited)
8
H'FFFD5
P6DR
8
P47
P67
P46
H'FFFD6
P7DR
8
P77
P76
P75
P74
P73
P72
P71
P70
Port 7
H'FFFD7
P8DR
8
⎯
⎯
⎯
P84
P83
P82
P81
P80
Port 8
H'FFFD8
P9DR
8
⎯
⎯
P95
P94
P93
P92
P91
P90
Port 9
H'FFFD9
PADR
8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port A
H'FFFDA
PBDR
8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Port B
H'FFFDB
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFDC
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFDD
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFDE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFDF
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Rev.5.00 Sep. 12, 2007 Page 641 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
Address
(Low)
Data
Register Bus
Name
Width Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'FFFE0
ADDRAH 8
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'FFFE1
ADDRAL 8
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFE2
ADDRBH 8
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'FFFE3
ADDRBL 8
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
Register Name
H'FFFE4
ADDRCH 8
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'FFFE5
ADDRCL 8
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFE6
ADDRDH 8
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'FFFE7
ADDRDL 8
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
H'FFFE8
ADCSR
8
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
H'FFFE9
ADCR
8
TRGE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Module
name
A/D
converter
Legend:
WDT: Watchdog timer
TPC: Programmable timing pattern controller
SCI:
Serial communication interface
Notes: 1. For write access to TCSR, TCNT, and RSTCSR, see section 12.2.4, Notes on Register
Access.
2. The address depends on the output trigger setting.
Rev.5.00 Sep. 12, 2007 Page 642 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
B.2
Functions
Register abbreviation
Address to which register
is mapped
Register name
TIER—Timer Interrupt Enable Register
H' 90
Name of on-chip
supporting module
FRT
Bit numbers
Bit
Initial bit values
Initial value
R/W:
6
5
ICIAE
ICIBE
ICICE
0
R/W
0
R/W
0
R/W
OCIDE OCIAE OCIBE
1
R/W
0
R/W
0
R/W
Read only
W
Write only
0
OVIE
⎯
1
R/W
1
⎯
Names of the bits.
Dashes (⎯) indicate
reserved bits.
Timer overflow interrupt enable
Possible types of
access
R
1
2
3
4
7
R/W Read and write
0
Interrupt requested by OVF flag is disabled
1
Interrupt requested by OVF flag is enabled
Output compare interrupt B enable
0
Interrupt requested by OCFB flag is disabled
1
Interrupt requested by OCFB flag is enabled
Full name of bit
Output compare interrupt A enable
0
Interrupt requested by OCFA flag is disabled
1
Interrupt requested by OCFA flag is enabled
Descriptions of
bit settings
Input capture interrupt D enable
0
Interrupt requested by ICFD flag is disabled
1
Interrupt requested by ICFD flag is enabled
Rev.5.00 Sep. 12, 2007 Page 643 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
P4DDR⎯Port 4 Data Direction Register
Bit
7
6
H'EE003
5
4
Port 4
3
2
1
0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
Initial value
Read/Write
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Port 4 input/output select
0
Generic input
1
Generic output
P6DDR⎯Port 6 Data Direction Register
Bit
7
⎯
Initial value
Read/Write
1
⎯
6
5
H'EE005
4
3
Port 6
2
1
0
P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Port 6 input/output select
Rev.5.00 Sep. 12, 2007 Page 644 of 764
REJ09B0396-0500
0
Generic input
1
Generic output
Appendix B Internal I/O Registers
P8DDR⎯Port 8 Data Direction Register
Bit
Modes 1 to 4
Initial value
Read/Write
H'EE007
7
6
5
⎯
⎯
⎯
1
⎯
1
⎯
1
⎯
Port 8
3
4
2
1
0
P84DDR P83DDR P82DDR P81DDR P80DDR
0
W
1
W
0
W
0
W
0
W
Port 8 input/output select
0
Generic input
1
Generic output
Port 8 input/output select
P9DDR⎯Port 9 Data Direction Register
Bit
Initial value
Read/Write
7
6
⎯
⎯
1
⎯
1
⎯
5
0
Generic input
1
CS output
H'EE008
4
3
Port 9
2
1
0
P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR
0
W
0
W
0
W
0
W
0
W
0
W
Port 9 input/output select
0
Generic input
1
Generic output
Rev.5.00 Sep. 12, 2007 Page 645 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
PADDR⎯Port A Data Direction Register
Bit
7
6
H'EE009
5
4
Port A
3
2
1
0
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Modes 3, 4
Initial value
Read/Write
1
⎯
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Modes 1, 2
Initial value
Read/Write
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Port A input/output select
PBDDR⎯Port B Data Direction Register
Bit
7
6
0
Generic input pin
1
Generic output pin
H'EE00A
5
4
3
Port B
2
1
0
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value
Read/Write
0
W
0
W
0
W
0
W
0
W
0
W
Port B input/output select
Rev.5.00 Sep. 12, 2007 Page 646 of 764
REJ09B0396-0500
0
Generic input
1
Generic output
0
W
0
W
Appendix B Internal I/O Registers
MDCR⎯Mode Control Register
Bit
Initial value
Read/Write
H'EE011
System control
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
MDS2
MDS1
MDS0
1
⎯
1
⎯
0
⎯
0
⎯
0
⎯
⎯*
R
⎯*
R
⎯*
R
Mode select 2 to 0
Bit 2
Bit 1
Bit 0
MD2
MD1
MD0
0
0
1
0
1
1
Operating Mode
0
⎯
1
Mode 1
0
Mode 2
1
Mode 3
0
Mode 4
1
⎯
0
⎯
1
⎯
Note: * Determined by the state of the mode pins (MD2 to MD0).
Rev.5.00 Sep. 12, 2007 Page 647 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
SYSCR⎯System Control Register
Bit
Initial value
Read/Write
H'EE012
System control
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
SSOE
RAME
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
1
R/W
RAM enable
0
1
On-chip RAM is disabled
On-chip RAM is enabled
Software standby output port enable
0
1
In software standby mode,
all address bus and bus
control signals are highimpedance
In software standby mode,
address bus retains output
state and bus control
signals are fixed high
NMI edge select
An interrupt is requested at the falling edge of NMI
0
An interrupt is requested at the rising edge of NMI
1
User bit enable
CCR bit 6 (UI) is used as an interrupt mask bit
0
CCR bit 6 (UI) is used as a user bit
1
Standby timer select 2 to 0
Bit 6
STS2
Bit 5
STS1
0
0
1
0
1
1
Bit 4
STS0
0
1
0
1
0
1
0
1
Standby Timer
Waiting Time = 8,192 states
Waiting Time = 16,384 states
Waiting Time = 32,768 states
Waiting Time = 65,536 states
Waiting Time = 131,072 states
Waiting Time = 26,2144 states
Waiting Time = 1,024 states
Illegal setting
Software standby
SLEEP instruction causes transition to sleep mode
0
SLEEP instruction causes transition to software standby mode
1
Rev.5.00 Sep. 12, 2007 Page 648 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
BRCR⎯Bus Release Control Register
H'EE013
Bus controller
7
6
5
4
3
2
1
0
A23E
A22E
A21E
A20E
⎯
⎯
⎯
BRLE
Modes Initial value
1, 2
Read/Write
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
0
R/W
Modes Initial value
3, 4
Read/Write
1
R/W
1
R/W
1
R/W
0
⎯
1
⎯
1
⎯
1
⎯
0
R/W
Bit
Bus release enable
Address 23 to 20 enable
0
Address output
1
Other input/output
The bus cannot be
released to an
external device
The bus can be
released to an
external device
0
1
ISCR⎯IRQ Sense Control Register
Bit
Initial value
Read/Write
7
6
⎯
⎯
0
R/W
0
R/W
5
H'EE014
4
3
Interrupt Controller
2
1
0
IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
IRQ5 to IRQ0 sense control
0
Interrupts are requested when IRQ5 toIRQ0 are low
1
Interrupts are requested by falling-edge input at IRQ5 to IRQ0
Rev.5.00 Sep. 12, 2007 Page 649 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
IER⎯IRQ Enable Register
Bit
Initial value
Read/Write
H'EE015
Interrupt Controller
7
6
5
4
3
2
1
0
⎯
⎯
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
IRQ5 to IRQ0 enable
0
IRQ5 to IRQ0 interrupts are disabled
1
IRQ5 to IRQ0 interrupts are enabled
ISR⎯IRQ Status Register
Bit
Initial value
Read/Write
H'EE016
Interrupt Controller
7
6
5
4
3
2
1
0
⎯
⎯
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
0
⎯
0
⎯
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
IRQ5 to IRQ0 flags
Bits 5 to 0
Setting and Clearing Conditions
IRQ5F to IRQ0F
[Clearing conditions]
• Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
0
• IRQnSC = 0, IRQn input is high, and interrupt exception
handling is being carried out.
• IRQnSC = 1 and IRQn interrupt exception handling is being
carried out.
[Setting conditions]
1
• IRQnSC = 0 and IRQn input is low.
• IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 5 to 0
Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 650 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
IPRA⎯Interrupt Priority Register A
H'EE018
Interrupt Controller
7
6
5
4
3
2
1
0
IPRA7
IPRA6
IPRA5
IPRA4
IPRA3
IPRA2
IPRA1
IPRA0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Initial value
Read/Write
Priority level A7 to A0
0
Priority level 0 (low priority)
1
Priority level 1 (high priority)
• Interrupt sources controlled by each bit
Bit
IPRA
Bit 7
Bit 6
Bit 5
Bit 4
IPRA7
IPRA6
IPRA5
IPRA4
IRQ0
IRQ1
IRQ2,
IRQ4,
WDT,
16-bit
16-bit
16-bit
IRQ3
IRQ5
DRAM
timer
timer
timer
Interrupt
Bit 3
source
Bit 2
IPRA3
Bit 1
IPRA2
IPRA1
Bit 0
IPRA0
interface, channel 0 channel 1 channel 2
A/D converter
IPRB⎯Interrupt Priority Register B
Bit
Initial value
Read/Write
H'EE019
Interrupt Controller
7
6
5
4
3
2
1
0
IPRB7
IPRB6
IPRB5
⎯
IPRB3
IPRB2
IPRB1
⎯
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Priority level B7 to B5, B3 to B1
0
Priority level 0 (low priority)
1
Priority level 1 (high priority)
• Interrupt sources controlled by each bit
Bit
IPRB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IPRB7
IPRB6
IPRB5
⎯
IPRB3
IPRB2
IPRB1
⎯
⎯
SCI
SCI
SCI
⎯
8-bit timer 8-bit timer
Interrupt
channels channels
source
0 and 1 2 and 3
DMAC
Bit 0
channel 0 channel 1 channel 2
Rev.5.00 Sep. 12, 2007 Page 651 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
DASTCR⎯D/A Standby Control Register
Bit
Initial value
Read/Write
H'EE01A
D/A converter
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DASTE
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
0
R/W
D/A standby enable
0
D/A output is disabled in software standby mode
1
D/A output is enabled in software standby mode
DIVCR⎯Division Control Register
Bit
Initial value
Read/Write
(Initial value)
H'EE01B
System control
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
DIV1
DIV0
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
0
R/W
0
R/W
Divide 1 and 0
Bit 1
Bit 0
DIV1
DIV0
0
1
Rev.5.00 Sep. 12, 2007 Page 652 of 764
REJ09B0396-0500
Frequency Division Ratio
0
1/1
1
1/2
0
1/4
1
1/8
(Initial value)
Appendix B Internal I/O Registers
MSTCRH⎯Module Standby Control Register H
H'EE01C
System control
2
1
0
7
6
5
4
3
PSTOP
⎯
⎯
⎯
⎯
0
1
1
1
1
0
0
0
⎯
⎯
⎯
R/W
R/W
R/W
Bit
Initial value
Read/Write
⎯
R/W
MSTPH2 MSTPH1 MSTPH0
Module standby H2 to H0
Selection bits for placing modules
in standby state.
Reserved bits
φ clock stop
Enables or disables φ clock output.
MSTCRL⎯Module Standby Control Register L
4
3
7
6
MSTPL7
⎯
Initial value
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
Bit
5
H'EE01D
System control
2
1
0
⎯
MSTPL0
0
0
0
R/W
R/W
MSTPL5 MSTPL4 MSTPL3 MSTPL2
R/W
Module standby L7, L5 to L2, L0
Selection bits for placing modules
in standby state.
Reserved bits
Rev.5.00 Sep. 12, 2007 Page 653 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
CSCR⎯Chip Select Control Register
Bit
Initial value
Read/Write
H'EE01F
Bus controller
7
6
5
4
3
2
1
0
CS7E
CS6E
CS5E
CS4E
⎯
⎯
⎯
⎯
0
R/W
0
R/W
0
R/W
0
R/W
1
⎯
1
⎯
1
⎯
1
⎯
Chip select 7 to 4 enable
Bit n
Description
CSnE
0
Output of chip select signal CSn is disabled (Initial value)
1
Output of chip select signal CSn is enabled
Note: n = 7 to 4
ABWCR⎯Bus Width Control Register
Bit
Modes 1, 3
Modes 2, 4
Initial value
Initial value
Read/Write
H'EE020
Bus controller
7
6
5
4
3
2
1
0
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
1
0
R/W
1
0
R/W
1
0
R/W
1
0
R/W
1
0
R/W
1
0
R/W
1
0
R/W
1
0
R/W
Area 7 to 0 bus width control
Bits 7 to 0
ABW7
Bus Width of Access Area
to ABW0
0
Areas 7 to 0 are 16-bit access areas
1
Areas 7 to 0 are 8-bit access areas
Rev.5.00 Sep. 12, 2007 Page 654 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
ASTCR⎯Access State Control Register
Bit
Initial value
Read/Write
H'EE021
Bus controller
7
6
5
4
3
2
1
0
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Area 7 to 0 access state control
Bits 7 to 0
AST7
Number of States in Access Area
to AST0
0
Areas 7 to 0 are two-state access areas
1
Areas 7 to 0 are three-state access areas
Rev.5.00 Sep. 12, 2007 Page 655 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
WCRH⎯Wait Control Register H
Bit
Initial value
Read/Write
H'EE022
Bus controller
7
6
5
4
3
2
1
0
W71
W70
W61
W60
W51
W50
W41
W40
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Area 4 wait control 1 and 0
0 No program wait is inserted
0
1 1 program wait state is inserted
1
0
2 program wait states are inserted
1
3 program wait states are inserted
Area 5 wait control 1 and 0
0 No program wait is inserted
0
1 1 program wait state is inserted
1
0
2 program wait states are inserted
1
3 program wait states are inserted
Area 6 wait control 1 and 0
0 No program wait is inserted
0
1 1 program wait state is inserted
1
0
2 program wait states are inserted
1
3 program wait states are inserted
Area 7 wait control 1 and 0
0 No program wait is inserted
0
1 1 program wait state is inserted
1
0
2 program wait states are inserted
1
3 program wait states are inserted
Rev.5.00 Sep. 12, 2007 Page 656 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
WCRL⎯Wait Control Register L
Bit
Initial value
Read/Write
H'EE023
Bus controller
7
6
5
4
3
2
1
0
W31
W30
W21
W20
W11
W10
W01
W00
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Area 0 wait control 1 and 0
0
1
0
No program wait is inserted
1
1 program wait state is inserted
0
2 program wait states are inserted
1
3 program wait states are inserted
Area 1 wait control 1 and 0
0
1
0
No program wait is inserted
1
1 program wait state is inserted
0
2 program wait states are inserted
1
3 program wait states are inserted
Area 2 wait control 1 and 0
0
1
0
No program wait is inserted
1
1 program wait state is inserted
0
2 program wait states are inserted
1
3 program wait states are inserted
Area 3 wait control 1 and 0
0
1
0
No program wait is inserted
1
1 program wait state is inserted
0
2 program wait states are inserted
1
3 program wait states are inserted
Rev.5.00 Sep. 12, 2007 Page 657 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
BCR⎯Bus Control Register
Bit
Initial value
Read/Write
7
6
ICIS1
ICIS0
1
R/W
1
R/W
H'EE024
5
4
3
BROME BRSTS1 BRSTS0
0
R/W
0
R/W
0
R/W
Bus controller
2
1
0
⎯
RDEA
WAITE
1
⎯
1
R/W
0
R/W
Wait pin enable
0
WAIT pin wait input is disabled
1
WAIT pin wait input is enabled
Area division unit select
0
Area divisions are as follows:
Area 0: 2 Mbytes Area 4: 1.93 Mbytes
Area 1: 2 Mbytes Area 5: 4 kbytes
Area 2: 8 Mbytes Area 6: 23.75 kbytes
Area 3: 2 Mbytes Area 7: 22 bytes
1
Areas 0 to 7 are the same size
(2 Mbytes )
Burst cycle select 0
0
Max. 4 words in burst access
1
Max. 8 words in burst access
Burst cycle select 1
0
Burst access cycle comprises 2 states
1
Burst access cycle comprises 3 states
Burst ROM enable
0
Area 0 is a basic bus interface area
1
Area 0 is a burst ROM interface area
Idle cycle insertion 0
0
No idle cycle is inserted in case of consecutive external read and write cycles
1
Idle cycle is inserted in case of consecutive external read and write cycles
Idle cycle insertion 1
0
No idle cycle is inserted in case of consecutive external read cycles for different areas
1
Idle cycle is inserted in case of consecutive external read cycles for different areas
Rev.5.00 Sep. 12, 2007 Page 658 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
DRCRA⎯DRAM Control Register A
Bit
7
H'EE026
6
5
4
3
DRAM interface
2
1
0
⎯
BE
Initial value
0
0
0
1
0
0
0
0
Read/Write
R/W
R/W
R/W
⎯
R/W
R/W
R/W
R/W
DRAS2 DRAS1 DRAS0
RDM SRFMD RFSHE
Refresh pin enable
0
RFSH pin refresh signal output is disabled
1
RFSH pin refresh signal output is enabled
Self-refresh mode
0
DRAM self-refreshing is disabled in
software standby mode
1
DRAM self-refreshing is enabled
in software standby modeV
RAS down mode
0
DRAM interface: RAS up mode selected
1
DRAM interface: RAS down mode selected
Burst access enable
0
Burst disabled (always full access)
1
DRAM space access performed in fast page mode
DRAM area select
DRAS2 DRAS1 DRAS0
0
0
1
1
0
Area 4
Area 3
Area 2
0
Normal
Normal
Normal
Normal
1
Normal
Normal
Normal
DRAM space
(CS2)
0
Normal
Normal
DRAM space DRAM space
(CS3)
(CS2)
1
Normal
Normal
DRAM space(CS2)*
0
Normal
1
1
Area 5
0
1
DRAM space DRAM space DRAM space
(CS4)
(CS3)
(CS2)
DRAM space DRAM space DRAM space DRAM space
(CS5)
(CS4)
(CS3)
(CS2)
DRAM space(CS4)*
DRAM space(CS2)*
DRAM space(CS2)*
Note: * A single CSn pin serves as a common RAS output pin for a number of
areas. Unused CSn pins can be used as input/output ports.
Rev.5.00 Sep. 12, 2007 Page 659 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
DRCRB⎯DRAM Control Register B
Bit
7
6
MXC1
MXC0
H'EE027
5
4
CSEL RCYCE
DRAM interface
3
2
1
0
⎯
TPC
RCW
RLW
Initial value
0
0
0
0
1
0
0
0
Read/Write
R/W
R/W
R/W
R/W
⎯
R/W
R/W
R/W
Refresh cycle wait control
0
Wait state (TRW) insertion is disabled
1
1 wait state (TRW) is inserted
RAS-CAS wait
0
Wait state (TrW) insertion is disabled
1
1 wait state (TrW) is inserted
TP cycle control
0
1-state precharge cycle is inserted
1
2-state precharge cycle is inserted
Refresh cycle enable
0
Refresh cycles are disabled
1
DRAM refresh cycles are enabled
CAS output pin select
0
PB4 and PB5 selected as UCAS and LCAS output pins
1
HWR and LWR selected as UCAS and LCAS output pins
Multiplex control 1 and 0
MXC1
MXC0
0
0
1
1
0
1
Description
Column address: 8 bits
Compared address:
Modes 1, 2
8-bit access space
16-bit access space
Modes 3, 4
8-bit access space
16-bit access space
A19 to A8
A19 to A9
A23 to A8
A23 to A9
Column address: 9 bits
Compared address:
Modes 1, 2
8-bit access space
16-bit access space
Modes 3, 4
8-bit access space
16-bit access space
A19 to A9
A19 to A10
A23 to A9
A23 to A10
Column address: 10 bits
Compared address:
Modes 1, 2
8-bit access space
16-bit access space
Modes 3, 4
8-bit access space
16-bit access space
A19 to A10
A19 to A11
A23 to A10
A23 to A11
Illegal setting
Rev.5.00 Sep. 12, 2007 Page 660 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
RTMCSR⎯Refresh Timer Control/Status Register
Bit
H'EE028
DRAM interface
7
6
5
4
3
2
1
0
CMF
CMIE
CKS2
CKS1
CKS0
⎯
⎯
⎯
Initial value
0
0
0
0
0
1
1
1
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
⎯
⎯
⎯
Refresh counter clock select
Description
CKS2
CKS1
CKS0
0
0
0
Count operation halted
1
φ/2 used as counter clock
0
φ/8 used as counter clock
1
φ/32 used as counter clock
0
φ/128 used as counter clock
1
φ/512 used as counter clock
0
φ/2048 used as counter clock
1
φ/4096 used as counter clock
1
1
0
1
Compare match interrupt enable
0
The CMI interrupt requested by the CMF flag is disabled
1
The CMI interrupt requested by the CMF flag is enabled
Compare match flag
0
[Clearing conditions]
• Cleared by a reset and in standby mode
• Cleared by reading CMF when CMF = 1, then writing 0 in CMF
1
[Setting condition]
When RTCNT = RTCOR
Note: * Only 0 can be written to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 661 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
RTCNT⎯Refresh Timer Counter
H'EE029
DRAM interface
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Incremented by internal clock selected
by bits CKS2 to CKS0 in RTMCSR
RTCOR⎯Refresh Time Constant Register
Bit
7
6
5
H'EE02A
4
3
DRAM interface
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RTCNT compare match period
Note: Only byte access should be used with this register.
P4PCR⎯Port 4 Input Pull-Up Control Register H'EE03E
Bit
7
6
5
4
3
Port 4
2
1
0
P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR
Initial value
Read/Write
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Port 4 input pull-up control 7 to 0
0
Input pull-up transistor is off
1
Input pull-up transistor is on
Note: Valid when the corresponding P4DDR bit is cleared to 0
(designating generic input).
Rev.5.00 Sep. 12, 2007 Page 662 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
MAR0A R/E/H/L⎯Memory Address Register 0A R/E/H/L
Bit
31
30
29
28
27
26
25
24
Initial value
Read/Write
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
23
H'FFF20 H'FFF21
H'FFF22 H'FFF23
22
21
Initial value
Read/Write
15
14
13
12
11
19
18
17
16
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W
MAR0AR
Bit
20
DMAC0
MAR0AE
10
9
8
7
6
5
Undetermined
4
3
2
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MAR0AH
MAR0AL
Source or destination address
Rev.5.00 Sep. 12, 2007 Page 663 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
ETCR0A H/L⎯Execute Transfer Count Register 0A H/L
H'FFF24 H'FFF25
DMAC0
• Short address mode
⎯ I/O mode and idle mode
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transfer counter
⎯ Repeat mode
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Initial value
Undetermined
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
ETCR0AH
ETCR0AL
Transfer counter
Initial count
• Full address mode
⎯ Normal mode
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Transfer counter
⎯ Block transfer mode
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Undetermined
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
ETCR0AH
ETCR0AL
Block size counter
Initial block size
Rev.5.00 Sep. 12, 2007 Page 664 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
IOAR0A⎯I/O Address Register 0A
Bit
Initial value
Read/Write
H'FFF26
7
6
5
R/W
R/W
R/W
4
3
Undetermined
R/W
R/W
DMAC0
2
1
0
R/W
R/W
R/W
Short address mode : source or destination address
Full address mode
: not used
Rev.5.00 Sep. 12, 2007 Page 665 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
DTCR0A⎯Data Transfer Control Register 0A
H'FFF27
DMAC0
• Short address mode
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTS1
DTS0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Data transfer select
Bit 2 Bit 1 Bit 0
DTS2 DTS1 DTS0
0
0
1
0
1
0
1
1
0
1
0
1
0
1
Data Transfer Activation Source
Compare match/input capture A
interrupt from 16-bit timer channel 0
Compare match/input capture A
interrupt from 16-bit timer channel 1
Compare match/input capture A
interrupt from 16-bit timer channel 2
A/D converter conversion end interrupt
SCI0 transmit-data-empty interrupt
SCI0 receive-data-full interrupt
Transfer in full address mode
Transfer in full address mode
Data transfer interrupt enable
Interrupt requested by
0
DTE bit is disabled
Interrupt requested by
1
DTE bit is enabled
Repeat enable
RPE DTIE
Description
0
0
I/O mode
1
0 Repeat mode
1
1 Idle mode
Data transfer increment/decrement
0
Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer
If DTSZ = 1, MAR is incremented by 2 after each transfer
1
Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer
If DTSZ = 1, MAR is decremented by 2 after each transfer
Data transfer size
0
1
Byte-size transfer
Word-size transfer
Data transfer enable
0
1
Data transfer is disabled
Data transfer is enabled
Rev.5.00 Sep. 12, 2007 Page 666 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
DTCR0A⎯Data Transfer Control Register 0A (cont)
H'FFF27
DMAC0
• Full address mode
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
DTE
DTSZ
SAID
SAIDE
DTIE
DTS2A
DTS1A
DTS0A
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Data transfer select 0A
0
1
Normal mode
Block transfer mode
Data transfer select 2A and 1A
Set both bits to 1
Data transfer interrupt enable
0
1
Interrupt requested by DTE bit is disabled
Interrupt requested by DTE bit is enabled
Source address increment/decrement (bit 5)
Source address increment/decrement enable (bit 4)
Bit 5
Bit 4
Increment/Decrement Enable
SAID SAIDE
0
MARA is held fixed
0
Incremented: If DTSZ = 0, MARA is incremented by 1 after each transfer
1
If DTSZ = 1, MARA is incremented by 2 after each transfer
0
MARA is held fixed
1
Decremented: If DTSZ = 0, MARA is decremented by 1 after each transfer
1
If DTSZ = 1, MARA is decremented by 2 after each transfer
Data transfer size
0
1
Byte-size transfer
Word-size transfer
Data transfer enable
0
1
Data transfer is disabled
Data transfer is enabled
Rev.5.00 Sep. 12, 2007 Page 667 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
MAR0B R/E/H/L⎯Memory Address Register 0B R/E/H/L
Bit
31
30
29
28
27
26
25
24
Initial value
Read/Write
1
1
1
1
1
1
1
1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
23
H'FFF28 H'FFF29
H'FFF2A H'FFF2B
22
21
Initial value
Read/Write
15
14
13
12
11
19
18
17
16
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W
MAR0BR
Bit
20
DMAC0
MAR0BE
10
9
8
7
6
5
Undetermined
4
3
2
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MAR0BH
MAR0BL
Source or destination address
Rev.5.00 Sep. 12, 2007 Page 668 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
ETCR0B H/L⎯Execute Transfer Count Register 0B H/L
H'FFF2C, H'FFF2D
DMAC0
• Short address mode
⎯ I/O mode and idle mode
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transfer counter
⎯ Repeat mode
Bit
Initial value
Read/Write
:
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Undetermined
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
ETCR0BH
ETCR0BL
Transfer counter
Initial count
• Full address mode
⎯ Normal mode
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Not used
⎯ Block transfer mode
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Block transfer counter
Rev.5.00 Sep. 12, 2007 Page 669 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
IOAR0B⎯I/O Address Register 0B
Bit
Initial value
Read/Write
H'FFF2E
7
6
5
R/W
R/W
R/W
4
3
Undetermined
R/W
R/W
DMAC0
2
1
0
R/W
R/W
R/W
Short address mode : source or destination address
Full address mode
Rev.5.00 Sep. 12, 2007 Page 670 of 764
REJ09B0396-0500
: not used
Appendix B Internal I/O Registers
DTCR0B⎯Data Transfer Control Register 0B
H'FFF2F
DMAC0
• Short address mode
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTS1
DTS0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Data transfer select
Bit 2 Bit 1 Bit 0
DTS2 DTS1 DTS0
0
0
1
0
1
0
1
1
0
1
0
1
0
1
Data Transfer Activation Source
Compare match/input capture A interrupt
from 16-bit timer channel 0
Compare match/input capture A interrupt
from 16-bit timer channel 1
Compare match/input capture A interrupt
from 16-bit timer channel 2
A/D converter conversion end interrupt
SCI0 transmit-data-empty interrupt
SCI0 receive-data-full interrupt
Falling edge of DREQ input
Low level of DREQ input
Data transfer interrupt enable
0
1
Interrupt requested by
DTE bit is disabled
Interrupt requested by
DTE bit is enabled
Repeat enable
Description
RPE DTIE
0
0
I/O mode
1
0 Repeat mode
1
1 Idle mode
Data transfer increment/decrement
0
1
Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer
If DTSZ = 1, MAR is incremented by 2 after each transfer
Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer
If DTSZ = 1, MAR is decremented by 2 after each transfer
Data transfer size
0
1
Byte-size transfer
Word-size transfer
Data transfer enable
0
1
Data transfer is disabled
Data transfer is enabled
Rev.5.00 Sep. 12, 2007 Page 671 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
DTCR0B⎯Data Transfer Control Register 0B (cont) H'FFF2F
DMAC0
• Full address mode
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
DTME
⎯
DAID
DAIDE
TMS
DTS2B
DTS1B
DTS0B
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Data transfer select 2B to 0B
Data transfer master enable
0
1
Bit 2 Bit 1 Bit 0
DTS2B DTS1B DTS0B
Data transfer is disabled
Data transfer is enabled
0
0
1
0
1
0
1
1
0
1
0
1
0
1
Data Transfer Activation Source
Normal Mode
Block Transfer Mode
Auto-request (burst mode)
Compare match/input capture A
interrupt from 16-bit timer channel 0
Not available
Compare match/input capture A
interrupt from 16-bit timer channel 1
Auto-request (cycle-steal mode)
Compare match/input capture A
interrupt from 16-bit timer channel 2
Not available
Not available
Not available
Falling edge of DREQ input
Low level input at DREQ input
A/D converter conversion end interrupt
Not available
Not available
Falling edge of DREQ input
Not available
Transfer mode select
0
1
Destination is the block area in block transfer mode
Source is the block area in block transfer mode
Destination address increment/decrement (bit 5)
Destination address increment/decrement enable (bit 4)
Bit 4
Bit 5
Increment/Decrement Enable
DAID DAIDE
0
MARB is held fixed
0
Incremented: If DTSZ = 0, MARB is incremented by 1 after each transfer
1
If DTSZ = 1, MARB is incremented by 2 after each transfer
0
MARB is held fixed
1
Decremented:
If DTSZ = 0, MARB is decremented by 1 after each transfer
1
If DTSZ = 1, MARB is decremented by 2 after each transfer
Rev.5.00 Sep. 12, 2007 Page 672 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
MAR1A R/E/H/L⎯Memory Address Register 1A R/E/H/L
Bit
31
30
29
28
27
26
25
24
Initial value
Read/Write
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
23
H'FFF30 H'FFF31
H'FFF32 H'FFF33
22
21
20
Initial value
Read/Write
15
14
13
12
11
18
17
16
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W
MAR1AR
Bit
19
DMAC1
MAR1AE
10
9
8
7
6
5
4
Undetermined
3
2
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MAR1AH
MAR1AL
Note: Bit functions are the same as for DMAC0.
ETCR1A H/L⎯Execute Transfer Count Register 1A H/L
Bit
Initial value
Read/Write
Bit
15
14
13
12
11
10
9
8
7
H'FFF34 H'FFF35
6
5
4
3
DMAC1
2
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Initial value
Undetermined
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
ETCR1AH
ETCR1AL
Note: Bit functions are the same as for DMAC0.
Rev.5.00 Sep. 12, 2007 Page 673 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
IOAR1A⎯I/O Address Register 1A
Bit
Initial value
Read/Write
H'FFF36
7
6
5
R/W
R/W
R/W
4
3
Undetermined
R/W
R/W
DMAC1
2
1
0
R/W
R/W
R/W
Note: Bit functions are the same as for DMAC0.
DTCR1A⎯Data Transfer Control Register 1A
H'FFF37
DMAC1
• Short address mode
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTS1
DTS0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
7
6
5
4
3
2
1
0
DTE
DTSZ
SAID
SAIDE
DTIE
DTS2A
DTS1A
DTS0A
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
• Full address mode
Bit
Initial value
Read/Write
Note: Bit functions are the same as for DMAC0.
Rev.5.00 Sep. 12, 2007 Page 674 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
MAR1B R/E/H/L⎯Memory Address Register 1B R/E/H/L
Bit
31
30
29
28
27
26
25
24
Initial value
Read/Write
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
23
H'FFF38 H'FFF39
H'FFF3A H'FFF3B
22
21
Initial value
Read/Write
15
14
13
12
11
19
18
17
16
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W
MAR1BR
Bit
20
DMAC1
MAR1BE
10
9
8
7
6
5
4
Undetermined
3
2
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MAR1BH
MAR1BL
Note: Bit functions are the same as for DMAC0.
ETCR1B H/L⎯Execute Transfer Count Register 1B H/L
Bit
Initial value
Read/Write
Bit
15
14
13
12
11
10
9
8
7
H'FFF3C H'FFF3D
6
5
4
3
2
DMAC1
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Initial value
Undetermined
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
ETCR1BH
ETCR1BL
Note: Bit functions are the same as for DMAC0.
Rev.5.00 Sep. 12, 2007 Page 675 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
IOAR1B⎯I/O Address Register 1B
Bit
Initial value
Read/Write
H'FFF3E
7
6
5
R/W
R/W
R/W
4
3
Undetermined
R/W
R/W
DMAC1
2
1
0
R/W
R/W
R/W
Note: Bit functions are the same as for DMAC0.
DTCR1B⎯Data Transfer Control Register 1B
H'FFF3F
DMAC1
• Short address mode
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTS1
DTS0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
7
6
5
4
3
2
1
0
DTME
⎯
DAID
DAIDE
TMS
DTS2B
DTS1B
DTS0B
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
• Full address mode
Bit
Initial value
Read/Write
Note: Bit functions are the same as for DMAC0.
Rev.5.00 Sep. 12, 2007 Page 676 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
TSTR⎯Timer Start Register
Bit
Initial value
Read/Write
H'FFF60
16-Bit Timer (Common)
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
STR2
STR1
STR0
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
0
R/W
0
R/W
0
R/W
Reserved bits
Counter start 0
0
16TCNT0 count halted
1
16TCNT0 counting
(Initial value)
Counter start 1
0
16TCNT1 count halted
1
16TCNT1 counting
(Initial value)
Counter start 2
0
16TCNT2 count halted (Initial value)
1
16TCNT2 countIng
Rev.5.00 Sep. 12, 2007 Page 677 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
TSNC⎯Timer Syncro Register
Bit
Initial value
Read/Write
H'FFF61
16-Bit Timer (Common)
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
SYNC2
SYNC1
SYNC0
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
0
R/W
0
R/W
0
R/W
Reserved bits
Timer sync 0
0
Channel 0 timer counter (16TCNT0) operates independently
(16TCNT0 presetting/clearing unrelated to other channels) (Initial value)
1
Channel 0 operates synchronously
16TCNT0 synchronous presetting/synchronous clearing possible
Timer sync 1
0
Channel 1 timer counter (16TCNT1) operates independently
(16TCNT1 presetting/clearing unrelated to other channels) (Initial value)
1
Channel 1 operates synchronously
16TCNT1 synchronous presetting/synchronous clearing possible
Timer sync 2
0
Channel 2 timer counter (16TCNT2) operates independently
(16TCNT2 presetting/clearing unrelated to other channels) (Initial value)
1
Channel 2 operates synchronously
16TCNT2 synchronous presetting/synchronous clearing possible
Rev.5.00 Sep. 12, 2007 Page 678 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
TMDR⎯Timer Mode Register
H'FFF62
16-Bit Timer (Common)
7
6
5
4
3
2
1
0
⎯
MDF
FDIR
⎯
⎯
PWM2
PWM1
PWM0
Initial value
1
0
R/W
1
⎯
0
R/W
1
Read/Write
⎯
⎯
0
R/W
0
R/W
0
R/W
Bit
PWM mode 0
0
Normal operation selected for channel 0
1
PWM mode selected for channel 0
(Initial value)
PWM mode 1
0
Normal operation selected for channel 1
1
PWM mode selected for channel 1
(Initial value)
PWM mode 2
0
Normal operation selected for channel 2
1
PWM mode selected for channel 2
(Initial value)
Flag direction
0
TISRC OVF flag set to 1 when 16TCNT2 overflows or underflows
1
TISRC OVF flag set to 1 when 16TCNT2 overflows
(Initial value)
Phase counting mode
0
Normal operation selected for channel 2
(Initial value)
1
Phase counting mode selected for channel 2
Rev.5.00 Sep. 12, 2007 Page 679 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
TOLR⎯Timer Output Level Setting Register
Bit
Initial value
Read/Write
H'FFF63
16-Bit Timer (Common)
7
6
5
4
3
2
1
0
⎯
⎯
TOB2
TOA2
TOB1
TOA1
TOB0
TOA0
1
1
⎯
⎯
0
W
0
W
0
W
0
W
0
W
0
W
Output level setting A0
0
TIOCA0 set to 0 output
1
TIOCA0 set to 1 output
Output level setting B0
0
TIOCB0 set to 0 output
1
TIOCB0 set to 1 output
(Initial value)
Output level setting A1
0
TIOCA1 set to 0 output
1
TIOCA1 set to 1 output
(Initial value)
Output level setting B1
0
TIOCB1 set to 0 output
1
TIOCB1 set to 1 output
(Initial value)
Output level setting A2
0
TIOCA2 set to 0 output
1
TIOCA2 set to 1 output
(Initial value)
Output level setting B2
0
TIOCB2 set to 0 output
1
TIOCB2 set to 1 output
(Initial value)
Rev.5.00 Sep. 12, 2007 Page 680 of 764
REJ09B0396-0500
(Initial value)
Appendix B Internal I/O Registers
TISRA⎯Timer Interrupt Status Register A
Bit
7
⎯
6
5
4
H'FFF64
3
2
⎯
IMIEA2 IMIEA1 IMIEA0
Initial value
1
0
0
0
1
Read/Write
⎯
R/W
R/W
R/W
⎯
1
16-Bit Timer (Common)
0
IMFA2 IMFA1 IMFA0
0
0
0
R/(W)* R/(W)* R/(W)*
Input capture/compare match flag A0
0
[Clearing conditions]
(Initial value)
• Read IMFA0 when IMFA0 =1, then write 0 in IMFA0
• DMAC activated by IMIA0 interrupt
1
[Setting conditions]
• 16TCNT0 = GRA0 when GRA0 functions as an output
compare register.
• 16TCNT0 value is transferred to GRA0 by an input
capture signal when GRA0 functions as an input
capture register.
Input capture/compare match flag A1
0
[Clearing conditions]
(Initial value)
• Read IMFA1 when IMFA1 =1, then write 0 in IMFA1
• DMAC activated by IMIA1 interrupt
1
[Setting conditions]
• 16TCNT1 = GRA1 when GRA1 functions as an output
compare register
• 16TCNT1 value is transferred to GRA1 by an input capture
signal when GRA1 functions as an input capture register
Input capture/compare match flag A2
0
[Clearing conditions]
(Initial value)
• Read IMFA2 when IMFA2 =1, then write 0 in IMFA2
• DMAC activated by IMIA2 interrupt
1
[Setting conditions]
• 16TCNT2 = GRA2 when GRA2 functions as an output
compare register
• 16TCNT2 value is transferred to GRA2 by an input capture
signal when GRA2 functions as an input capture register
Input capture/compare match interrupt enable A0
0
IMIA0 interrupt requested by IMFA0 flag is disabled
1
IMIA0 interrupt requested by IMFA0 flag is enabled
(Initial value)
Input capture/compare match interrupt enable A1
0
IMIA1 interrupt requested by IMFA1 flag is disabled
1
IMIA1 interrupt requested by IMFA1 flag is enabled
(Initial value)
Input capture/compare match interrupt enable A2
0
IMIA2 interrupt requested by IMFA2 flag is disabled
1
IMIA2 interrupt requested by IMFA2 flag is enabled
(Initial value)
Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 681 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
TISRB⎯Timer Interrupt Status Register B
Bit
7
⎯
6
5
4
H'FFF65
3
2
⎯
IMIEB2 IMIEB1 IMIEB0
Initial value
1
0
0
0
1
Read/Write
⎯
R/W
R/W
R/W
⎯
1
16-Bit Timer (Common)
0
IMFB2 IMFB1 IMFB0
0
0
0
R/(W)* R/(W)* R/(W)*
Input capture/compare match flag B0
0
[Clearing condition]
(Initial value)
Read IMFB0 when IMFB0 =1, then write 0 in IMFB0
1
[Setting conditions]
• 16TCNT0 = GRB0 when GRB0 functions as an
output compare register.
• 16TCNT0 value is transferred to GRB0 by an input
capture signal when GRB0 functions as an input
capture register.
Input capture/compare match flag B1
0
[Clearing condition]
(Initial value)
Read IMFB1 when IMFB1 =1, then write 0 in IMFB1
1
[Setting conditions]
• 16TCNT1 = GRB1 when GRB1 functions as an output
compare register
• 16TCNT1 value is transferred to GRB1 by an input capture
signal when GRB1 functions as an input capture register
Input capture/compare match flag B2
0
[Clearing condition]
(Initial value)
Read IMFB2 when IMFB2 =1, then write 0 in IMFB2
1
[Setting conditions]
• 16TCNT2 = GRB2 when GRB2 functions as an output
compare register
• 16TCNT2 value is transferred to GRB2 by an input capture
signal when GRB2 functions as an input capture register
Input capture/compare match interrupt enable B0
0
IMIB0 interrupt requested by IMFB0 flag is disabled
1
IMIB0 interrupt requested by IMFB0 flag is enabled
(Initial value)
Input capture/compare match interrupt enable B1
0
IMIB1 interrupt requested by IMFB1 flag is disabled
1
IMIB1 interrupt requested by IMFB1 flag is enabled
(Initial value)
Input capture/compare match interrupt enable B2
0
IMIB2 interrupt requested by IMFB2 flag is disabled
1
IMIB2 interrupt requested by IMFB2 flag is enabled
Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 682 of 764
REJ09B0396-0500
(Initial value)
Appendix B Internal I/O Registers
TISRC⎯Timer Interrupt Status Register C
Bit
7
⎯
Initial value
1
Read/Write
⎯
6
5
4
R/W
16-Bit Timer (Common)
3
2
1
0
⎯
OVF2
OVF1
OVF0
0
0
1
0
0
0
R/W
R/W
⎯
OVIE2 OVIE1 OVIE0
0
H'FFF66
R/(W)* R/(W)* R/(W)*
Overflow flag 0
0
[Clearing condition]
(Initial value)
Read OVF0 when OVF0 =1, then write 0 in OVF0
1
[Setting condition]
16TCNT0 overflowed from H'FFFF to H'0000
Overflow flag 1
0
[Clearing condition]
(Initial value)
Read OVF1 when OVF1 =1, then write 0 in OVF1
1
[Setting condition]
16TCNT1 overflowed from H'FFFF to H'0000
Overflow flag 2
0
1
[Clearing condition]
(Initial value)
Read OVF2 when OVF2 =1, then write 0 in OVF2
[Setting condition]
16TCNT2 overflowed from H'FFFF to H'0000 or
underflowed from H'0000 to H'FFFF
Overflow interrupt enable 0
0
OVI0 interrupt requested by OVF0 flag is disabled
1
OVI0 interrupt requested by OVF0 flag is enabled
(Initial value)
Overflow interrupt enable 1
0
OVI1 interrupt requested by OVF1 flag is disabled
1
OVI1 interrupt requested by OVF1 flag is enabled
(Initial value)
Overflow interrupt enable 2
0
OVI2 interrupt requested by OVF2 flag is disabled
1
OVI2 interrupt requested by OVF2 flag is enabled
(Initial value)
Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 683 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
16TCR0⎯Timer Control Register 0
Bit
7
⎯
6
H'FFF68
5
4
3
16-Bit Timer Channel 0
2
1
0
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value
1
0
0
0
0
0
0
0
Read/Write
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer prescaler 2 to 0
Bit 2
Bit 1
Bit 0
TPSC2
TPSC1
TPSC0
0
0
1
0
1
1
0
1
0
1
0
1
0
1
Description
Internal clock: Counts on φ
(Initial value)
Internal clock: Counts on φ/2
Internal clock: Counts on φ/4
Internal clock: Counts on φ/8
External clock A: Counts on TCLKA pin input
External clock B: Counts on TCLKB pin input
External clock C: Counts on TCLKC pin input
External clock D: Counts on TCLKD pin input
Clock edge 1 and 0
Bit 4
Bit 3
CKEG1
CKEG0
0
0
0
1
1
⎯
Description
Counts on rising edge
Counts on falling edge
Counts on both rising and falling edges
(Initial value)
Counter clear 1 and 0
Bit 6
Bit 5
CCLR1
CCLR0
0
1
0
1
0
1
Description
16TCNT clearing disabled
(Initial value)
16TCNT cleared by GRA compare match/input capture
16TCNT cleared by GRB compare match/input capture
Synchronous clear. 16TCNT cleared in synchronization with counter
clearing of other timers operating synchronously.
Rev.5.00 Sep. 12, 2007 Page 684 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
TIOR0⎯Timer I/O Control Register 0
Bit
H'FFF69
16-Bit Timer Channel 0
7
6
5
4
3
2
1
0
⎯
IOB2
IOB1
IOB0
⎯
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
⎯
R/W
R/W
R/W
⎯
R/W
R/W
R/W
I/O control A2 to A0
Bit 2
Bit 1
Bit 0
IOA2
IOA1
IOA0
0
1
0
0
0
1
1
0
1
0
1
0
1
1
Description
GRA is output
Pin output at compare match disabled (Initial value)
compare register 0 output at GRA compare match
1 output at GRA compare match
Toggle output at GRA compare match
(1 output on channel 2 only)
GRA is input
capture register
Input capture in GRA at rising edge
Input capture in GRA at falling edge
Input capture at both rising and falling edges
I/O control B2 to B0
Bit 6
Bit 5
Bit 4
IOB2
IOB1
IOB0
0
1
0
0
0
1
1
0
1
0
1
0
1
1
Description
GRB is output
Pin output at compare match disabled (Initial value)
compare register 0 output at GRB compare match
1 output at GRB compare match
Toggle output at GRB compare match
(1 output on channel 2 only)
GRB is input
capture register
Input capture in GRB at rising edge
Input capture in GRB at falling edge
Input capture at both rising and falling edges
16TCNT0H/L⎯Timer Counter 0H/L
Bit
Initial value
Read/Write
15
14
13
12
11
H'FFF6A
H'FFF6B
10
9
8
7
16-Bit Timer Channel 0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up-counter
Rev.5.00 Sep. 12, 2007 Page 685 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
GRA0H/L⎯General Register A0 H/L
Bit
Initial value
Read/Write
15
14
13
12
11
H'FFF6C
H'FFF6D
10
9
8
7
16-Bit Timer Channel 0
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare/input capture dual-function register
GRB0H/L⎯General Register B0 H/L
Bit
Initial value
Read/Write
15
14
13
12
11
H'FFF6E
H'FFF6F
10
9
8
7
16-Bit Timer Channel 0
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare/input capture dual-function register
16TCR1⎯Timer Control Register 1
Bit
Initial value
Read/Write
H'FFF70
16-Bit Timer Channel 1
7
6
5
4
3
2
1
0
⎯
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
1
⎯
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W
0
Note: Bit functions are the same as for 16-bit timer channel 0.
TIOR1⎯Timer I/O Control Register 1
Bit
Initial value
Read/Write
H'FFF71
16-Bit Timer Channel 1
7
6
5
4
3
2
1
0
⎯
IOB2
IOB1
IOB0
⎯
IOA2
IOA1
IOA0
1
⎯
0
R/W
0
R/W
0
R/W
1
⎯
0
R/W
0
R/W
0
R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
Rev.5.00 Sep. 12, 2007 Page 686 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
16TCNT1H/L⎯Timer Counter 1H/L
Bit
Initial value
Read/Write
15
14
13
12
11
H'FFF72
H'FFF73
10
9
8
7
6
16-Bit Timer Channel 1
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
GRA1H/L⎯General Register A1 H/L
Bit
Initial value
Read/Write
15
14
13
12
11
H'FFF74
H'FFF75
10
9
8
7
6
16-Bit Timer Channel 1
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
GRB1H/L⎯General Register B1 H/L
Bit
Initial value
Read/Write
15
14
13
12
11
H'FFF76
H'FFF77
10
9
8
7
6
16-Bit Timer Channel 1
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
16TCR2⎯Timer Control Register 2
Bit
Initial value
Read/Write
H'FFF78
16-Bit Timer Channel 2
7
6
5
4
3
2
1
0
⎯
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
1
⎯
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Notes: 1. Bit functions are the same as for 16-bit timer channel 0.
2. The settings of bits CKEG1 and CKEG0 and bits TPSC2 to TPSC0 in 16TCR2 are invalid when phase
counting mode is selected for channel 2.
Rev.5.00 Sep. 12, 2007 Page 687 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
TIOR2⎯Timer I/O Control Register 2
Bit
Initial value
Read/Write
H'FFF79
16-Bit Timer Channel 2
7
6
5
4
3
2
1
0
⎯
IOB2
IOB1
IOB0
⎯
IOA2
IOA1
IOA0
1
⎯
0
0
0
0
0
0
R/W
R/W
R/W
1
⎯
R/W
R/W
R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
16TCNT2H/L⎯Timer Counter 2H/L
Bit
Initial value
Read/Write
15
14
13
12
11
H'FFF7A
H'FFF7B
10
9
8
7
6
16-Bit Timer Channel 2
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Phase counting mode: Up/down-counter
Other modes: Up-counter
GRA2H/L⎯General Register A2 H/L
Bit
Initial value
Read/Write
15
14
13
12
11
H'FFF7C
H'FFF7D
10
9
8
7
6
16-Bit Timer Channel 2
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
GRB2H/L⎯General Register B2 H/L
Bit
Initial value
Read/Write
H'FFF7E
H'FFF7F
16-Bit Timer Channel 2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for 16-bit timer channel 0.
Rev.5.00 Sep. 12, 2007 Page 688 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
8TCR0⎯Timer Control Register 0
8TCR1⎯Timer Control Register 1
Bit
Initial value
Read/Write
H'FFF80
H'FFF81
8-bit timer channel 0
8-bit timer channel 1
7
6
5
4
3
2
1
0
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Clock select 2 to 0
0
0
0
Clock input is disabled
1
Internal clock, counted on rising
edge of φ/8
0
Internal clock, counted on rising
edge of φ/64
1
Internal clock, counted on rising
edge of φ/8192
0
Channel 0:
Count on 8TCNT1 overflow signal*
Channel 1:
Count on 8TCNT0 compare match
A*
1
External clock, counted on falling edge
0
External clock, counted on rising edge
1
External clock, counted on both
rising and falling edges
1
0
1
1
Note: * If the clock input of channel 0 is the 8TCNT1
overflow signal and that of channel 1 is the
8TCNT0 compare match signal, no
incrementing clock is generated. Do not use
this setting.
Counter clear 1 and 0
0
1
0
Clearing is disabled
1
Cleared by compare match A
0
Cleared by compare match B/input capture B
1
Cleared by input capture B
Timer overflow interrupt enable
0
OVI interrupt requested by OVF is disabled
1
OVI interrupt requested by OVF is enabled
Compare match interrupt enable A
0
CMIA interrupt requested by CMFA is disabled
1
CMIA interrupt requested by CMFA is enabled
Compare match interrupt enable B
0
CMIB interrupt requested by CMFB is disabled
1
CMIB interrupt requested by CMFB is enabled
Rev.5.00 Sep. 12, 2007 Page 689 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
8TCSR0⎯Timer Control/Status Register 0
Bit
Initial value
Read/Write
H'FFF82
8-bit timer channel 0
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ADTE
OIS3
OIS2
OS1
OS0
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Output select A1 and A0
Bit 1 Bit 0
Description
OS1
OS0
0
0
No change at compare match A
1
0 output at compare match A
0
1 output at compare match A
1
Output toggles at compare
match A
1
Output/input capture edge select B3 and B2
ICE in Bit 3
8TCSR1 OIS3
Bit 2
Description
OIS2
0
0
1
0
1
1
0
No change at compare match B
1
0 output at compare match B
0
1 output at compare match B
1
Output toggles at compare match B
0
TCORB input capture on rising edge
1
TCORB input capture on falling edge
0
TCORB input capture on both rising
and falling edges
1
A/D trigger enable
TRGE*
Bit 4
Description
ADTE
0
0
1
0
1
1
A/D converter start requests by compare match
A or an external trigger are disabled
A/D converter start requests by compare match
A or an external trigger are enabled
A/D converter start requests by an external trigger are enabled, and
A/D converter start requests by compare match A are disabled
A/D converter start requests by compare match A are enabled, and
A/D converter start requests by an external trigger are disabled
Note: * TRGE is bit 7 of the A/D control register (ADCR).
Timer overflow flag
0
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF.
1
[Setting condition]
8TCNT overflows from H'FF to H'00.
Compare match flag A
0
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA.
1
[Setting condition]
8TCNT = TCORA
Compare match/input capture flag B
0
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB.
1
[Setting conditions]
• 8TCNT = TCORB
• The 8TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register.
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Rev.5.00 Sep. 12, 2007 Page 690 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
8TCSR1⎯Timer Control/Status Register 1
Bit
Initial value
Read/Write
H'FFF83
8-bit timer channel 1
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ICE
OIS3
OIS2
OS1
OS0
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Output select A1 and A0
Bit 1 Bit 0
Description
OS1
OS0
0
0
No change at compare match A
1
0 output at compare match A
0
1 output at compare match A
1
1
Output toggles at compare
match A
Output/input capture edge select B3 and B2
ICE in Bit 3
8TCSR1 OIS3
0
0
Bit 2
0
No change at compare match B
1
0 output at compare match B
0
1 output at compare match B
1
Output toggles at compare match
B
1
0
0
1
1
1
Description
OIS2
0
1
TCORB input capture on rising
edge
TCORB input capture on falling
edge
TCORB input capture on both
rising and falling edges
Input capture enable
0
TCORB is a compare match register
1
TCORB is an input capture register
Timer overflow flag
0
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF.
1
[Setting condition]
8TCNT overflows from H'FF to H'00.
Compare match flag A
0
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA.
1
[Setting condition]
8TCNT = TCORA
Compare match/input capture flag B
0
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB.
1
[Setting conditions]
• 8TCNT = TCORB
• The 8TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register.
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Rev.5.00 Sep. 12, 2007 Page 691 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
TCORA0⎯Timer Constant Register A0
TCORA1⎯Timer Constant Register A1
H'FFF84
H'FFF85
8-bit timer channel 0
8-bit timer channel 1
TCORA0
Bit
Initial value
Read/Write
15
1
TCORA1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB0⎯Timer Constant Register B0
TCORB1⎯Timer Constant Register B1
H'FFF86
H'FFF87
8-bit timer channel 0
8-bit timer channel 1
TCORB0
Bit
Initial value
Read/Write
15
14
13
12
11
TCORB1
10
9
8
7
6
5
H'FFF88
H'FFF89
2
1
0
8-bit timer channel 0
8-bit timer channel 1
8TCNT0
Initial value
Read/Write
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
8TCNT0⎯Timer Counter 0
8TCNT1⎯Timer Counter 1
Bit
4
15
14
13
12
11
8TCNT1
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.5.00 Sep. 12, 2007 Page 692 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
TCSR⎯Timer Control/Status Register
WDT
7
6
5
4
3
2
1
0
OVF
WT/IT
TME
⎯
⎯
CKS2
CKS1
CKS0
0
R/(W)*
0
R/W
0
R/W
1
⎯
1
⎯
0
R/W
0
R/W
0
R/W
Bit
Initial value
Read/Write
H'FFF8C
Clock select 2 to 0
CKS2 CKS1 CKS0
0
0
1
0
1
1
Description
0
φ/2
1
φ/32
0
φ/64
1
φ/128
0
φ/256
1
φ/512
0
φ/2048
1
φ/4096
Timer enable
Timer disabled
0
• TCNT is initialized to H'00 and
halted
Timer enabled
1
• TCNT is counting
Timer mode select
0
Interval timer:
requests interval timer interrupts
Watchdog timer:
1
generates a reset signal
Overflow flag
0
1
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
[Setting condition]
TCNT changes from H'FF to H'00
Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 693 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
TCNT⎯Timer Counter
Bit
Initial value
Read/Write
H'FFF8D (read), H'FFF8C (write)
WDT
7
6
5
4
3
2
1
0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Count value
RSTCSR⎯Reset Control/Status Register
Bit
Initial value
Read/Write
H'FFF8F (read), H'FFF8E (write)
WDT
7
6
5
4
3
2
1
0
WRST
RSTOE
⎯
⎯
⎯
⎯
⎯
⎯
0
R/(W)*
0
R/W
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
Reset output enable
0
External output of reset signal is disabled
1
External output of reset signal is enabled
Watchdog timer reset
0
[Clearing conditions]
• Reset signal at RES pin
• Read WRST when WRST = 1, then write 0 in WRST
[Setting condition]
1
TCNT overflow generates a reset signal
Note: * Only 0 can be written in bit 7, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 694 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
8TCR2⎯Timer Control Register 2
8TCR3⎯Timer Control Register 3
Bit
Initial value
Read/Write
H'FFF90
H'FFF91
8-bit timer channel 2
8-bit timer channel 3
7
6
5
4
3
2
1
0
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Clock select 2 to 0
CKS2 CKS1 CKS0
Clock input is disabled
1
Internal clock, counted on rising edge
of φ/8
0
Internal clock, counted on rising edge
of φ/64
1
Internal clock, counted on rising edge
of φ/8192
0
Channel 2:
Count on 8TCNT3 overflow signal*
Channel 3:
Count on 8TCNT2 compare match A*
1
External clock, counted on falling edge
0
External clock, counted on rising edge
1
External clock, counted on both
rising and falling edges
0
0
1
0
1
Description
0
1
Note: * If the clock input of channel 2 is the 8TCNT3 overflow
signal and that of channel 3 is the 8TCNT2 compare
match signal, no incrementing clock is generated. Do
not use this setting.
Counter clear 1 and 0
0
1
0
Clearing is disabled
1
Cleared by compare match A
0
Cleared by compare match B/input capture B
1
Cleared by input capture B
Timer overflow interrupt enable
0
OVI interrupt requested by OVF is disabled
1
OVI interrupt requested by OVF is enabled
Compare match interrupt enable A
0
CMIA interrupt requested by CMFA is disabled
1
CMIA interrupt requested by CMFA is enabled
Compare match interrupt enable B
0
CMIB interrupt requested by CMFB is disabled
1
CMIB interrupt requested by CMFB is enabled
Rev.5.00 Sep. 12, 2007 Page 695 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
8TCSR2⎯Timer Control/Status Register 2
8TCSR3⎯Timer Control/Status Register 3
8TCSR2
Bit
Initial value
Read/Write
8TCSR3
Bit
Initial value
Read/Write
H'FFF92
H'FFF93
8-bit timer channel 2
8-bit timer channel 3
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
⎯
OIS3
OIS2
OS1
OS0
0
R/(W)*
0
R/(W)*
0
R/(W)*
1
⎯
0
R/W
0
R/W
0
R/W
0
R/W
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ICE
OIS3
OIS2
OS1
OS0
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Output select A1 and A0
Bit 1 Bit 0
Description
OS1
OS0
0
0
No change at compare match A
1
0 output at compare match A
0
1 output at compare match A
1
Output toggles at compare
match A
1
Output/input capture edge select B3 and B2
ICE in Bit 3
8TCSR3 OIS3
Bit 2
Description
OIS2
0
0
0
No change at compare match B
1
0 output at compare match B
0
1 output at compare match B
1
1
0
0
1
1
Output toggles at compare match
B
TCORB input capture on rising
edge
1
TCORB input capture on falling
edge
0
1
TCORB input capture on both
rising and falling edges
Input capture enable
0
TCORB is a compare match register
1
TCORB is an input capture register
Timer overflow flag
0
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF.
1
[Setting condition]
8TCNT overflows from H'FF to H'00.
Compare match/input capture flag A
0
1
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA.
[Setting condition]
8TCNT = TCORA
Compare match/input capture flag B
0
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB.
1
[Setting conditions]
• 8TCNT = TCORB
• The 8TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register.
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Rev.5.00 Sep. 12, 2007 Page 696 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
TCORA2⎯Timer Constant Register A2
TCORA3⎯Timer Constant Register A3
H'FFF94
H'FFF95
8-bit timer channel 2
8-bit timer channel 3
TCORA2
Bit
Initial value
Read/Write
15
1
TCORA3
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB2⎯Timer Constant Register B2
TCORB3⎯Timer Constant Register B3
H'FFF96
H'FFF97
8-bit timer channel 2
8-bit timer channel 3
TCORB2
Bit
Initial value
Read/Write
15
14
13
12
TCORB3
11
10
9
8
7
6
5
4
H'FFF98
H'FFF99
Initial value
Read/Write
0
15
14
13
12
8TCNT3
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DADR0⎯D/A Data Register 0
Bit
1
8-bit timer channel 2
8-bit timer channel 3
8TCNT2
Initial value
Read/Write
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
8TCNT2⎯Timer Counter 2
8TCNT3⎯Timer Counter 3
Bit
3
H'FFF9C
D/A
7
6
5
4
3
2
1
0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
D/A conversion data
Rev.5.00 Sep. 12, 2007 Page 697 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
DADR1⎯D/A Data Register 1
Bit
Initial value
Read/Write
H'FFF9D
D/A
7
6
5
4
3
2
1
0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
D/A conversion data
Rev.5.00 Sep. 12, 2007 Page 698 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
DACR⎯D/A Control Register
D/A
7
6
5
4
3
2
1
0
DAOE1
DAOE0
DAE
⎯
⎯
⎯
⎯
⎯
0
R/W
0
R/W
0
R/W
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
Bit
Initial value
Read/Write
H'FFF9E
D/A enable
Bit 7
Bit 6
Bit 5
DAOE1
DAOE0
DAE
0
0
⎯
Description
D/A conversion is disabled
in channels 0 and 1
D/A conversion is enabled
in channel 0
0
1
0
D/A conversion is disabled
in channel 1
0
1
1
1
0
0
D/A conversion is enabled
in channels 0 and 1
D/A conversion is disabled
in channel 0
D/A conversion is enabled
in channel 1
1
0
1
D/A conversion is enabled
in channels 0 and 1
1
1
⎯
D/A conversion is enabled
in channels 0 and 1
D/A output enable 0
0
DA0 analog output is disabled
1
Channel-0 D/A conversion and DA0
analog output are enabled
D/A output enable 1
0
DA1 analog output is disabled
1
Channel-1 D/A conversion and DA1
analog output are enabled
Rev.5.00 Sep. 12, 2007 Page 699 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
TPMR⎯TPC Output Mode Register
Bit
Initial value
Read/Write
H'FFFA0
TPC
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
G3NOV
G2NOV
G1NOV
G0NOV
1
⎯
1
⎯
1
⎯
1
⎯
0
R/W
0
R/W
0
R/W
0
R/W
Group 0 non-overlap
0
Normal TPC output in group 0. Output values
change at compare match A in the selected
16-bit timer channel
1
Non-overlapping TPC output in group 0,
controlled by compare match A and B in the
selected 16-bit timer channel
Group 1 non-overlap
0
Normal TPC output in group 1. Output values change
at compare match A in the selected 16-bit timer channel
1
Non-overlapping TPC output in group 1, controlled by
compare match A and B in the selected 16-bit timer channel
Group 2 non-overlap
0
Normal TPC output in group 2. Output values change at
compare match A in the selected 16-bit timer channel
1
Non-overlapping TPC output in group 2, controlled by
compare match A and B in the selected 16-bit timer channel
Group 3 non-overlap
0
Normal TPC output in group 3. Output values change at
compare match A in the selected 16-bit timer channel
1
Non-overlapping TPC output in group 3, controlled by
compare match A and B in the selected 16-bit timer channel
Rev.5.00 Sep. 12, 2007 Page 700 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
TPCR⎯TPC Output Control Register
H'FFFA1
TPC
7
6
5
4
3
2
1
0
G3CMS1
G3CMS0
G2CMS1
G2CMS0
G1CMS1
G1CMS0
G0CMS1
G0CMS0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Bit
Initial value
Read/Write
Group 0 compare match select 1 and 0
Bit 1
Bit 0
G0CMS1 G0CMS0
0
0
1
0
1
1
16-Bit Timer Channel Selected as Output Trigger
TPC output group 0 (TP3 to TP0) is triggered by
compare match in 16-bit timer channel 0
TPC output group 0 (TP3 to TP0) is triggered by
compare match in 16-bit timer channel 1
TPC output group 0 (TP3 to TP0) is triggered by
compare match in 16-bit timer channel 2
Group 1 compare match select 1 and 0
Bit 3
Bit 2
G1CMS1 G1CMS0
0
0
1
1
16-Bit Timer Channel Selected as Output Trigger
TPC output group 1 (TP7 to TP4) is triggered by
compare match in 16-bit timer channel 0
TPC output group 1 (TP7 to TP4) is triggered by
compare match in 16-bit timer channel 1
0
TPC output group 1 (TP7 to TP4) is triggered by
1
compare match in 16-bit timer channel 2
Group 2 compare match select 1 and 0
Bit 5
Bit 4
16-Bit Timer Channel Selected as Output Trigger
G2CMS1 G2CMS0
0
1
0
1
0
1
TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 0
TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 1
TPC output group 2 (TP11 to TP8) is triggered by compare match in 16-bit timer channel 2
Group 3 compare match select 1 and 0
Bit 7
Bit 6
G3CMS1 G3CMS0
0
1
0
1
0
1
16-Bit Timer Channel Selected as Output Trigger
TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 0
TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 1
TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit timer channel 2
Rev.5.00 Sep. 12, 2007 Page 701 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
NDERB⎯Next Data Enable Register B
Bit
Initial value
Read/Write
H'FFFA2
TPC
7
6
5
4
3
2
1
0
NDER15
NDER14
NDER13
NDER12
NDER11
NDER10
NDER9
NDER8
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Next data enable 15 to 8
Bits 7 to 0
Description
NDER15
to NDER8
TPC outputs TP15 to TP8 are disabled
0
(NDR15 to NDR8 are not transferred to PB7 to PB0)
TPC outputs TP15 to TP8 are enabled
(NDR15 to NDR8 are transferred to PB7 to PB0)
1
NDERA⎯Next Data Enable Register A
Bit
Initial value
Read/Write
H'FFFA3
TPC
7
6
5
4
3
2
1
0
NDER7
NDER6
NDER5
NDER4
NDER3
NDER2
NDER1
NDER0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Next data enable 7 to 0
Bits 7 to 0
Description
NDER7
to NDER0
TPC outputs TP7 to TP0 are disabled
0
1
(NDR7 to NDR0 are not transferred to PA7 to PA0)
TPC outputs TP7 to TP0 are enabled
(NDR7 to NDR0 are transferred to PA7 to PA0)
Rev.5.00 Sep. 12, 2007 Page 702 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
NDRB⎯Next Data Register B
H'FFFA4/H'FFFA6
TPC
• Same trigger for TPC output groups 2 and 3
⎯ Address H'FFFA4
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
NDR15
NDR14
NDR13
NDR12
NDR11
NDR10
NDR9
NDR8
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Store the next output data for TPC output group 3
Store the next output data for TPC output group 2
⎯ Address H'FFFA6
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
• Different triggers for TPC output groups 2 and 3
⎯ Address H'FFFA4
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
NDR15
NDR14
NDR13
NDR12
⎯
⎯
⎯
⎯
0
R/W
0
R/W
0
R/W
0
R/W
1
⎯
1
⎯
1
⎯
1
⎯
Store the next output data for TPC output group 3
⎯ Address H'FFFA6
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
NDR11
NDR10
NDR9
NDR8
1
⎯
1
⎯
1
⎯
1
⎯
0
R/W
0
R/W
0
R/W
0
R/W
Store the next output data for TPC output group 2
Rev.5.00 Sep. 12, 2007 Page 703 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
NDRA⎯Next Data Register A
H'FFFA5/H'FFFA7
TPC
• Same trigger for TPC output groups 0 and 1
⎯ Address H'FFFA5
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Store the next output data for TPC output group 1
Store the next output data for TPC output group 0
⎯ Address H'FFFA7
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
• Different triggers for TPC output groups 0 and 1
⎯ Address H'FFFA5
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
⎯
⎯
⎯
⎯
0
R/W
0
R/W
0
R/W
0
R/W
1
⎯
1
⎯
1
⎯
1
⎯
Store the next output data for TPC output group 1
⎯ Address H'FFFA7
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
NDR3
NDR2
NDR1
NDR0
1
⎯
1
⎯
1
⎯
1
⎯
0
R/W
0
R/W
0
R/W
0
R/W
Store the next output data for TPC output group 0
Rev.5.00 Sep. 12, 2007 Page 704 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
SMR⎯Serial Mode Register
SCI0
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Initial value
Read/Write
H'FFFB0
Clock select 1 and 0
Bit 1 Bit 0
CKS1 CKS0
0
1
Clock Source
0
φ clock
1
φ/4 clock
0
φ/16 clock
1
φ/64 clock
Multiprocessor mode
0
1
Multiprocessor function disabled
Multiprocessor function selected
Stop bit length
0
One stop bit
1
Two stop bits
Parity mode
0
Even parity
1
Odd parity
Parity enable
0
Parity bit is not added or checked
1
Parity bit is added and checked
Character length
0
8-bit data
1
7-bit data
Communication mode (for serial communication interface)
0
Asynchronous mode
1
Synchronous mode
GSM mode (for smart card interface)
0
TEND flag is set 12.5 etu* after start bit
1
TEND flag is set 11.0 etu* after start bit
Note: * etu: Elementary time unit (time required to transmit one bit)
Rev.5.00 Sep. 12, 2007 Page 705 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
BRR⎯Bit Rate Register
Bit
Initial value
Read/Write
H'FFFB1
SCI0
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Serial communication bit rate setting
Rev.5.00 Sep. 12, 2007 Page 706 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
SCR⎯Serial Control Register
Bit
Initial value
Read/Write
H'FFFB2
SCI0
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Clock enable 1 and 0
(for serial communication interface)
Bit 1 Bit 0
Description
CKE1 CKE0
Internal clock, SCK pin
Asynchronous mode
available for generic I/O
0
Internal clock, SCK pin
Synchronous mode
used for serial clock output
0
Internal clock, SCK pin
Asynchronous mode
used for clock output
1
Internal clock, SCK pin
Synchronous mode
used for serial clock output
External clock, SCK pin
Asynchronous mode
used for clock input
0
External clock, SCK pin
Synchronous mode
used for serial clock input
1
External clock, SCK pin
Asynchronous mode
used for clock input
1
External clock, SCK pin
Synchronous mode
used for serial clock input
Receive enable
0
1
Receiving is
disabled
Receiving is
enabled
Transmit enable
0
1
Transmitting is disabled
Transmitting is enabled
Clock enable 1 and 0 (for smart card interface)
SMR Bit 1 Bit 0
Description
GM CKE1 CKE0
SCK pin available for generic I/O
0
0
0
SCK pin used for clock output
1
SCK pin output fixed low
0
0
SCK pin used for clock output
1
1
SCK pin output fixed high
0
1
SCK pin used for clock output
1
Transmit-end interrupt enable
0
1
Transmit-end interrupt requests (TEI) are disabled
Transmit-end interrupt requests (TEI) are enabled
Multiprocessor interrupt enable
0
1
Multiprocessor interrupts are disabled (normal receive operation)
Multiprocessor interrupts are enabled
Receive interrupt enable
0
Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled
1
Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled
Transmit interrupt enable
0
Transmit-data-empty interrupt request (TXI) is disabled
1
Transmit-data-empty interrupt request (TXI) is enabled
Rev.5.00 Sep. 12, 2007 Page 707 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
TDR⎯Transmit Data Register
Bit
Initial value
Read/Write
H'FFFB3
SCI0
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Serial transmit data
Rev.5.00 Sep. 12, 2007 Page 708 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
SSR⎯Serial Status Register
SCI0
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER/ERS
PER
TEND
MPB
MPBT
1
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
1
R
0
R
0
R/W
Bit
Initial value
Read/Write
H'FFFB4
Multiprocessor bit transfer
0 Multiprocessor bit value in transmit data is 0
1 Multiprocessor bit value in transmit data is 1
Multiprocessor bit
0
1
Multiprocessor bit value in receive data is 0
Multiprocessor bit value in receive data is 1
Transmit end (for serial communication interface)
0
[Clearing conditions]
• Read TDRE when TDRE = 1, then write 0 in TDRE.
• The DMAC writes data in TDR.
1
[Setting conditions]
• Reset or transition to standby mode
• TE is cleared to 0 in SCR.
• TDRE is 1 when last bit of 1-byte serial character is
transmitted.
Transmit end (for smart card interface)
0
[Clearing conditions]
• Read TDRE when TDRE = 1, then write 0 in TDRE.
• The DMAC writes data in TDR.
1
[Setting conditions]
• Reset or transition to standby mode
• TE is cleared to 0 in SCR and FER/ERS is cleared to 0.
• TDRE is 1 and FER/ERS is 0 (normal transmission)
2.5 etu* (when GM = 0) or 1.0 etu (when GM = 1) after
1-byte serial character is transmitted.
Note: * etu: Elementary time unit (time required to transmit one bit)
Parity error
0
1
[Clearing conditions] • Reset or transition to standby mode
• Read PER when PER = 1, then write 0 in PER.
[Setting condition]
Parity error (parity of receive data does not match parity
setting of O/E bit in SMR)
Framing error (for serial communication interface)
0
1
[Clearing conditions] • Reset or transition to standby mode
• Read FER when FER = 1, then write 0 in FER.
[Setting condition]
Framing error (stop bit is 0)
Error signal status (for smart card interface)
0
1
[Clearing conditions] • Reset or transition to standby mode
• Read ERS when ERS = 1, then write 0 in ERS.
[Setting condition]
A low error signal is received.
Overrun error
0
[Clearing conditions] • Reset or transition to standby mode
• Read ORER when ORER = 1, then write 0 in ORER.
1
[Setting condition]
Overrun error (reception of the next serial data ends when RDRF = 1)
Receive data register full
0
1
[Clearing conditions] • Reset or transition to standby mode
• Read RDRF when RDRF = 1, then write 0 in RDRF.
• The DMAC reads data from RDR.
[Setting condition]
Serial data is received normally and transferred from RSR to RDR.
Transmit data register empty
0
[Clearing conditions] • Read TDRE when TDRE = 1, then write 0 in TDRE.
• The DMAC writes data in TDR.
[Setting conditions]
1
• Reset or transition to standby mode
• TE is 0 in SCR.
• Data is transferred from TDR to TSR, enabling new data to be written in TDR
Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 709 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
RDR⎯Receive Data Register
H'FFFB5
SCI0
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Serial receive data
SCMR⎯Smart Card Mode Register
Bit
Initial value
Read/Write
H'FFFB6
SCI0
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
SDIR
SINV
⎯
SMIF
1
⎯
1
⎯
1
⎯
1
⎯
0
R/W
0
R/W
1
⎯
0
R/W
Smart card interface mode select
0
Smart card interface function
is disabled
(Initial value)
1
Smart card interface function
is enabled
Smart card data invert
Unmodified TDR contents are transmitted
0
1
(Initial value)
Receive data is stored unmodified in RDR
Inverted TDR contents are transmitted
Received data are inverted before storage in RDR
Smart card data transfer direction
TDR contents are transmitted LSB-first
0
1
Rev.5.00 Sep. 12, 2007 Page 710 of 764
REJ09B0396-0500
Receive data is stored LSB-first in RDR
TDR contents are transmitted MSB-first
Receive data is stored MSB-first in RDR
(Initial value)
Appendix B Internal I/O Registers
SMR⎯Serial Mode Register
Bit
Initial value
Read/Write
H'FFFB8
SCI1
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Note: Bit functions are the same as for SCI0.
BRR⎯Bit Rate Register
Bit
Initial value
Read/Write
H'FFFB9
SCI1
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Note: Bit functions are the same as for SCI0.
SCR⎯Serial Control Register
Bit
Initial value
Read/Write
H'FFFBA
SCI1
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Note: Bit functions are the same as for SCI0.
TDR⎯Transmit Data Register
Bit
Initial value
Read/Write
H'FFFBB
SCI1
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Note: Bit functions are the same as for SCI0.
Rev.5.00 Sep. 12, 2007 Page 711 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
SSR⎯Serial Status Register
Bit
Initial value
Read/Write
H'FFFBC
SCI1
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER/ERS
PER
TEND
MPB
MPBT
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
1
R
0
R
0
R/W
Notes: Bit functions are the same as for SCI0.
* Only 0 can be written, to clear the flag.
RDR⎯Receive Data Register
H'FFFBD
SCI1
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Note: Bit functions are the same as for SCI0.
SCMR⎯Smart Card Mode Register
Bit
Initial value
Read/Write
H'FFFBE
SCI1
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
SDIR
SINV
⎯
SMIF
1
⎯
1
⎯
1
⎯
1
⎯
0
R/W
0
R/W
1
⎯
0
R/W
Note: Bit functions are the same as for SCI0.
SMR⎯Serial Mode Register
Bit
Initial value
Read/Write
H'FFFC0
SCI2
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Note: Bit functions are the same as for SCI0.
Rev.5.00 Sep. 12, 2007 Page 712 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
BRR⎯Bit Rate Register
Bit
Initial value
Read/Write
H'FFFC1
SCI2
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Note: Bit functions are the same as for SCI0.
SCR⎯Serial Control Register
Bit
Initial value
Read/Write
H'FFFC2
SCI2
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Note: Bit functions are the same as for SCI0.
TDR⎯Transmit Data Register
Bit
Initial value
Read/Write
H'FFFC3
SCI2
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Note: Bit functions are the same as for SCI0.
SSR⎯Serial Status Register
Bit
Initial value
Read/Write
Notes:
H'FFFC4
SCI2
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER/ERS
PER
TEND
MPB
MPBT
1
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
1
R
0
R
0
R/W
Bit functions are the same as for SCI0.
* Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 713 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
RDR⎯Receive Data Register
H'FFFC5
SCI2
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Note: Bit functions are the same as for SCI0.
SCMR⎯Smart Card Mode Register
SCI2
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
SDIR
SINV
⎯
SMIF
1
⎯
1
⎯
1
⎯
1
⎯
0
R/W
0
R/W
1
⎯
0
R/W
Bit
Initial value
Read/Write
H'FFFC6
Note: Bit functions are the same as for SCI0.
P4DR⎯Port 4 Data Register
Bit
Initial value
Read/Write
H'FFFD3
Port 4
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 4 pins
P6DR⎯Port 6 Data Register
Bit
Initial value
Read/Write
H'FFFD5
Port 6
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P63
P62
P61
P60
*
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Data for port 6 pins
Note: * Determined by pin P67.
Rev.5.00 Sep. 12, 2007 Page 714 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
P7DR⎯Port 7 Data Register
Bit
Initial value
Read/Write
H'FFFD6
Port 7
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
⎯*
⎯*
⎯*
⎯*
⎯*
⎯*
⎯*
⎯*
R
R
R
R
R
R
R
R
Data for port 7 pins
Note: * Determined by pins P77 to P70.
P8DR⎯Port 8 Data Register
Bit
Initial value
Read/Write
H'FFFD7
Port 8
7
6
5
4
3
2
1
0
⎯
⎯
⎯
P84
P83
P82
P81
P80
1
⎯
1
⎯
1
⎯
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Data for port 8 pins
P9DR⎯Port 9 Data Register
Bit
Initial value
Read/Write
H'FFFD8
Port 9
7
6
5
4
3
2
1
0
⎯
⎯
P95
P94
P93
P92
P91
P90
1
⎯
1
⎯
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Data for port 9 pins
PADR⎯Port A Data Register
Bit
Initial value
Read/Write
H'FFFD9
Port A
7
6
5
4
3
2
1
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Data for port A pins
Rev.5.00 Sep. 12, 2007 Page 715 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
PBDR⎯Port B Data Register
Bit
Initial value
Read/Write
H'FFFDA
Port B
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Data for port B pins
ADDRA H/L⎯A/D Data Register A H/L
Bit
Initial value
Read/Write
15
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
0
R
0
R
0
R
0
R
0
R
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
R
8
0
R
7
0
R
6
A/D
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯
0
R
14
H'FFFE0, H'FFFE1
0
R
0
R
ADDRAH
ADDRAL
A/D conversion data
10-bit data giving an A/D conversion result
ADDRB H/L⎯A/D Data Register B H/L
Bit
Initial value
Read/Write
15
14
13
12
11
10
H'FFFE2, H'FFFE3
9
8
7
6
A/D
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯
⎯
⎯
⎯
⎯
⎯
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
ADDRBH
0
R
0
R
0
R
0
R
0
R
0
R
ADDRBL
A/D conversion data
10-bit data giving an A/D conversion result
Rev.5.00 Sep. 12, 2007 Page 716 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
ADDRC H/L⎯A/D Data Register C H/L
Bit
Initial value
Read/Write
15
14
13
12
11
10
H'FFFE4, H'FFFE5
9
8
7
6
A/D
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯
⎯
⎯
⎯
⎯
⎯
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
ADDRCH
ADDRCL
A/D conversion data
10-bit data giving an A/D conversion result
ADDRD H/L⎯A/D Data Register D H/L
Bit
Initial value
Read/Write
15
14
13
12
11
10
H'FFFE6, H'FFFE7
9
8
7
6
A/D
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯
⎯
⎯
⎯
⎯
⎯
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
ADDRDH
ADDRDL
A/D conversion data
10-bit data giving an A/D conversion result
ADCR⎯A/D Control Register
Bit
Initial value
Read/Write
H'FFFE9
A/D
7
6
5
4
3
2
1
0
TRGE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
R/W
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
1
⎯
0
R/W
Trigger Enable
0
A/D conversion start by external trigger or 8-bit timer
compare match is disabled
1
A/D conversion is started by falling edge of external
trigger signal (ADTRG) or 8-bit timer compare match
Rev.5.00 Sep. 12, 2007 Page 717 of 764
REJ09B0396-0500
Appendix B Internal I/O Registers
ADCSR⎯A/D Control/Status Register
A/D
7
6
5
4
3
2
1
0
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
0
R/(W)*
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Initial value
Read/Write
H'FFFE8
Channel select
Clock select
Conversion time =
Group Selection Channel Selection
Description
0
134 states (maximum)
CH2
CH1 CH0 Single Mode
Scan Mode
AN0
0
AN0
Conversion time =
1
0
1
AN1
AN0, AN1
70 states (maximum)
0
0
AN2
AN0 to AN2
1
1
AN3
AN0 to AN3
0
AN4
AN4
0
Scan mode
1
AN5
AN4, AN5
1
Single mode
0
0
AN6
AN4 to AN6
1
1
Scan mode
1
AN7
AN4 to AN7
A/D start
0 A/D conversion is stopped
1. Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends
1 2. Scan mode: A/D conversion starts and continues, cycling among the selected channels ADST
is cleared to 0 by software, by a reset, or by a transition to standby mode
A/D interrupt enable
0
1
A/D end interrupt request is disabled
A/D end interrupt request is enabled
A/D end flag
0
1
[Clearing conditions]
• Read ADF when ADF = 1, then write 0 in ADF
• The DMAC is activated by an ADI interrupt
[Setting conditions]
• Single mode: A/D conversion ends
• Scan mode: A/D conversion ends in all selected channels
Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 718 of 764
REJ09B0396-0500
Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams
Port 4 Block Diagram
Reset
16-bit bus mode
R
Q
D
P4 n PCR
C
RP4P
WP4P
Reset
R
Q
Write to external
address
Internal data bus (lower)
8-bit bus mode
Internal data bus (upper)
C.1
D
P4 n DDR
C
WP4D
Reset
R
Q
P4n
D
P4n DR
C
WP4
RP4
Read external
address
Legend:
WP4P: Write to P4PCR
RP4P: Read P4PCR
WP4D: Write to P4DDR
WP4: Write to port 4
RP4: Read port 4
Note: n = 0 to 7
Figure C.1 Port 4 Block Diagram
Rev.5.00 Sep. 12, 2007 Page 719 of 764
REJ09B0396-0500
Appendix C I/O Port Block Diagrams
C.2
Port 6 Block Diagrams
R
Q
D
P60 DDR
C
WP6D
Reset
Internal data bus
Reset
Bus controller
WAIT
input
enable
R
P60
Q
D
P60 DR
C
WP6
RP6
Bus controller
WAIT
input
Legend:
WP6D: Write to P6DDR
WP6: Write to port 6
RP6: Read port 6
Figure C.2 (a) Port 6 Block Diagram (Pin P60)
Rev.5.00 Sep. 12, 2007 Page 720 of 764
REJ09B0396-0500
Appendix C I/O Port Block Diagrams
R
Q
D
P6 1 DDR
C
WP6D
Reset
Internal data bus
Reset
Bus
controller
Bus release
enable
R
P61
Q
D
P61 DR
C
WP6
RP6
BREQ input
Legend:
WP6D: Write to P6DDR
WP6: Write to port 6
RP6: Read port 6
Figure C.2 (b) Port 6 Block Diagram (Pin P61)
Rev.5.00 Sep. 12, 2007 Page 721 of 764
REJ09B0396-0500
Appendix C I/O Port Block Diagrams
R
Q
D
P6 2 DDR
C
WP6D
Reset
Internal data bus
Reset
R
Q
P62
D
P62 DR
C
WP6
Bus controller
Bus release
enable
BACK
output
RP6
Legend:
WP6D: Write to P6DDR
WP6: Write to port 6
RP6: Read port 6
Figure C.2 (c) Port 6 Block Diagram (Pin P62)
Rev.5.00 Sep. 12, 2007 Page 722 of 764
REJ09B0396-0500
Appendix C I/O Port Block Diagrams
Hardware standby
Internal data bus
φ output enable
φ output
P67
RP6
Legend:
RP6: Read port 6
Figure C.2 (d) Port 6 Block Diagram (Pin P67)
Port 7 Block Diagrams
RP7
P7 n
Internal data bus
C.3
A/D converter
Analog input
Legend:
RP7: Read port 7
Input enable
Channel select signal
Note: n = 0 to 5
Figure C.3 (a) Port 7 Block Diagram (Pins P70 to P75)
Rev.5.00 Sep. 12, 2007 Page 723 of 764
REJ09B0396-0500
RP7
P7 n
Internal data bus
Appendix C I/O Port Block Diagrams
A/D converter
Analog input
Input enable
Channel select signal
D/A converter
Output enable
Analog output
Legend:
RP7: Read port 7
Note: n = 6 and 7
Figure C.3 (b) Port 7 Block Diagram (Pins P76 and P77)
Rev.5.00 Sep. 12, 2007 Page 724 of 764
REJ09B0396-0500
Appendix C I/O Port Block Diagrams
Port 8 Block Diagrams
Reset
R
Q
D
P80DDR
C
WP8D
Internal data bus
C.4
Reset
R
Q
D
P80DR
C
P80
WP8
Refresh controller
Output enable
RFSH
output
RP8
Interrupt controller
IRQ0 input
Legend:
WP8D: Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
Figure C.4 (a) Port 8 Block Diagram (Pin P80)
Rev.5.00 Sep. 12, 2007 Page 725 of 764
REJ09B0396-0500
SSOE
Software
standby
Reset
R
Q
D
P8nDDR
C
Internal data bus
Appendix C I/O Port Block Diagrams
Bus controller
WP8D
CS2
CS3 output
Reset
R
Q
D
P8nDR
C
P8n
WP8
RP8
Interrupt controller
IRQ1
IRQ2 input
Legend:
WP8D: Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
SSOE: Software standby output port enable
Note: n = 1 and 2
Figure C.4 (b) Port 8 Block Diagram (Pins P81, P82)
Rev.5.00 Sep. 12, 2007 Page 726 of 764
REJ09B0396-0500
SSOE
Software
standby
Reset
R
Q
D
P83DDR
C
Internal data bus
Appendix C I/O Port Block Diagrams
Bus controller
WP8D
CS1 output
Reset
R
Q
D
P83DR
C
P83
WP8
RP8
Interrupt controller
IRQ3 input
A/D converter
ADTRG input
Legend:
WP8D: Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
SSOE: Software standby output port enable
Figure C.4 (c) Port 8 Block Diagram (Pin P83)
Rev.5.00 Sep. 12, 2007 Page 727 of 764
REJ09B0396-0500
SSOE
Software
standby
Reset
R
Q
D
P84DDR
C
Internal data bus
Appendix C I/O Port Block Diagrams
Bus controller
WP8D
CS0 output
Reset
R
Q
D
P84DR
C
P84
WP8
RP8
Legend:
WP8D: Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
SSOE: Software standby output port enable
Figure C.4 (d) Port 8 Block Diagram (Pin P84)
Rev.5.00 Sep. 12, 2007 Page 728 of 764
REJ09B0396-0500
Appendix C I/O Port Block Diagrams
C.5
Port 9 Block Diagrams
Reset
Q
D
P9 0 DDR
C
WP9D
Reset
Internal data bus
R
R
Q
P90
D
P90 DR
C
WP9
SCI
Output
enable
Serial
transmit
data
Guard
time
RP9
Legend:
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
Figure C.5 (a) Port 9 Block Diagram (Pin P90)
Rev.5.00 Sep. 12, 2007 Page 729 of 764
REJ09B0396-0500
Reset
R
Q
D
P91DDR
C
Internal data bus
Appendix C I/O Port Block Diagrams
WP9D
Reset
R
Q
D
P91DR
C
P91
WP9
SCI
Output enable
Serial transmit data
Guard time
RP9
Legend:
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
Figure C.5 (b) Port 9 Block Diagram (Pin P91)
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Appendix C I/O Port Block Diagrams
R
Q
D
P9 2 DDR
C
WP9D
Reset
Internal data bus
Reset
SCI
Input enable
R
P92
Q
D
P9 2 DR
C
WP9
RP9
Serial receive
data
Legend:
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
Figure C.5 (c) Port 9 Block Diagram (Pin P92)
Rev.5.00 Sep. 12, 2007 Page 731 of 764
REJ09B0396-0500
Reset
R
Q
D
P93DDR
C
WP9D
Reset
Internal data bus
Appendix C I/O Port Block Diagrams
SCI
Input enable
R
Q
D
P93DR
C
P93
WP9
RP9
Serial receive data
Legend:
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
Figure C.5 (d) Port 9 Block Diagram (Pin P93)
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Appendix C I/O Port Block Diagrams
R
Q
D
P9 4DDR
C
WP9D
Reset
Internal data bus
Reset
SCI
Clock input
enable
R
Q
P94
D
P9 4 DR
C
WP9
Clock output
enable
Clock output
RP9
Clock input
Interrupt
controller
IRQ 4 input
Legend:
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
Figure C.5 (e) Port 9 Block Diagram (Pin P94)
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Appendix C I/O Port Block Diagrams
R
Q
D
P9 5DDR
C
WP9D
Reset
Internal data bus
Reset
SCI
Clock input
enable
R
Q
P95
D
P9 5 DR
C
WP9
Clock output
enable
Clock output
RP9
Clock input
Interrupt
controller
IRQ 5 input
Legend:
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
Figure C.5 (f) Port 9 Block Diagram (Pin P95)
Rev.5.00 Sep. 12, 2007 Page 734 of 764
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Appendix C I/O Port Block Diagrams
C.6
Port A Block Diagrams
Internal data bus
Reset
R
Q
D
PA n DDR
C
WPAD
Reset
TPC
output
enable
R
Q
PA n
TPC
D
PA n DR
C
Next data
WPA
Output
trigger
DMA controller
Output
enable
Transfer
end output
RPA
16-bit timer
Counter
clock input
Legend:
WPAD: Write to PADDR
WPA: Write to port A
RPA: Read port A
8-bit timer
Counter
clock input
Note: n = 0 and 1
Figure C.6 (a) Port A Block Diagram (Pins PA0, PA1)
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Appendix C I/O Port Block Diagrams
Internal data bus
Reset
R
Q
D
PA n DDR
C
WPAD
Reset
TPC
output
enable
R
Q
PA n
TPC
D
PA n DR
C
Next
data
WPA
Output
trigger
16-bit timer
Output
enable
Compare
match
output
RPA
Legend:
WPAD: Write to PADDR
WPA: Write to port A
RPA: Read port A
Input
capture
Counter
clock
input
8-bit timer
Counter
clock input
Note: n = 2 and 3
Figure C.6 (b) Port A Block Diagram (Pins PA2, PA3)
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Appendix C I/O Port Block Diagrams
Software standby
R
Q
D
PAnDDR
C
WPAD
Internal address bus
Address output enable
Mode 3/4
Reset
Internal data bus
SSOE
Bus released
TPC
Reset
TPC output
enable
R
PA n
Q
D
PAnDR
Next data
WPA
C
Output trigger
16-bit timer
Output enable
Compare match
output
PRA
Input capture
Legend:
WPAD: Write to PADDR
WPA: Write to port A
RPA: Read port A
SSOE: Software standby output port enable
Notes: 1. n = 4 to 7
2. PA7 address output enable is fixed at 1 in modes 3 and 4.
Figure C.6 (c) Port A Block Diagram (Pins PA4 to PA7)
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Appendix C I/O Port Block Diagrams
Port B Block Diagrams
Internal data bus
C.7
Software standby
SSOE
Reset
R
Q
D
PBnDDR
C
Bus released
Bus controller
CS7
CS5 output
WPBD
CS output enable
Reset
TPC
TPC output enable
R
Q
D
PBnDR
C
PBn
Next data
WPB
Output trigger
8-bit timer
Output enable
Compare match output
RPB
Legend:
WPBD: Write to PBDDR
WPB: Write to port B
RPB: Read port B
SSOE: Software standby output port enable
Note: n = 0 and 2
Figure C.7 (a) Port B Block Diagram (Pins PB0, PB2)
Rev.5.00 Sep. 12, 2007 Page 738 of 764
REJ09B0396-0500
Internal data bus
Appendix C I/O Port Block Diagrams
Software standby
Reset
SSOE
R
Q
D
PBnDDR
C
Bus released
Bus controller
CS6
CS4 output
WPBD
CS output enable
TPC
TPC output enable
Reset
R
Q
D
PBnDR
C
PBn
Next data
WPB
Output trigger
8-bit timer
Output enable
Compare match output
RPB
TMO2
TMO3 input
DMAC
DREQ0
DREQ1 input
Legend:
WPBD: Write to PBDDR
WPB: Write to port B
RPB: Read port B
SSOE: Software standby output port enable
Note: n = 1 and 3
Figure C.7 (b) Port B Block Diagram (Pins PB1, PB3)
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REJ09B0396-0500
Appendix C I/O Port Block Diagrams
Internal data bus
Reset
R
Q
D
PB 4 DDR
C
TPC
WPBD
Reset
TPC output
enable
R
Q
PB4
D
PB 4 DR
C
Next data
WPB
Output trigger
Bus controller
CAS output enable
CAS output
RPB
Legend:
WPBD: Write to PBDDR
WPB: Write to port B
RPB: Read port B
Figure C.7 (c) Port B Block Diagram (Pin PB4)
Rev.5.00 Sep. 12, 2007 Page 740 of 764
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Internal data bus
Appendix C I/O Port Block Diagrams
Reset
R
Q
D
PB5DDR
C
SCI
Clock input
enable
WPBD
Reset
TPC
R
Q
PB5
TPC output enable
D
PB5DR
C
Next data
WPB
Output trigger
Bus controller
CAS output enable
CAS output
SCI
Clock output enable
Clock output
RPB
Clock input
Legend:
WPBD: Write to PBDDR
WPB: Write to port B
RPB: Read port B
Figure C.7 (d) Port B Block Diagram (Pin PB5)
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REJ09B0396-0500
Appendix C I/O Port Block Diagrams
Internal data bus
Reset
R
Q
PB 6 DDR
D
C
WPBD
TPC
Reset
TPC output enable
R
Q
PB6
PB6 DR
D
Next data
C
WPB
Output trigger
SCI
Output enable
Serial transmit data
Guard time
RPB
Legend:
WPBD: Write to PBDDR
WPB: Write to port B
RPB: Read port B
Figure C.7 (e) Port B Block Diagram (Pin PB6)
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Appendix C I/O Port Block Diagrams
Internal data bus
Reset
R
Q
PB 7 DDR
D
C
WPBD
Reset
TPC
TPC output
enable
R
PB7
Q
PB7 DR
SCI
Input enable
D
Next data
C
WPB
Output trigger
RPB
SCI
Serial receive
data
Legend:
WPBD: Write to PBDDR
WPB: Write to port B
RPB: Read port B
Figure C.7 (f) Port B Block Diagram (Pin PB7)
Rev.5.00 Sep. 12, 2007 Page 743 of 764
REJ09B0396-0500
Appendix D Pin States
Appendix D Pin States
D.1
Port States in Each Mode
Table D.1
Port States in Each Processing State
Port Name
Pin Name
Mode
Hardware
Standby
Mode
Software Standby Mode
Bus-Released State
Program
Execution
State
RESO
⎯
T*
T
T
T*1
T*1
A19 to A0
1 to 4
L
T
[SSOE = 0]
T
T
A19 to A0
Reset
1
[SSOE = 1]
Keep
D15 to D8
1 to 4
T
T
T
T
D15 to D8
AS, RD,
HWR, LWR
1 to 4
H
T
[SSOE = 0]
T
T
AS, RD, HWR,
LWR
[SSOE = 1]
H
P47 to P40
1, 3
T
T
Keep
Keep
I/O port
2, 4
T
T
T
T
D7 to D0
P60
1 to 4
T
T
Keep
Keep
I/O port
WAIT
P61
1 to 4
T
T
[BRLE = 0]
Keep
T
I/O port
BREQ
L
[BRLE = 0]
I/O port
[BRLE = 1]
T
P62
1 to 4
T
T
[BRLE = 0]
Keep
[BRLE = 1]
BACK
[BRLE = 1]
H
P67
P77 to P70
1 to 4
1 to 4
Clock
output
T
T
T
[PSTOP = 0]
H
[PSTOP = 0]
φ
[PSTOP = 0]
φ
[PSTOP = 1]
Keep
[PSTOP = 1]
Keep
[PSTOP = 1]
Input port
T
T
Input port
Rev.5.00 Sep. 12, 2007 Page 744 of 764
REJ09B0396-0500
Appendix D Pin States
Port Name
Pin Name
P80
Mode
1 to 4
Reset
T
Hardware
Standby
Mode
T
Program
Execution
State
Software Standby Mode
Bus-Released State
• When DRAM space
is not selected*2
• When DRAM space [RFSHE = 0]
I/O port
is not selected*2
[RFSHE = 0]
Keep
[RFSHE = 0]
Keep
[RFSHE = 1]
Illegal setting
[RFSHE = 1]
Illegal setting
• When DRAM space
is selected*3
[RFSHE = 1]
RFSH
• When DRAM space
is selected*3
[RFSHE = 0]
Keep
[RFSHE = 0]
Keep
[RFSHE = 1,
SRFMD = 0, SSOE = 0]
T
[RFSHE = 1]
T
[RFSHE = 1,
SRFMD = 0, SSOE = 1]
H
[RFSHE = 1,
SRFMD = 1]
RFSH
P81
1 to 4
T
T
• RAS3 output*4
• RAS3 output*4
T
• RAS3 output
RAS3
[SSOE = 0]
T
• Otherwise*5
[SSOE = 1]
H
[DDR = 0]
Keep
[DDR = 0]
Input port
[DDR = 1]
T
[DDR = 1]
• Otherwise*5
[DDR = 0]
T
• Otherwise
CS3
[DDR = 1, SSOE = 0]
T
[DDR = 1, SSOE = 1]
H
Rev.5.00 Sep. 12, 2007 Page 745 of 764
REJ09B0396-0500
Appendix D Pin States
Port Name
Pin Name
P82
Mode
1 to 4
Reset
T
Hardware
Standby
Mode
Software Standby Mode
Bus-Released State
Program
Execution
State
T
• RAS2 output*3
• RAS2 output*3
• RAS2 output
RAS2
[SSOE = 0]
T
• Otherwise*2
T
[SSOE = 1]
H
[DDR = 0]
Keep
[DDR = 0]
Input port
[DDR = 1]
T
[DDR = 1]
CS2
• Otherwise*2
[DDR = 0]
T
• Otherwise
[DDR = 1, SSOE = 0]
T
[DDR = 1, SSOE = 1]
H
P83
1 to 4
T
T
[DDR = 0]
T
[DDR = 0]
Keep
[DDR = 0]
Input port
[DDR = 1, SSOE = 0]
T
[DDR = 1]
T
[DDR = 1]
CS1
[DDR = 0]
T
[DDR = 0]
Keep
[DDR = 0]
Input port
[DDR = 1, SSOE = 0]
T
[DDR = 1]
T
[DDR = 1]
CS0
[DDR = 1, SSOE = 1]
H
P84
1 to 4
H
T
[DDR = 1, SSOE = 1]
H
P95 to P90
1 to 4
T
T
Keep
Keep
I/O port
PA3 to PA0
1 to 4
T
T
Keep
Keep
I/O port
PA6 to PA4
1, 2
T
T
Keep
Keep
T
• Address output*
3, 4
T
[SSOE = 0]
T
[SSOE = 1]
Keep
• Otherwise*7
Keep
Rev.5.00 Sep. 12, 2007 Page 746 of 764
REJ09B0396-0500
6
• Address output*
T
• Otherwise*7
Keep
I/O port
6
• Address
output
A23 to A21
• Otherwise
• I/O port
Appendix D Pin States
Reset
Hardware
Standby
Mode
Software Standby Mode
Bus-Released State
Program
Execution
State
1, 2
T
T
Keep
Keep
I/O port
3, 4
L
T
[SSOE = 0]
T
T
A20
Port Name
Pin Name
Mode
PA7
[SSOE = 1]
Keep
PB1, PB0
1 to 4
T
T
• CS output*8
[SSOE = 0]
T
[SSOE = 1]
H
• CS output*8
• Otherwise*
• CS output
CS7, CS6
T
9
• Otherwise
I/O port
Keep
• Otherwise*9
Keep
PB2
1 to 4
T
T
• RAS5 output*10
[SSOE = 0]
T
[SSOE = 1]
H
• CS output*11
[SSOE = 0]
T
• RAS5 output*10
• RAS5 output
RAS5
T
• CS output *
11
• CS output
CS5
T
• Otherwise*12
• Otherwise
I/O port
Keep
[SSOE = 1]
H
• Otherwise*12
Keep
PB3
1 to 4
T
T
• RAS4 output*13
[SSOE = 0]
T
[SSOE = 1]
H
• CS output*14
[SSOE = 0]
T
• RAS4 output*13
• CS output *14
Keep
• CS output
CS4
T
• Otherwise*
• RAS4 output
RAS4
T
15
• Otherwise
I/O port
[SSOE = 1]
H
• Otherwise*15
Keep
Rev.5.00 Sep. 12, 2007 Page 747 of 764
REJ09B0396-0500
Appendix D Pin States
Port Name
Pin Name
PB5, PB4
Mode
1 to 4
Reset
T
Hardware
Standby
Mode
Software Standby Mode
Bus-Released State
Program
Execution
State
T
• CAS output*16
• CAS output*16
• CAS output
[SSOE = 0]
T
[SSOE = 1]
H
T
• Otherwise*17
Keep
UCAS,
LCAS
• Otherwise
I/O port
• Otherwise*17
Keep
PB7, PB6
1 to 4
T
T
Keep
Keep
I/O port
Legend:
H:
High
L:
Low
T:
High-impedance state
Keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register
Notes: 1. Low only when WDT overflow causes a reset.
2. When bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) are all
cleared to 0.
3. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
set to 1.
4. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is 010, 100, or 101.
5. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 010, 100, or 101.
6. When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is
cleared to 0.
7 When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is
set to 1.
8. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is set to 1.
9. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is cleared
to 0.
10. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is 101.
11. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 101, and bit CS5E in CSCR (chip select control register) is set
to 1.
12. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 101, and bit CS5E in CSCR (chip select control register) is
cleared to 0.
Rev.5.00 Sep. 12, 2007 Page 748 of 764
REJ09B0396-0500
Appendix D Pin States
13. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is 100, 101, or 110.
14. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control
register) is set to 1.
15. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control
register) is cleared to 0.
16. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
set to 1, and bit CSEL in DRCRB (DRAM control register B) is cleared to 0.
17. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
set to 1, and bit CSEL in DRCRB (DRAM control register B) is set to 1; or, when bits
DRAS2, DRAS1, and DRAS0 are cleared to 0.
Rev.5.00 Sep. 12, 2007 Page 749 of 764
REJ09B0396-0500
Appendix D Pin States
D.2
Pin States at Reset
Modes 1 and 2: Figure D.1 is a timing diagram for the case in which RES goes low during an
external memory access in mode 1 or 2. As soon as RES goes low, all ports are initialized to the
input state. AS, RD, HWR, LWR, and CS0 go high, and D15 to D0 go to the high-impedance state.
The address bus is initialized to the low output level 2.5 φ clock cycles after the low level of RES
is sampled. Clock pin P67/φ goes to the output state at the next rise of φ after RES goes low.
Access to external
memory
T1
T2
T3
P67/φ
RES
Internal reset
signal
A19 to A0
H'00000
CS0
AS, RD
(read)
HWR, LWR
(write)
D15 to D0
(write)
High impedance
I/O port,
CS7 to CS1
High impedance
Figure D.1 Reset during Memory Access (Modes 1 and 2)
Rev.5.00 Sep. 12, 2007 Page 750 of 764
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Appendix D Pin States
Modes 3 and 4: Figure D.2 is a timing diagram for the case in which RES goes low during an
external memory access in mode 3 or 4. As soon as RES goes low, all ports are initialized to the
input state. AS, RD, HWR, LWR, and CS0 go high, and D15 to D0 go to the high-impedance state.
The address bus is initialized to the low output level 2.5 φ clock cycles after the low level of RES
is sampled. However, when PA4 to PA6 are used as address bus pins, or when P83 to P81 and PB0 to
PB3 are used as CS output pins, they go to the high-impedance state at the same time as RES goes
low. Clock pin P67/φ goes to the output state at the next rise of φ after RES goes low.
Access to external
memory
T1
T2
T3
P67/φ
RES
Internal reset
signal
A20 to A0
H'000000
CS0
AS, RD
(read)
HWR, LWR
(write)
D15 to D0
(write)
High impedance
I/O port,
PA4/A23 to PA6/
A21, CS7 to CS1
High impedance
Figure D.2 Reset during Memory Access (Modes 3 and 4)
Rev.5.00 Sep. 12, 2007 Page 751 of 764
REJ09B0396-0500
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10
system clock cycles before the STBY signal goes low, as shown below. RES must r⊕emain
low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
STBY
t1 ≥ 10tcyc
t2 ≥ 0 ns
RES
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents
do not need to be retained, RES does not have to be driven low as in (1).
Timing of Recovery from Hardware Standby Mode: Drive the RES signal low approximately
100 ns before STBY goes high.
STBY
t ≥ 100 ns
RES
Rev.5.00 Sep. 12, 2007 Page 752 of 764
REJ09B0396-0500
tOSC
Appendix F List of Product Codes
Appendix F List of Product Codes
Table F.1
H8/3007, H8/3006 Product Code Lineup
Part No.
Product Code
Mark Code
Package Code
H8/3007 5.0 V ±10%
(5 V)
HD6413007F
HD6413007F
100-pin QFP (FP-100B)
HD6413007TE
HD6413007TE
100-pin TQFP (TFP-100B)
HD6413007FP
HD6413007FP
100-pin QFP (FP-100A)
HD6413007VF
100-pin QFP (FP-100B)
HD6413007VTE
100-pin TQFP (TFP-100B)
HD6413007VFP
HD6413007VFP
100-pin QFP (FP-100A)
HD6413006F
HD6413006F
100-pin QFP (FP-100B)
HD6413006TE
HD6413006TE
100-pin TQFP (TFP-100B)
HD6413006FP
HD6413006FP
100-pin QFP (FP-100A)
HD6413006VF
100-pin QFP (FP-100B)
HD6413006VTE
100-pin TQFP (TFP-100B)
HD6413006VFP
100-pin QFP (FP-100A)
2.7 to 5.5 V HD6413007VF
(Low voltage)
HD6413007VTE
H8/3006 5.0 V ±10%
(5 V)
2.7 to 5.5 V HD6413006VF
(Low voltage)
HD6413006VTE
HD6413006VFP
Rev.5.00 Sep. 12, 2007 Page 753 of 764
REJ09B0396-0500
Appendix G Package Dimensions
Appendix G Package Dimensions
The package dimention that is shown in the Renesas Semiconductor Package Data Book has
priority.
JEITA Package Code
P-QFP100-14x14-0.50
RENESAS Code
PRQP0100KA-A
Previous Code
FP-100B/FP-100BV
MASS[Typ.]
1.2g
HD
*1
D
75
51
76
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
50
bp
c
c1
HE
*2
E
b1
ZE
Terminal cross section
26
100
1
25
c
F
A2
A
ZD
θ
A1
L
L1
Detail F
e
*3
y
bp
x
M
Figure G.1 Package Dimensions (FP-100B)
Rev.5.00 Sep. 12, 2007 Page 754 of 764
REJ09B0396-0500
Reference Dimension in Millimeters
Symbol
Min
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
Nom Max
14
14
2.70
15.7 16.0 16.3
15.7 16.0 16.3
3.05
0.00 0.12 0.25
0.17 0.22 0.27
0.20
0.12 0.17 0.22
0.15
0°
8°
0.5
0.08
0.10
1.0
1.0
0.3 0.5 0.7
1.0
Appendix G Package Dimensions
JEITA Package Code
P-TQFP100-14x14-0.50
RENESAS Code
PTQP0100KA-A
Previous Code
TFP-100B/TFP-100BV
MASS[Typ.]
0.5g
HD
*1
D
75
51
76
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
50
bp
c
c1
HE
*2
E
b1
Reference Dimension in Millimeters
Symbol
Terminal cross section
ZE
Min
1
A
25
ZD
c
100
A2
26
Index mark
θ
F
A1
L
L1
Detail F
e
*3
y
bp
x
M
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
Nom Max
14
14
1.00
15.8 16.0 16.2
15.8 16.0 16.2
1.20
0.00 0.10 0.20
0.17 0.22 0.27
0.20
0.12 0.17 0.22
0.15
8°
0°
0.5
0.08
0.10
1.00
1.00
0.4 0.5 0.6
1.0
Figure G.2 Package Dimensions (TFP-100B)
Rev.5.00 Sep. 12, 2007 Page 755 of 764
REJ09B0396-0500
Appendix G Package Dimensions
JEITA Package Code
P-QFP100-14x20-0.65
RENESAS Code
PRQP0100JE-B
Previous Code
FP-100A/FP-100AV
MASS[Typ.]
1.7g
HD
*1
D
80
51
81
50
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
bp
c
c1
HE
ZE
*2
E
b1
Terminal cross section
Reference Dimension in Millimeters
Symbol
31
100
Min
1
30
c
A2
A
ZD
F
θ
A1
L
L1
Detail F
e
*3
y
bp
x
M
Figure G.3 Package Dimensions (FP-100A)
Rev.5.00 Sep. 12, 2007 Page 756 of 764
REJ09B0396-0500
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
Nom Max
20
14
2.70
24.4 24.8 25.2
18.4 18.8 19.2
3.10
0.00 0.20 0.30
0.24 0.32 0.40
0.30
0.12 0.17 0.22
0.15
0°
10°
0.65
0.13
0.15
0.58
0.83
1.0 1.2 1.4
2.4
Appendix H Comparison of H8/300H Series Product Specifications
Appendix H Comparison of H8/300H Series Product
Specifications
H.1
1
Differences between H8/3067 and H8/3062 Group, H8/3048 Group,
H8/3006 and H8/3007, and H8/3002
Item
H8/3067, H8/3062
Group
H8/3048
Group
Operating Mode 5
mode
16 MB ROM enabled
expanded mode
1 MB ROM
enabled
expanded
mode
Mode 6
H8/3006, H8/3007
H8/3002
64 KB single-chip mode 16 MB ROM
enabled
expanded
mode
2
Interrupt Internal interrupt 36 (H8/3067)
controller sources
27 (H8/3062)
30
36
30
3
Bus
Burst ROM
controller interface
No
Yes
No
Idle cycle
Yes
insertion function
No
Yes
No
Wait mode
4 modes
2 modes
4 modes
Yes (H8/3067)
No (H8/3062)
2 modes
Wait state numberPer area
setting
4
DRAM
interface
Common
Per area
to all areas
Common
to all areas
Address output
method
Choice of address update Fixed
mode (mask ROM and
flash memory R versions
only)
Fixed
Fixed
Connectable
areas
Area 2/3/4/5
(H8/3067 only)
Area 3
Area 2/3/4/5
Area 3
Precharge cycle Yes (H8/3067 only)
insertion function
No
Yes
No
Fast page mode Yes (H8/3067 only)
No
Yes
No
Address shift
amount
8 bit/9 bit
8 bit/9 bit/10 bit
8 bit/9 bit
8 bit/9 bit/10 bit
(H8/3067 only)
Rev.5.00 Sep. 12, 2007 Page 757 of 764
REJ09B0396-0500
Appendix H Comparison of H8/300H Series Product Specifications
H8/3067, H8/3062
Group
H8/3048
Group
16-bit
timers
8-bit
timers
ITU
Number of
channels
16 bits × 3
Pulse output
Item
5
H8/3006, H8/3007
H8/3002
16-bit
timers
8-bit
timers
ITU
8 bits × 4
16 bits × 5
(16 bits × 2)
16 bits × 3
8 bits × 4
16 bits × 5
(16 bits × 2)
6 pins
4 pins
(2 pins)
12 pins
6 pins
4 pins
(2 pins)
12 pins
Input capture
6
2
10
6
2
10
External clock
4 systems 4 systems
(selectable) (fixed)
4 systems 4 systems 4 systems
(selectable) (selectable) (fixed)
4 systems
(selectable)
Internal clock
φ, φ/2, φ/4,
φ/8
φ/8, φ/64,
φ/8192
φ, φ/2, φ/4,
φ/8
φ, φ/2, φ/4,
φ/8
φ/8, φ/64,
φ/8192
φ, φ/2, φ/4,
φ/8
Complementary
PWM function
No
No
Yes
No
No
Yes
Resetsynchronous
PWM function
No
No
Yes
No
No
Yes
Buffer operation No
No
Yes
No
No
Yes
Output
initialization
function
Yes
No
No
Yes
No
No
PWM output
3
4 (2)
5
3
4 (2)
5
Timer functions
DMAC activation 3 channels No
(H8/3067
only)
4 channels 3 channels No
4 channels
A/D conversion
activation
Yes
No
No
Yes
No
8 sources
3 sources
×5
3 sources
×3
8 sources
3 sources
×5
No
Interrupt sources 3 sources
×3
6
TPC
Time base
3 kinds, 16-bit timer
base
4 kinds,
ITU base
3 kinds, 16-bit timer
base
4 kinds,
ITU base
7
WDT
Reset signal
external output
function
Yes (except products
with on-chip flash
memory)
Yes
Yes
Yes
8
SCI
Number of
channels
3 channels (H8/3067)
2 channels 3 channels
2 channels
Smart card
interface
Supported on all
channels
Supported
on SCI0
only
No
2 channels (H8/3062)
Rev.5.00 Sep. 12, 2007 Page 758 of 764
REJ09B0396-0500
Supported on all
channels
Appendix H Comparison of H8/300H Series Product Specifications
H8/3067, H8/3062
Group
Item
9
10
A/D
Conversion start External trigger/8-bit
converter trigger input
timer compare match
Pin
control
H8/3048
Group
H8/3006, H8/3007
H8/3002
External
trigger
External trigger/8-bit
timer compare match
External
trigger
134/266
70/134
134/266
Conversion
states
70/134
φ pin
φ/input port multiplexing φ output
only
φ/input port multiplexing φ output
only
A20 in 16 MB ROM A20 / I/O port multiplexing A20 output
enabled
expanded mode
Address bus,
High-level output/highAS, RD, HWR,
impedance selectable
LWH, CS7 to CS0, (RFSH: H8/3067 only)
RFSH in software
standby state
11
Flash
memory
functions
High-level High-level output/highimpedance selectable
output
(except CS0)
High-level
output
(except CS0)
Low-level
output
(CS0)
Low-level
output
(CS0)
CS7 to CS0 in bus- High-impedance
released state
High-level
output
Program/erase
voltage
12 V application
unnecessary.
Single-power-supply
programming.
12 V
application
from off-chip
Block divisions
8 blocks
16 blocks
High-impedance
High-level
output
Rev.5.00 Sep. 12, 2007 Page 759 of 764
REJ09B0396-0500
Appendix H Comparison of H8/300H Series Product Specifications
H.2
Comparison of Pin Functions of 100-Pin Package Products
(FP-100B, TFP-100B)
Table H.1
Pin Arrangement of Each Product (FP-100B, TFP-100B)
On-chip-ROM Products
ROMless Products
Pin
No.
H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group
1
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
2
PB0/TP8/TMO0/
CS7
PB0/TP8/TMO0/
CS7
PB0/TP8/
TIOCA3
PB0/TP8/
TIOCA3
PB0/TP8/TMO0/
CS7
PB0/TP8/
TIOCA3
3
PB1/TP9/TMIO1/ PB1/TP9/TMIO1/ PB1/TP9/
DREQ0/CS6
CS6
TIOCB3
PB1/TP9/
TIOCB3
PB1/TP9/TMIO1/
DREQ0/CS6
PB1/TP9/
TIOCB3
4
PB2/TP10/TMO2/ PB2/TP10/TMO2/ PB2/TP10/
CS5
CS5
TIOCA4
PB2/TP10/
TIOCA4
PB2/TP10/TMO2/
CS5
PB2/TP10/
TIOCA4
5
PB3/TP11/
TMIO3/DREQ1/
CS4
PB3/TP11/
TMIO3/CS4
PB3/TP11/
TIOCB4
PB3/TP11/
TIOC4
PB3/TP11/
TMIO3/DREQ1/
CS4
PB3/TP11/
TIOCB4
6
PB4/TP12/
UCAS
PB4/TP12
PB4/TP12/
TOCXA4
PB4/TP12/
TOCXA4
PB4/TP12/
UCAS
PB4/TP12/
TOCXA4
7
PB5/TP13/
LCAS/SCK2
PB5/TP13
PB5/TP13/
TOCXB4
PB5/TP13/
TOCXB4
PB5/TP13/
LCAS/SCK2
PB5/TP13/
TOCXB4
8
PB6/TP14/TxD2
PB6/TP14
PB6/TP14/
DREQ0/CS7
PB6/TP14/
DREQ0
PB6/TP14/TxD2
PB6/TP14/
DREQ0
9
PB7/TP15/RxD2
PB7/TP15
PB7/TP15/
PB7/TP15/
DREQ1/ADTRG DREQ1/ADTRG
PB7/TP15/RxD2
PB7/TP15/
DREQ1/ADTRG
10
RESO/FWE*
RESO/FWE*
RESO/VPP*
RESO
RESO
11
Vss
Vss
Vss
Vss
Vss
Vss
12
P90/TxD0
P90/TxD0
P90/TxD0
P90/TxD0
P90/TxD0
P90/TxD0
13
P91/TxD1
P91/TxD1
P91/TxD1
P91/TxD1
P91/TxD1
P91/TxD1
14
P92/RXD0
P92/RXD0
P92/RXD0
P92/RXD0
P92/RXD0
P92/RXD0
15
P93/RXD1
P93/RXD1
P93/RXD1
P93/RXD1
P93/RXD1
P93/RXD1
16
P94/SCK0/IRQ4
P94/SCK0/IRQ4
P94/SCK0/IRQ4
P94/SCK0/IRQ4
P94/SCK0/IRQ4
P94/SCK0/IRQ4
17
P95/SCK1/IRQ5
P95/SCK1/IRQ5
P95/SCK1/IRQ5
P95/SCK1/IRQ5
P95/SCK1/IRQ5
P95/SCK1/IRQ5
18
P40/D0
P40/D0
P40/D0
P40/D0
P40/D0
P40/D0
19
P41/D1
P41/D1
P41/D1
P41/D1
P41/D1
P41/D1
20
P42/D2
P42/D2
P42/D2
P42/D2
P42/D2
P42/D2
21
P43/D3
P43/D3
P43/D3
P43/D3
P43/D3
P43/D3
22
Vss
Vss
Vss
Vss
Vss
Vss
23
P44/D4
P44/D4
P44/D4
P44/D4
P44/D4
P44/D4
24
P45/D5
P45/D5
P45/D5
P45/D5
P45/D5
P45/D5
Rev.5.00 Sep. 12, 2007 Page 760 of 764
REJ09B0396-0500
RESO
H8/3006, H8/3007 H8/3002
Appendix H Comparison of H8/300H Series Product Specifications
On-chip-ROM Products
ROMless Products
Pin
No.
H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group
H8/3006, H8/3007 H8/3002
25
P46/D6
P46/D6
P46/D6
P46/D6
P46/D6
26
P47/D7
P47/D7
P47/D7
P47/D7
P47/D7
P47/D7
27
P30/D8
P30/D8
P30/D8
P30/D8
D8
D8
28
P31/D9
P31/D9
P31/D9
P31/D9
D9
D9
29
P32/D10
P32/D10
P32/D10
P32/D10
D10
D10
30
P33/D11
P33/D11
P33/D11
P33/D11
D11
D11
31
P34/D12
P34/D12
P34/D12
P34/D12
D12
D12
32
P35/D13
P35/D13
P35/D13
P35/D13
D13
D13
33
P36/D14
P36/D14
P36/D14
P36/D14
D14
D14
34
P37/D15
P37/D15
P37/D15
P37/D15
D15
D15
35
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
36
P10/A0
P10/A0
P10/A0
P10/A0
A0
A0
37
P11/A1
P11/A1
P11/A1
P11/A1
A1
A1
38
P12/A2
P12/A2
P12/A2
P12/A2
A2
A2
39
P13/A3
P13/A3
P13/A3
P13/A3
A3
A3
40
P14/A4
P14/A4
P14/A4
P14/A4
A4
A4
41
P15/A5
P15/A5
P15/A5
P15/A5
A5
A5
42
P16/A6
P16/A6
P16/A6
P16/A6
A6
A6
43
P17/A7
P17/A7
P17/A7
P17/A7
A7
A7
44
Vss
Vss
Vss
Vss
Vss
Vss
45
P20/A8
P20/A8
P20/A8
P20/A8
A8
A8
46
P21/A9
P21/A9
P21/A9
P21/A9
A9
A9
47
P22/A10
P22/A10
P22/A10
P22/A10
A10
A10
48
P23/A11
P23/A11
P23/A11
P23/A11
A11
A11
49
P24/A12
P24/A12
P24/A12
P24/A12
A12
A12
50
P25/A13
P25/A13
P25/A13
P25/A13
A13
A13
51
P26/A14
P26/A14
P26/A14
P26/A14
A14
A14
52
P27/A15
P27/A15
P27/A15
P27/A15
A15
A15
53
P50/A16
P50/A16
P50/A16
P50/A16
A16
A16
54
P51/A17
P51/A17
P51/A17
P51/A17
A17
A17
55
P52/A18
P52/A18
P52/A18
P52/A18
A18
A18
56
P53/A19
P53/A19
P53/A19
P53/A19
A19
A19
P46/D6
Rev.5.00 Sep. 12, 2007 Page 761 of 764
REJ09B0396-0500
Appendix H Comparison of H8/300H Series Product Specifications
On-chip-ROM Products
ROMless Products
Pin
No.
H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group
H8/3006, H8/3007 H8/3002
57
Vss
Vss
Vss
Vss
Vss
Vss
58
P60/WAIT
P60/WAIT
P60/WAIT
P60/WAIT
P60/WAIT
P60/WAIT
59
P61/BREQ
P61/BREQ
P61/BREQ
P61/BREQ
P61/BREQ
P61/BREQ
60
P62/BACK
P62/BACK
P62/BACK
P62/BACK
P62/BACK
P62/BACK
61
P67/φ
P67/φ
φ
φ
P67/φ
φ
62
STBY
STBY
STBY
STBY
STBY
STBY
63
RES
RES
RES
RES
RES
RES
64
NMI
NMI
NMI
NMI
NMI
NMI
65
Vss
Vss
Vss
Vss
Vss
Vss
66
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
67
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
68
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
69
P63/AS
P63/AS
P63/AS
P63/AS
AS
AS
70
P64/RD
P64/RD
P64/RD
P64/RD
RD
RD
71
P65/HWR
P65/HWR
P65/HWR
P65/HWR
HWR
HWR
72
P66/LWR
P66/LWR
P66/LWR
P66/LWR
LWR
LWR
73
MD0
MD0
MD0
MD0
MD0
MD0
74
MD1
MD1
MD1
MD1
MD1
MD1
75
MD2
MD2
MD2
MD2
MD2
MD2
76
AVcc
AVcc
AVcc
AVcc
AVcc
AVcc
77
VREF
VREF
VREF
VREF
VREF
VREF
78
P70/AN0
P70/AN0
P70/AN0
P70/AN0
P70/AN0
P70/AN0
79
P71/AN1
P71/AN1
P71/AN1
P71/AN1
P71/AN1
P71/AN1
80
P72/AN2
P72/AN2
P72/AN2
P72/AN2
P72/AN2
P72/AN2
81
P73/AN3
P73/AN3
P73/AN3
P73/AN3
P73/AN3
P73/AN3
82
P74/AN4
P74/AN4
P74/AN4
P74/AN4
P74/AN4
P74/AN4
83
P75/AN5
P75/AN5
P75/AN5
P75/AN5
P75/AN5
P75/AN5
84
P76/AN6/DA0
P76/AN6/DA0
P76/AN6/DA0
P76/AN6/DA0
P76/AN6/DA0
P76/AN6
85
P77/AN7/DA1
P77/AN7/DA1
P77/AN7/DA1
P77/AN7/DA1
P77/AN7/DA1
P77/AN7
86
AVss
AVss
AVss
AVss
AVss
AVss
87
P80/RFSH/IRQ0 P80/IRQ0
P80/RFSH/IRQ0 P80/RFSH/IRQ0
P80/RFSH/IRQ0
P80/RFSH/IRQ0
88
P81/CS3/IRQ1
P81/CS3/IRQ1
P81/CS3/IRQ1
P81/CS3/IRQ1
P81/CS3/IRQ1
Rev.5.00 Sep. 12, 2007 Page 762 of 764
REJ09B0396-0500
P81/CS3/IRQ1
Appendix H Comparison of H8/300H Series Product Specifications
On-chip-ROM Products
ROMless Products
Pin
No.
H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group
H8/3006, H8/3007 H8/3002
89
P82/CS2/IRQ2
P82/CS2/IRQ2
P82/CS2/IRQ2
P82/CS2/IRQ2
P82/CS2/IRQ2
P82/CS2/IRQ2
90
P83/CS1/IRQ3/
ADTRG
P83/CS1/IRQ3/
ADTRG
P83/CS1/IRQ3
P83/CS1/IRQ3
P83/CS1/IRQ3/
ADTRG
P83/CS1/IRQ3
91
P84/CS0
P84/CS0
P84/CS0
P84/CS0
P84/CS0
P84/CS0
92
Vss
Vss
Vss
Vss
Vss
Vss
93
PA0/TP0/
TEND0/TCLKA
PA0/TP0/TCLKA PA0/TP0/
TEND0/TCLKA
PA0/TP0/
TEND0/TCLKA
PA0/TP0/
TEND0/TCLKA
PA0/TP0/
TEND0/TCLKA
94
PA1/TP1/
TEND1/TCLKB
PA1/TP1/TCLKB PA1/TP1/
TEND1/TCLKB
PA1/TP1/
TEND1/TCLKB
PA1/TP1/
TEND1/TCLKB
PA1/TP1/
TEND1/TCLKB
95
PA2/TP2/
PA2/TP2/
PA2/TP2/
PA2/TP2/
TIOCA0/TCLKC TIOCA0/TCLKC TIOCA0/TCLKC TIOCA0/TCLKC
PA2/TP2/
TIOCA0/TCLKC
PA2/TP2/
TIOCA0/TCLKC
96
PA3/TP3/
PA3/TP3/
PA3/TP3/
PA3/TP3/
TIOCB0/TCLKD TIOCB0/TCLKD TIOCB0/TCLKD TIOCB0/TCLKD
PA3/TP3/
TIOCB0/TCLKD
PA3/TP3/
TIOCB0/TCLKD
97
PA4/TP4/
TIOCA1/A23
PA4/TP4/
TIOCA1/A23
PA4/TP4/
PA4/TP4/
TIOCA1/CS6/A23 TIOCA1/A23
PA4/TP4/
TIOCA1/A23
PA4/TP4/
TIOCA1/A23
98
PA5/TP5/
TIOCB1/A22
PA5/TP5/
TIOCB1/A22
PA5/TP5/
PA5/TP5/
TIOCB1/CS5/A22 TIOCB1/A22
PA5/TP5/
TIOCB1/A22
PA5/TP5/
TIOCB1/A22
99
PA6/TP6/
TIOCA2/A21
PA6/TP6/
TIOCA2/A21
PA6/TP6/
PA6/TP6/
TIOCA2/CS4/A21 TIOCA2/A21
PA6/TP6/
TIOCA2/A21
PA6/TP6/
TIOCA2/A21
100
PA7/TP7/
TIOCB2/A20
PA7/TP7/
TIOCB2/A20
PA7/TP7/
TIOCB2/A20
PA7/TP7/
TIOCB2/A20
PA7/TP7/
TIOCB2/A20
Note:
*
PA7/TP7/
TIOCB2/A20
Functions as RESO in the mask ROM versions, and as FWE in the flash memory and
flash memory R versions.
Rev.5.00 Sep. 12, 2007 Page 763 of 764
REJ09B0396-0500
Appendix H Comparison of H8/300H Series Product Specifications
Rev.5.00 Sep. 12, 2007 Page 764 of 764
REJ09B0396-0500
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8/3006, H8/3007
Publication Date: 1st Edition, December 1997
Rev.5.00, September 12, 2007
Published by:
Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by:
Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 6.0
H8/3006, H8/3007
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan