Cypress CY7C1041BV33L-12ZC 256k x 16 static ram Datasheet

041BV33
CY7C1041BV33
256K x 16 Static RAM
Features
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
• High speed
— tAA = 12 ns
• Low active power
— 612 mW (max.)
• Low CMOS standby power (Commercial L version)
— 1.8 mW (max.)
• 2.0V Data Retention (600 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Functional Description
The CY7C1041BV33 is a high-performance CMOS Static
RAM organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041BV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
TSOP II
Top View
256K x 16
ARRAY
1024 x 4096
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
I/O0 – I/O7
I/O8 – I/O15
A9
A10
A 11
A 12
A 13
A14
A15
A16
A17
COLUMN
DECODER
BHE
WE
CE
OE
BLE
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
Selection Guide
-12
-15
-17
-20
-25
Maximum Access Time (ns)
12
15
17
20
25
Maximum Operating Current (mA) Comm’l
190
170
160
150
130
Ind’l
-
190
180
170
150
Com’l/Ind’l
8
8
8
8
8
0.5
0.5
0.5
0.5
0.5
Maximum CMOS Standby
Current (mA)
Com’l
Cypress Semiconductor Corporation
Document #: 38-05168 Rev. **
L
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised November 15, 2001
CY7C1041BV33
Maximum Ratings
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Current into Outputs (LOW) ........................................ 20 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Range
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
Commercial
DC Voltage Applied to Outputs
in High Z State[1] ....................................–0.5V to VCC + 0.5V
Industrial
Ambient
Temperature[2]
VCC
0°C to +70°C
3.3V ± 0.3V
–40°C to +85°C
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
-12
Min.
-15
Max.
VOH
Output HIGH Voltage
VCC = Min.,
IOH = –4.0 mA
2.4
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH Voltage
2.2
VCC
+ 0.5
VIL
Input LOW Voltage[1]
–0.5
IIX
Input Load Current
GND < VI < VCC
IOZ
Output Leakage Current
GND < VOUT < VCC, Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max., f = fMAX =
1/tRC
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Min.
2.4
0.4
Comm’l
Ind’l
Com’l/Ind’l
Com’l
L
Max.
Unit
V
0.4
V
2.2
VCC
+ 0.5
V
0.8
–0.5
0.8
V
–1
+1
–1
+1
µA
–1
+1
–1
+1
µA
190
170
mA
-
190
mA
40
40
mA
8
8
mA
0.5
0.5
mA
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “Instant On” case temperature.
Document #: 38-05168 Rev. **
Page 2 of 11
CY7C1041BV33
Electrical Characteristics Over the Operating Range (continued)
Test Conditions
Parameter
-17
Description
-20
Min. Max. Min.
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[1]
IIX
Input Load Current
GND < VI < VCC
IOZ
Output Leakage
Current
GND < VOUT < VCC,
Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f=0
2.4
-25
Max.
2.4
0.4
Min.
Max.
Unit
0.4
V
V
2.4
0.4
V
2.2
VCC +
0.5
2.2
VCC +
0.5
2.2
VCC +
0.5
–0.5
0.8
–0.5
0.8
–0.5
0.8
V
–1
+1
–1
+1
–1
+1
µA
–1
+1
–1
+1
–1
+1
µA
mA
Comm’l
160
150
130
Ind’l
180
170
150
40
40
40
mA
8
8
8
mA
0.5
0.5
0.5
mA
Com’l/Ind’l
Com’l
L
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max.
Unit
8
pF
8
pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 317 Ω
3.3V
OUTPUT
OUTPUT
30 pF
ALL INPUT PULSES
THÉVENIN EQUIVALENT
R2
351Ω
INCLUDING
JIG AND
SCOPE
(a)
Document #: 38-05168 Rev. **
167 Ω
(b)
3.3V
90%
1.73V
GND
Rise time: 1 V/ns
10%
90%
10%
Fall time:
1 V/ns
Page 3 of 11
CY7C1041BV33
Switching Characteristics[4] Over the Operating Range
-12
Parameter
Description
Min.
-15
Max.
Min.
-17
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
12
15
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
12
tDOE
OE LOW to Data Valid
6
tLZOE
OE LOW to Low Z
12
3
15
ns
15
17
ns
7
8
ns
3
0
ns
0
tHZOE
OE HIGH to High Z
CE LOW to Low Z[6]
tHZCE
CE HIGH to High Z[5, 6]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
12
15
17
ns
tDBE
Byte Enable to Data Valid
6
7
7
ns
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
3
7
ns
tLZCE
WRITE CYCLE
6
ns
17
3
0
[5, 6]
17
3
6
0
7
0
0
7
3
6
7
0
0
ns
ns
0
7
ns
ns
ns
8
ns
[7, 8]
tWC
Write Cycle Time
12
15
17
ns
tSCE
CE LOW to Write End
10
12
12
ns
tAW
Address Set-Up to Write End
10
12
12
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
10
12
12
ns
tSD
Data Set-Up to Write End
7
8
9
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z[6]
3
3
3
ns
[5, 6]
tHZWE
WE LOW to High Z
tBW
Byte Enable to End of Write
6
10
7
12
8
12
ns
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05168 Rev. **
Page 4 of 11
CY7C1041BV33
Switching Characteristics[4] Over the Operating Range (continued)
-20
Parameter
Description
Min.
-25
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
25
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
20
25
ns
tDOE
OE LOW to Data Valid
8
10
ns
tLZOE
OE LOW to Low Z
20
25
3
5
0
OE HIGH to High Z
tLZCE
CE LOW to Low Z[6]
tHZCE
CE HIGH to High Z[5, 6]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
8
ns
10
3
5
8
ns
ns
0
[5, 6]
tHZOE
ns
ns
ns
10
ns
20
25
ns
8
10
ns
0
0
0
ns
0
8
ns
10
ns
WRITE CYCLE[7, 8]
tWC
Write Cycle Time
20
25
tSCE
CE LOW to Write End
13
15
ns
tAW
Address Set-Up to Write End
13
15
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
13
15
ns
tSD
Data Set-Up to Write End
9
10
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low Z[6]
3
5
ns
tHZWE
WE LOW to High Z[5, 6]
tBW
Byte Enable to End of Write
8
ns
10
13
15
ns
ns
Data Retention Characteristics Over the Operating Range (For L version only)
Parameter
Conditions[10]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[3]
Chip Deselect to Data
Retention Time
tR[9]
Operation Recovery Time
Min.
Max.
2.0
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
Unit
V
330
µA
0
ns
tRC
ns
Notes:
9. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds.
10. No input may exceed VCC + 0.5V.
Document #: 38-05168 Rev. **
Page 5 of 11
CY7C1041BV33
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
VDR > 2V
3.0V
tR
tCDR
CE
1041BV33–
Switching Waveforms
[11, 12]
Read Cycle No. 1
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1041BV33-6
Read Cycle No. 2 (OE Controlled)
[12, 13]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
IICC
CC
50%
IISB
SB
1041BV33-7
Notes:
11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05168 Rev. **
Page 6 of 11
CY7C1041BV33
Switching Waveforms (continued)
[14, 15]
Write Cycle No. 1 (CE Controlled)
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATAI/O
1041BV33-8
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATAI/O
1041BV33-9
Notes:
14. Data I/O is high-impedance if OE or BHE and/or BLE= VIH.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high–impedance state.
Document #: 38-05168 Rev. **
Page 7 of 11
CY7C1041BV33
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
1041BV33-10
Truth Table
CE
OE
WE
BLE
BHE
H
L
I/O0–I/O7
I/O8–I/O15
Mode
Power
X
X
X
X
High Z
High Z
Power Down
Standby (ISB)
L
H
L
L
Data Out
Data Out
Read All Bits
Active (ICC)
L
L
H
L
H
Data Out
High Z
Read Lower Bits Only
Active (ICC)
L
L
H
H
L
High Z
Data Out
Read Upper Bits Only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write All Bits
Active (ICC)
L
X
L
L
H
Data In
High Z
Write Lower Bits Only
Active (ICC)
L
X
L
H
L
High Z
Data In
Write Upper Bits Only
Active (ICC)
L
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
Document #: 38-05168 Rev. **
Page 8 of 11
CY7C1041BV33
Ordering Information
Speed
(ns)
12
15
17
20
25
Ordering Code
CY7C1041BV33-12VC
CY7C1041BV33L-12VC
CY7C1041BV33-12ZC
CY7C1041BV33L-12ZC
CY7C1041BV33-15VC
CY7C1041BV33L-15VC
CY7C1041BV33-15ZC
CY7C1041BV33L-15ZC
CY7C1041BV33-15VI
CY7C1041BV33-15ZI
CY7C1041BV33-17VC
CY7C1041BV33L-17VC
CY7C1041BV33-17ZC
CY7C1041BV33L-17ZC
CY7C1041BV33-17VI
CY7C1041BV33-17ZI
CY7C1041BV33-20VC
CY7C1041BV33L-20VC
CY7C1041BV33-20ZC
CY7C1041BV33L-20ZC
CY7C1041BV33-20VI
CY7C1041BV33-20ZI
CY7C1041BV33-25VC
CY7C1041BV33L-25VC
CY7C1041BV33-25ZC
CY7C1041BV33L-25ZC
CY7C1041BV33-25VI
CY7C1041BV33-25ZI
Document #: 38-05168 Rev. **
Package
Name
V34
V34
Z44
Z44
V34
V34
Z44
Z44
V34
Z44
V34
V34
Z44
Z44
V34
Z44
V34
V34
Z44
Z44
V34
Z44
V34
V34
Z44
Z44
V34
Z44
Package Type
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
44-Pin TSOP II Z44
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
44-Pin TSOP II Z44
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
44-Pin TSOP II Z44
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
44-Pin TSOP II Z44
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
44-Pin TSOP II Z44
44-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
Operating
Range
Commercial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 9 of 11
CY7C1041BV33
Package Diagrams
44-Lead (400-Mil) Molded SOJ V34
51-85082-B
44-Pin TSOP II Z44
51-85087-A
Document #: 38-05168 Rev. **
Page 10 of 11
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1041BV33
Document Title: CY7C1041BV33 256K x 16 SRAM
Document Number: 38-05168
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
111840
11/17/01
DSG
Change from Spec number: 38-00932 to 38-05168
Document #: 38-05168 Rev. **
Page 11 of 11
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