LINER LTC2926IGN Mosfet-controlled power supply tracker Datasheet

LTC2926
MOSFET-Controlled
Power Supply Tracker
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FEATURES
DESCRIPTIO
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The LTC2926 provides a simple solution for tracking and
sequencing up to three power supply rails. An N-channel
MOSFET and a few resistors per channel configure the
load voltages to ramp up and down together, with voltage
offsets, with time delays or with different ramp rates.
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■
■
■
■
■
Flexible Power Supply Tracking and Sequencing
Adjustable Ramp Rates, Offsets and Time Delays
Controls Three Supplies with Series MOSFETs
Integrated Remote Sense Switching
FAULT Input/Output
STATUS Output/Power Good Input
Available in 20-Lead Narrow SSOP and 20-Lead QFN
(4mm × 5mm) Packages
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APPLICATIO S
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■
■
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VCORE and VI/O Supply Tracking
Microprocessor, DSP and FPGA Supplies
Servers
Communications Systems
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
*Protected by U.S. Patents including 6897717.
Automatic remote sense switching compensates for voltage
drops across the MOSFETs. The LTC2926 provides two
integrated switches as well as a signal to control optional
additional external N-channel MOSFET sense switches.
The LTC2926 includes I/O signals for communication with
other devices. The status output asserts after tracking and
sequencing have completed. A low voltage on the power
good input after an adjustable timeout period causes load
disconnect. A low voltage on the fault I/O causes immediate load disconnect. Until it is reset, a fault latch prevents
tracking and keeps the loads disconnected.
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TYPICAL APPLICATIO
1.8V MODULE
IRF7413Z
3.3V SLAVE2
1.8V
SLAVE1
OUT
100Ω
SENSE
10Ω
1.8V SLAVE1
500mV/DIV
3.3V MODULE
IRF7413Z
3.3V
SLAVE2
OUT
0.1µF
100Ω
SENSE
10Ω
D1
VCC
SGATE2
SGATE1
5ms/DIV
S1
2926 TA01b
15.0k
D2
FB1
15.0k
15.0k
3.3V SLAVE2
9.53k
RAMPBUF
S2
TRACK1
15.0k
LTC2926
9.53k
VCC
FAULT
4.02k
10k
STATUS/PGI
10k
ON/OFF
500mV/DIV
VCC
TRACK2
4.02k
1.8V SLAVE1
FB2
FAULT
ON
STATUS
MGATE
GND
PGTMR
RAMP
0.1µF
5ms/DIV
2926 TA01c
2926 TA01
1µF
2926fa
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LTC2926
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W W
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ABSOLUTE
AXI U RATI GS
(Notes 1, 2)
Supply Voltage (VCC) ................................. –0.3V to 10V
Input Voltages
ON ......................................................... –0.3V to 10V
RAMP .............................................–0.3V to VCC + 1V
TRACK1, TRACK2 ........................–0.3V to VCC + 0.3V
PGTMR ........................................–0.3V to VCC + 0.3V
Input/Output Voltages
FAULT .................................................... –0.3V to 10V
STATUS/PGI (Note 3) .......................... –0.3V to 11.5V
Output Voltages
RAMPBUF ....................................–0.3V to VCC + 0.3V
FB1, FB2, D1, S1, D2, S2 ....................... –0.3V to 10V
MGATE, RSGATE (Note 3)................... –0.3V to 11.5V
SGATE1, SGATE2 (Note 3) .................. –0.3V to 11.5V
RMS Currents
TRACK1, TRACK2 ................................................5mA
FB1, FB2 ..............................................................5mA
D1, S1, D2, S2 ...................................................30mA
Operating Temperature
LTC2926C ................................................ 0°C to 70°C
LTC2926I ............................................. –40°C to 85°C
Storage Temperature Range
GN Package ....................................... –65°C to 150°C
UFD Package...................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
GN Package ...................................................... 300°C
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PACKAGE/ORDER I FOR ATIO
FB1
3
18 FB2
S1
4
17 S2
SGATE1
5
16 SGATE2
D1
6
15 D2
ON
7
14 STATUS/PGI
PGTMR
8
13 RSGATE
FAULT
9
12 MGATE
GND 10
16 FB2
S1 2
15 S2
SGATE1 3
14 SGATE2
21
D1 4
13 D2
12 STATUS/PGI
ON 5
11 RSGATE
PGTMR 6
11 RAMP
GN PACKAGE
20-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 85°C/W
TRACK2
20 19 18 17
FB1 1
7
8
9 10
MGATE
19 TRACK2
RAMP
20 RAMPBUF
2
GND
1
FAULT
VCC
TRACK1
RAMPBUF
TOP VIEW
VCC
TRACK1
TOP VIEW
UFD PACKAGE
20-LEAD (4mm × 5mm) PLASTIC QFN
EXPOSED PAD (PIN 21) IS GND
PCB CONNECTION OPTIONAL
TJMAX = 125°C, θJA = 43°C/W
ORDER PART NUMBER
ORDER PART NUMBER
UFD PART MARKING*
LTC2926CGN
LTC2926IGN
LTC2926CUFD
LTC2926IUFD
2926
2926
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.*The temperature grade is identified by a label on the shipping container.
2926fa
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LTC2926
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
VCC
Input Supply Voltage
Operating Range
ICC
Input Supply Current
UNITS
●
2.9
3.3
5.5
V
ITRACKn = 0mA, IFBn = 0mA,
IRAMPBUF = 0mA
●
1.5
2.5
3.5
mA
ITRACKn = –1mA, IFBn = –1mA,
IRAMPBUF = –3mA
●
8.5
9.5
10.5
mA
VCC Rising
●
2.2
2.4
2.6
V
●
15
50
75
mV
●
1.20
1.23
1.26
V
●
40
75
110
mV
0
±100
nA
Supply Voltage
VCC(UVLO)
Input Supply Undervoltage Lockout
ΔVCC(UVLO)
Input Supply Undervoltage Lockout
Hysteresis
Control and I/O
VON(TH)
ON Pin Threshold Voltage
ΔVON(TH)
ON Pin Threshold Voltage Hysteresis
ION
ON Pin Input Current
VON Rising
VON = 1.2V, VCC = 5.5V
●
VON(CLR)
ON Pin Fault Clear Threshold Voltage
VON Falling
●
0.465
0.500
0.535
V
tCLR
Fault Clear Delay
VON Falling
●
1
3
10
µs
VON(ARM)
ON Pin Fault Arm Threshold Voltage
VON Rising
●
0.565
0.600
0.635
V
tARM
Fault Arm Delay
VON Rising
●
1
4.5
10
µs
VFAULT(TH)
FAULT Pin Input Threshold Voltage
VFAULT Falling
●
0.465
0.500
0.535
V
–3.0
–8.5
–13
µA
100
400
mV
IFAULT(UP)
FAULT Pin Pull-up Current
Fault Latch Clear, VFAULT = 1.5V
●
VFAULT(OL)
FAULT Pin Output Low Voltage
Fault Latch Set, IFAULT = 5mA, VCC = 2.7V
●
VFAULT(OH)
FAULT Pin Output High Voltage
(VCC – VFAULT)
Fault Latch Clear, IFAULT = –1µA
●
300
550
900
mV
VPGI(TH)
STATUS/PGI Pin Input Threshold
Voltage
VSTATUS/PGI Rising
●
1.10
1.23
1.36
V
ΔVPGI(TH)
STATUS/PGI Pin Input Threshold
Voltage Hysteresis
●
30
75
150
mV
IPGI(UP)
STATUS/PGI Pin Pull-Up Current
STATUS/PGI On, VSTATUS/PGI = 1.5V
●
–7
–10
–13
µA
VSTATUS(OL)
STATUS/PGI Pin Output Low Voltage
VON Low, ISTATUS/PGI = 5mA, VCC = 2.7V
●
200
400
mV
VSTATUS(OH)
STATUS/PGI Pin Output High Voltage
(VSTATUS/PGI – VCC)
ISTATUS/PGI = –1µA
●
5.0
5.5
6.0
V
VPGTMR(TH)
PGTMR Pin Threshold Voltage
VPGTMR Rising
●
1.10
1.23
1.36
V
IPGTMR(UP)
PGTMR Pin Pull-Up Current
ON High, VPGTMR = 1V
●
–8
–10
–12
µA
IPGTMR(DN)
PGTMR Pin Pull-Down Current
ON Low, VPGTMR = 0.1V, VCC = 2.7V
●
0.5
4
10
mA
VPGTMR(CLR)
PGTMR Pin Clear Threshold Voltage
VPGTMR Falling
●
50
100
150
mV
IRAMP(IN)
RAMP Pin Input Current
0V < VRAMP < 5.5V, VCC = 5.5V
●
0
±1
µA
VRAMPBUF(OS)
Ramp Buffer Offset Voltage
VRAMP = 1/2 VCC, IRAMPBUF = 0mA
●
0
±10
mV
VRAMPBUF(OL)
RAMPBUF Pin Output Low Voltage
IRAMPBUF = 3mA
●
32
60
mV
Ramp Buffer
2926fa
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LTC2926
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
VRAMPBUF(OH)
RAMPBUF Pin Output High Voltage
(VCC – VRAMPBUF)
IRAMPBUF = –3mA
IERROR(%)
IFBn to ITRACKn Current Mismatch
(IFBn – ITRACKn)/ITRACKn • 100%
VTRACK
VFB(REF)
MIN
TYP
MAX
UNITS
●
60
80
mV
ITRACKn = –10µA
ITRACKn = –1mA
●
●
0
0
±3
±3
%
%
TRACK Pins Voltage
ITRACKn = –10µA
ITRACKn = –1mA
●
●
0.776
0.776
0.800
0.800
0.824
0.824
V
V
FB Pins Internal Reference Voltage
VTRACKn = VCC, IFBn = 0mA
●
0.784
0.800
0.816
V
Tracking Channels
IFB(LEAK)
FB Pins Leakage Current
VFBn = 0.8V, VCC = 5.5V
●
0
±10
nA
VFB(CLAMP)
FB Pins Clamp Voltage
–1mA < IFBn < –1µA
●
1.7
2.0
2.4
V
Master Ramp and Supply
ΔVMGATE
MGATE Pin External N-Channel Gate
Drive (VMGATE – VCC)
IMGATE = –1µA
●
5.0
5.5
6.0
V
IMGATE(UP)
MGATE Pin Pull-Up Current
Fault Latch Clear, VON High, VMGATE = 3.3V
●
–7
–10
–13
µA
IMGATE(DN)
MGATE Pin Pull-Down Current
Fault Latch Clear, VON Low, VMGATE = 3.3V
●
7
10
13
µA
IMGATE(FAULT)
MGATE Pin Fault Pull-Down Current
Fault Latch Set, VON High, VMGATE = 5.5V,
VCC = 5.5V
●
5
20
50
mA
ΔVSGATE
SGATE Pins External N-Channel Gate
Drive (VSGATEn – VCC)
ISGATEn = –1µA, VFBn = 0.75V
●
5.0
5.5
6.0
V
ISGATE(UP)
SGATE Pins Pull-Up Current
Fault Latch Clear, VFBn = VFB(REF) – 10mV,
VSGATEn = 3.3V
●
–6
–10
–13
µA
ISGATE(DN)
SGATE Pins Pull-Down Current
Fault Latch Clear, VFBn = VFB(REF) + 10mV,
VSGATEn = 3.3V
●
6
10
13
µA
ISGATE(UPFST)
SGATE Pins Fast Pull-Up Current
Fault Latch Clear, VFBn = 0V, VSGATEn = 3.3V
●
–21
–30
–39
µA
ISGATE(DNFST)
SGATE Pins Fast Pull-Down Current
Fault Latch Clear, VFBn = 1V, VSGATEn = 3.3V
●
21
30
39
µA
Fault Latch Set, VON High, VSGATEn = 5.5V,
VCC = 5.5V
●
5
20
50
mA
V
Slave Supplies
ISGATE(FAULT)
SGATE Pins Fault Pull-Down Current
Remote Sense Switches
ΔVRSGATE
RSGATE Pin External N-Channel Gate
Drive (VRSGATE – VCC)
IRSGATE = –1µA
●
5.0
5.5
6.0
IRSGATE(UP)
RSGATE Pin Pull-Up Current
Fault Latch Clear, Switches On, VRSGATE = 0V
●
–7
–10
–13
µA
IRSGATE(DN)
RSGATE Pin Pull-Down Current
Fault Latch Clear, Switches Off,
VRSGATE = 3.3V
●
7
10
13
µA
IRSGATE(FAULT)
RSGATE Pin Fault Pull-Down Current
Fault Latch Set, Switches Off,
VRSGATE = 5.5V, VCC = 5.5V
●
5
20
50
mA
VRSGATE(TH)
RSGATE Pin Threshold Voltage
Ramping Completed on Pin Low, RSGATE
Falling
●
1.10
1.23
1.36
V
RSW(ON)
Remote Sense Switch On-Resistance
Switches On, VDn = VCC + 0.3V, ISn = –10mA
●
2
10
Ω
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into the device pins are positive; all currents out of
the device pins are negative. All voltages are referenced to ground unless
otherwise specified.
Note 3: The MGATE, SGATE1, SGATE2, RSGATE and STATUS/PGI pins are
internally limited to a minimum of 11.5V. Driving these pins to voltages
beyond the clamp level may damage the part.
2926fa
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LTC2926
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TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25°C, VCC = 3.3V
unless otherwise specified.
Supply Current vs Supply Voltage
Supply Current vs Temperature
10
IRAMPBUF = –3mA
ITRACKn = –1mA
IFBn = –1mA
10
0.808
IRAMPBUF = –3mA
ITRACKn = –1mA
IFBn = –1mA
8
6
IRAMPBUF = 0mA
ITRACKn = 0mA
IFBn = 0mA
4
0.812
ICC (mA)
6
IRAMPBUF = 0mA
ITRACKn = 0mA
IFBn = 0mA
4
2
3.0
3.5
4.0 4.5
VCC (V)
5.0
5.5
–25
0
25
50
TEMPERATURE (°C)
75
2926 G01
6
MGATE, RSGATE, SGATE1, SGATE2 PINS
GATE DRIVE (V)
5.6
5.4
–25
0
25
50
TEMPERATURE (°C)
GATE DRIVE = VPIN – VCC
30
MGATE, RSGATE, SGATE1, SGATE2 PINS
25
SGATE1,
SGATE2 PINS
FAST PULL-UP
MODE
3
2
MGATE, RSGATE,
SGATE1, SGATE2 PINS
PULL-UP MODE
1
100
Gate Fault Pull-Down Currents vs
Supply Voltage
GATE DRIVE = VPIN – VCC
4
75
2926 G03
5
20
15
10
5
FAULT LATCH SET
IGATE = –1µA
0
3.0
3.5
4.0 4.5
VCC (V)
5.0
5.5
6.0
0
5
10
15
20
ILOAD (µA)
25
30
MGATE, RSGATE Fault Pull-Down
Currents vs Temperature
30
3.0
3.5
4.0 4.5
VCC (V)
5.0
5.5
6.0
2926 G07
30
MGATE, RSGATE PINS
SGATE1, SGATE2 PINS
25
VCC = 5.5V
20
15
VCC = 3.3V
10
0
–50
0
2.5
SGATE Fault Pull-Down Current vs
Temperature
25
5
35
2926 G06
2926 G05
ISGATE(PD) (mA)
5.0
2.5
IMGATE(PD), IRSGATE(PD) (mA)
GATE DRIVE (V)
0.788
–50
Gate Drive Voltages vs
Load Current
5.8
5.2
100
2926 G02
Gate Drive Voltages vs
Supply Voltage
6.0
ITRACK = –1mA
0.792
0
–50
6.0
0.800
0.796
2
0
2.5
ITRACK = –10µA
0.804
IGATE(PD) (mA)
ICC (mA)
8
Track Pin Voltage vs Temperature
12
VTRACK (V)
12
FAULT LATCH SET
–25
0
25
50
TEMPERATURE (°C)
15
75
100
2926 G08
VCC = 3.3V
10
5
VCC = 2.9V
VCC = 5.5V
20
0
–50
FAULT LATCH SET
–25
VCC = 2.9V
0
25
50
TEMPERATURE (°C)
75
100
2926 G09
2926fa
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LTC2926
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TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25°C, VCC = 3.3V
unless otherwise specified.
RAMPBUF Output Low Voltage vs
Temperature
40
VCC = 2.9V
VCC = 5.5V
10
0
–50
STATUS/PGI PIN
200
ISTATUS/PGI = 5mA
VCC = 2.9V
30
20
250
IRAMPBUF = –3mA
VOH = VCC – VRAMPBUF
80
VOH (mV)
VOL (mV)
100
IRAMPBUF = 3mA
60
VCC = 5.5V
40
0
25
50
TEMPERATURE (°C)
75
100
2926 G10
0
–50
150
100
FAULT PIN
IFAULT = 5mA
20
–25
Logic Output Low Voltages vs
Supply Voltage
VOL (mV)
50
RAMPBUF Output High Voltage vs
Temperature
50
–25
0
25
50
TEMPERATURE (°C)
75
100
2926 G11
0
2.5
3.0
3.5
4.0 4.5
VCC (V)
5.0
5.5
6.0
2926 G12
2926fa
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LTC2926
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PI FU CTIO S GN/UFD Packages
D1, S1, D2, S2 (Pins 6, 4, 15, 17/Pins 4, 2, 13, 15):
Remote Sense Switches #1 and #2. A 10Ω (max) switch
connects each pair of pins (D1/S1 and D2/S2) after MGATE,
SGATE1 and SGATE2 are all fully enhanced (MGATE >
RAMP + 4.9V or RAMP > VCC, and SGATE1, SGATE2 >
VCC + 4.9V). The switch can be used to compensate for
the voltage drop across the external MOSFET that controls
a slave or the master supply. Connect the switch between
the load and the supply’s sense node. Before the external
MOSFET is fully enhanced, a resistor between the supply’s
output and sense nodes provides local feedback. When
the ON pin voltage is low, the switch will open before the
MGATE, SGATE1 and SGATE2 pins will ramp down. Leave
unused switch terminal pairs unconnected.
Exposed Pad (Pin 21, UFD Package Only): Exposed pad
may be left open or connected to device GND.
FAULT (Pin 9/Pin 7): Negative-Logic Fault Input/Output.
Under normal conditions the internal fault latch is not set
and an 8.5µA current pulls up FAULT to a diode drop below
VCC. When the voltage at FAULT is pulled below 0.5V, a
fault condition is latched and an internal N-channel MOSFET pulls FAULT to GND until the latch is reset. The fault
condition also pulls STATUS/PGI low, opens the remote
sense switches, and pulls MGATE, SGATE1 and SGATE2
to GND to disconnect the master and slave supplies from
their loads. Pulling STATUS/PGI below 1V after the power
good time-out delay also latches a fault. The fault latch is
reset when the ON pin voltage is below 0.5V, or when VCC
is undervoltage. The fault latch is armed when the ON pin
voltage exceeds 0.6V. To auto-retry after a fault, connect
FAULT to the ON pin. Leave the FAULT pin unconnected
if it is unused.
FB1, FB2 (Pins 3, 18/Pins 1, 16): Feedback Control Input/Outputs. Each FB pin connects to the feedback node
of a slave supply. Connect an FB pin to the tap point of a
resistive voltage divider between the source (load side)
of the external MOSFET and GND. For a slave supply with
an accessible feedback path, no external MOSFET may
be necessary. In that case, connect an FB pin to the tap
point of a resistive voltage divider between the supply
generator’s feedback node and GND. To prevent damage
to the slave supply, the FB pins will not force the slave’s
feedback node above 2.4V. In addition, it will not actively
sink current even when the LTC2926 is not powered. Tie
unused FB pins to GND.
GND (Pin 10/Pin 8): Device Ground.
MGATE (Pin 12/Pin 10): Master Gate Drive for External
N-Channel MOSFET/Master Ramp. When the ON pin is
high, an internal 10µA current charges the gate of an
external N-channel MOSFET. A capacitor from MGATE
to GND sets the master ramp rate. Add a 10Ω resistor
between the capacitor and the MOSFET’s gate to prevent
high frequency oscillations. An internal charge pump
guarantees that the MGATE pin voltage will pull up to
5.5V above VCC, which ensures that logic-level N-channel
MOSFETs are fully enhanced. When the ON pin is pulled
low, the MGATE pin is pulled to GND by a 10µA current
source. Upon a fault condition, the MGATE pin is pulled
low immediately with 20mA. To create a master ramp
signal without an external MOSFET, tie the MGATE pin to
the RAMP pin. A weak internal clamp on the RAMP pin
limits MGATE to VCC + 1V in this case. Leave the MGATE
pin unconnected if it is unused.
ON (Pin 7/Pin 5): On Control Input. The ON pin has
a threshold of 1.23V with 75mV of hysteresis. A high
causes 10µA to flow out of the MGATE pin, ramping up
the supplies. A low causes 10µA to flow into the MGATE
pin, ramping down the supplies. Pull the ON pin below
0.5V to reset the fault latch. Pull the ON pin above 0.6V
after a fault latch reset to arm the fault latch.
PGTMR (Pin 8/Pin 6): Power Good Timer. Connect an
external capacitor between PGTMR and GND to set the
Power Good Time-Out Delay. When the ON pin is above
1.23V, a 10µA current pulls up PGTMR to VCC, otherwise
an internal N-channel MOSFET pulls PGTMR to GND. If
the voltage on PGTMR exceeds 1.23V and the voltage
on STATUS/PGI is not above 1.23V, a fault condition is
latched, the remote sense switches are opened, and FAULT,
STATUS/PGI, MGATE, SGATE1, SGATE2 and RSGATE will
be immediately pulled to GND. To disable the Power Good
Timer tie PGTMR to GND.
2926fa
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LTC2926
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PI FU CTIO S GN/UFD Packages
RAMP (Pin 11/ Pin 9): Ramp Buffer Input. Connect the
RAMP pin to the master ramp signal to force the slave
supplies to track it. When the RAMP pin is connected to
the source of an external N-channel MOSFET, the slave
supplies track the MOSFET’s source, the master supply
voltage, as it ramps up and down. When a master supply
is not required, the RAMP pin can be tied directly to the
MGATE pin to form a master ramp voltage. In this configuration, the supplies track the capacitor on the MGATE pin as
it is charged and discharged by the 10µA current source
that is controlled by the ON pin. The RAMP pin is weakly
clamped to VCC + 1V. Do not drive RAMP above VCC with
a low impedance source to avoid sinking large currents
into the pin. Ground the RAMP pin if it is unused.
RAMPBUF (Pin 20/Pin 18): Ramp Buffer Output. The
RAMPBUF pin provides a low impedance buffered version of the signal on the RAMP pin. This buffered output
drives the resistive voltage dividers that connect to the
TRACK pins. Limit the capacitance at the RAMPBUF pin
to less than 100pF.
RSGATE (Pin 13/Pin 11): Gate Drive for Internal and
External N-Channel MOSFET Remote Sense Switches. A
remote sense path between a load and the sense input of
its supply generator automatically compensates for voltage
drops across the tracking MOSFET. After the series MOSFETs are fully enhanced, a 10µA current pulls up RSGATE.
An internal charge pump guarantees that RSGATE will
pull up to 5.5V above VCC, which ensures that logic-level
N-channel MOSFETs are fully enhanced. When the voltage
at RSGATE exceeds VCC + 4.9V, the STATUS/PGI pull-down
is released. When the ON pin is low, a 10µA current source
pulls RSGATE to GND. Supplies will not track down until
the RSGATE pin voltage falls below 1.23V, which ensures
that the remote sense switches open before the loads are
disconnected. Connect RSGATE to the gates of additional
external N-channel MOSFETs to create more remote sense
switches. Upon a fault condition, the RSGATE pin is pulled
low immediately with 20mA. Optionally connect a capacitor between RSGATE and GND to set the switch-on rate
or to add delay between switch closure and STATUS/PGI
assertion. Leave RSGATE unconnected if it is unused.
SGATE1, SGATE2 (Pins 5, 16/Pins 3, 14): Slave Gate Controllers for External N-Channel MOSFETs. Each SGATE pin
ramps a slave supply by controlling the gate of an external
N-channel MOSFET so that its source terminal follows the
tracking profile set by external resistors and the master
ramp. It is a good practice to add a 10Ω resistor between
this pin and the MOSFET’s gate to prevent high frequency
oscillations. An internal charge pump guarantees that the
SGATE pin voltage will pull up to 5.5V above VCC, which
ensures that logic-level N-channel MOSFETs are fully
enhanced. Leave unused SGATE pins unconnected.
STATUS/PGI (Pin 14/Pin 12): Status Output/Power Good
Input. A 10µA current pulls up STATUS/PGI when MGATE,
SGATE1 and SGATE2 are fully enhanced, and the remote
sense switches are closed, otherwise an internal N-channel
MOSFET pulls down STATUS/PGI. If the STATUS/PGI pin
is pulled below 1V after the power-good time-out delay
(see PGTMR pin description), the fault latch is set, and
MGATE, SGATE1, SGATE2 and RSGATE are all pulled low
immediately. An internal charge pump guarantees that the
STATUS/PGI pin voltage will pull up to 5.5V above VCC.
An external pull-up resistor may be added to limit the
STATUS/PGI voltage to logic levels. Leave the STATUS/PGI
pin unconnected if it is unused.
TRACK1, TRACK2 (Pins 2, 19/Pins 20, 17): Tracking Control Inputs. A resistive voltage divider between RAMPBUF
and each TRACK pin determines the tracking profile of
each supply channel. Each TRACK pin pulls up to 0.8V,
and the current supplied at TRACK is mirrored at FB. The
TRACK pins are capable of supplying at least 1mA when
VCC = 2.9V. They may be capable of supplying up to 10mA
when the supply is at 5.5V, so care should be taken not to
short this pin for extended periods. Limit the capacitance
at the TRACK pins to less than 25pF. Leave unused TRACK
pins unconnected.
VCC (Pin 1/Pin 19): Positive Voltage Supply. Operating
range is from 2.9V to 5.5V. An undervoltage lockout resets
the part when the supply is below 2.4V. VCC should be
bypassed to GND with a 0.1µF capacitor.
2926fa
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2.4V
+
VCC
–
VCC
UVLO
FAST PULL-DOWN
U
CLEAR/ARM
SIGNAL LATCH
ON
+
0.6V
–
0.5V
+
VCC
R
DELAY
S
Q
8.5µA
FAULT LATCH
CLR/ARM
R
S
Q
FAULT
FAULT
DELAY
–
+
1.23V
–
+
0.5V
–
VCC
10µA
+
0.1V
–
PGTMR
UVLO
PGTMR HIGH
PGI LOW
+
–
1.23V
+
1.23V
–
RSGATE
+
VCC + 4.9V
–
RSGATE
+
1.23V
–
MGATE
+
RAMP + 4.9V
–
RAMP
+
VCC
–
SGATE1
+
VCC + 4.9V
–
SGATE2
+
–
10µA
STATUS/PGI
UVLO
CHARGE
PUMP
10µA
GATE UP
10µA
MGATE
FAST
PULL-DOWN
CHARGE
PUMP
10µA
RSGATE UP
RSGATE
FAST
PULL-DOWN
10µA
VCC + 4.9V
CHARGE
PUMP
D1
S1
D2
S2
CHARGE
PUMP
VCC
SGATE2
10µA/30µA
0.8V
VCC
TRACK2
0.8V
+
UP/DOWN
SGATE1
–
+
10µA/30µA
FAST
PULL-DOWN
FB2
–
TRACK1
RAMPBUF
FB1
RAMP
1x
GND
2926 BD
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Power Supply Tracking and Sequencing
Operation
The LTC2926 handles a variety of power-up profiles to
satisfy the requirements of digital logic circuits including
FPGAs, PLDs, DSPs and microprocessors. These requirements fall into one of the four general categories illustrated
in Figures 1 to 4.
The LTC2926 provides a simple solution to allow all of
the power supply tracking and sequencing profiles shown
in Figures 1 to 4. A single LTC2926 controls up to three
supplies: two “slave” supplies that track a “master” signal.
With just four resistors and an external N-channel MOSFET,
each slave supply is configured to ramp up and down as
a function of the master signal. This master signal can
be a third supply that is ramped up through an external
MOSFET, whose ramp rate is set with a single capacitor,
or it can be a signal generated by tying the MGATE and
RAMP pins together to an external capacitor.
Some applications require that the potential difference
between two power supplies must never exceed a specified voltage. This requirement applies during power-up
and power-down as well as during steady-state operation,
often to prevent destructive latch-up in a dual supply IC.
Typically, this is achieved by ramping the supplies up
and down together (Figure 1). In other applications it is
desirable to have the supplies ramp up and down ratiometrically (Figure 2) or with fixed voltage offsets between
them (Figure 3).
Certain applications require one supply to come up after
another. For example, a system clock may need to start
before a block of logic. In this case, the supplies are sequenced as in Figure 4, where the 1.8V supply ramps up
completely followed by the 2.5V supply.
Tracking Cell and Gate Controller Cell
The LTC2926’s operation is based on the combination of
a tracking cell and a gate controller cell that is shown in
Figure 5. The tracking cell servos the TRACK pin at 0.8V,
and the current supplied by the TRACK pin is mirrored at the
FB pin. The gate controller cell servos the FB pin at 0.8V by
driving the gate of the external N-channel MOSFET (QEXT),
and establishes the slave output voltage at the source of
the MOSFET based on the TRACK pin current and resistors
MASTER
SLAVE2
SLAVE2
SLAVE1
SLAVE1
500mV/DIV
500mV/DIV
5ms/DIV
2926 F01
5ms/DIV
Figure 1. Coincident Tracking
2926 F02
Figure 2. Ratiometric Tracking
MASTER
SLAVE2
SLAVE2
SLAVE1
SLAVE1
500mV/DIV
500mV/DIV
5ms/DIV
Figure 3. Offset Tracking
2926 F03
5ms/DIV
2926 F04
Figure 4. Supply Sequencing
2926fa
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QEXT
SUPPLY
SLAVE
LTC2926
TRACKING CELL
GATE CONTROLLER CELL
VCC
VCC + 5V
0.8V
+
+
10µA
SGATE
0.8V
–
–
MASTER
RAMP
RTB
RTA
10µA
RFB
TRACK
FB
ITRACK
IFB
2926 F05
RFA
Figure 5. Simplified Tracking Cell and Gate Controller Cell Combination
RFA and RFB. The slave output voltage varies as a function
of the master signal with terms set by RTA and RTB. By
selecting appropriate values of RTA and RTB, it is possible
to generate any of the profiles in Figures 1 to 4.
Controlling the Ramp-Up and Ramp-Down Behavior
The operation of the LTC2926 is most easily understood by
referring to the simplified functional diagram in Figure 6.
When the ON pin is low, the remote sense switch is opened
and the MGATE pin is pulled to ground causing the master
signal to remain low. Since the current through RTB1 is at
its maximum when the master signal is low, the current
sourced by FB1 is also at its maximum. The current forces
the FB1 pin voltage above 0.8V, which pulls the SGATE1
pin low and disconnects the slave’s supply generator. The
minimum voltage across the slave load is a function of the
maximum FB1 current, the feedback divider resistors, and
the load resistance (see Load Requirements).
When the ON pin rises above 1.23V, the master signal
ramps up, and the slave supply tracks the master signal.
The master ramp rate is set by an external capacitor driven
by a 10µA current source from an internal charge pump. If
no external MOSFET is used for the master signal, the ramp
rate is set by tying the MGATE and RAMP pins together
at one terminal of the external capacitor (see Ratiometric
Tracking Example or Supply Sequencing Example). The
MGATE pin voltage will be limited to VCC + 1V (max) by
the weak internal clamp on the RAMP pin.
The rising master signal decreases the tracking current
mirrored out of the FB1 pin. The gate controller circuitry
maintains 0.8V at FB1 by driving the SGATE1 voltage and,
via the external MOSFET source-follower, the slave supply
output. When the slave supply output reaches the slave
supply module voltage, the FB1 pin will fall below 0.8V
and the gate controller will drive the SGATE1 pin above
VCC to fully enhance the MOSFET.
After the MGATE, SGATE1 and SGATE2 pins reach their
maximum voltages, the RSGATE pin is pulled up by a
10µA current source from an internal charge pump,
which closes the integrated remote sense switches. The
integrated remote sense switch allows the slave supply
generator to compensate for voltage drop across the slave’s
MOSFET (Q1).
When the ON pin falls below VON(TH) – ΔVON(TH), typically
1.16V, the remote sense switch opens and the MGATE pin
pulls down with 10µA. The master signal and the slave
supplies will fall at the same rate as they rose previously,
following the tracking or sequencing profile in reverse.
The ON pin can be controlled by a digital I/O pin or it
can be used to monitor an input supply. By connecting a
resistive voltage divider from an input supply to the ON
pin, the supplies will ramp up only after the monitored
supply reaches a preset voltage.
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SUPPLY MODULE
Q0
MASTER
OUT
CMGATE
SUPPLY MODULE
Q1
SLAVE1
OUT
RX1
SENSE
VCC
MGATE
RAMP
REMOTE SENSE SWITCH
D1
S1
MGATE
+
RAMP + 4.9V
–
CHARGE
PUMP
SGATE1
+
VCC + 4.9V
–
10µA
TO
RSGATE
PIN
10µA
SGATE2
+
VCC + 4.9V
–
CHARGE
PUMP
ON/OFF
ON
10µA
+
1.23V
–
10µA
RAMPBUF
1x
VCC
CHARGE
PUMP
0.8V
0.8V
+
10µA
SGATE1
+
–
RTB1
10µA
–
RFB1
TRACK1
FB1
GND
RTA1
RFA1
2926 F06
Figure 6. Simplified Functional Block Diagram
Optional Master Supply MOSFET
Figure 7 illustrates how an optional external N-channel
MOSFET (device Q0) can ramp up a supply that doubles as
the master signal. The MOSFET’s gate is tied to the MGATE
pin and its source is tied to the RAMP pin. The MGATE pin
sources or sinks 10µA to ramp the MOSFET’s gate up or
down at a rate set by the external capacitor connected to
the MGATE pin. The series MOSFET controls any supply
with an output voltage between 0V and VCC.
To compensate for voltage drop across the master supply
MOSFET, add an optional external remote sense switch
(device Q3 in Figure 7) connected between RAMP and the
sense input of the master voltage supply module. Tie the
gate of the external switch MOSFET to the RSGATE pin
for automatic remote sense switching.
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3.3V MODULE
1.8V MODULE
Q0
Q1
IN OUT
VIN
MASTER
RX0
1.8V
SLAVE1
IN OUT
VIN
RX1
Q3
SENSE
SENSE
10Ω
10Ω
2.5V MODULE
1.8V MODULE
Q1
1.8V
SLAVE1
IN OUT
VIN
Q2
CMGATE
RX2
RX1
SENSE
2.5V
SLAVE2
IN OUT
VIN
NC
SENSE
10Ω
10Ω
RSGATE MGATE RAMP SGATE1 SGATE2
2.5V MODULE
Q2
IN OUT
VIN
CMGATE
RX2
D2
VIN
SENSE
10Ω
RSGATE
D1
2.5V
SLAVE2
0.1µF
MGATE RAMP SGATE1 SGATE2
TRACK2
S2
TRACK1
RTA2
FAULT
RFA1
RTB2
RFB2
TRACK2
FB2
VIN
FAULT
PGTMR
STATUS/PGI
FAULT
ON
10k
GND
PGTMR
STATUS/PGI
STATUS
2926 F08
CPGTMR
Figure 8. Typical Application Without Master Supply
10k
GND
ON/OFF
RFA2
RFA2
VIN
10k
VIN
10k
FB1
LTC2926
RTA1
FB2
VIN
RFB1
ON
RFA1
RFB2
S1
RAMPBUF
ON/OFF
LTC2926
RTA1
RTB1
FAULT
RFB1
FB1
RTB2
VCC
RTA2
S2
TRACK1
D2
0.1µF
S1
RTB1
D1
VIN
VCC
RAMPBUF
STATUS
2926 F07
CPGTMR
Figure 7. Typical Application with Master Supply
Ramp Buffer
The RAMPBUF pin provides a buffered version of the RAMP
pin voltage that drives the resistive dividers on the TRACK
pins. When there is no external MOSFET, it sources or sinks
up to 3mA to drive the track resistors even though the
MGATE pin only supplies 10µA (Figure 8). The RAMPBUF
pin also proves useful in systems with an external MOSFET.
If RTBn were directly connected to the MOSFET’s source
(the master output), the servo mechanism of the tracking
cell could potentially drive the master output towards 0.8V
when the MOSFET is off. The ramp buffer prevents this
by eliminating that path for current.
Fault Input/Output
The FAULT pin allows external upstream monitoring circuits
to control and to communicate with the LTC2926. The pin
is driven internally by an N-channel MOSFET pull-down
to GND, and by an 8.5µA pull-up to VCC through a series
diode. Under normal conditions, the MOSFET is off and the
current pulls the FAULT pin voltage high. When an upstream
monitor signal pulls FAULT below 0.5V, the LTC2926’s
internal fault latch is set, which immediately opens the
remote sense switches and cuts off the master and slave
supplies by pulling MGATE, SGATE1 and SGATE2 to GND.
A fault also activates the internal MOSFET pull-down on the
STATUS/PGI pin, which indicates to external downstream
monitoring circuits that the supplies are no longer valid
(see Status Output). Until the fault latch is reset, the supplies stay disconnected and an internal pull-down keeps
the FAULT pin low as a signal to upstream monitors.
Fault latch reset is initiated by bringing the ON pin voltage
below 0.5V, and completed when PGTMR is <0.1V. Reducing the VCC pin voltage below VCC(UVLO) – ΔVCC(UVLO),
typically 2.35V, also resets the fault latch. After it is
cleared, the fault latch is armed by bringing the ON pin
voltage above 0.6V. No faults can be latched until after
the latch is armed.
The FAULT pin is pulled up by 8.5µA to VCC through a
Schottky diode, which allows the pin to be pulled safely
above the LTC2926’s supply if required. Leave the FAULT
pin unconnected if it is unused.
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Status Output
The output aspect of the STATUS/PGI pin allows the
LTC2926 to control and communicate with external
downstream circuits. The pin is driven internally by an
N-channel MOSFET pull-down to GND and a 10µA pullup to an internal charge pump. The pull-down keeps the
STATUS/PGI pin low until MGATE, SGATE1 and SGATE2
are fully enhanced, and the remote sense switches are
closed. The pull-down then shuts off, and STATUS/PGI
pin rises, indicating to downstream monitors that the
supplies are fully ramped up. The STATUS/PGI pin pulls
low when the MGATE, SGATE1, SGATE2 or RSGATE pin
is low, either because a fault has been latched, or because
the ON pin is low.
An internal charge pump rail at VCC + 5.5V sources the
STATUS/PGI pull-up current. An external resistor may be
added to create logic level voltages, or the pin may be
used to enhance the gates of external N-channel MOSFET
switches, if desired.
time allotted. If supply ramping completes, any downstream
circuits that pull down the STATUS/PGI pin after the timer
duration also will trip the timeout circuit. A fault caused
by a power good timeout has the same effect as a fault
triggered by the FAULT pin: supplies are disconnected
and the fault latch is set. The fault latch may be cleared as
described in the Fault Input/Output section above.
The power good timer duration is configured by a capacitor
tied between PGTMR and GND. The pin’s 10µA current
source ramps up the capacitor voltage when the ON pin is
high, otherwise 4mA pulls PGTMR to GND. The capacitor,
CPGTMR, required to configure the power good timeout
duration, tPGTMR, is determined from:
CPGTMR =
10µA • tPGTMR
1.23V
If the power good timeout feature is not used, tie PGTMR
to GND.
Retry on Fault
Power Good Timeout
The input aspect of the STATUS/PGI pin allows external
downstream monitoring circuits to control the LTC2926 as
shown in Figure 9. The power good timeout circuit disconnects the supply generators if for any reason the voltage
level of the STATUS/PGI pin is not high after the timeout
period. During a ramp-up, the timeout circuit will trip if the
internal pull-down on STATUS/PGI fails to release, which
indicates that supply ramping was not completed in the
Q1
1.8V
SOURCE
1.8V
SLAVE1
10Ω
Q2
2.5V
SOURCE
2.5V
SLAVE2
LTC2904
10Ω
SGATE1 SGATE2
ON/OFF
ON
RFB1
FB1
RFA1
LTC2926
STATUS/PGI
V2
V1
RST
S2
RST
S1
GND
TOL
LOAD VOLTAGE
MONITOR
(10% TOLERANCE)
RFB2
GND PGTMR FB2
2926 F09
RFA2
CPGTMR
Figure 9. External Load Monitor Controlling LTC2926 via Power
Good Input
The LTC2926 continuously attempts to ramp up the supplies
after a fault if the FAULT pin is tied to the ON pin. When
the FAULT and ON pins go low together, the internal fault
latch is set by the falling FAULT pin, and the fault latch is
reset by the falling ON pin. A short internal delay of several
microseconds guarantees triggering of fast pull-down
circuits on the RSGATE, MGATE, SGATE1 and SGATE2
pins, which opens the remote sense switches and disconnects the master and slave supplies before the fault latch
is reset. If no external signal pulls down the FAULT pin,
the internal 8.5µA pull-up current or an external pull-up
resistor increases the ON (and FAULT) pin voltage above
0.6V, which arms the fault latch. A ramp-up begins when
ON is above 1.23V.
In applications where the LTC2926 is configured for fault
retry, some details of the retry behavior are determined by
the source and duration of the fault signal. When a fault
is triggered by an external pull-down signal on the FAULT
(and ON) pin, supply ramping will not restart until the low
input ceases. When a power good fault is triggered by an
external pull-down signal on the STATUS/PGI pin, supply
ramping restarts immediately. If the low signal persists
2926fa
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through the power good timeout period, a fault and retry
will subsequently occur.
To ensure a consistent power good timeout period, the
LTC2926 requires the PGTMR pin voltage to fall below 0.1V
for the fault latch reset to complete. The ON pin needs to be
held low for only 10µs to initiate fault reset; it is allowed to
go high while the timing capacitor on PGTMR discharges
to 0.1V (see Functional Block Diagram).
When a resistive voltage divider drives the ON and FAULT
pins together, include the contribution of IFAULT(UP) when
choosing the resistor values (Figure 10a). When a logic
output drives both pins, up to 30kΩ of series resistance
may be added to limit the output current while the fault
pull-down is active (Figure 10b).
VIN
RONB
VON
LTC2926
VCC
ON
VCC
RONA
IFAULT(UP)
FAULT
FAULT LATCH
RONA
VON =
•V
RONA + RONB IN
Q
R
GND
+ (RONA || RONB) • IFAULT(UP)
S
(a)
VIN
RSERIES
IOUT
LTC2926
VCC
ON
VCC
For applications that require more than two remote sense
switches, connect the RSGATE pin to the gates of additional
external N-channel MOSFETs. An internal charge pump
guarantees that RSGATE will reach VCC + 5.5V, which allows full enhancement of logic-level MOSFETs with source
or drain voltages up to VCC.
The switches are open when supply ramping has not
completed to avoid creating a power path between the
supply generator and the load. When the remote sense
switches are open, the supply generator’s sense input must
be connected locally to its output through a resistor that
is much larger than the remote sense switch resistance
of 10Ω (max); a 100Ω resistor is adequate for most applications as in Figure 7.
Some supply modules have built-in resistors of 10Ω or
less between their out and sense pins, which may require
a lower switch resistance. Choose an external N-channel
MOSFET with an RDS(on) that is at most 1/10 the module
out-to-sense resistance, but that is still much larger than
the RDS(on) of the power path MOSFET.
FAULT LATCH
Q
LIMIT IOUT WITH RSERIES
RSERIES ≤ 30kΩ
The LTC2926 provides integrated remote sense switches
that solve the problem of voltage drops in the external series
MOSFETs that control supply ramping. A switch creates
a feedback path from a slave supply output to the slave
supply generator sense input that allows the generator
to compensate for the I • R drop across the controlling
MOSFET (see, for example, Figure 6). After the supply
ramping is complete, but before the internal pull-down
releases the STATUS/PGI pin, the two integrated remote
sense switches are closed.
If neither external remote sense switches nor a status activation delay is required, leave the RSGATE pin
unconnected.
IFAULT(UP)
FAULT
Automatic Remote Sense Switching
GND
S
R
2926 F10
(b)
Figure 10. Fault Retry Configurations, (a) Resistive Voltage
Divider and (b) Logic Driven
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SUPPLY
MODULE
+ VDS –
Q0
MASTER
SUPPLY
OUT
LOAD
RX
ISW
MGATE
Q3
To minimize switch current, choose RX >> RDS. In applications that use the LTC2926’s integrated remote sense
switches, ISW must not exceed the Absolute Maximum
Ratings for switch pin currents.
It is recommended design practice to satisfy both
resistance value conditions.
SENSE
RSGATE
SGATE Voltage at Ramp Start/End
(a)
+ VDS –
VOUT
VSUPPLY
RDS
IL
RX
RSW
ISW
VSENSE
(b)
2926 F11
Figure 11. Supply and Sense Path Detail, (a) Functional Diagram
and (b) Equivalent Circuit When Remote Sense Switch Is Closed
Considerations when Using Remote Sense Switches
Consider the supply and sense path detail functional
diagram and equivalent circuit in Figure 11. For proper
compensation of the I • R drop across the external control
MOSFET Q0 by the supply module, the voltage at its sense
pin input must be equal to the supply voltage at the load.
Solving for VSENSE in the equivalent circuit yields:
⎛ RX
⎞
⎛ RSW ⎞
VSENSE = ⎜
•
V
+
SUPPLY
⎜⎝ R + R ⎟⎠ • VOUT
⎝ R X + RSW ⎟⎠
X
SW
For the best compensation, i.e., VSENSE ≈ VSUPPLY, choose
RX >> RSW.
The remote sense switch is intended to be a low-current
voltage feedback path. The control MOSFET (Q0 in Figure
11a) should carry all but a tiny fraction of the entire load
current. The remote sense switch current is:
⎛
⎞
RDS
ISW = ILOAD • ⎜
⎝ R X + RSW + RDS ⎟⎠
When the master ramp is 0V (before ramp up or after
ramp down), the control MOSFET ideally conducts no
current. If the tracking profile has no delay or offset, the
gate control loops may force the SGATE pins either to
ground or to just below the MOSFET threshold voltage,
depending on reference offsets, resistor mismatches and
the load resistance. In both cases the slave load will be at
about 0V, but if a known state of SGATE is desired, include
an offset in the tracking profile.
To guarantee grounding of the SGATE pins at RAMP = 0V,
include a positive offset, VOS, based on the maximum slave
supply voltage, VSLAVE(max), and the tracking/feedback
resistor tolerance. Note that at the start of ramp up, the
gate capacitance of the MOSFET must be charged to the
threshold voltage before the source begins ramping. The
SGATE pins do provide extra current to speed the initial
charging.
Calculate the required VOS from:
VOS ≥ k • VSLAVE(max)
For 1% resistors k = 1/8, for 5% resistors k = 1/4, for
10% resistors k = 2/5.
To guarantee the SGATE pins sit at the MOSFET threshold
voltages at RAMP = 0V, include a negative offset. Note that
when the master ramp goes to 0V, the slave supplies will
remain above ground by the magnitude of the offset.
Calculate the required VOS from:
VOS ≤ –k • VSLAVE(max)
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Q0
MASTER
VIN
SUPPLY MODULE
Q1
VIN
SLAVE1
IN OUT
RX1
2. Choose the feedback resistors based on the slave
supply voltage and slave load.
10Ω
SENSE
10Ω
SUPPLY MODULE
Q2
VIN
SLAVE2
IN OUT
0.1µF
RX2
CMGATE
SENSE
10Ω
VCC
D2
S1
RAMPBUF
S2
RFB1
RTB1
TRACK1
RFB ≥ 100 • RL (recommended),
RFB ≥ 23 • RL (required)
FB1
RFA1
LTC2926
RTB2
RFB2
TRACK2
VIN
10k
FAULT
FAULT
ON/OFF
ON
RFA2
10k
GND
PGTMR
STATUS/PGI
STATUS
2926 F12
CPGTMR
⎛ 1− TOLR ⎞
RFA < RFB • ⎜
⎝ 1+ TOLR ⎟⎠
Figure 12. Three-Supply Application
Three-Step Design Procedure
The following three-step design procedure allows one
to choose the FBn resistors, RFAn and RFBn, the TRACKn
resistors, RTAn and RTBn, and the master ramp capacitor,
CMGATE, that give any of the tracking or sequencing profiles
shown in Figures 1 to 4. A three-supply application circuit
is shown in Figure 12.
1. Set the ramp rate of the master signal.
Solve for the value of CMGATE, the capacitor on the MGATE
pin, based on the desired ramp rate (volts per second)
of the master ramp signal, SM, and the MGATE pull-up
current IMGATE, which is nominally 10µA.
CMGATE =
IMGATE
SM
(2)
Second, determine a value for the lower feedback resistor,
RFA, that will ensure that the LTC2926 fully enhances the
gate of the slave control MOSFET at the end of ramping.
Select RFA based on RFB, the resistor tolerance, TOLR, and
the maximum slave supply voltage, VSLAVE(max):
FB2
VIN
RTA2
It is important that the feedback resistors are significantly
larger than the load resistance, especially as the slave
voltage nears ground (see Load Requirements).
First determine the effective slave load resistance, RL (not
shown), at low slave voltage levels, and select the value
of the top feedback resistor, RFB, to satisfy:
MGATE RAMP SGATE1 SGATE2
D1
RTA1
If the master ramp signal is not a master supply, tie the
RAMP pin to the MGATE pin.
(1)
If the master ramp signal is a master supply, consider
the gate capacitance of the required external N-channel
MOSFET. If the gate capacitance is comparable to CMGATE,
reduce the external capacitor’s value to compensate for
the gate capacitance of the MOSFET.
⎛ VSLAVE (max) ⎞
⎜⎝ 0.784V − 1⎟⎠
(3)
Note: Choose the value of VSLAVE(max) to cover all slave
supply voltage tolerances by a good margin. Exceeding the
VSLAVE(max) voltage used for this calculation can result in
triggering a Power Good Fault unintentionally.
If the slave generator has an accessible resistive divider
and a ground-based voltage reference, it may be able to
be controlled without a series MOSFET. In that case, let
the generator’s design set RFA and RFB, substitute the
generator’s reference voltage for VFB(REF) in step 3, and
see the subsection Slave Control Without MOSFETs.
3. Solve for the tracking resistors that set the desired
ramp rate and voltage offset or time delay of the slave
supply.
Choose a ramp rate for the slave supply, SS. If the slave
supply tracks coincidently with the master supply or with
only a fixed offset or delay, then the slave ramp rate equals
the master ramp rate. Be sure that the slave ramp rate and
its offset or delay allows the slave voltage to finish ramping
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MASTER
SLAVE2
SLAVE1
500mV/DIV
500mV/DIV
2926 F13
5ms/DIV
5ms/DIV
Figure 13. Coincident Tracking Waveforms from Figure 14 Circuit
before the master ramp reaches its final value; otherwise,
the slave supply voltage will be held below its intended
level. Calculate the upper track resistor, RTB, from:
⎛S ⎞
R TB = RFB • ⎜ M ⎟
⎝ SS ⎠
(4)
Choose a voltage difference between the master and slave
ramps, ΔV, if offset tracking is desired. If a time delay is
desired for supply sequencing, calculate an effective voltage difference based on the master ramp rate. If neither
voltage offset nor time delay is required, set ΔV = 0V.
Coincident Tracking Example
A typical three-supply application is shown in Figure 14.
The master signal is 3.3V, the slave 1 supply is a 1.8V
module, and the slave 2 supply is a 2.5V module. Allow for
±10% tolerance of the slave supply voltages. Both slave
supplies track coincidently with the 3.3V master supply
that is controlled by an external MOSFET. The ramp rate of
the supplies is 100V/s. The slave supplies’ minimum load
resistances are 150Ω. The external configuration resistors
Q0
IRF7413Z
3.3V VIN
1.8V MODULE
ΔV = a voltage difference (offset tracking), or
(5a)
ΔV = SM • tDLY (supply sequencing), or
(5b)
ΔV = 0V (coincident/ratiometric tracking)
(5c)
3.3V
RX1
100Ω
10Ω
SENSE
3.3V
1.8V
SLAVE1
IN OUT
10Ω
Q2
IRF7413Z
2.5V MODULE
Use the following formula to determine the lower track
resistors, RTA, using the TRACK pin voltage, VTRACK, and
the FB pin internal reference voltage, VFB(REF), both from
the Electrical Characteristics:
3.3V
MASTER
Q1
IRF7413Z
IN OUT
RX2
100Ω
2.5V
SLAVE2
CMGATE
0.1µF
0.1µF
SENSE
10Ω
VCC
MGATE RAMP SGATE1 SGATE2
D1
R TA =
VTRACK
VFB(REF )
RFB
+
VFB(REF )
RFA
V
∆V
− TRACK +
R TB
R TB
(6)
Note that large ratios of slave ramp rate to master ramp
rate, SS/SM, may result in negative values for RTA. In such
cases increase the offset or delay, or reduce the slave ramp
rate to realize positive values of RTA.
D2
S1
RAMPBUF
S2
RFB1
15.0k
RTB1
15.0k
TRACK1
RTB2
15.0k
FB1
RTA1
9.53k
RFA1
9.53k
LTC2926
TRACK2
RTA2
5.76k
FB2
VIN
VIN
10k
FAULT
ON/OFF
RFB2
15.0k
RFA2
5.76k
10k
FAULT
ON
STATUS/PGI
GND
PGTMR
RSGATE
STATUS
NC
2926 F14
CPGTMR
1µF
Figure 14. Coincident Tracking Example
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have 1% tolerance. The 3-step design procedure detailed
above can be used to determine component values. Only
the slave 1 supply is considered here, as the procedure
is the same for the slave 2 supply.
1. Set the ramp rate of the master signal.
From Equation 1:
CMGATE =
10µA
= 0.1µF
100 V s
2. Choose the feedback resistors based on the slave supply
voltage and slave load.
RL = 150Ω
From Equation 2:
RFB ≥ 100 • 150Ω = 15kΩ
Choose RFB = 15.0kΩ.
From Equation 3:
⎛ 0.99 ⎞
RFA < 15.0kΩ • ⎜
⎝ 1.01 ⎟⎠
⎛ 1.98 V
⎞
⎜⎝ 0.784V − 1⎠⎟ = 9.64kΩ
Choose RFA = 9.53kΩ.
3. Solve for the tracking resistors that set the desired ramp
rate and voltage offset or time delay of the slave supply.
From Equation 4:
⎛ 100 V s ⎞
R TB = 15.0kΩ • ⎜
= 15.0kΩ
⎝ 100 V s ⎟⎠
Since no offset or delay is required, Equation 5c applies:
ΔV = 0V
From Equation 6:
R TA =
0.8 V
= 9.53kΩ
0.8 V
0.8 V
0.8 V
0V
+
−
+
15.0kΩ 9.53kΩ 15.0kΩ 15.0kΩ
In this example, all supplies remain low while the ON pin
is held below 1.23V. When the ON pin rises above 1.23V,
10µA pulls up CMGATE and the gate of MOSFET Q0 at 100V/s.
The source of Q0 follows the gate and pulls up the output
to 3.3V at the rate of 100V/s. This output serves as the
master ramp and is buffered from the RAMP pin to the
RAMPBUF pin. As the master output and the RAMPBUF
pin rise, the current from the TRACK pins is reduced. Consequently, the voltage at the FB pins begins to fall below
0.8V, which causes the SGATE pins to rise. The sources
of the slave supply MOSFETs, Q1 and Q2, follow the rising
SGATE signals, and the slave supplies track the master
supply. When all the supplies have finished ramping, the
RSGATE pin voltage rises to close the integrated remote
sense switches, which allows the slave supply modules
to compensate for voltage drops in the series MOSFETs. If
the supplies have ramped within the power good timeout
period (about 123ms in this example), the STATUS/PGI
pin will rise, indicating completed ramping. When the
ON pin is again pulled below 1.23V, the STATUS/PGI pin
falls and the RSGATE pin falls, which opens the remote
sense switches. Next, 10µA will pull down CMGATE and the
gate of MOSFET Q0 at 100V/s. If the loads on the outputs
are sufficient, all outputs will track down coincidently at
100V/s.
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SLAVE2
SLAVE1
500mV/DIV
500mV/DIV
2926 F15
5ms/DIV
5ms/DIV
Figure 15. Ratiometric Tracking Waveforms from Figure 16 Circuit
Ratiometric Tracking Example
This example converts the coincident tracking example to
the ratiometric tracking profile shown in Figure 15, using
two slave supplies and a master ramp signal (not a master
ramp supply). The ramp rate of the master signal remains
unchanged (Step 1), the minimum load resistance of the
slave loads remains unchanged (Step 2), and there is no
delay in ratiometric tracking. Only Step 3 of the three-step
design procedure needs to be considered. In this example,
3.3V
1.8V
SLAVE1
IN OUT
RX1
100Ω
SENSE
10Ω
Q2
IRF7413Z
2.5V MODULE
3.3V
IN OUT
RX2
100Ω
SENSE
0.1µF
3.3V
VIN
2.5V
SLAVE2
CMGATE
0.1µF
ΔV = 0V
From Equation 6:
D2
S1
RAMPBUF
S2
R TA =
RFB1
15.0k
RTB1
24.9k
TRACK1
FB1
RTA1
7.68k
RFA1
9.53k
LTC2926
TRACK2
RTA2
5.36k
FB2
VIN
VIN
10k
FAULT
ON/OFF
Choose RTB = 24.9kΩ.
MGATE RAMP SGATE1 SGATE2
D1
RTB2
18.2k
⎛ 100 V s ⎞
R TB = 15.0kΩ • ⎜
= 25kΩ
⎝ 60 V s ⎟⎠
Since no offset or delay is required, Equation 5c applies:
10Ω
VCC
3. Solve for the tracking resistors that set the desired ramp
rate and voltage offset or time delay of the slave supply.
From Equation 4:
Q1
IRF7413Z
1.8V MODULE
the ramp rate of the 1.8V slave supply is 60V/s, and the
ramp rate of the 2.5V supply is 83.3V/s. Always verify that
the chosen ramp rate will allow the supplies to ramp-up
completely before RAMPBUF reaches VCC. If the 1.8V slave
supply were to ramp up at 50V/s it would only reach 1.65V
because the RAMPBUF signal would reach its final value
of VCC = 3.3V before the slave supply reached 1.8V.
RFB2
15.0k
RFA2
5.76k
0.8 V
0.8 V
0.8 V
0.8 V
0V
+
−
+
15.0kΩ 9.53kΩ 24.9kΩ 24.9kΩ
= 7.61kΩ
Choose RTA = 7.68kΩ.
10k
FAULT
ON
STATUS/PGI
GND
PGTMR
RSGATE
STATUS
NC
2926 F16
CPGTMR
1µF
Figure 16. Ratiometric Tracking Example
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MASTER
SLAVE2
SLAVE1
500mV/DIV
500mV/DIV
5ms/DIV
5ms/DIV
2926 F17
Figure 17. Offset Tracking Waveforms from Figure 18 Circuit
Offset Tracking Example
Converting the circuit in the coincident tracking example to
the offset tracking profile shown in Figure 17 is relatively
simple. Here the 1.8V slave supply ramps up 1V below the
master, and the 2.5V slave supply ramps up 0.5V below
the master. The ramp rate remains the same (100V/s), as
do the slave supplies’ minimum load resistances, so there
are no changes necessary to steps 1 or 2 of the three-step
Q0
IRF7413Z
3.3V VIN
1.8V MODULE
3.3V
1.8V
SLAVE1
IN OUT
RX1
100Ω
10Ω
SENSE
RX2
100Ω
2.5V
SLAVE2
CMGATE
0.1µF
0.1µF
SENSE
MGATE RAMP SGATE1 SGATE2
D2
S1
RAMPBUF
S2
RFB1
15.0k
RTB1
15.0k
TRACK1
FB1
RTA1
5.36k
RFA1
9.53k
LTC2926
TRACK2
RTA2
4.64k
FB2
VIN
10k
FAULT
VIN
0.8 V
0.8 V
0.8 V
0.8 V
1.0 V
+
−
+
15.0kΩ 9.53kΩ 15.0kΩ 15.0kΩ
= 5.31kΩ
Choose RTA = 5.36kΩ.
RFB2
15.0k
RFA2
5.76k
10k
FAULT
ON/OFF
ΔV = 1.0V
R TA =
D1
RTB2
15.0k
⎛ 100 V s ⎞
R TB = 15.0kΩ • ⎜
= 15kΩ
⎝ 100 V s ⎟⎠
From Equation 6:
10Ω
VCC
From Equation 4:
Since offset is required, Equation 5a applies:
Q2
IRF7413Z
IN OUT
3. Solve for the tracking resistors that set the desired ramp
rate and voltage offset or time delay of the slave supply.
Choose RTB = 15.0kΩ.
10Ω
2.5V MODULE
3.3V
3.3V
MASTER
Q1
IRF7413Z
design procedure. Only step 3 must be considered. Be
sure to verify that the chosen voltage offsets will allow
the slave supplies to ramp up completely. In this example,
if the voltage offset on the 1.8V supply were 2V, it could
ramp up only to 3.3V – 2V = 1.3V.
ON
STATUS/PGI
GND
PGTMR
RSGATE
STATUS
NC
2926 F18
CPGTMR
1µF
Figure 18. Offset Tracking Example
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SLAVE2
SLAVE1
500mV/DIV
500mV/DIV
5ms/DIV
5ms/DIV
2926 F19
Figure 19. Supply Sequencing Waveforms from Figure 20 Circuit
Supply Sequencing Example
In Figure 19, the two slave supplies are sequenced using a
master ramp signal. As in the ratiometric tracking example,
the master signal ramps up at 100V/s, and the minimum
slave loads are the same as the coincident example, so
steps 1 and 2 remain the same. The 1.8V slave 1 supply
ramps up at 1000V/s beginning 10ms after the master
signal starts to ramp up. The 2.5V slave 2 supply ramps
up at 1000V/s beginning 20ms after the master signal
Q1
IRF7413Z
1.8V MODULE
3.3V
1.8V
SLAVE1
IN OUT
RX1
100Ω
SENSE
3. Solve for the tracking resistors that set the desired ramp
rate and voltage offset or time delay of the slave supply.
From Equation 4:
⎛ 100 V s ⎞
R TB = 15.0kΩ • ⎜
= 1.5kΩ
⎝ 1000 V s ⎟⎠
10Ω
Choose RTB = 1.50kΩ.
Q2
IRF7413Z
2.5V MODULE
3.3V
starts to ramp up. Note that not every combination of
ramp rates and delays is possible. Small delays and large
ratios of slave ramp rate to master ramp rate may result
in solutions that require negative resistors. In such cases,
either the delay must be increased or the ratio of slave
ramp rate to master ramp rate must be reduced.
IN OUT
RX2
100Ω
SENSE
0.1µF
3.3V
VIN
2.5V
SLAVE2
CMGATE
0.1µF
ΔV = 100V/s • 10ms = 1V
10Ω
VCC
Since a delay is required, Equation 5b applies:
From Equation 6:
MGATE RAMP SGATE1 SGATE2
D1
D2
S1
RAMPBUF
S2
R TA =
RFB1
15.0k
RTB1
1.50k
TRACK1
RTB2
2.49k
FB1
RTA1
2.94k
RFA1
9.53k
LTC2926
TRACK2
RTA2
1.33k
FB2
VIN
VIN
10k
FAULT
ON/OFF
RFB2
24.9k
Choose RTA = 2.94kΩ.
RFA2
9.53k
Note that the values of RFA2 and RFB2 are larger than those
of the Coincident Tracking Example. Larger feedback resistor values resulted in larger tracking resistor values for
RTA2 and RTB2, which limits the maximum TRACK2 pin
current to <1mA; see Final Sanity Checks.
10k
FAULT
ON
STATUS/PGI
GND
PGTMR
RSGATE
2926 F20
CPGTMR
1µF
STATUS
NC
0.8 V
= 2.96kΩ
0.8 V
0.8 V
0.8 V
1V
+
−
+
15.0kΩ 9.53kΩ 1.50kΩ 1.50kΩ
Figure 20. Supply Sequencing Example
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Slave Control Without MOSFETs
The LTC2926 can control tracking and sequencing of a
slave supply without a MOSFET if the supply generator’s
output voltage is set by an accessible resistive voltage
divider and if its voltage reference is ground-based. Tracking currents mirrored to the FB pins are injected into the
feedback nodes of the supply generators to control the
output voltage. When master ramp signal has reached
it maximum voltage, the FB pin current is zero, and the
LTC2926 has no effect on the output voltage accuracy,
transient response or stability of the generator.
To control a supply generator (e.g., DC/DC converter) with
a feedback reference voltage VFB(GEN) of 0.75V or less,
connect the FB pin of the LTC2926 to the tap point of the
generator’s resistive divider, as shown in Figure 21a. Follow steps 1 and 3 of the Three-Step Design Procedure to
set the ramp rates and tracking profile. Use the feedback
resistor values required by the supply generator for RFA
and RFB in step 3.
A generator with VFB(GEN)>0.75V may be controlled without
a MOSFET if the slave voltage is large enough (see Figure
22). First follow steps 1 and 3 of the Three-Step Design
Procedure to set the ramp rates and tracking profile.
SUPPLY GENERATOR
IN
0.75V
and
VFB(GEN)
RFAB = RFA – RFAA
and tie the LTC2926’s FB pin to the node in between. The
new tap point allows the LTC2926’s FB pin to see <0.75V
at the end of ramp-up. Finally, scale the track resistors to
match RFAA:
R′TA =
RFAA
• R and
RFAA + RFAB TA
R′TB =
RFAA
•R
RFAA + RFAB TB
Voltage regulators that force their reference voltage between their output and feedback nodes do not employ a
ground-based reference, and thus will not be controllable
by the LTC2926 without a series MOSFET.
SUPPLY GENERATOR
OUT
SLAVE
VIN
IN
OUT
RFB
Slave Supply Control Without
a MOSFET
SLAVE
6
VFB(GEN)
VFB(GEN)
GND
FB
4
GND
RFA
LTC2926
FB
RFAB
LTC2926
RAMPBUF SGATE
RAMPBUF SGATE
NC
CONTROL VIA
FB PIN AND
SPLIT RFA
RESISTOR
5
–
+
RFB
–
+
RFAA ≤ RFA •
NC
RFAA
VSLAVE (V)
VIN
Use the feedback resistor values required by the supply
generator in step 3. Next, split resistor RFA as in Figure
21b, so that
CONTROL
VIA FB PIN
3
2
′
RTB
RTB
TRACK
FB
GND
TRACK
′
RTA
RTA
FB
MOSFET
CONTROL ONLY
1
GND
2926 F21
0
0
(a)
(b)
Figure 21. Slave Supply Control Without a MOSFET
(a) Generator Reference VFB(GEN) ≤ 0.75V and (b) Generator Reference VFB(GEN) > 0.75V
0.25
0.50 0.75 1.00
VFB(GEN) (V)
1.25
1.50
2926 F22
Figure 22. Regions of Possible
Slave Control Without a MOSFET
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Final Sanity Checks
Load Requirements
The collection of equations below is useful for identifying
unrealizable solutions.
A weak resistive load can cause static and dynamic tracking errors. The behavior of the source-follower topology
of MOSFET-controlled tracking relies on the load’s ability to support the ramp rates and tracking currents of a
particular application. Consider the simplified slave load
schematic in Figure 23.
As stated in step 3 of the design procedure, the slave
supply must finish ramping before the master signal has
reached its final voltage. This can be verified with the
following equation:
⎛ R ⎞
VMASTER > VTRACK • ⎜ 1+ TB ⎟
⎝ R ⎠
TA
Here, VTRACK = 0.8V. VMASTER is the final voltage of the
master signal, either the supply voltage ramped up through
the optional external MOSFET or VCC when no MOSFET
is present.
It is possible to choose resistor values that require the
LTC2926 to supply more current than the Electrical Characteristics table guarantees. To avoid this condition, check
that each TRACK pin’s current, ITRACKn, does not exceed
1mA, and that the RAMPBUF pin current, IRAMPBUF, does
not exceed ±3mA.
To confirm that ITRACKn ≤ 1mA, verify that:
VTRACK
≤ 1mA
R TA || R TB
Check that the RAMPBUF pin will not be forced to sink
more than 3mA when it is at 0V and will not be forced to
source more than 3mA when it is at VMASTER.
VTRACK
VTRACK
+
≤ 3mA and
R TA1 || R TB1 R TA 2 || R TB2
VMASTER
V
+ MASTER ≤ 3mA
R TA1 + R TB1 R TA 2 + R TB2
SUPPLY
MODULE
SLAVEn
Qn
OUT
LOAD
RFB
SGATEn
FBn
LTC2926
RL
CL
RFA
2926 F23
Figure 23. Simplified Slave Supply Load
When the supplies are ramped down quickly, the load must
be capable of sinking enough current to support the ramp
rate. For example, if there is a large output capacitance and
a weak resistive load on a particular supply, that supply’s
falling rate will be limited by the RC time constant of the
load. In Figure 24, the falling 2.5V slave cannot keep up
with the falling master ramp.
When the supplies are near ground, the load must be
capable of sinking the tracking current without creating
a large offset voltage. For weak resistive loads and slave
voltage levels near ground, the tracking current (at its
maximum there) can be in excess of the load’s current
demand. Having no capability for sinking current, the
MOSFET shuts off. All of the mirrored tracking current that
flows through RFB also flows through the load resistance,
RL, which creates a voltage offset between the slave and
ground. In Figure 24, the 1.8V supply shows an offset
from ground.
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Layout Considerations
MASTER
Be sure to place a 0.1µF bypass capacitor as near as possible to the supply pin of the LTC2926.
SLAVE2
SLAVE1
LARGE τL = RLCL
500mV/DIV
To minimize the noise on the slave supplies’ outputs, keep
the traces connecting the FB pins of the LTC2926 and the
feedback nodes of the slave supplies’ resistive voltage
dividers as short as possible. In addition, do not route
those traces next to signals with fast transitions times.
Figure 24. Tracking Effects of Weak Resistive Load
To get the best compensation of the series I • R drops
of the external MOSFETs, make sure the supply output
nodes and the supply generator sense connections use
Kelvin-sensing. The feedback resistive voltage divider
should Kelvin-sense the slave supply output node for
accuracy, as well.
RL ≈ RFB
5ms/DIV
2926 F24
Under worst-case conditions, FB pin voltages may reach
the maximum clamp voltage of 2.4V. To limit the slave
voltage offset to below 100mV, choose RFB ≥ 23 • RL.
Add a resistor in parallel with the load to strengthen weak
resistive loads as required.
Start-Up Delays
SUPPLY
MODULE
Q1
Often power supplies do not start up immediately when
their input supplies are applied. If the LTC2926 tries to ramp
up these power supplies as soon as the input supply is
present, the start-up of the outputs may be delayed, which
defeats the tracking circuit. Make sure the ON pin does not
initiate ramp-up until all supply sources are available.
OUT
100Ω
KELVIN-SENSE
CONNECTIONS
SENSE
GND
D1 SGATE1 S1
KELVIN-SENSE
CONNECTIONS
MINIMIZE
TRACE
LENGTH
LTC2926
FB1
VCC
RAMP Pin Clamp
GND
0.1µF
The RAMP pin is weakly clamped to the VCC pin. When
MGATE and RAMP are tied together their pin voltages will
not exceed VCC + 1V. If the RAMP pin is driven by a low
impedance source that can exceed VCC, include a series
resistor to limit the current to <20µA. Use 50kΩ per source
volt above VCC.
10Ω
RFB
MINIMIZE
TRACE LENGTH
SLAVE
LOAD
RFA
KELVIN-SENSE
CONNECTIONS
2926 F25
Figure 25. Layout Considerations
2926fa
25
LTC2926
U
PACKAGE DESCRIPTIO
GN Package
20-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
.045 ±.005
20 19 18 17 16 15 14 13 12
.254 MIN
.150 – .165
.0165 ± .0015
11
.229 – .244
(5.817 – 6.198)
.058
(1.473)
REF
.150 – .157**
(3.810 – 3.988)
.0250 BSC
1
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
× 45°
(0.38 ± 0.10)
.0075 – .0098
(0.19 – 0.25)
2 3
4
5 6
7
8
.0532 – .0688
(1.35 – 1.75)
9 10
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
.0250
(0.635)
BSC
GN20 (SSOP) 0204
2926fa
26
LTC2926
U
PACKAGE DESCRIPTIO
UFD Package
20-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1711)
0.70 ±0.05
4.50 ± 0.05
2.65 ± 0.05
3.10 ± 0.05 (2 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.65 ± 0.05
(2 SIDES)
4.10 ± 0.05
5.50 ± 0.05
2.65 ± 0.10
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ± 0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.30 TYP
R = 0.115
TYP
19 20
0.75 ± 0.05
0.40 ± 0.05
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ± 0.10
(2 SIDES)
3.65 ± 0.10
(2 SIDES)
(UFD20) QFN 0304
0.25 ± 0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2926fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2926
U
TYPICAL APPLICATIO
Chaining to Track/Sequence More Supplies
SUPPLY GENERATOR 4
Q4
SLAVE4
IN OUT
VIN
RX4
SENSE
10Ω
SUPPLY GENERATOR 3
Q3
VIN
SLAVE3
IN OUT
RX3
SENSE
10Ω
VCC
D1
D2
SGATE1
SGATE2
S1
0.1µF
S2
RFB3
ON
MGATE
RAMP
RAMPBUF
NC
FB1
LTC2926
RFA3
RFB4
RTB3
VCC
FB2
TRACK1
RSGATE
RTA3
RTB4
NC
RFA4
10k
10k
FAULT
TRACK2
GND PGTMR STATUS/PGI
RTA4
SUPPLY GENERATOR 2
Q2
VIN
SLAVE2
IN OUT
RX2
SENSE
10Ω
SUPPLY GENERATOR 1
Q1
VIN
SLAVE1
IN OUT
RX1
SENSE
10Ω
D1
D2
SGATE1
SGATE2
VCC
RONB
S1
0.1µF
S2
RFB1
ON
FB1
RONA
RFA1
MGATE
CMGATE
RAMP
RAMPBUF
RFB2
LTC2926
FB2
RFA2
RTB1
TRACK1
RSGATE
RTA1
RTB2
FAULT
TRACK2
RTA2
GND PGTMR STATUS/PGI
CPGTMR
NC
FAULT
STATUS
2926 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC2908
Precision Six Supply Monitor
Four Fixed (Various Levels) and Two Adjustable Input Thresholds
LTC2920-1/LTC2920-2
Single/Dual Power Supply Margining Controllers
Single or Dual, Symmetric/Asymmetric High and Low Margining
LTC2921/LTC2922
Power Supply Trackers with Input Monitors
Monitor up to Five Supplies, Includes Remote Sense Switches
LTC2923
Power Supply Tracking Controller
Controls Two Supplies Without FETs, MSOP-10 and DFN-12 Packages
LTC2925
Multiple Power Supply Tracking Controller with
Power Good Timeout
Controls Three Supplies Without FETs, Includes Three Shutdown Control
Pins
LTC2927
Single Power Supply Tracking Controller
Controls Single Supply Without FETs, Daisy-Chain for Multiple Supplies
2926fa
28 Linear Technology Corporation
LT 0506 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
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