Maxim MAX7470 Hdtv continuously variable anti-aliasing filter Datasheet

19-0548; Rev 0; 5/06
HDTV Continuously Variable
Anti-Aliasing Filters
Features
The MAX7469/MAX7470 triple-channel, anti-aliasing filters and buffers are ideal for high-definition (HD) and
standard-definition (SD) television (TV) applications.
Compatible with 1080i, 720p, 720i, 480p, and 480i
scanning system standards and computer format signals, the MAX7469/MAX7470 support component video
(Y Pb Pr, GsBR, and RGBHV), as well as composite
(CVBS) and S-video (Y/C).
Continuously Variable Anti-Aliasing Filter
5MHz to 34MHz in 256 Steps
The MAX7469/MAX7470 limit the input bandwidth for
anti-aliasing and out-of-band noise reduction prior to
digital conversion by an ADC or video decoder. The
MAX7469/MAX7470 frequency response can be continuously varied in 256 linear steps through an I2C* interface from below SD resolution to beyond HD resolution.
The output buffers of the MAX7469/MAX7470 drive a
2VP-P video signal into a standard 150Ω load. The inputs
are AC-coupled, and the outputs can be either DC- or
AC-coupled. The MAX7469 has a gain of 0dB, and the
MAX7470 has a gain of +6dB. Both devices are available
in a 20-pin TQFN package and are fully specified over
the 0°C to +85°C upper-commercial temperature range.
Accepts Any Input Sync Format
Sync on Y, Sync on G, External Sync (Positive
or Negative)
Sync on All Channels
Applications
Supports All Standard Video and Computer Input
Formats
480i, 480p, 720i, 720p, 1080i
QVGA, VGA, SVGA, XGA, SXGA, UXGA
Y Pb Pr, GsBR, RGBHV, Y/C, CVBS
Buffered Outputs Drive Standard 150Ω Video
Load
0dB (MAX7469)
+6dB (MAX7470)
DC- or AC-Coupled Outputs
Single +5V Analog and +3.3V Digital Supplies
5mW Power-Down Mode
20-Pin TQFN Lead-Free Package
HDTV (LCD, PDP, DLP, CRT)
Set-Top Boxes
Personal Video Recorders
Home Theaters
GND
A1
A0
AVDD
TOP VIEW
GND
Pin Configuration
15
14
13
12
11
*Purchase of I2C components from Maxim Integrated Products,
Inc., or one of its sublicensed Associate Companies, conveys a
license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the
I2C Standard Specification defined by Philips.
Ordering Information
IN1 16
10
OUT1
GND 17
9
AVDD
8
OUT2
7
AVDD
6
OUT3
PART
IN2 18
MAX7469
MAX7470
GND 19
1
2
3
4
5
EXTSYNC
SCL
SDA
DVDD
+
DGND
IN3 20
*EP
PIN-PACKAGE
BUFFER
GAIN (dB)
PKG
CODE
MAX7469UTP+
20 TQFN-EP*
0
T2055-4
MAX7470UTP+**
20 TQFN-EP*
+6
T2055-4
Note: All devices are specified over the 0°C to +85°C operating
temperature range.
+ Indicates lead-free packaging.
*EP = Exposed pad.
**Future product—contact factory for availability.
TQFN (5mm x 5mm)
*EXPOSED PAD.
SEE PIN DESCRIPTION FOR CONNECTION.
Typical Operating Circuit appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX7469/MAX7470
General Description
MAX7469/MAX7470
HDTV Continuously Variable
Anti-Aliasing Filters
ABSOLUTE MAXIMUM RATINGS
AVDD to GND............................................................-0.3V to +6V
DVDD to DGND.........................................................-0.3V to +4V
IN_, EXTSYNC to GND .................................................................
..................................-0.3V to the lower of (AVDD + 3V) and +6V
OUT_ to GND ...............................................................................
..................................-0.3V to the lower of (AVDD + 3V) and +6V
A_ to GND ....................................................................................
..................................-0.3V to the lower of (AVDD + 3V) and +6V
SCL, SDA to DGND ..................................................-0.3V to +6V
Continuous Power Dissipation (TA = +70°C)
20-Pin TQFN (derate 33.3mW/°C above +70°C) ...2666.7mW
Maximum Current into IN_, A_, GND,
SCL, SDA, and EXTSYNC............................................±50mA
Operating Temperature Range...............................0°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = +5V ±5%, DVDD = 2.7V to 3.6V, RLOAD = 150Ω to GND, CIN = 0.1µF, TA = 0°C to +85°C, unless otherwise noted. Typical
values are at AVDD = 5V, DVDD = 3.3V, TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
HD: f = 100kHz to 30MHz, relative to
100kHz (Note 1)
Filter Passband Response
Filter Stopband Attenuation
Group Delay Deviation
Group Delay Matching
APB
ASB
ΔtG
tG(MATCH)
Bypass Frequency Response
MIN
TYP
MAX
-3
-0.6
+1
±0.1
±1.0
UNITS
dB
SD: f = 100kHz to 5.75MHz, relative to
100kHz (Note 2)
HD: f = 74MHz (Note 1)
45
57
SD: f = 27MHz (Note 2)
52
63
HD: 100kHz to 30MHz, relative to 100kHz
(Note 1)
20
SD: 100kHz to 5.75MHz, relative to 100kHz
(Note 2)
15
HD: channel to channel, 100kHz to 2MHz,
(Note 1)
5
dB
ns
ns
SD: channel to channel, 100kHz to 500kHz,
(Note 2)
1.5
-3dB, bypass mode, independent of filter
setting
100
MHz
SD Differential Gain
dG
Five-step modulated staircase (Note 2)
0.25
%
SD Differential Phase
dφ
Five-step modulated staircase (Note 2)
0.25
Degrees
Signal-to-Noise Ratio
SNR
Output signal (2VP-P) to RMS noise (100kHz
to 30MHz), f = 30MHz
69
dB
SD Line-Time Distortion
HDIST
Deviations in a line with an 18µs, 100 IRE
bar; 1 line = 63.5µs (Note 2)
0.3
%
SD Field-Time Distortion
VDIST
Deviations in 130 lines with 18µs, 100 IRE
bars (Note 2)
0.3
%
2
________________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
(AVDD = +5V ±5%, DVDD = 2.7V to 3.6V, RLOAD = 150Ω to GND, CIN = 0.1µF, TA = 0°C to +85°C, unless otherwise noted. Typical
values are at AVDD = 5V, DVDD = 3.3V, TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
To 1% with 100 IRE step
(Note 4)
Clamp Settling Time
Minimum Functional Input Sync
Amplitude
MIN
TYP
Positive
350
Negative
650
MAX
H
125
Low-Frequency Gain (Note 1)
UNITS
mV
MAX7469
-0.5
0
+0.5
MAX7470
5.5
6
6.5
dB
Low-Frequency Gain Matching
100kHz
0.05
dB
Maximum Output Voltage
Amplitude
DC to 30MHz
2.4
VP-P
MAX7469
2.4
MAX7470
1.2
Maximum Input Voltage
Amplitude
Channel-to-Channel Isolation
VP-P
62
Output Clamping Level Variation
(Notes 1, 4)
Power-Supply Rejection Ratio
PSRR
dB
±100
DC
50
mV
dB
DIGITAL INPUTS (EXTSYNC, A1, A0)
Input Logic-High Voltage
VIH
Input Logic-Low Voltage
VIL
Input Leakage Current
IIN
Input Capacitance
CIN
2.0
VIN = 0 to DVDD
V
±1
0.8
V
±10
µA
6
pF
DIGITAL INPUTS (SDA, SCL)
Input Logic-High Voltage
VIH
Input Logic-Low Voltage
VIL
Input Hysteresis
0.7 x
DVDD
0.3 x
DVDD
0.05 x
DVDD
VHYST
Input Leakage Current
IIN
Input Capacitance
CIN
V
VIN = 0 to DVDD
V
V
±0.1
±10
6
µA
pF
DIGITAL OUTPUT (SDA)
Output Logic-Low Voltage
Tri-State Leakage Current
Tri-State Output Capacitance
VOL
IL
ISINK = 3mA
0.4
VIN = 0 to DVDD
±0.1
COUT
±10
6
V
µA
pF
POWER REQUIREMENTS
Analog Supply Voltage Range
AVDD
4.75
5
5.25
V
Digital Supply Voltage Range
DVDD
2.7
3.3
3.6
V
180
200
Power-down mode, no load
1
1.5
fSCL = 400kHz
25
Analog Supply Current
IAVDD
Digital Supply Current
IDVDD
Normal operation, no load
mA
µA
_______________________________________________________________________________________
3
MAX7469/MAX7470
ELECTRICAL CHARACTERISTICS (continued)
MAX7469/MAX7470
HDTV Continuously Variable
Anti-Aliasing Filters
TIMING CHARACTERISTICS
(AVDD = +5V ±5%, DVDD = 2.7V to 3.6V, RLOAD = 150Ω to GND, CIN = 0.1µF, TA = 0°C to +85°C, unless otherwise noted. Typical
values are at AVDD = 5V, DVDD = 3.3V, TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
Serial-Clock Frequency
fSCL
0
Bus Free Time Between STOP (P)
and START (S) Condition
tBUF
1.3
µs
Hold Time (Repeated) START (Sr)
Condition
tHD;STA
0.6
µs
After this period, the first clock pulse is
generated
SCL Pulse-Width Low
tLOW
1.3
µs
SCL Pulse-Width High
tHIGH
0.6
µs
Setup Time for a Repeated
START (Sr) Condition
tSU;STA
0.6
µs
Data Hold Time
tHD;DAT
Data Setup Time
(Note 5)
0.0
0.9
µs
tSU;DAT
100
Rise Time of Both SDA and SCL
Signals, Receiving
tr
0
300
ns
Fall Time of Both SDA and SCL
Signals, Receiving
tf
0
300
ns
Fall Time of SDA Signal,
Transmitting
tf
20 +
0.1Cb
250
ns
Setup Time for STOP (P)
Condition
tSU;STO
Capacitive Load for Each Bus
Line
Cb
Pulse Width of Spikes that Are
Suppressed by the Input Filter
tSP
(Note 6)
ns
0.6
(Note 7)
0
µs
400
pF
50
ns
Note 1: The filter passband edge is set to code 255.
Note 2: The filter passband edge is set to code 40.
Note 3: 1H is the total line period, depending on the video standard. For NTSC, this is 63.5µs; for HDTV, the line period is 29.64µs.
Note 4: The clamp level is at the sync tip for signals with sync pulses, and at the blanking level otherwise.
Note 5: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 6: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3VDD and 0.7VDD.
Note 7: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
4
________________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
tf
tLOW
tSU;DAT
tr
tf
tHD;STA
tSP
tr
tSP
SCL
tSU;STA
tHD;STA
tHD;DAT
tHIGH
tSU;STO
Sr
S
P
S
Figure 1. 2-Wire, Serial-Interface Timing Diagram
Typical Operating Characteristics
(AVDD = +5V, DVDD = 3.3V, RLOAD = 150Ω to GND, CLOAD = 0 to 20pF to GND, CIN = 0.1µF, TA = +25°C, unless otherwise noted.)
-30
CODE 255
CODE 90
-50
-0.5
CODE 40
-1.0
CODE 90
-1.5
-60
-2.0
-70
-2.5
1
10
100
FREQUENCY (MHz)
PASSBAND FLATNESS (MAX7470)
6.5
CODE 255
-60
10
100
MAX7469 toc03
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
GROUP DELAY
2T RESPONSE (1 IRE = 7.14mV)
SD
300mV/div
60
DELAY (ns)
CODE 90
5.0
CODE 90
MAX7469 toc06
70
CODE 40
5.5
1
80
6.0
CODE 255
-40
-50
90
MAX7469 toc04
7.0
-30
-70
0.1
1000
CODE 220
MAX7469 toc05
0.1
CODE 40
-20
CODE 220
-3.0
-80
RESPONSE (dB)
RESPONSE (dB)
CODE 220
-40
0
-10
0
CODE 40
-20
10
MAX7469 toc02
0.5
RESPONSE (dB)
RESPONSE (dB)
1.0
MAX7469 toc01
0
-10
FREQUENCY RESPONSE (MAX7470)
PASSBAND FLATNESS (MAX7469)
FREQUENCY RESPONSE (MAX7469)
10
4.5
50
40
HD
300mV/div
30
4.0
CODE 220
3.5
CODE 255
20
10
0
3.0
0.1
1
MAX7469/MAX7470
SDA
10
FREQUENCY (MHz)
100
0.1
1
10
100
200ns/div
FREQUENCY (MHz)
_______________________________________________________________________________________
5
Typical Operating Characteristics (continued)
(AVDD = +5V, DVDD = 3.3V, RLOAD = 150Ω to GND, CLOAD = 0 to 20pF to GND, CIN = 0.1µF, TA = +25°C, unless otherwise noted.)
MODULATED 12.5T RESPONSE
(1 IRE = 7.14mV)
-3dB FREQUENCY
vs. CONTROL CODE
400ns/div
0.1
0
-0.1
-0.2
1
2
3
4
5
6
7
DIFFERENTIAL PHASE
0.2
0.1
0
36
MAX7469 toc09
MAX7469 toc08
0.2
MEASURED -3dB FREQUENCY (MHz)
300mV/div
DIFFERENTIAL PHASE (deg)
300mV/div
DIFFERENTIAL GAIN (%)
DIFFERENTIAL GAIN
MAX7469 toc07
30
24
18
12
6
-0.1
-0.2
0
1
2
3
4
5
6
7
0
51
102
153
CODE
BYPASS-MODE FREQUENCY RESPONSE
MAX7470
0
16
MAX7469
DELAY (ns)
-5
-10
-15
-20
MAX7469 toc11
5
BYPASS-MODE GROUP DELAY
20
MAX7469 toc10
10
RESPONSE (dB)
MAX7469/MAX7470
HDTV Continuously Variable
Anti-Aliasing Filters
12
8
-25
-30
4
-35
-40
0
0.1
1
10
100
FREQUENCY (MHz)
6
1000
0.1
1
10
100
FREQUENCY (MHz)
________________________________________________________________________________________
204
255
HDTV Continuously Variable
Anti-Aliasing Filters
PIN
NAME
1
DGND
FUNCTION
2
EXTSYNC
3
SCL
I2C-Compatible Serial-Clock Input
4
SDA
I2C-Compatible Serial-Data Input/Output
5
DVDD
Digital Power Supply. Bypass to DGND with a 0.1µF capacitor. See the Power-Supply Bypassing and
Layout Considerations section.
6
OUT3
Video Output 3. OUT3 can be either DC- or AC-coupled.
7, 9, 11
AVDD
Analog Power Supply. Bypass to GND with a 0.1µF capacitor. See the Power-Supply Bypassing and
Layout Considerations section.
8
OUT2
Video Output 2. OUT2 can be either DC- or AC-coupled.
10
OUT1
12
A0
I2C Device Address Bit 0
13
A1
I2C Device Address Bit 1
14, 15, 17, 19
GND
16
IN1
Video Input 1. AC-couple IN1 with a series 0.1µF capacitor.
18
IN2
Video Input 2. AC-couple IN2 with a series 0.1µF capacitor.
20
IN3
Video Input 3. AC-couple IN3 with a series 0.1µF capacitor.
—
EP
Exposed Pad. Internally connected to GND. Do not route any PC board traces under package. Connect
EP to the ground plane. See the Power-Supply Bypassing and Layout Considerations section.
Digital Ground. See the Power-Supply Bypassing and Layout Considerations section.
External Sync Input. EXTSYNC has an internal 3MΩ resistor to ground. Connect to ground if not used.
Video Output 1. OUT1 can be either DC- or AC-coupled.
Ground. Connect all GND pins to the ground plane. See the Power-Supply Bypassing and Layout
Considerations section.
Detailed Description
The MAX7469/MAX7470 are complete video anti-aliasing solutions, ideal for fixed-pixel HDTV display technologies, such as plasma and LCD, which digitize the
input video signal and then scale the resolution to
match the native pixel format of the display. With a software-selectable corner frequency ranging from 5MHz
to 34MHz, the MAX7469/MAX7470 support both SD
and HD video signals, including 1080i, 720p, 720i,
480p, and 480i. Higher bandwidth computer resolution
signals are also supported.
Integrated lowpass filters limit the analog video input
bandwidth for anti-aliasing and out-of-band noise
reduction prior to sampling by an ADC or video
decoder. By allowing the corner frequency to be adjusted from below SD resolution to beyond HD resolutions
in 256 linear steps, the filter’s corner frequency can be
optimized dynamically for a specific input video signal
and the sampling frequency of the ADC or video
decoder. For applications requiring a passband greater
than the maximum frequency setting, a filter bypass
mode is also provided.
An I2C interface allows a microcontroller (µC) to configure the MAX7469/MAX7470s’ performance and functionality, including the clamp voltage, the filter corner
frequency, the sync source (internal/external), filter
bypassing, etc.
The Typical Operating Circuit shows the MAX7469/
MAX7470 block diagram and typical external connections.
Sync Detector and Clamp Settings
The MAX7469/MAX7470 use a video clamp circuit to
establish a DC offset for the incoming video signal after
the AC-coupling capacitor. This video clamp sets the DC
bias level of the circuit at the optimum operating point.
The MAX7469/MAX7470 support both internal and
external sync detection. Selection of internal vs. external
detection is achieved by programming the command
byte (see Table 3). After extracting the sync information
from channel 1 (or an external sync: SYNCA, SYNCB, or
SYNC), the MAX7469/MAX7470 clamp the video signal
during the sync tip portion of the video. Select one of
two possible clamp levels according to the input signal
format. Use the low level when the input signal contains
sync information, such as a Y (luma) or CVBS signal.
_______________________________________________________________________________________
7
MAX7469/MAX7470
Pin Description
MAX7469/MAX7470
HDTV Continuously Variable
Anti-Aliasing Filters
Table 1. Clamp Levels
INPUT SIGNAL
FORMAT
CLAMP LEVEL
CHANNEL 1 CHANNEL 2 CHANNEL 3
Y Pb Pr
Low
High
High
GSBR
Low
High
High
CVBS Y C
Low
Low
High
Y Pb Pr (sync on
all signals)
Low
Low
Low
RGBHV
High
High
High
Use the high level for bipolar signals, such as C (chroma) or Pb/Pr. See Table 1 for more details.
Component/Composite Selection
The MAX7469/MAX7470 accept component or composite inputs. When configured for composite video
inputs, the color-burst filter is enabled; if configured for
component video inputs, the color-burst filter is disabled. This filter is separate from the main filter and not
in the direct signal path so that it has no effect on the
overall frequency response. With normal video signals
and levels, the use of this color-burst filter has a negligible effect on the sync detection. It has a more significant effect under conditions of low-signal amplitude
coupled with higher relative amplitude color burst.
External Sync Detection (EXTSYNC)
When filtering a video signal without embedded sync
information, such as computer formats (RGBHV) with
separate sync signals, use the external sync mode (see
Table 3) and apply the horizontal sync source to the
EXTSYNC pin. The sync detector determines when the
clamp circuit is turned on.
The MAX7469/MAX7470 are able to detect positive or
negative polarity external syncs with TTL logic levels.
Use the I2C interface to program the polarity of the
external sync signal.
Filter
The internal video filter delivers an optimized response
with a steep transition band to achieve a wide passband along with excellent stopband rejection. In addition, the filter is optimized to provide an excellent time
domain response with low overshoot.
Setting the Filter Frequency
Use the I2C interface to vary the frequency response
(-3dB cutoff frequency) of the filter in the MAX7469/
MAX7470 from less than the SD passband to beyond the
HD passband in 256 linear steps. Write command byte
12h to access the frequency register, followed by an 8-bit
8
data word that corresponds to the desired frequency. See
the Frequency Register section for more details.
The frequency set by the MAX7469/MAX7470 is the
-3dB point. Set the frequency according to the desired
flat passband response.
Optimizing the Frequency Response
Select the frequency response according to the resolution
of the video-signal format. High-definition signals require
higher bandwidth, while standard-definition signals
require less bandwidth. The actual bandwidth contained
in the video signal is a function of the visual resolution of
the signal. This bandwidth is typically less than what is
indicated by the format resolution (1080i, 720p, etc.). For
more information, see Maxim Application Note 750:
Bandwidth Versus Video Resolution, which is available on
www.maxim-ic.com.
The frequency response can be optimized to improve
the overall performance. It is important, at a minimum, to
meet the Nyquist criterion. Beyond this, the frequency
response can be further optimized. In oversampled systems, the sample rate is significantly more than the
desired passband response. The extra frequency span
between the passband and the sample rate contains
noise and other undesirable interferers that can be eliminated by setting the corner frequency of the filter to just
pass the desired bandwidth. This results in a higher signal-to-noise ratio of the overall system.
Filter Bypass
The MAX7469/MAX7470 offer selectable filter bypassing that allows the input video signals to bypass the
internal filters and reach the output buffers unfiltered.
Write the appropriate command byte to enable (0Eh) or
disable (0Fh) filter-bypass mode as shown Table 3.
Output Buffer
Each output buffer can drive a 2VP-P signal into a 150Ω
video load. The MAX7469/MAX7470 can drive a DC- or
AC-coupled load. Output AC-coupling capacitors can
be eliminated when driving a cable, thereby eliminating
the normal adverse effects caused by these large
capacitors, such as line, and field-time distortion, also
known as droop. The output DC level is controlled to
limit the DC voltage on the cable so that the blanking
level of the video signal is always less than 1V, meeting
digital TV specification. See the Output Considerations
section for more information.
Gain Options
The MAX7469 features an overall gain of 0dB, while the
MAX7470 features an overall gain of +6dB. Use the
MAX7470 when driving a back-matched cable and the
________________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
Output Clamp Level
The MAX7469/MAX7470 output can be DC- or ACcoupled. The nominal output clamp level in the
DC-coupled case depends on the clamp voltage setting and can be determined according to Table 2.
Table 2. Output Clamp Level
CLAMP SETTING
OUTPUT CLAMP LEVEL (V)
Low
1.0 (typ)
High
1.6 (typ)
As shown in the Sync Detector and Clamp Settings
section, the low clamp level is used for signals with
sync information and determines the voltage level of the
sync tip, while the high clamp level is used for signals
without sync information and sets the blanking level.
The absolute voltage level of the output signal is relative to the output clamp level. A video signal containing
sync information (i.e., CVBS or Y) is unipolar above the
clamp level and conversely, a video signal without sync
(i.e., Pb Pr or C) is bipolar around the clamp level.
Power-Down Mode
The MAX7469/MAX7470 include a power-down mode
that reduces the supply current from 180mA (typ) to 1mA
(typ) by powering down the analog circuitry. The I2C
interface remains active, allowing the device to return to
full-power operation. The clamp settling time (see the
Electrical Characteristics section) limits the wake-up time
of the MAX7469/MAX7470. After exiting the power-down
mode, the MAX7469/MAX7470 resume normal operation
using the settings stored prior to power-down. The
power-down and wake-up modes are controlled through
the command byte (see Table 3). A software reset sets
the control/status register to its default conditions, but
the frequency register is not affected.
Power-On Reset (POR)
The MAX7469/MAX7470 include a POR circuit that
resets the internal registers and I2C interface to their
default conditions (see Tables 4, 5, and 6).
Serial Interface
The MAX7469/MAX7470 feature an I2C-compatible, 2-wire
serial interface consisting of a bidirectional serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facilitate
bidirectional communication between the MAX7469/
MAX7470 and the master at rates up to 400kHz.
The MAX7469/MAX7470 have a command interpreter
that is accessed by writing a valid command byte.
Once a command byte is written to the MAX7469/
MAX7470, the command interpreter updates the control/status register accordingly. See the Control/Status
Register section for more information. The command
interpreter also controls access to the frequency register through a command byte (see the Command Byte
(Write Cycle) section).
The MAX7469/MAX7470 are transmit/receive slave-only
devices, relying upon a master to generate a clock signal. The master (typically a µC) initiates data transfer on
the bus and generates SCL.
A master device communicates to the MAX7469/
MAX7470 by transmitting the proper address (see the
Slave Address section) followed by a command and/or
data words. Each transmit sequence is framed with a
START (S) or REPEATED START (Sr) condition and a
STOP (P) condition.
The SDA driver is an open-drain output, requiring a
pullup resistor (2.4kΩ or greater) to generate a logichigh voltage. Optional resistors (24Ω) in series with
SDA and SCL protect the device inputs from high-voltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot of the bus signals.
Bit Transfer
Each SCL rising edge transfers 1 data bit. Nine clock
cycles are required to transfer the data into or out of the
MAX7469/MAX7470. The data on SDA must remain stable
during the high period of the SCL clock pulse. Changes in
SDA while SCL is high are read as control signals (see the
START and STOP Conditions section). When the serial
interface is inactive, SDA and SCL idle high.
_______________________________________________________________________________________
9
MAX7469/MAX7470
MAX7469 when driving an ADC or video decoder with an
input range the same as the input to the MAX7469. For
added flexibility, the MAX7469 accepts input signals with
twice the standard video-signal range, which can be
used for driving an ADC or video decoder with an input
signal range that accepts a larger signal swing. The
MAX7470 can also be used to drive an ADC or video
decoder when a gain of two is desired.
MAX7469/MAX7470
HDTV Continuously Variable
Anti-Aliasing Filters
START and STOP Conditions
A master device initiates communication by issuing a
START condition, a high-to-low transition on SDA with SCL
high (Figure 2). The master terminates transmission by a
STOP condition (see the Acknowledge Bit (ACK) and NotAcknowledge Bit (NACK) section). A STOP condition is a
low-to-high transition on SDA while SCL is high (Figure 2).
The STOP condition frees the bus. If a repeated START
condition is generated instead of a STOP condition, the
bus remains active. When a STOP condition or incorrect
address
is
detected,
the
MAX7469/
MAX7470 then ignore all communication on the I2C bus
until the next START or REPEATED START condition,
minimizing digital noise and feedthrough.
condition occurs in the same high pulse as a START
condition (Figure 3). This condition is not a legal I2C format; at least one clock pulse must separate any START
and STOP conditions. The MAX7469/MAX7470 discard
any data received during a data transfer aborted by an
early STOP condition.
Repeated START (Sr) Conditions
An Sr condition is used to indicate a change in direction of data flow (see the Read Cycle section). Sr can
also be used when the bus master is writing to several
I2C devices and does not want to relinquish control of
the bus. The MAX7469/MAX7470 serial interface supports continuous write operations with (or without) an Sr
condition separating them.
Early STOP Conditions
The MAX7469/MAX7470 recognize a STOP condition at
any point during transmission except when a STOP
S
Sr
P
SCL
SDA
Figure 2. START/STOP Conditions
LEGAL STOP CONDITION
ILLEGAL STOP CONDITION
SCL
SCL
SDA
SDA
STOP
START
START
ILLEGAL STOP
Figure 3. Early STOP Conditions
10
_______________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
Slave Address
A bus master initiates communication with a slave device
by issuing a START condition, followed by the 7-bit slave
address (Figure 5). When idle, the MAX7469/MAX7470
wait for a START condition, followed by their slave
address. The serial interface compares each address bit
by bit, allowing the interface to power down and disconnect from SCL immediately if an incorrect address is
detected. After recognizing a START condition followed
by the correct address, the MAX7469/MAX7470 are
ready to accept or send data. The least significant bit
(LSB) of the address byte (R/W) determines whether the
master is writing to or reading from the
MAX7469/MAX7470 (R/W = 0 selects a write condition,
R/W = 1 selects a read condition). After receiving the
proper address, the MAX7469/MAX7470 (slave) issue an
ACK by pulling SDA low for one clock cycle.
The MAX7469/MAX7470 slave address consists of 5
fixed bits, A6–A2 (set to 10010), followed by 2 pin-programmable bits, A1 and A0. The most significant
address bit (A6) is transmitted first, followed by the
remaining bits. Addresses A1 and A0 can also be driven
dynamically if required, but the values must be stable
when they are expected in the address sequence.
S
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
SCL
9
8
1
Figure 4. Acknowledge and Not-Acknowledge Bits
.
SDA
1
0
MSB
0
1
0
A1
A0
R/W
ACK
LSB
SCL
Figure 5. Slave-Address Byte Definition
______________________________________________________________________________________
11
MAX7469/MAX7470
Acknowledge Bit (ACK) and Not-Acknowledge Bit
(NACK)
Successful data transfers are acknowledged with an
acknowledge bit (ACK) or a not-acknowledge bit
(NACK). Both the master and the MAX7469/MAX7470
(slave) generate acknowledge bits. To generate an
acknowledge, the receiving device must pull SDA low
before the rising edge of the acknowledge-related clock
pulse (ninth pulse) and keep it low during the high period
of the clock pulse (Figure 4). To generate a NACK, the
receiver allows SDA to be pulled high before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and leaves it high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or
if a system fault has occurred. In the event of an unsuccessful data transfer, the master should reattempt communication at a later time.
The MAX7469/MAX7470 generate an acknowledge bit
when receiving an address or data by pulling SDA low
during the ninth clock pulse. When transmitting data
during a read, the MAX7469/MAX7470 do not drive
SDA during the ninth clock pulse (i.e., the external
pullups define the bus as a logic-high) so that the
receiver of the data can pull SDA low to acknowledge
receipt of data.
MAX7469/MAX7470
HDTV Continuously Variable
Anti-Aliasing Filters
Command Byte (Write Cycle)
A write cycle begins with the bus master issuing a
START condition followed by 7 address bits (Figure 5)
and 1 write bit (R/W = 0). After successfully receiving its
address, the MAX7469/MAX7470 (slave) issue an ACK.
The slave recognizes the next byte after a successfully
received address as the command byte (Table 3).
Use the command byte to configure the MAX7469/
MAX7470. While most of the commands listed in Table
3 modify the functionality of the MAX7469/MAX7470,
some commands prepare the device for further data
transfers (see the Control/Status Register and
Frequency Register sections). If the write cycle is prematurely aborted, the register is not updated, and the
Table 3. Command Byte Definition
COMMAND BYTE:
INDIVIDUAL BIT DEFINITIONS
DESCRIPTION
C7
C6
C5
C4
C3
C2
C1
C0
0
0
0
0
0
0
0
0
Enters power-down mode.
0
0
0
0
0
0
0
1
Wake-up; resumes normal operation using the frequency/status previously stored
(unless power has been cycled).
0
0
0
0
0
0
1
0
Sets IN1 clamp voltage level to low.
0
0
0
0
0
0
1
1
Sets IN1 clamp voltage level to high.
0
0
0
0
0
1
0
0
Sets IN2 clamp voltage level to low.
0
0
0
0
0
1
0
1
Sets IN2 clamp voltage level to high.
0
0
0
0
0
1
1
0
Sets IN3 clamp voltage level to low.
0
0
0
0
0
1
1
1
Sets IN3 clamp voltage level to high.
0
0
0
0
1
0
0
0
Selects component input, color-burst filter disabled.
0
0
0
0
1
0
0
1
Selects composite input, color-burst filter enabled.
0
0
0
0
1
0
1
0
Selects internal sync.
0
0
0
0
1
0
1
1
Selects external sync.
0
0
0
0
1
1
0
0
Selects positive polarity external sync.
0
0
0
0
1
1
0
1
Selects negative polarity external sync.
0
0
0
0
1
1
1
0
Enables filters.
0
0
0
0
1
1
1
1
Disables filters, enters bypass mode.
0
0
0
1
0
0
0
0
Resets the control/status register to the default values as described in the Control/
Status Register section. This command does not affect the frequency register.
0
0
0
1
0
0
0
1
Requests a control/status register read. The interface expects an Sr condition to
follow with address and read/write set to read so data can be driven onto the bus.
0
0
0
1
0
0
1
0
Loads the frequency register with the data byte following the command byte.
0
0
0
1
0
0
1
1
Requests a frequency register read. The interface expects an Sr condition to follow
with address and read/write set to read so data can be driven onto the bus.
12
_______________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
Read Cycle
In read mode (R/W = 1), the MAX7469/MAX7470 write
the contents of the control/status or frequency registers
to the bus. When the command byte indicates a read
operation of either the control/status or the frequency
register, the serial interface expects an Sr condition to
SCL
SDA
1
0
0
SDA
DIRECTION
1
0
A1
A0
R/W
IN TO MAX7469/MAX7470
ACK
0
0
0
1
0
0
1
0
C7
C6
C5
C4
C3
C2
C1
C0
OUT
ACK
IN
OUT
START
SCL (CONT)
F7
SDA (CONT)
F6
F5
F4
SDA
DIRECTION
F3
F2
F1
F0
ACK
IN
OUT
IN
COMMAND BYTE C7–C0 IS 0010010.
STOP
Figure 6. Write Sequence to Update the Frequency Register
SCL
SDA
1
SDA
DIRECTION
0
0
1
0
A1
IN TO MAX7469/MAX7470
START
THE COMMAND BYTE IS FOR POWER-DOWN.
A0
R/W
ACK
OUT
0
0
0
0
0
0
0
0
C7
C6
C5
C4
C3
C2
C1
C0
IN
ACK
OUT
IN
STOP
Figure 7. Write Sequence for a Command Byte
______________________________________________________________________________________
13
MAX7469/MAX7470
follow the command byte. After sending an Sr, the master sends the MAX7469/MAX7470 slave address byte
followed by a R/W bit (set to 1 to indicate a read). The
slave device (MAX7469/MAX7470) generates an ACK
for the second address word and immediately after the
ACK clock pulse, the direction of data flow reverses.
The slave (MAX7469/MAX7470) then transmits 1 byte of
data containing the value of the register that was
write sequence must be repeated. Figures 6 and 7
show examples of write sequences.
MAX7469/MAX7470
HDTV Continuously Variable
Anti-Aliasing Filters
SCL
SDA
1
0
SDA
DIRECTION
0
1
0
A1
A0
ACK
R/W
IN TO MAX7469/MAX7470
ACK
0
0
0
1
0
0
1/0
1
C7
C6
C5
C4
C3
C2
C1
C0
OUT
IN
OUT
START
SCL (CONT)
1
SDA (CONT)
0
0
1
SDA
DIRECTION
0
A1
A0
R/W
ACK
D7
D6
IN
D5
D4
D3
D2
D1
D0
ACK
OUT
IN
Sr
STOP
Figure 8. Basic Read Sequence
selected in the command byte. Figure 8 shows a basic
read sequence.
Note: The master has to write a command byte,
requesting to read the control/status or frequency register, to the slave (MAX7469/MAX7470) before the master can read the contents of the selected register.
Table 5. Control/Status Register Bit
Description
BIT
Control/Status Register
The MAX7469/MAX7470 store their status in an 8-bit
register that can be read back by the master. The individual bits of the control/status register are summarized
in Tables 4 and 5. The power-on default value of this
register is 03h.
Frequency Register
The frequency response (-3dB passband edge) of the
MAX7469/MAX7470 can be continuously varied in 256
linear steps by changing the codes in the frequency register (Table 6). See the Command Byte (Write Cycle) section for a write sequence to update the frequency register.
Table 4. Control/Status Register
CONTROL/STATUS REGISTER
S7
S6
S5
S4
S3
S2
S1
S0
DESCRIPTION
S7
0 = component input signal selected (default).
1 = composite input signal selected.
S6
0 = internal sync enabled (default).
1 = external sync enabled.
S5
0 = external sync: positive polarity (default).
1 = external sync: negative polarity.
S4
0 = normal operation mode (default).
1 = power-down mode.
S3
0 = filters enabled (default).
1 = bypass mode—no filtering.
S2
0 = clamp voltage for IN1 set to low (default).
1 = clamp voltage for IN1 set to high.
S1
0 = clamp voltage for IN2 set to low.
1 = clamp voltage for IN2 set to high (default).
S0
0 = clamp voltage for IN3 set to low.
1 = clamp voltage for IN3 set to high (default).
Table 6. Frequency Register Setting for Different Video-Signal Formats
F7
F6
F5
F4
F3
F2
F1
F0
CODE NO.
APPROXIMATE FREQUENCY
(-3dB) MHz
Standard Definition (Interlaced)
0
0
1
0
1
0
0
0
40
10
Standard Definition (Progressive)
0
1
0
1
1
0
1
0
90
15
VIDEO-SIGNAL FORMAT
High-Definition Low Bandwidth
1
1
0
1
1
1
0
0
220
30
High-Definition High Bandwidth
1
1
1
1
1
1
1
1
255
34 (default)
14
_______________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
Applications Information
Input Considerations
Use 0.1µF ceramic capacitors to AC-couple the inputs.
The inputs cannot be DC-coupled. The internal clamp
circuit stores a DC voltage across the input capacitors
to obtain the appropriate output DC voltage level.
Increasing the value of these capacitors to improve linetime distortion is not necessary due to the extremely low
input leakage current yielding a very low line-time distortion performance.
The MAX7469/MAX7470 provide a high input impedance to allow a nonzero source impedance to be used,
such as when the input is connected directly to a backmatched video cable, ensuring the external resistance
determines the termination impedance.
Output Considerations
The MAX7469/MAX7470 outputs can be DC- or ACcoupled. The MAX7470, with its +6dB gain, is typically
connected to a 75Ω series back-match resistor followed by the video cable. Because of the inherent
divide-by-two of this configuration, the blanking level of
the video signal is always less than 1V, which complies
with digital TV requirements.
The MAX7469, with its 0dB gain, is typically connected
to an ADC or video decoder. This can be a DC or AC
connection. If a DC connection is used, ensure that the
DC input requirements of the ADC or video decoder
are compatible.
If an AC connection is used, choose an AC-coupling
capacitor value that ensures that the lowest frequency
content in the video signal is passed and the line-time
distortion is kept within desired limits. The selection of
this value is a function of the input impedance and,
more importantly, the input leakage of the circuit being
driven. Use a video clamp to reestablish the DC level, if
not already included in the subsequent circuit.
The outputs of the MAX7469/MAX7470 are fully protected
against a short-circuit condition either to ground or the
positive supply of the device.
Power-Supply Bypassing and Layout
Considerations
The MAX7469/MAX7470 operate from a single +5V analog supply and a +3.3V digital supply. Bypass AVDD to
GND with a 0.1µF capacitor and an additional 1µF
capacitor in parallel for additional low-frequency decoupling. Determine the proper power-supply bypassing
necessary by taking into account the desired disturbance level tolerable on the output, the power-supply
rejection of the MAX7469/MAX7470, and the amplitude
and frequency of the disturbance signals present in the
vicinity of the MAX7469/MAX7470. Use an extensive
ground plane to ensure optimum performance. The three
AVDD pins (pins 7, 9, and 11) that supply the individual
channels can be connected together and bypassed as
one, provided the components are close to the pins.
Bypass DV DD to DGND with a 0.1µF capacitor. All
ground pins (GND) must be connected to a low impedance ground plane as close as possible to the device.
Place the input termination resistors as close as possible to the device. Alternatively, the terminations can be
placed further from the device if the PC board traces
are designed to be a controlled impedance of 75Ω.
Minimize parasitic capacitance as much as possible to
avoid performance degradation in the upper frequency
range possible with the MAX7469/MAX7470.
Refer to the MAX7469/MAX7470 evaluation kit for a
proven PC board layout.
Exposed Pad and Heat Dissipation
The MAX7469/MAX7470 TQFN package has an
exposed pad on its bottom. This pad is electrically connected, internal to the device, to GND. Do not route any
PC board traces under the package.
The MAX7469/MAX7470 typically dissipate 900mW of
power, therefore, pay careful attention to heat dispersion. The use of at least a two-layer board with a good
ground plane is recommended. To maximize heat dispersion, place copper directly under the MAX7469/
MAX7470 package so that it matches the outline of the
plastic encapsulated area. Do the same thing on the
bottom ground plane layer and then place as many
vias as possible connecting the top and bottom layers
to thermally connect it to the ground plane.
Maxim has evaluated a four-layer board using FR-4
material and 1oz copper with equal areas of metal on
the top and bottom side coincident with the plastic
encapsulated area of the 20-pin TQFN package. The
two middle layers are used as power and ground
______________________________________________________________________________________
15
MAX7469/MAX7470
I2C Compatibility
The MAX7469/MAX7470 are compatible with existing
I2C systems supporting standard I2C 8-bit communications. The general call address is ignored, and CBUS
formats are not supported. The device’s address is
compatible with 7-bit I2C addressing protocol only; 10bit address formats are not supported.
MAX7469/MAX7470
HDTV Continuously Variable
Anti-Aliasing Filters
planes. The board has 21, 15-mil, plated-through via
holes between the top, bottom, and ground plane layers. Thermocouple measurements confirm device temperatures to be safely within maximum limits.
Chip Information
PROCESS: BiCMOS
Typical Operating Circuit
AVDD
EXT SYNC
MAX7469
MAX7470
SYNC DETECTOR
Y/G
IN1
DECODER
0dB
(+6dB)
OUT1
A/D
5MHz TO 34MHz
PROGRAMMABLE PASSBAND
LOWPASS FILTER
CLAMP/
BIAS
0.1μF
0.1μF
75Ω
Pb/B
IN2
0.1μF
0dB
(+6dB)
CLAMP/
BIAS
OUT2
A/D
5MHz TO 34MHz
PROGRAMMABLE PASSBAND
LOWPASS FILTER
0.1μF
75Ω
Pr/R
IN3
0.1μF
0dB
(+6dB)
CLAMP/
BIAS
OUT3
A/D
5MHz TO 34MHz
PROGRAMMABLE PASSBAND
LOWPASS FILTER
0.1μF
75Ω
FREQUENCY
SELECT
BYPASS
CLAMP LEVEL
I2C
INTERFACE
EXT SYNC
ENABLE
( ) FOR MAX7470
GND
SCL SDA
DVDD
A1
A0
DGND
16
_______________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
QFN THIN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2006 Maxim Integrated Products
Heslington
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX7469/MAX7470
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
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