Revised August 1999 74F544 Octal Registered Transceiver General Description Features The 74F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. The A outputs are guaranteed to sink 24 mA while the B outputs are rated for 64 mA. The 74F544 inverts data in both directions. ■ 8-bit octal transceiver ■ Back-to-back registers for storage ■ Separate controls for data flow in each direction ■ A outputs sink 24 mA, B outputs sink 64 mA Ordering Code: Order Number 74F544SC Package Number M24B Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F544MSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74F544SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009555 www.fairchildsemi.com 74F544 Octal Registered Transceiver April 1988 74F544 Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL Description HIGH/LOW Output IOH/IOL OEAB A-to-B Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA OEBA B-to-A Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA CEAB A-to-B Enable Input (Active LOW) 1.0/2.0 20 µA/−1.2 mA CEBA B-to-A Enable Input (Active LOW) 1.0/2.0 20 µA/−1.2 mA LEAB A-to-B Latch Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA LEBA B-to-A Latch Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA A0–A7 A-to-B Data Inputs or B-to-A 3-STATE Outputs B0–B7 70 µA/−650 µA −3 mA/24 mA (20 mA) 3.5/1.083 70 µA/−650 µA 600/106.6(80) −12 mA/64 mA (48 mA) B-to-A Data Inputs or A-to-B 3-STATE Outputs 3.5/1.083 150/40(33.3) Data I/O Control Table Functional Description The 74F544 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A0–A7 or take data from B0–B7, as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA inputs. Inputs CEAB LEAB OEAB Latch Status Output Buffers H X X Latched High Z X H X Latched — L L X Transparent — X X H — High Z L X L — Driving H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note: A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH 10% VCC 2.5 Voltage 10% VCC 2.4 10% VCC 2.0 5% VCC 2.7 5% VCC 2.7 VOL IIH IBVI Typ Recognized as a LOW Signal −1.2 V Voltage 10% VCC 0.55 Input HIGH Current Input HIGH Current Output HIGH VIN = 2.7V (except An, Bn) 7.0 µA Max VIN = 7.0V (except An, Bn) 0.5 mA Max VIN = 5.5V (An, Bn) 250 µA Max VOUT = VCC (An, Bn) V 0.0 µA 0.0 mA Max 70 µA Max VOUT = 2.7V (An, Bn) −650 µA Max VOUT = 0.5V (An, Bn) mA Max 500 µA 0.0V VOUT = 5.25V (An, Bn) 4.75 Output Leakage 3.75 −0.6 Input LOW Current −1.2 Output Short-Circuit Current IOL = 24 mA (An) Max 5.0 Output Leakage Current IOH = −15 mA (Bn) µA Current IOS Min Min 20.0 IIL + IOZL (except An, Bn) V Input HIGH Output Leakage Current IIN = −18 mA, IOH = −3 mA (An, Bn) 0.5 IIH + IOZH Min IOH = −1 mA (An) Circuit Current IIL V 10% VCC Test IOD 0.8 Output LOW Input Leakage Conditions Recognized as a HIGH Signal IOH = −3 mA (An, Bn) Leakage Current VID VCC V V Breakdown (I/O) ICEX Units IOH = −1 mA (An) Breakdown Test IBVIT Max 2.0 −60 −150 −100 −225 IOL = 64 mA (Bn) IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (OEAB, OEBA) VIN = 0.5V (CEAB, CEBA) VOUT = 0V (An) VOUT = 0V (Bn) IZZ Bus Drainage Test ICCH Power Supply Current 70 105 mA Max VO = HIGH ICCL Power Supply Current 85 130 mA Max VO = LOW ICCZ Power Supply Current 83 125 mA Max VO = HIGH Z 3 www.fairchildsemi.com 74F544 Absolute Maximum Ratings(Note 1) 74F544 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max Min Max Min Max tPLH Propagation Delay 3.0 7.0 9.5 3.0 12.0 3.0 10.5 tPHL Transparent Mode 3.0 5.0 6.5 2.5 8.5 3.0 7.5 Units ns An to Bn or Bnto An tPLH Propagation Delay 6.0 10.0 13.0 6.0 18.0 6.0 14.5 tPHL LEBA to An 4.0 7.0 9.5 4.0 11.5 4.0 10.5 tPLH Propagation Delay 6.0 10.0 13.0 6.0 18.0 6.0 14.5 tPHL LEAB to Bn 4.0 7.0 9.5 4.0 11.5 4.0 10.5 tPZH Output Enable Time 3.0 7.0 9.0 3.0 11.0 3.0 10.0 tPZL OEBA or OEAB to An or Bn 4.0 7.5 10.5 4.0 13.0 4.0 12.0 tPHZ Output Disable Time 1.0 6.0 8.0 2.0 10.0 1.0 9.0 tPLZ OEBA or OEAB to An or Bn 2.5 5.5 10.5 2.0 9.5 2.5 11.5 CEBA or CEAB to An or Bn ns ns ns CEBA or CEAB to An or Bn AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C VCC = +5.0V VCC = +5.0V Min Max Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 3.0 3.0 3.0 tS(L) An or Bn to LEBA or LEAB 3.0 3.0 3.0 tH(H) Hold Time, HIGH or LOW 3.0 3.0 3.0 tH(L) An or Bn to LEBA or LEAB 3.0 3.0 3.0 tW(L) Latch Enable, B to A 6.0 9.0 7.5 Pulse Width, LOW www.fairchildsemi.com 4 Units Max ns ns 74F544 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA24 5 www.fairchildsemi.com 74F544 Octal Registered Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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