BB504M Built in Biasing Circuit MOS FET IC VHF&UHF RF Amplifier REJ03G0837-0700 (Previous ADE-208-982E) Rev.7.00 Aug.10.2005 Features • • • • Built in Biasing Circuit; To reduce using parts cost & PC board space. Low noise; NF = 1.0 dB typ. at f = 200 MHz, NF = 1.75 dB typ. at f =900 MHz High gain; PG = 30 dB typ. at f = 200 MHz, PG = 22 dB typ. at f = 900 MHz Withstanding to ESD; Built in ESD absorbing diode. Withstand up to 200 V at C = 200 pF, Rs = 0 conditions. • Provide mini mold packages; MPAK-4 (SOT-143Rmod) Outline RENESAS Package code: PLSP0004ZA-A (Package name: MPAK-4) 2 3 1 4 Notes: 1. Marking is “DS–”. 2. BB504M is individual type number of RENESAS BBFET. Rev.7.00 Aug 10, 2005 page 1 of 9 1. Source 2. Gate1 3. Gate2 4. Drain BB504M Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate1 to source voltage Symbol VDS VG1S Ratings 6 Unit V +6 –0 V Gate2 to source voltage VG2S V Drain current Channel power dissipation Channel temperature Storage temperature ID Pch Tch Tstg +6 –0 30 150 150 –55 to +150 mA mW °C °C Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current Gate1 to source cutoff voltage Symbol V(BR)DSS V(BR)G1SS V(BR)G2SS IG1SS IG2SS VG1S(off) Min 6 +6 +6 — — 0.6 Typ — — — — — 0.85 Max — — — +100 +100 1.1 Unit V V V nA nA V VG2S(off) 0.6 0.85 1.1 V Drain current ID(op) 13 16 19 mA VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 120 kΩ Forward transfer admittance |yfs| 24 29 34 mS Input capacitance Output capacitance Reverse transfer capacitance Power gain (1) Noise figure (1) ciss coss crss PG NF 1.7 1.0 — 25 — 2.1 1.4 0.027 30 1.0 2.5 1.8 0.05 — 1.8 pF pF pF dB dB VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 120 kΩ, f = 1 kHz VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 120 kΩ f = 1 MHz Power gain (2) Noise figure (2) PG NF 17 — 22 1.75 — 2.3 dB dB Gate2 to source cutoff voltage Rev.7.00 Aug 10, 2005 page 2 of 9 Test conditions ID = 200 µA, VG1S = VG2S = 0 IG1 = +10 µA, VG2S = VDS = 0 IG2 = +10 µA, VG1S = VDS = 0 VG1S = +5 V, VG2S = VDS = 0 VG2S = +5 V, VG1S = VDS = 0 VDS = 5 V, VG2S = 4 V ID = 100 µA VDS = 5 V, VG1S = 5 V ID = 100 µA VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 120 kΩ f = 200 MHz VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 120 kΩ f = 900 MHz BB504M Test Circuits • DC Biasing Circuit for Operating Characteristics Items (ID(op), |yfs|, Ciss, Coss, Crss, NF, PG) VG2 VG1 RG Gate 2 Gate 1 Drain Source A ID • 200 MHz Power Gain, Noise Figure Test Circuit 1000p 1000p 47k VT VG2 VT 1000p 47k 1000p 47k BBFET Output(50Ω) 1000p L2 Input(50Ω) L1 10p max 1000p 1000p 36p 1SV70 RG RFC 120k 1SV70 1000p VD = VG1 L1 : Φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns L2 : Φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns RFC : Φ1mm Enameled Copper Wire,Inside dia 5mm, 2Turns Rev.7.00 Aug 10, 2005 page 3 of 9 Unit Resistance (Ω) Capacitance (F) BB504M • 900 MHz Power Gain, Noise Figure Test Circuit VD VG1 VG2 C6 C4 C5 R1 R2 C3 R3 RFC D G2 Output L3 L4 G1 Input S L1 L2 C1 C1, C2 C3 C4 to C6 R1 R2 R3 C2 : : : : : : Variable Capacitor (10pF MAX) Disk Capacitor (1000pF) Air Capacitor (1000pF) 120 kΩ 47 kΩ 4.7 kΩ L2: L1: 10 3 3 8 10 26 (Φ1mm Copper wire) Unit:mm 21 L4: L3: 18 10 10 7 7 29 RFC : Φ1mm Copper wire with enamel 4turns inside dia 6mm Rev.7.00 Aug 10, 2005 page 4 of 9 BB504M Typical Output Characteristics 200 50 0 50 100 150 Drain Current ID (mA) 3V 2V 4 VG2S = 1 V 1 2 3 4 5 8k Ω =6 4 5 30 VDS = 5 V RG = 120 kΩ 24 f = 1 kHz 4V 3V 18 2V 12 6 VG2S = 1 V 0 1 2 3 4 Gate1 Voltage VG1 (V) Gate1 Voltage VG1 (V) Power Gain vs. Gate Resistance Noise Figure vs. Gate Resistance 40 5 4 Noise Figure NF (dB) 35 Power Gain PG (dB) 3 Forward Transfer Admittance vs. Gate1 Voltage 8 30 25 10 10 2 Drain Current vs. Gate1 Voltage 12 15 1 Drain to Source Voltage VDS (V) 4V 20 4 Ambient Temperature Ta (°C) VDS = 5 V RG = 120 kΩ 0 kΩ 0 18 Ω 0k 22 8 0 200 20 16 12 82 10 k Ω 15 0 1 2 k 0 kΩ 0 kΩ Ω 100 16 G 150 VG2S = 4 V VG1 = VDS R Drain Current ID (mA) 20 Forward Transfer Admittance |yfs| (mS) Channel Power Dissipation Pch (mW) Maximum Channel Power Dissipation Curve VDS = 5 V VG1 = 5 V VG2S = 4 V f = 200 MHz 20 50 100 200 500 1000 Gate Resistance RG (kΩ) Rev.7.00 Aug 10, 2005 page 5 of 9 3 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 200MHz 2 1 0 10 20 50 100 200 500 1000 Gate Resistance RG (kΩ) BB504M Noise Figure vs. Gate Resistance Power Gain vs. Gate Resistance 4 40 Noise Figure NF (dB) Power Gain PG (dB) 35 30 25 20 15 10 10 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 900 MHz 20 50 3 2 1 0 10 500 1000 100 200 VDS = 5V VG1 = 5 V VG2S = 4 V f = 900 MHz Gate Resistance RG (kΩ) Input Capacitance Ciss (pF) Drain Current ID (mA) 500 1000 4 20 10 VDS = VG1=5 V VG2S = 4 V 20 50 100 200 3 2 VDS = VG1= 5 V RG = 120 kΩ f = 1 MHz 1 0 500 1000 0 1 2 3 4 Gate Resistance RG (kΩ) Gate2 to Source Voltage VGS2 (V) Gain Reduction vs. Gate2 acto Source Voltage Gain Reduction vs. Gate2 acto Source Voltage 0 0 Gain Reduction GR (dB) Gain Reduction GR (dB) 100 200 Input Capacitance vs. Gate2 to Source Voltage 30 10 20 30 VDS = VG1 = 5 V RG = 120 kΩ f = 200 MHz 40 50 50 Gate Resistance RG (kΩ) Drain Current vs. Gate Resistance 0 10 20 4 3 2 20 30 0 VDS = VG1 = 5 V RG = 120 kΩ f = 900 MHz 40 50 1 Gate2 to Source Voltage VGS2 (V) Rev.7.00 Aug 10, 2005 page 6 of 9 10 4 3 2 1 0 Gate2 to Source Voltage VGS2 (V) BB504M S11 Parameter vs. Frequency .8 1 S21 Parameter vs. Frequency 90° 1.5 .6 Scale: 1 / div. 60° 120° 2 .4 3 4 5 .2 30° 150° 10 .2 0 .4 .6 .8 1 1.5 2 3 45 10 180° 0° −10 −5 −4 −.2 −3 −.4 −30° −150° −2 −.6 −.8 −1 Test Condition: VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 120 kΩ , Zo = 50Ω 50 to 1000 MHz (50 MHz step) S22 Parameter vs. Frequency Scale: 0.004/ div. .8 60° 120° −90° Test Condition: VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 120 kΩ , Zo = 50Ω 50 to 1000 MHz (50 MHz step) S12 Parameter vs. Frequency 90° −60° −120° −1.5 1 .6 1.5 2 .4 3 30° 150° 4 5 .2 10 180° 0° .2 0 .4 .6 .8 1 1.5 2 3 45 10 −10 −5 −4 −.2 −30° −150° −3 −.4 −120° −60° −90° Test Condition: VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 120 kΩ , Zo = 50Ω 50 to 1000 MHz (50 MHz step) Rev.7.00 Aug 10, 2005 page 7 of 9 −2 −.6 −.8 −1 −1.5 Test Condition: VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 120 kΩ , Zo = 50Ω 50 to 1000 MHz (50 MHz step) BB504M S Parameter (VDS = VG1 = 5V, VG2S = 4 V, RG = 120 kΩ, Zo = 50 Ω) f(MHz) S11 S21 S12 S22 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 MAG. 1.000 0.993 0.991 0.984 0.978 0.970 0.958 0.954 0.945 0.932 0.920 0.910 0.900 0.887 0.870 0.863 ANG. -3.3 -7.2 -10.9 -15.0 -19.0 -22.8 -26.7 -30.3 -33.8 -37.5 -40.6 -44.3 -47.5 -50.9 -54.4 -57.6 MAG. 2.80 2.78 2.77 2.74 2.72 2.68 2.64 2.60 2.56 2.50 2.46 2.41 2.37 2.31 2.27 2.22 ANG. 175.9 170.9 166.1 161.2 156.5 151.8 147.2 142.7 138.6 134.1 129.8 125.7 121.6 117.8 113.6 110.0 MAG. 0.00106 0.00171 0.00253 0.00356 0.00442 0.00485 0.00576 0.00642 0.00689 0.00712 0.00765 0.00804 0.00798 0.00787 0.00785 0.00758 ANG. 58.8 75.7 75.1 77.4 78.2 80.0 74.7 71.7 73.3 71.8 70.7 69.9 69.1 67.8 70.8 73.3 MAG. 0.990 0.992 0.991 0.987 0.985 0.982 0.978 0.973 0.968 0.963 0.958 0.952 0.947 0.942 0.936 0.929 ANG. -2.4 -4.7 -7.2 -9.6 -12.2 -14.7 -17.1 -19.6 -22.0 -24.2 -26.7 -28.9 -31.3 -33.4 -35.8 -37.9 850 900 950 1000 0.853 0.839 0.827 0.819 -60.9 -63.6 -66.5 -70.1 2.18 2.12 2.07 2.04 105.8 102.2 98.6 94.9 0.00721 0.00694 0.00716 0.00667 75.2 75.8 88.1 92.7 0.924 0.917 0.912 0.906 -40.3 -42.5 -44.5 -46.7 Rev.7.00 Aug 10, 2005 page 8 of 9 BB504M Package Dimensions JEITA Package Code RENESAS Code SC-61AA Package Name PLSP0004ZA-A MASS[Typ.] MPAK-4 / MPAK-4V D 0.013g A e e2 b1 Q c B B E HE Reference Symbol L A LP L1 A A3 x M S b A e2 A2 e I1 A b5 S b b2 e1 A1 y S b1 b3 c1 c c1 I1 c b4 A-A Section B-B Section Pattern of terminal position areas A A1 A2 A3 b b1 b2 b3 c c1 D E e e2 HE L L1 LP x y b4 b5 e1 I1 Q Dimension in Millimeters Min 1.0 0 1.0 0.35 0.55 0.1 2.7 1.35 2.2 0.35 0.15 0.25 Nom 1.1 0.25 0.42 0.62 0.4 0.6 0.13 0.11 1.5 0.95 0.85 2.8 Max 1.3 0.1 1.2 0.5 0.7 0.15 3.1 1.65 3.0 0.75 0.55 0.65 0.05 0.05 0.55 0.75 1.95 1.05 0.3 Ordering Information Part Name BB504MDS-TL-E Quantity 3000 Shipping Container φ 178 mm Reel, 8 mm Emboss Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.7.00 Aug 10, 2005 page 9 of 9 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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