AD AD1940 Sigmadsp-tm multichannel 28-bit audio processor Datasheet

4
AD1940
VOLTAGE
REGULATOR
28
2
SERIAL DATA/
TDM INPUTS
2
2
MASTER
CLOCK
INPUT
SPI I/O
28
DSP CORE
PLL
DATA FORMAT:
5.23 (SINGLE
PRECISION)
10.46 (DOUBLE
PRECISION)
4
SERIAL
CONTROL
INTERFACE
RAM
ROM
SERIAL
DATA/
TDM
OUTPUTS
tLIH
tBIH
BCLK_IN
tBIL
tLIS
LRCLK_IN
tSIS
SDATA_INX
LEFT-JUSTIFIED
MODE
MSB
MSB-1
tSIH
tSIS
SDATA_INX
I2S-JUSTIFIED
MODE
MSB
tSIH
tSIS
tSIS
SDATA_INX
RIGHT-JUSTIFIED
MODE
LSB
MSB
tSIH
tSIH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
tLCH
tBIH
tTS
BCLK_OUTX
tBIL
tLOS
LRCLK_OUTX
SDATA_OUTX
LEFT-JUSTIFIED
MODE
SDATA_OUTX
I2S-JUSTIFIED
MODE
tSDDS
tSDDM
MSB
MSB-1
tSDDS
tSDDM
MSB
tSDDS
tSDDM
SDATA_OUTX
RIGHT-JUSTIFIED
MODE
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
LSB
tCLS
tCLH
tCLPH
tCCPL
tCCPH
CLATCH
CCLK
CDATA
tCDH
tCDS
COUT
tCOD
tMP
MCLK
RESETB
tRLPW
48 47 46 45 44 43 42 41 40 39 38 37
VDD 1
MCLK 2
RESERVED 3
PLL_CTRL0 4
PLL_CTRL1 5
PLL_CTRL2 6
PLL_GND 7
36
PIN 1
INDICATOR
35
34
33
AD1940
TOP VIEW
(Not to Scale)
PLL_VDD 8
NC 9
SDATA_OUT3
SDATA_OUT2
30 SDATA_OUT1
31
28
SDATA_OUT0
ODVDD
BCLK_OUT0
LRCLK_OUT0
25 VDD
27
BCLK_IN 11
GND 12
26
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
LRCLK_OUT1
ODVDD
32
29
LRCLK_IN 10
GND
BCLK_OUT1
2
DATA MEMORY
6k 28
SERIAL
DATA/TDM
INPUT
GROUP
2
PLL MODE
SELECT
2
TARGET/SLEW
RAM
64 28
RESETB
28 28
DSP CORE
SERIAL DATA/
TDM OUTPUT
GROUP
DATA FORMAT:
5.23 (SINGLE PRECISION)
10.46 (DOUBLE PRECISION)
MCLK
PLL
MASTER
CLOCK
INPUT
SPI I/O
GROUP
2
CONTROL
REGISITER
4
SERIAL
CONTROL
PORT
TRAP REG.
PROGRAM
RAM
1536 40
PARAMETER
RAM
1024 28
COEFFICIENT
ROM
512 28
SAFELOAD
REGISTER
MEMORY CONTROLLERS
VOLTAGE REGULATOR
4
REGULATOR
GROUP
4-BIT SIGN EXTENSION
DATA IN
DIGITAL
CLIPPER
SIGNAL PROCESSING
(5.23 FORMAT)
SERIAL PORT
1.23
5.23
5.23
1.23
CLATCH
CCLK
BYTE 0
CDATA
BYTE 1
BYTE 2
BYTE 3
CLATCH
CCLK
CDATA
COUT
BYTE 1
BYTE 0
HI-Z
DATA
DATA
DATA
HI-Z
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
10
20
TIME (ms)
30
1
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1
–1
0
5
10
15
20
TIME (ms)
25
30
35
1
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1
0
10
20
TIME (ms)
30
0
10
20
TIME (ms)
30
–1
0
10
20
TIME (ms)
30
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
LSB
MSB
SDATA
MSB
LSB
1 /F S
SDATA
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
MSB
LSB
MSB
LSB
1 /FS
SDATA
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
MSB
LSB
1 /FS
MSB
LSB
LRCLK
256 BCLKs
BCLK
32 BCLKs
DATA
SLOT 1
SLOT 2 SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
SLOT 8
LRCLK
BCLK
MSB
MSB–1
MSB–2
DATA
LRCLK
BCLK
MSB TDM
SDATA
MSB TDM
CH
0
SLOT 0
32
BCLKs
8TH
CH
SLOT 1
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
SDATA_IN0
SDATA_OUT0
SDATA_IN1
SDATA_OUT1
SDATA_IN2
SDATA_OUT2
SDATA_IN3
SDATA_OUT3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
DVDD
FZT953
+
10 F
100nF
+
10 F
1k
100nF
1nF
AD1940
0.75
0.60
0.45
9.00 BSC
SQ
1.60
MAX
37
48
1
1.45
1.40
1.35
0.15
0.05
10°
6°
2°
SEATING
PLANE
36
PIN 1
SEATING
PLANE
7.00
BSC SQ
TOP VIEW
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
(PINS DOWN)
VIEW A
25
12
13
0.50
BSC
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
24
0.27
0.22
0.17
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RDAC
VDD
RDAC
EEPROM
VLOGIC
GND
SCL
SDA
A
RDAC
REGISTER
W
B
I2C
SERIAL
INTERFACE
8
DATA
8
CONTROL
AD0
AD1
COMMAND
DECODE LOGIC
AD5259
ADDRESS
DECODE LOGIC
POWERON RESET
CONTROL LOGIC
VLOGIC
VDD
A
EEPROM
SCL
SDA
AD0
AD1
RDAC
REGISTER
AND
LEVEL
SHIFTER
I2C
SERIAL
INTERFACE
W
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
CONTROL
LOGIC
GND
B
W 1
AD0 2
AD5259
10
A
9
B
AD1 3
8 VDD
TOP VIEW
SDA 4 (Not to Scale) 7 GND
SCL 5
6
VLOGIC
t8
t6
t2
t9
SCL
t2
t4
t3
t8
t7
t10
t5
t9
SDA
t1
P
S
S
P
W 1
10
A
9
B
TOP VIEW
SDA 4 (Not to Scale)
8
VDD
7
GND
SCL 5
6
VLOGIC
AD0 2
AD1 3
AD5259
1.5
0.25
1.3
0.20
2.7V
1.1
0.15
0.9
0.10
0.7
0.05
0.5
0
0.3
–0.05
0.1
–0.10
–0.1
–0.15
–0.3
–40 C
+25 C
+85 C
–0.20
5.5V
–0.5
0
32
64
96
128
160
CODE (Decimal)
–0.25
192
224
256
0.5
0
32
64
96
128
160
CODE (Decimal)
192
224
256
0.25
0.4
0.20
2.7V
0.3
0.15
0.2
0.10
0.1
0.05
0
0
–0.1
–0.05
2.7V
–0.2
5.5V
–0.10
5.5V
–0.3
–0.15
–0.4
–0.20
–0.5
–0.25
0
32
64
96
128
160
CODE (Decimal)
192
224
256
0
0.25
0.25
0.20
0.20
0.15
0.15
32
64
2.7V
0.10
96
128
160
CODE (Decimal)
192
224
256
96
128
160
CODE (Decimal)
192
224
256
5.5V
0.10
TA = +85 C
0.05
0.05
0
0
–0.05
–0.05
–0.10
–0.10
–0.15
–0.15
TA = +25 C
–0.20
TA = –40 C
–0.25
0
32
64
96
128
160
CODE (Decimal)
192
224
256
–0.20
–0.25
0
32
64
0.5
2.0
0.4
1.8
0.3
1.6
0.2
1.4
ZSE @ VDD = 2.7V
0.1
–40 C
1.2
+25 C
0
1.0
–0.1
0.8
–0.2
0.6
–0.3
0.4
ZSE @ VDD = 5.5V
–0.4
0.2
+85 C
–0.5
0
32
64
96
128
160
CODE (Decimal)
192
224
256
0
–40
–20
0
20
40
TEMPERATURE ( C)
60
80
60
80
60
80
1
0.5
0.4
0.3
TA = –40 C
0.2
TA = +85 C
0.1
0
VDD = 5.5V
–0.1
TA = +25 C
–0.2
–0.3
–0.4
–0.5
0
32
64
96
128
160
CODE (Decimal)
192
224
256
0.1
–40
0
6
–0.5
5
–20
0
20
40
TEMPERATURE ( C)
4
–1.0
–1.5
VDD = 5.5V
3
FSE @ VDD = 5.5V
2
–2.0
1
FSE @ VDD = 2.7V
–2.5
–3.0
–40
VDD = 2.7V
0
–20
0
20
40
TEMPERATURE ( C)
60
80
–1
–40
–20
0
20
40
TEMPERATURE ( C)
400
100k
120
300
50k
100k
200
100
10k
Rt @ VDD = 5.5V
100
80
0
50k
–100
Rt @ VDD = 5.5V
60
–200
40
–300
5k
–400
5k
20
10k Rt @ VDD = 5.5V
Rt @ VDD = 5.5V
–500
–600
0
32
64
96
128
160
CODE (Decimal)
192
224
256
0
–40
70
0
60
–6
50
–12
40
–18
30
–20
0
20
10
20H
10H
08H
04H
02H
–36
0
01H
–42
–10
80
40H
–30
100k
60
80H
–24
10k
20
40
TEMPERATURE ( C)
–48
–20
5k
50k
–30
–54
–40
0
32
64
96
128
160
CODE (Decimal)
192
224
256
–60
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100k
FREQUENCY (Hz)
1M
10M
0
350
–6
300
–12
–18
250
RWB @ VDD = 2.7V
–24
200
–30
150
–36
80H
40H
20H
10H
08H
04H
02H
–42
100
RWB @ VDD = 5.5V
–48
50
0
–40
01H
–54
–20
0
20
40
TEMPERATURE ( C)
60
80
–60
1k
10k
0
10k
80H
–6
40H
–12
20H
–18
VDD = VLOGIC = 5V
1k
10H
–24
08H
–30
04H
–36
VDD = VLOGIC = 3V
02H
–42
100
01H
–48
–54
–60
1k
10k
100k
FREQUENCY (Hz)
10
1M
0
1
2
3
4
5
VIH (V)
0
80
80H
–6
CODE = MIDSCALE, VA = VLOGIC, VB = 0V
40H
–12
PSRR @ VLOGIC = 5V DC
20H
–18
10% p-p AC
60
10H
–24
08H
–30
40
PSRR @ VLOGIC = 3V DC
04H
–36
10% p-p AC
02H
–42
01H
–48
20
–54
–60
1k
10k
100k
FREQUENCY (Hz)
0
100
1M
1k
10k
FREQUENCY (Hz)
0
–6
–12
100k
80kHz
–18
50k
160kHz
10k
800kHz
5k
2MHz
–24
–30
–36
VW
1
–42
SCL
–48
2
–54
–60
1k
10k
100k
FREQUENCY (Hz)
1M
10M
400ns/DIV
100k
1M
VW
VW
1
1
SCL
2
1 s/DIV
200ns/DIV
VA
V+ = VDD
1LSB = V+/2N
DUT
A
V+
VDD
W
V+ = VDD
DUT
A
W
V+
B
B
VMS
DUT
A
IW
A W
VMS
DUT
W
VMS2
AD8610
–5V
+2.5V
RSW = 0.1V
ISW
CODE = 0x00
W
IW = VDD/RNOMINAL
VW
ISW
RW = [VMS1 – VMS2]/IW
B
VMS1
+5V
W
OFFSET
GND
DUT
A
VMS
VDD
VIN
B
B
(
VMS
NO CONNECT
DUT
10%
PSRR (dB) = 20 LOG
VMS%
PSS (%/%) =
VDD%
B
GND TO VDD
0.1V
VOUT
)
A
A
A
W
B
W
B
W
B
VI
A
W
B
A
RS
D7
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
RS
RS
W
RS
B
VO
A
D7
D6
D5
D4
D3
D2
D1
D0
SIGN
26
25
24
23
22
21
20
SIGN
7 BITS FOR INTEGER NUMBER
A
D7
D6
D5
D4
D3
D2
D1
D0
2–1
2–2
2–3
2–4
2–5
2–6
2–7
2–8
8 BITS FOR DECIMAL NUMBER
A
VDD
A
W
B
VDD
GND
C2
10 F
+
VDD
C1
0.1 F
AD5259
VLOGIC
GND
SCL
SDA
GND
VCC (~3.3V)
5V
VCC (~3.3V) SUPPLIES POWER 14.4V
TO BOTH THE
R1
MICRO AND THE
70k
LOGIC SUPPLY OF
THE DIGITAL POT
C1
AD5259
1 F
R6
R5
VDD
10k
10k
VLOGIC
R2
A
10k
SCL
MCU
W
B
SDA
14.4V
R1
70k
C1
1 F
AD5259
R6
10k
R5
10k
VLOGIC
A
SCL
MCU
GND
–
VDD
SDA
B
R2
10k
W
GND
R3
25k
R3
25k
U1
AD8565
+
3.5V < VCOM < 4.5V
–
U1
AD8565
+
3.5V < VCOM < 4.5V
INDEX
AREA
3.00 BSC
10
6
10
1.50
BCS SQ
4.90 BSC
3.00 BSC
1
PIN 1
INDICATOR
3.00
BSC SQ
0.50
BSC
5
1
2.48
2.38
2.23
EXPOSED
PAD
TOP VIEW
(BOTTOM VIEW)
PIN 1
6
0.50 BSC
0.95
0.85
0.75
0.15
0.00
1.10 MAX
0.27
0.17
SEATING
PLANE
0.23
0.08
8°
0°
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
0.80
0.60
0.40
0.80
0.75
0.70
SEATING
PLANE
0.80 MAX
0.55 TYP
SIDE VIEW
0.30
0.23
0.18
0.50
0.40
0.30
0.05 MAX
0.02 NOM
0.20 REF
5
1.74
1.64
1.49
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