ATMEL AT29LV512-25TC 512k 64k x 8 3-volt only cmos flash memory Datasheet

AT29LV512
Features
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Single Supply Voltage, Range 3V to 3.6V
3-Volt-Only Read and Write Operation
Software Protected Programming
Low Power Dissipation
15 mA Active Current
20 µA CMOS Standby Current
Fast Read Access Time - 200 ns
Sector Program Operation
Single Cycle Reprogram (Erase and Program)
512 Sectors (128 bytes/sector)
Internal Address and Data Latches for 128-Bytes
Fast Sector Program Cycle Time - 20 ms Max.
Internal Program Control and Timer
DATA Polling for End of Program Detection
Typical Endurance > 10,000 Cycles
CMOS and TTL Compatible Inputs and Outputs
Commercial and Industrial Temperature Ranges
512K (64K x 8)
3-volt Only
CMOS Flash
Memory
Description
The AT29LV512 is a 3-volt-only in-system Flash programmable erasable read only
memory (PEROM). Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less
than 20 µA. The device endurance is such that any sector can typically be written to
in excess of 10,000 times.
(continued)
Pin Configurations
Pin Name
Function
A0 - A15
Addresses
AT29LV512
PLCC Top View
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC
No Connect
TSOP Top View
Type 1
0177I
4-43
Description (Continued)
To allow for simple in-system reprogrammability, the
AT29LV512 does not require high input voltages for programming. Three-volt-only commands determine the operation of the device. Reading data out of the device is
similar to reading from an EPROM. Reprogramming the
AT29LV512 is performed on a sector basis; 128-bytes of
data are loaded into the device and then simultaneously
programmed.
During a reprogram cycle, the address locations and 128bytes of data are captured at microprocessor speed and
internally latched, freeing the address and data bus for
other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then
program the latched data using an internal control timer.
The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been
detected, a new access for a read or program can begin.
Block Diagram
Device Operation
READ: The AT29LV512 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus
contention.
SOFTWARE DATA PROTECTION PROGRAMMING:
The AT29LV512 has 512 individual sectors, each 128bytes. Using the software data protection feature, byte
loads are used to enter the 128-bytes of a sector to be
programmed. The AT29LV512 can only be programmed
or reprogrammed using the software data protection feature. The device is programmed on a sector basis. If a byte
of data within the sector is to be changed, data for the entire 128-byte sector must be loaded into the device. The
AT29LV512 automatically does a sector erase prior to
loading the data into the sector. An erase command is not
required.
Software data protection protects the device from inadvertent programming. A series of three program commands
to specific addresses with specific data must be presented
to the device before programming may occur. After writing
the three-byte command sequence (and after tWC), the entire device is protected. The same three program commands must begin each program operation. All software
program commands must obey the sector program timing
specifications. Power transitions will not reset the software
data protection feature, however the software feature will
guard against inadvertent program cycles during power
transitions.
Any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data
will be written to the device; however, for the duration of
tWC, a read operation will effectively be a polling operation.
After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
on the WE or CE input with CE or WE low (respectively)
and OE high. The address is latched on the falling edge of
CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE.
The 128-bytes of data must be loaded into each sector.
Any byte that is not loaded during the programming of its
sector will be erased to read FFh. Once the bytes of a sector are loaded into the device, they are simultaneously
programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low transition
on WE (or CE) within 150 µs of the low to high transition of
WE (or CE) of the preceding byte. If a high to low transition
is not detected within 150 µs of the last low to high transition, the load period will end and the internal programming
(continued)
4-44
AT29LV512
AT29LV512
Device Operation (Continued)
period will start. A7 to A15 specify the sector address. The
sector address must be valid during each high to low transition of WE (or CE). A0 to A6 specify the byte address
within the sector. The bytes may be loaded in any order;
sequential loading is not required. Once a programming
operation has been initiated, and for the duration of tWC, a
read operation will effectively be a polling operation.
to use the software product identification mode to identify
the part (i.e. using the device code), and have the system
software use the appropriate sector size for program operations. In this manner, the user can have a common
board design for 256K to 4-megabit densities and, with
each density’s sector size in a memory map, have the system software apply the appropriate sector size.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT29LV512 in
the following ways: (a) VCC sense— if VCC is below 1.8V
(typical), the program function is inhibited. (b) VCC power
on delay— once VCC has reached the VCC sense level,
the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit— holding any one
of OE low, CE high or WE high inhibits program cycles. (d)
Noise filter— pulses of less than 15 ns (typical) on the WE
or CE inputs will not initiate a program cycle.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
INPUT LEVELS: While operating with a 3.3V ±10%
power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines
can only be driven from 0 to 3.6 volts.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish
DATA POLLING: The AT29LV512 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
TOGGLE BIT: I n a d d i t i o n t o DATA p o l l i n g t h e
AT29LV512 provides another method for determining the
end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE: The entire device
can be erased by using a 6-byte software code. Please
see Software Chip Erase application note for details.
Absolute Maximum Ratings*
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to VCC + 0.6V
Voltage on A9
(including NC Pins)
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
4-45
DC and AC Operating Range
AT29LV512-15
Com.
Operating
Temperature (Case)
Ind.
VCC Power Supply (1)
AT29LV512-20
AT29LV512-25
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
3.3V ± 0.3V
3.3V ± 0.3V
3.3V ± 0.3V
1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an operational
mode is started.
Operating Modes
Mode
CE
OE
WE
Ai
I/O
Read
VIL
VIL
VIH
Ai
DOUT
Program (2)
VIL
VIH
VIL
Ai
DIN
X
X
High Z
Standby/Write Inhibit
VIH
X
(1)
Program Inhibit
X
X
VIH
Program Inhibit
X
VIL
X
Output Disable
X
VIH
X
High Z
Product Identification
Hardware
VIL
VIL
A1 - A15 = VIL, A9 = VH (3),
A0 = VIL
A1 - A15 = VIL, A9 = VH (3),
A0 = VIH
VIH
Software (5)
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
Manufacturer Code (4)
Device Code (4)
A0 = VIL
Manufacturer Code (4)
A0 = VIH
Device Code (4)
4. Manufacturer Code: 1F, Device Code: 3D.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units
VIN = 0V to VCC
1
µA
VI/O = 0V to VCC
1
µA
Com.
20
µA
Ind.
50
µA
ILI
Input Load Current
ILO
Output Leakage Current
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
1
mA
ICC
VCC Active Current
f = 5 MHz; IOUT = 0 mA; VCC = 3.6V
15
mA
VIL
Input Low Voltage
0.6
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 1.6 mA; VCC = 3.0V
VOH
Output High Voltage
IOH = -100 µA; VCC = 3.0V
4-46
AT29LV512
2.0
V
.45
2.4
V
V
AT29LV512
AC Read Characteristics
AT29LV512-15
AT29LV512-20
Max
Units
200
250
ns
200
250
ns
0
120
ns
0
60
ns
Symbol
Parameter
tACC
Address to Output Delay
150
tCE (1)
CE to Output Delay
150
tOE (2)
OE to Output Delay
0
70
0
100
tDF (3, 4)
CE or OE to Output Float
0
40
0
50
tOH
Output Hold from OE, CE or
Address, whichever occurred first
0
AC Read Waveforms
Min
Max
Min
AT29LV512-25
Max
Min
0
0
ns
(1, 2, 3, 4)
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC .
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
after an address change without impact on tACC .
3. tDF is specified from OE or CE whichever occurs first
(CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
Units
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
Conditions
1. These parameters are characterized and not 100% tested.
4-47
AC Byte Load Characteristics
Symbol
Parameter
Min
tAS, tOES
Address, OE Set-up Time
10
ns
tAH
Address Hold Time
100
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
200
ns
tDS
Data Set-up Time
100
ns
tDH, tOEH
Data, OE Hold Time
10
ns
tWPH
Write Pulse Width High
200
ns
AC Byte Load Waveforms
(1, 2)
WE Controlled
CE Controlled
4-48
AT29LV512
Max
Units
AT29LV512
Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
tWC
Write Cycle Time
20
ms
tAS
Address Set-up Time
10
ns
tAH
Address Hold Time
100
ns
tDS
Data Set-up Time
100
ns
tDH
Data Hold Time
10
ns
tWP
Write Pulse Width
200
ns
tBLC
Byte Load Cycle Time
tWPH
Write Pulse Width High
150
200
µs
ns
Software Protected Program Waveform (1, 2, 3)
Notes: 1. OE must be high when WE and CE are both low.
2. A7 through A15 must specify the sector address
during each high to low transition of WE (or CE)
after the software code has been entered.
Programming Algorithm
3. All bytes that are not loaded within the sector being
programmed will be indeterminate.
(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA
TO
(3)
SECTOR (128 BYTES)
WRITES ENABLED
ENTER DATA
PROTECT STATE
(2)
Notes for software program code:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Data Protect state will be re-activated at end of program cycle.
3. 128-bytes of data MUST BE loaded.
4-49
Data Polling Characteristics
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
(1)
Min
Typ
Max
Units
10
ns
10
ns
(2)
tOE
OE to Output Delay
tWR
Write Recovery Time
ns
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
(1)
Min
Typ
Max
Units
10
ns
10
ns
(2)
tOE
OE to Output Delay
tOEHP
OE High Pulse
tWR
Write Recovery Time
ns
150
ns
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms
(1, 3)
Notes: 1. Toggling either OE or CE or both OE and CE will
operate toggle bit.
4-50
AT29LV512
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address
should not vary.
AT29LV512
Software Product (1)
Identification Entry
Software Product (1)
Identification Exit
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 20 mS
ENTER PRODUCT
IDENTIFICATION
(2, 3, 5)
MODE
PAUSE 20 mS
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
Notes for software product identification:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A15 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1F
Device Code: 3D
4-51
Ordering Information
tACC
ICC (mA)
Ordering Code
Package
0.02
AT29LV512-15JC
AT29LV512-15TC
32J
32T
Commercial
(0° to 70°C)
15
0.05
AT29LV512-15JI
AT29LV512-15TI
32J
32T
Industrial
(-40° to 85°C)
15
0.02
AT29LV512-20JC
AT29LV512-20TC
32J
32T
Commercial
(0° to 70°C)
15
0.05
AT29LV512-20JI
AT29LV512-20TI
32J
32T
Industrial
(-40° to 85°C)
15
0.02
AT29LV512-25JC
AT29LV512-25TC
32J
32T
Commercial
(0° to 70°C)
15
0.05
AT29LV512-25JI
AT29LV512-25TI
32J
32T
Industrial
(-40° to 85°C)
(ns)
Active
Standby
150
15
200
250
Package Type
32J
32 Lead, Plastic J-Leaded Chip Carrier (PLCC)
32T
32 Lead, Thin Small Outline Package (TSOP)
4-52
AT29LV512
Operation Range
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