ALSC ASM2I9942P Low voltage 1:18 clock distribution chip Datasheet

ASM2I9942P
May 2005
rev 0.3
Low Voltage 1:18 Clock Distribution Chip
Features
With low output impedance (≈12Ω), in both the HIGH and
ƒ
LVPECL Clock Input
ƒ
2.5V
LVCMOS
LOW logic states, the output buffers of the ASM2I9942P
Outputs
for
Pentium
IITM*
With an output impedance of 12Ω, the ASM2I9942P can
Microprocessor Support
ƒ
200pS
Maximum
are ideal for driving series terminated transmission lines.
Targeted
Output–to–Output
drive two series terminated transmission lines from each
output. This capability gives the ASM2I9942P an effective
Skew
fanout of 1:36. The ASM2I9942P provides enough copies
ƒ
Maximum Output Frequency of 250MHz @3.3 VCC
of low skew clocks for most high performance synchronous
ƒ
32–Lead LQFP and TQFP Packaging
systems.
ƒ
Single 3.3V or 2.5V Supply
The differential LVPECL inputs of the ASM2I9942P allow
ƒ
Pin and Function compatible with MPC942P
the device to interface directly with a LVPECL fanout buffer
to build very wide clock fanout trees or to couple to a high
Functional Description
The ASM2I9942P is a 1:18 low voltage clock distribution
chip with 2.5V or 3.3V LVCMOS output capabilities. The
device is offered in two versions; the ASM2I9942C has an
frequency clock source. The OE pins will place the outputs
into a high impedance state. The OE pin has an internal
pullup resistor.
LVCMOS input clock while the ASM2I9942P has a
The ASM2I9942P is a single supply device. The VCC power
LVPECL input clock. The 18 outputs are 2.5V or 3.3V
pins require either 2.5V or 3.3V. The 32 lead LQFP and
LVCMOS compatible and feature the drive strength to drive
TQFP package is chosen to optimize performance, board
50Ω series or parallel terminated transmission lines. With
space and cost of the device. The 32–lead LQFP and
output-to-output skews of 200pS, the ASM2I9942P is ideal
TQFP have a 7x7mm2 body size with conservative 0.8mm
as a clock distribution chip for the most demanding of
pin spacing.
synchronous systems. The 2.5V outputs also make the
device ideal for supplying clocks for a high performance
Pentium IITM microprocessor based design.
* Pentium II is a trademark of Intel Corporation
Block Diagram
Table 1. Function Table
Q0
PECL_CLK
PECL_CLK
Q1-Q16
Q17
OE
Output
0
1
HIGH IMPEDANCE
OUTPUTS ENABLED
OE
(Int. Pullup)
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
ASM2I9942P
May 2005
rev 0.3
Q6
Q7
Q8
VCC
Q9
Q10
Q11
GND
Pin Diagram
24
23
22
21
20
19
18
17
GND
25
16
VCC
Q5
26
15
Q12
Q4
27
14
Q13
Q3
28
13
Q14
VCC
29
12
GND
Q2
30
11
Q15
Q1
31
10
Q16
Q0
32
9
Q17
5
NC
PECL_CLK
Table 2. Pin Description
Pin #
Pin Name
6
7
8
VCC
4
VCC
3
PECL_CLK
2
OE
GND
1
GND
ASM2I9942P
I/O
Type
Function
5
6
PECL_CLK,
PECL_CLK
Input
LVPECL
LVPECL Clock Inputs
3
OE
Input
LVCMOS
Output enable/disable
(high–impedance tristate)
4
NC
-
32,31,30,28,27,26,24,23,22,20,19,18,15,
14,13,11,10,9
-
No connect
Q0 – Q17
Output
LVCMOS
1,2,12,17,25
GND
Supply
Ground
7,8,16,21,29
VCC
Supply
VCC
Clock outputs
Negative power supply (GND)
for I/O and core.
Positive power supply for I/O and
core. All VCC pins must be
connected to the positive power
supply for correct operation
Table 3. Absolute Maximum Rating1
Symbol
Min
Max
Unit
Supply Voltage
–0.3
3.6
V
VI
Input Voltage
–0.3
IIN
TStor
Input Current
Storage Temperature Range
VCC + 0.3
±20
125
mA
°C
VCC
Parameter
–40
V
Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
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ASM2I9942P
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rev 0.3
Table 4. DC Characteristics (TA = 0°to 70°C, VCC = 2.5V ± 5%)
Symbol
Characteristic
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VPP
Input Swing PECL_CLK
VX
Input Crosspoint PECL_CLK
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIN
Input Current
Min
Typ
2.0
Max
Unit
VCC
V
0.8
V
0.6
1.0
V
VCC–1.0
VCC–0.6
V
2.0
V
IOH = –16 mA
0.5
V
IOL = 16 mA
±200
µA
CIN
Input Capacitance
4.0
pF
CPD
Power Dissipation Capacitance
14
pF
ZOUT
Output Impedance
12
ICC
Maximum Quiescent Supply Current
0.5
Condition
Per Output
Ω
5.0
mA
Max
Unit
Table 5. AC Characteristics (TA = 0°to 70°C, VCC = 2.5V ± 5%)
Symbol
Characteristic
Min
Typ
Fmax
Maximum Frequency
200
MHz
tPLH
Propagation Delay
1.8
4.0
nS
tPHL
Propagation Delay
2.0
4.3
nS
tsk(o)
Output-to-Output Skew within one bank
tsk(pr)
Part–to–Part Skew 1
150
2.2
pS
1.3
pS
1.0
nS
Max
Unit
VCC
V
0.8
V
0.6
1.0
V
VCC–1.0
VCC–0.6
tsk(pr)
tr, tf
2
Part–to–Part Skew
Output Rise/Fall Time
0.1
Condition
nS
Note: 1. Across temperature and voltage ranges, includes output skew.
2. For a specific temperature and voltage, includes output skew.
Table 6. DC Characteristics (TA = 0°to 70°C, VCC = 3.3V ± 5%)
Symbol
Characteristic
Min
Typ
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
2.4
VPP
Input Swing PECL.CLK
VX
Input Crosspoint PECL_CLK
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIN
Input Current
CIN
Input Capacitance
4.0
pF
CPD
Power Dissipation Capacitance
14
pF
2.4
ZOUT
Output Impedance
12
ICC
Maximum Quiescent Supply Current
0.5
Condition
V
V
IOH = –20 mA
0.6
V
IOL = 20 mA
±200
µA
Per Output
Ω
5.0
mA
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
3 of 10
ASM2I9942P
May 2005
rev 0.3
Table 7. AC Characteristics (TA = 0°to 70°C, VCC = 3.3V ± 5%)
Symbol
Characteristic
Min
Fmax
Maximum Frequency
tPLH
Propagation Delay
1.5
tPHL
tsk(o)
Propagation Delay
1.5
Typ
Max
Unit
250
MHz
3.2
nS
3.6
nS
Output-to-output Skew within one bank
150
pS
tsk(pr)
1
Part–to–Part Skew
1.7
nS
tsk(pr)
tr, tf
Part–to–Part Skew2
1.0
pS
1.0
nS
Output Rise/Fall Time
0.1
Condition
Note: 1. Across temperature and voltage ranges, includes output skew.
2. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
4 of 10
ASM2I9942P
May 2005
rev 0.3
per output, (Μ)ΣCL represents the external capacitive
output load, N is the number of active outputs (N is
always 12 in case of the ASM2I9942P). The
ASM2I9942P supports driving transmission lines to
maintain high signal integrity and tight timing parameters.
Any transmission line will hide the lumped capacitive load
at the end of the board trace, therefore, ΣCL is zero for
controlled transmission line systems and can be
eliminated from equation 1. Using parallel termination
output termination results in equation 2 for power
dissipation.
Power Consumption of the ASM2I9942P and
Thermal Management
The ASM2I9942P AC specification is guaranteed for the
entire operating frequency range up to 250MHz. The
ASM2I9942P power consumption and the associated
long-term reliability may decrease the maximum
frequency limit, depending on operating conditions such
as clock frequency, supply voltage, output loading,
ambient temperature, vertical convection and thermal
conductivity of package and board. This section
describes the impact of these parameters on the junction
temperature and gives a guideline to estimate the
ASM2I9942P die junction temperature and the associated
device reliability.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination, VOL, IOL, VOH and IOH are
a function of the output termination technique and DCQ is
the clock signal duty cycle. If transmission lines are used
ΣCL is zero in equation 2 and can be eliminated. In
general, the use of controlled transmission line
techniques eliminates the impact of the lumped capacitive
loads at the end lines and greatly reduces the power
dissipation of the device. Equation 3 describes the die
junction temperature TJ as a function of the power
consumption.
Table 8. Die junction temperature and MTBF
Junction temperature
(°C)
MTBF (Years)
100
20.4
110
9.1
120
4.2
130
2.0
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable
MTBF, the die junction temperature of the ASM2I9942P
needs to be controlled and the thermal impedance of the
board/package should be optimized.The power dissipated
in the ASM2I9942P is represented in equation 1.
Where ICCQ is the static current consumption of the
ASM2I9942P, CPD is the power dissipation capacitance
Where Rthja is the thermal impedance of the package
(junction to ambient) and TA is the ambient temperature.
According to Table 8, the junction temperature can be
used to estimate the long-term device reliability. Further,
combining equation 1 and equation 2 results in a
maximum operating frequency for the ASM2I9942P in a
series terminated transmission line system, equation 4.



PTOT =  I CCQ + VCC ⋅ f CLOCK ⋅  N ⋅ C PD + ∑ C L  ⋅ VCC
M






PTOT = VCC ⋅  I CCQ + VCC ⋅ f CLOCK ⋅  N ⋅ C PD + ∑ C L  + ∑ DC Q ⋅ I OH (VCC − VOH ) + (1 − DC Q ) ⋅ I OL ⋅ VOL
M
 P


T J = T A + PTOT ⋅ Rthja
[
f CLOCKMAX =
C PD
1
2
⋅ N ⋅ VCC
T

− TA
⋅  JMAX
− (I CCQ ⋅ VCC )
 Rthja

Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
Equation 1
]
Equation 2
Equation 3
Equation 4
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ASM2I9942P
May 2005
rev 0.3
TJ,MAX should be selected according to the MTBF
system requirements and Table 8. Rthja can be derived
from Table 9. The Rthja represent data based on 1S2P
boards, using 2S2P boards will result in lower thermal
impedance than indicated below.
Table 9. Thermal package impedance of the
32LQFP
Convection,
Rthja (1P2S
Rthja (2P2S
board), °C/W
board), °C/W
LFPM
Still air
100 lfpm
200 lfpm
300 lfpm
400 lfpm
500 lfpm
86
76
71
68
66
60
61
56
54
53
52
49
If the calculated maximum frequency is below 350 MHz, it
becomes the upper clock speed limit for the given
application conditions. The following eight derating charts
describe the safe frequency operation range for the
ASM2I9942P. The charts were calculated for a maximum
tolerable die junction temperature of 110°C (120°C),
corresponding to an estimated MTBF of 9.1 years
(4 years), a supply voltage of 3.3V and series terminated
transmission line or capacitive loading. Depending on a
given set of these operating conditions and the available
device convection a decision on the maximum operating
frequency can be made.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
6 of 10
ASM2I9942P
May 2005
rev 0.3
Package Information
32-lead TQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0472
…
1.2
A1
0.0020
0.0059
0.05
0.15
A2
0.0374
0.0413
0.95
1.05
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.2
a
0°
7°
0°
7°
e
0.031 BASE
0.8 BASE
Low Voltage 1:18 Clock Distribution Chip
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7 of 10
ASM2I9942P
May 2005
rev 0.3
32-lead LQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0630
…
1.6
A1
0.0020
0.0059
0.05
0.15
A2
0.0531
0.0571
1.35
1.45
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.20
e
a
0.031 BASE
0°
7°
0.8 BASE
0°
7°
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
8 of 10
ASM2I9942P
May 2005
rev 0.3
Ordering Information
Marking
Ordering Code
Package Type
Operating Range
ASM2I9942P-32-LT
ASM2I9942PL
32-pin LQFP, Tray
Industrial
ASM2I9942P-32-LR
ASM2I9942PL
32-pin LQFP,Tape and Reel
Industrial
ASM2I9942PG-32-LT
ASM2I9942PGL
32-pin LQFP, Tray, Green
Industrial
ASM2I9942PG-32-LR
ASM2I9942PGL
32-pin LQFP,Tape and Reel, Green
Industrial
ASM2I9942P-32-ET
ASM2I9942PE
32-pin TQFP, Tray
Industrial
ASM2I9942P-32-ER
ASM2I9942PE
32-pin TQFP,Tape and Reel
Industrial
ASM2I9942PG-32-ET
ASM2I9942PGE
32-pin TQFP, Green
Industrial
ASM2I9942PG-32-ER
ASM2I9942PGE
32-pin TQFP,Tape and Reel, Green
Industrial
Device Ordering Information
A S M 2 I 9 9 4 2 P G - 3 2 - L R
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
9 of 10
ASM2I9942P
May 2005
rev 0.3
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM2I9942P
Document Version: 0.3
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
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Low Voltage 1:18 Clock Distribution Chip
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