Cypress CY2DP814ZCT 1:4 clock fanout buffer Datasheet

CY2DP814
1:4 Clock Fanout Buffer
Features
Description
■
Low-voltage operation
The Cypress CY2 series of network circuits are produced
using advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
■
VDD = 3.3V
■
1:4 fanout
■
Single input configurable for LVDS, LVPECL, or LVTTL
■
Four differential pairs of LVPECL outputs
■
Drives 50-ohm load
■
Low input capacitance
■
Less than 4 ns typical propagation delay
■
85 ps typical output-to-output skew
■
Industrial versions available
■
Available in TSSOP package
The Cypress CY2DP814 fanout buffer features a single LVDSor a single LVPECL-compatible input and four LVPECL output
pairs.
Designed for data communications clock management applications, the fanout from a single input reduces loading on the
input clock.
The CY2DP814 is ideal for both level translations from
single-ended to LVPECL, and/or for the distribution of
LVDS-based clock signals. The Cypress CY2DP814 has
configurable input between logic families. The input can be
selectable for an LVPECL, LVTTL or LVDS signal, while the
output drivers support LVPECL capable of driving 50-ohm
lines.
Logic Block Diagram
EN1 1
EN2 8
16 Q1A
15 Q1B
14 Q2A
13 Q2B
IN+ 6
IN- 7
LVDS /
LVPECL /
LVTTL
12 Q3A
11 Q3B
CONFIG 2
10 Q4A
9 Q4B
OUTPUT
LVPECL
Cypress Semiconductor Corporation
Document #: 38-07060 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 22, 2008
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CY2DP814
Pin Configuration
EN1
CONFIG
VDD
VDD
GND
IN+
INEN2
1
2
3
4
5
6
7
8
CY2DP814
Figure 1. 16-Pin TSSOP/SOIC
16
15
14
13
12
11
10
9
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
16 pin TSSOP / SOIC
Pin Description
Pin Number
Pin Name
Pin Standard Interface
Description
6, 7
IN+, IN–
Configurable
Differential input pair or single line. LVPECL default.
See CONFIG below.
2
CONFIG
LVTTL/LVCMOS
Converts inputs from the default
LVPECL/LVDS
(logic = 0)
to LVTTL/LVCMOS (logic = 1).
See Figure 6 and Figure 7 for additional information
1, 8
EN1, EN2
LVTTL/LVCMOS
Enable/disable logic. See Function Table below for
details.
16, 15, 14, 13, 12, 11, 10, 9
Q1A, Q1B,
Q2A, Q2B,
Q3A, Q3B,
Q4A, Q4B
LVPECL
Differential outputs.
3, 4
VDD
POWER
Positive supply voltage.
5
GND
POWER
Ground.
Document #: 38-07060 Rev. *E
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CY2DP814
Maximum Ratings[1, 2]
Supply Voltage to Ground Potential
(Outputs only) ........................................ –0.3V to VDD + 0.3V
Storage Temperature: ................................. –65°C to +150°C
DC Input Voltage ................................... –0.3V to VDD + 0.3V
Ambient Temperature: .................................. –40°C to +85°C
DC Output Voltage................................. –0.3V to VDD + 0.9V
Supply Voltage to Ground Potential
Power Dissipation........................................................ 0.75W
(Inputs and VCC only) .......................................–0.3V to 4.6V
Table 1. EN1 EN2 Function Table
Enable Logic
Input
Outputs
EN1
EN2
IN+
IN–
QnA
QnB
H
H
H
L
H
L
H
L
H
L
H
L
L
L
H
L
H
L
L
H
X
X
Z
Z
Table 2. Input Receiver Configuration for Differential or LVTTL/LVCMOS
CONFIG Pin 2 Binary Value
1
Input Receiver Family
Input Receiver Type
LVTTL in LVCMOS
0
Single ended, non-inverting, inverting, void of bias resistors.
LVDS
Low voltage differential signaling
LVPECL
Low voltage pseudo (positive) emitter coupled logic
Table 3. Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal
Ground
VCC
Ground
VCC
Input Condition
IN– Pin 7
IN+ Pin 6
IN– Pin 7
IN+ Pin 6
IN+ Pin 6
IN– Pin 7
IN+ Pin 6
IN– Pin 7
LVTTL/LVCMOS INPUT LOGIC
Input Logic
Output Logic Q pins
Input
True
Input
Invert
Input
Invert
Input
True
Table 4. Power Supply Characteristics
Parameter
Description
Test Conditions
Min
ICCD
Dynamic Power Supply Current VDD = Max.
Input toggling 50% Duty Cycle, Outputs Loaded
IC
Total Power Supply Current
VDD = Max.
Input toggling 50% Duty Cycle, Outputs Loaded,
fL= 100 MHz
Typ
Max
Unit
1.5
2.0
mA/MHz
90
100
mA
Table 5. DC Electrical Characteristics: 3.3V–LVDS Input
Parameter
Description
Conditions
Min
VID
Magnitude of Differential Input Voltage
100
VIC
Common-Mode of Differential Input Voltage
IVIDI (min. and max.)
IVIDI
/2
IIH
Input High Current
VDD = Max.
IIL
Input Low Current
VDD = Max.
II
Input High Current
VDD = Max., VIN = VDD(max.)
Typ Max Unit
600 mV
2.4–
(IVIDI /2)
V
VIN = VDD
±10
±20
μA
VIN = VSS
±0
±20
μA
±20
μA
Notes
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Document #: 38-07060 Rev. *E
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CY2DP814
Table 6. DC Electrical Characteristics: 3.3V–LVPECL Input
Parameter
Description
Condition
Min
Guaranteed Logic High Level
Typ
400
Max
Unit
2600
mV
2250
mV
±20
μA
I VID I
Differential Input Voltage p-p
VCM
Common-mode Voltage
IIH
Input High Current
VDD = Max.
VIN = VDD
±10
IIL
Input Low Current
VDD = Max.
VIN = VSS
±10
±20
μA
II
Input High Current
VDD = Max., VIN = VDD(max.)
±20
μA
Max
Unit
1650
Table 7. DC Electrical Characteristics: 3.3V–LVTTL/LVCMOS Input
Parameter
Description
Condition
VIH
Input High Voltage
Guaranteed Logic High Level
VIL
Input Low Voltage
Guaranteed Logic Low Level
Min
Typ
2
V
0.8
V
IIH
Input High Current
VDD = Max.
VIN = 2.7V
1
μA
IIL
Input Low Current
VDD = Max.
VIN = 0.5V
–1
μA
II
Input High Current
VDD = Max., VIN = VDD(max.)
20
μA
VIK
Clamp Diode Voltage
VDD = Min., IIN = –18 mA
–1.2
V
VH
Input Hysteresis
–0.7
80
mV
Table 8. DC Electrical Characteristics: 3.3V–LVPECL Output
Parameter
Description
Condition
Min
Typ
Max
Unit
I VOD I
Driver Differential Output Voltage p-p
VDD = Min., VIN = VIH or VIL RL = 50 ohm
1000
–
3600
mV
I VOC I
Driver common-mode p-p
VDD = Min., VIN = VIH or VIL RL = 50 ohm
–
–
226
mV
Rise Time
Differential 20% to 80%
CL–10 pF RL and CL to
GND
RL = 50 ohm
300
800
ps
2.1
–
3.0
V
–
–
–125
–
Fall Time
VOH
Output High Voltage
VDD = Min., VIN = VIH or VIL IOH = –12 mA
VOL
Output Low Voltage
User-defined (see Figure 1)
IOS
Short Circuit Current
VDD = Max., VOUT = GND
V
–150
mA
Table 9. AC Switching Characteristics @ 3.3V VDD = 3.3V ±5%, Temperature = –40°C to +85°C
Parameter
Description
Conditions
Min
Typ
Max
Unit
IN [+,–] to Q[A,B] Data & Clock Speed
tPLH
Propagation Delay—Low to High
3
4
5
ns
tPHL
Propagation Delay—High to Low
3
4
5
ns
tPD
Propagation Delay
3
4
5
ns
VOD = 100 mV
EN [1,2] to Q[A,B] Control Speed
tPE
Enable (EN) to functional operation
–
–
6
ns
Tpd
Functional operation to Disable
–
–
5
ns
tSK(0)
Output Skew: Skew between outputs of the same package (in phase)
–
0.085
0.2
ns
tSK(p)
Pulse Skew: Skew between opposite transitions of the same output
(tPHL–tPLH)
–
0.2
–
ns
tSK(t)
Package Skew: Skew between outputs of different packages at the VID = 100 mV
same power supply voltage, temperature and package type. Same
input signal level and output load.
–
–
1
ns
Document #: 38-07060 Rev. *E
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CY2DP814
Figure 2. Differential PECL Output
VDD - 2V
VDD
Q
Q
Device concept
User Defined
VTT & RTT
Table 10. High-frequency Parametrics
Parameter
Description
Conditions
Max
Unit
50% Duty Cycle tW(50–50)
Standard Load Circuit
450
MHz
Maximum Frequency
VDD = 3.3V
20% Duty Cycle tW(20–80)
LVPECL Input
Vin = VIH(Max.)/VIL(Min.)
Vout = VOH(Min.)/VOL (Max.) (Limit)
175
MHz
Minimum Pulse
VDD = 3.3V
LVPECL Input
Vin = VIH(Max.)/VIL(Min.) F = 100 MHz
Vout = VOH(Min.)/VOL(Max.).(Limit)
Fmax
Maximum Frequency
VDD = 3.3V
Fmax(20)
TW
Min
Typ
900
ps
Figure 3. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3, 4, 5, 6, 7]
A
T PA
150
P ulse
G enera tor
B
150
50
10pF
TPC
V D D -2V
50
GND
T PB
E n1
E n2
S tan dard T erm in ation
V 1A
1.4 V
1 .2 V C M
0 V D if f e r e n t ia l
V 1B
1.0 V
V 0Y
1.4 V
1 .2 V C M
0 V D if f e r e n t ia l
1.0 V
V 0Z
T PLH
TPHL
80%
0 V D if f e r e n t ia l
V0Y V0Z
20%
t
R
t
F
Notes
3. RL = 50 ohm ± 1%; Zline = 50 ohm 6 = Ó.
4. CL includes instrumentation and fixture capacitance within 6 mm of the UT.
5. TPA and B are used for prop delay and rise/fall measurements. TPC is used for VOC measurements only and otherwise connected to VDD – 2.
6. When measuring Tr/Tf, tpd, VOD point TPC is held at VDD – 2.0V.
7. LVCMOS/LVTTL single-ended input value. Ground either input: when on the B side, non-inversion takes place. If A side is grounded, the signal becomes the complement
of the input on B side. See Table 3.
Document #: 38-07060 Rev. *E
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CY2DP814
Figure 4. Test Circuit and Voltage Definitions for the Driver Common-mode Output Voltage[3, 4, 5, 7, 8]
A
TPA
150
P u ls e
G e n e ra to r
50
TPC
B
150
En1
En2
50
GND
TPB
VOC
VOD
S ta n d a rd T e rm in a tio n
V I(A )
1 .4 V
V I(B )
1 .0 V
V o c (p p )
VDD
V o c (s s )
Figure 5. Test Circuit and Voltage Definitions for the Differential Output Signal [3, 4, 5, 6, 7]
A
TPA
150
Pulse
Generator
B
150
50
10pF
TPC
VDD-2V
50
GND
TPB
En1
En2
Standard Termination
VI(A)
1.4V
VI(B)
1.0V
100%
80%
0.0V
20%
0%
tF
Document #: 38-07060 Rev. *E
tR
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CY2DP814
Figure 6. Test Circuit and Voltage Definitions for the Driver Common-Mode Output Voltage[3, 4, 5, 8, 9]
P uls e
G en era to r
P uls e
G e nerator
TPA
50
TPC VDD-2V
50
TPB
VOC
En1
En2
Parallel Termination
+
DE
Q
tpd
tpe
Figure 7. LVTTL/LVCMOS
Figure 8. LVDS/LVPECL
LVPECL &
LVDS
INPUT A
LVCM OS / LVTTL
INPUT B
GND
In C o n fig
InConfig
1
0
L V D S /L V P E C L
LVTTL/LVCMOS
Ordering Information
Part Number
CY2DP814ZCT
Package Type
Product Flow
16-pin TSSOP–Tape and Reel
Commercial, 0°C to 70 °C
CY2DP814ZXC
16-pin TSSOP
Commercial, 0°C to 70 °C
CY2DP814ZXCT
16-pin TSSOP–Tape and Reel
Commercial, 0°C to 70 °C
CY2DP814ZXI
16-pin TSSOP
Industrial, –40°C to 85 °C
CY2DP814ZXIT
16-pin TSSOP–Tape and Reel
Industrial, –40°C to 85 °C
Pb free
Notes
8. VOC measurement requires equipment with a 3-dB bandwidth of at least 300 MHz.
9. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF < 1 ns; pulse re-rate = 50 Mpps; pulse width = 10 ± 0.2 ns.
Document #: 38-07060 Rev. *E
Page 7 of 9
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CY2DP814
Package Drawing and Dimensions
Figure 9. 16-Pin TSSOP 4.40 mm Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
MAX.
1
REFERENCE JEDEC MO-153
6.25[0.246]
6.50[0.256]
PACKAGE WEIGHT 0.05 gms
PART #
4.30[0.169]
4.50[0.177]
Z16.173
STANDARD PKG.
ZZ16.173 LEAD FREE PKG.
16
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
4.90[0.193]
5.10[0.200]
0.05[0.002]
0.15[0.006]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85091-*A
Note
10. LVPECL or LVDS differential input value.
Document #: 38-07060 Rev. *E
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CY2DP814
Document History Page
Document Title: CY2DP814 1:4 Clock Fanout Buffer
Document Number: 38-07060
REV.
ECN No.
Submission
Date
Orig. of
Change
**
10785
06/07/01
IKA
*A
115610
07/02/02
CTK
Range of VCM
*B
122746
12/15/02
RBI
Added power-up requirements to maximum ratings information.
*C
382376
See ECN
RGL
Added Lead-free device for TSSOP commercial
Removed pruned parts
Added typical values
*D
403374
See ECN
RGL
Added Lead-free for TSSOP Industrial
*E
2595534
10/23/08
CXQ
Removed CY2DP814ZC from the Ordering Information
Updated template
Description of Change
Convert from IMI to Cypress
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
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assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07060 Rev. *E
Revised October 22, 2008
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